ece compilation 190

1

PART 1

1.1 DOs AND DON’Ts Inside the Laboratory Room

1.2 Safety Precautions

1.3 Breadboarding Guide

1.4 Guidelines in Performing an Experiment

1.5 Up/Down Thinking

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1.1 DOs AND DON’Ts Inside the Laboratory Room

Dos

1. Read and follow the safety precautions given here to avoid any untoward accident

2. Familiarize yourself with the layout of your laboratory room, including the location of

some materials used during an emergency such as fire extinguisher and first-aid kit.

3. Do read and follow the Standard Operating Procedure (SOP) inside the laboratory room

in order to perform your experiment smoothly.

4. Refer to the breadboarding guide for faster, accurate and safe construction of

experimental circuits.

5. Be more careful when working with circuits carrying a current greater than 0.03

ampere to avoid severe electric shock.

6. Familiarize yourself with the proper use and care of the laboratory equipment and

instruments.

7. Take care in performing any laboratory experiment and handling materials.

8. Check the functionality of all equipment and materials before and after use.

9. Keep your working area clean.

10. Do your work quietly.

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DON’Ts

1. Do not eat, drink or smoke inside the laboratory room.

2. Do not write anything on the chairs, tables and walls of the laboratory room.

3. Do not play with the equipment and experiment materials while performing the

experiment.

4. Do not place wet materials or containers filled with liquid on top of or near the laboratory

equipment and components.

5. Do not perform an experiment with your hands wet.

6. Do not let any part of your body touch the ground when you are working with high

voltage or high currents circuits.

7. Do not panic in case of emergency.

8. Do not perform any cardiopulmonary resuscitation to a victim of any accident (e.g

electric shock) unless you are qualified or authorized to do so.

9. Do not apply mechanical shock to the equipment and measuring instruments especially

to those with analog meter reading.

10. Do not directly touch a person who has just suffered electric shock.

11. Do not use long wire connector.

12. Do not touch both end terminals of a capacitor or inductor unless you are sure that it is

already discharged.

13. Do not place any combustible materials near the power outlet or the experimental circuit.

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1.2 Safety Precautions

1. Do not place any combustible materials near the power outlet

2. Avoid using a power cord with defects such as loose contact and exposed conductors.

3. Avoid using connecting wires with exposed conductors.

4. Make sure that the size of the connecting wires used in experimental circuit is large enough

to carry the current flowing in the circuit.

5. Do all wiring connections with the power OFF.

6. Check all the wiring and components for proper connections, sizes, values, and orientations

before turning the circuit’s power ON.

7. Be careful when working with circuits carrying a current greater than 30 mA. Currents of

about 50 mA can cause severe electric shock, and currents of about 100 mA can kill a

person.

8. Remove any jewelry which is conductive.

9. Avoid touching both end terminals of a capacitor or inductor unless you are sure that it has

been discharged.

10. Check your measuring instrument for proper voltage/current/resistance settings before

making any measurement.

11. Do not use any instrument, component or material above its rated voltage, current and

power.

12. Refer to the instrument’s user manual for its care and safe use.

13. Refer to the breadboarding guide for the components’ safety.

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1.3 Breadboarding Guide

Before you perform the experiments in this manual, it is helpful to read these time-tested guidelines

on breadboarding a circuit:

1. Do all wiring with the power OFF.

2. Keep the wiring and component lead as short as possible.

3. Wire the supply leads first to the Integrated Circuit.

4. Try to wire all the ground leads to one point, the common power supply. This type of

connection is called star grounding. Do not use a ground bus.

5. Recheck the wiring before applying power to the circuit.

6. Connect signal voltages to the circuit only when the IC is powered.

7. Take all measurements with respect to ground. For example, if a resistor is connected

between two terminals of an IC, do not connect either a meter or an oscilloscope across the

resistor, instead, measure the voltage on one side of the resistor and then on the other side

and calculate the voltage across the resistor.

8. Avid using ammeters, if possible. Measure the voltage as in the step 7 and calculate the

current.

9. Disconnect the input signal before the direct current (DC) power is removed.

10. The ICs will stand as much abuse. But never:

a. Reverse the polarity of the power supplies.

b. Drive the component’s particularly the IC’s, input pins above the +Vcc potential.

c. Leave all input signal connected with no power on the IC.

or: leave all input signals with no power connected to the IC.

11. If unwanted oscillations appear at the output and the circuit connections seem correct:

a. Connect a 0.1 µF capacitor between the IC’s + V pin and the ground.

b. Shorten your leads and

c. Check the test instrument, signal generator, load and power supply ground leads.

They should come together at one point.

http://en.wikipedia.org/wiki/Mu_(letter)

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1.5 Guidelines in Performing an Experiment

These guidelines are important for the students to perform the experiment smoothly, obtain

accurate data and results; and come up with a good observation, analysis and conclusion, within

the allowed laboratory hours, without damaging any of the components or equipment, and without

hurting anybody inside the laboratory class.

1. Read and apply the DO’s and DON’Ts inside the laboratory room.

2. Read and apply the safety precautions.

3. Read and apply the breadboarding.

4. Understand clearly the objectives of the experiment.

5. Read the questions given in the experiment and try to answer them on paper.

6. Thoroughly read and understand the procedure.

7. From the procedures and respective experiment circuits, determine which are the independent

and dependent variables for you to know which variables in the experiment should be

observed.

An independent variable is one whose value is not affected in any way by any change in

value of another variable. Its value is constant at any given condition or being varied in the

experiment.

A dependent variable is one whose value is affected, i.e, increase or decreases as the

independent variables change.

8. Refer to the safety precautions and breadboarding guides for proper circuit construction and

operation.

9. Be aware of and consistent with the units used on each variable for accurate reading and

recording and interpretation of data obtained from the experiment.

10. Apply the up/down thinking method in observing and analyzing the effects of the independent

variables on the dependent variables.

11. From your observation and analysis, and based on the experiment objectives, derive the

conclusion. The conclusion is usually written in one sentence only.

You may now proceed with your first experiment.

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1.5 Up/Down Thinking

Experiment performance does not end with the complete gathering of data and results from the

experimental circuits. The gathered data and results must be properly observed and analyzed in

order to come up with a correct conclusion and meet the given objectives of the experiment.

UP/DOWN THINKING is introduced by Albert Paul Malvino in his book Electronic principle

which is very helpful in observing and analyzing the results of an experiment. It will help you

understand how circuit works, use formulas intelligently and arrive at a correct conclusion. It can

also be used to troubleshoot your experimental circuit whenever a problem occurs during an

experiment.

UP/DOWN THINKING is a method of analyzing the effect of varying an independent variable

on the dependent variable in a circuit. When an independent variable increases, each of the

dependent variables will usually respond by increasing or decreasing. It can applied in a circuit

following the given steps below:

1. Determine the variables in the circuit.

2. Determine which of these are independent and dependent variables.

3. Determine the mathematical equation or formula that shows the relationship between these

two variables.

4. Using the formula, determine the changes (up/increase or down/decrease) on the dependent

variable as you make changes to the independent variables.

EXAMPLE: Below is a simple circuit with a resistor connected across a voltage source. From this

circuit, we have three variables: the voltage V, resistor R, and the current I. You will see ho

Up/Down thinking can be applied, with the use of one basic formula to two different condition.

Given circuit:

The tables show two different conditions that might occur on the given circuit.

CONDITION1: CONDITION 2:

Table A: R=100 Ω Table B: V=5V

VOLTAGE,V CURRENT, I RESISTOR, R CURRENT, I

1V 100Ω

3V 250Ω

5V 500Ω,

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Applying Up/Down Thinking

Step:

1. Variables are V, I, and R.

2. In condition 1, as shown in Table A, resistor R is constant and the voltage V changes from

1V to 3V, then to 5V. The current I is unknown and has to be determined. Therefore R and

V are the independent variables and I is the dependent variable. In condition 2, as shown

in Table B, voltage V is constant and the resistor R changes from 100Ω to 500 Ω. the current

I is still the unknown variable. Therefore, same as in condition 1, R and V are the

independent variables and I is the dependent variable.

3. Ohm’s Law shows the relationship among the three variables found in the given circuit

above. This formula is:

𝐼 =𝑉

𝑅

4. By using Ohm’s Law, we can complete tables A and B:

Table A: R=100 Ω Table B: V=5V

VOLTAGE,V CURRENT, I RESISTOR, R CURRENT, I

1V 0.01A 100Ω 0.05A

3V 0.03A 250Ω 0.02A

5V 0.05A 500Ω, 0.01A

The table can be expressed as follows:

Table A: “If R= k, as V , I ; and as V , I .”

This means that I R is constant, and V increases ( ), I also increases ( ); and as V decreases

( ), I also decreases ( ).

Table B: “If V = k, as R ,I ; and as R ,I .”

This means that if V is constant, and R increases ( ), I decreases ( ); and as R decreases ( ),

I increases ( ).

We can now conclude, on that given circuit, that “with the resistor held constant, current is directly

proportional to the supply voltage”; and “with the supply voltage held constant, current is inversely

proportional to the resistance”.

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PART 2

2.1 Titles of Experiment and their Objectives

2.2 Summary List of Required Materials

2.3 DTL-05 Digital Trainer Functional Features

2.4 Definition of Terms and Variables Used in the Experimental Circuits

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2.1 Titles of Experiment and their Objectives

EXPT. NO. 1: NUMBER SYSTEM

OBJECTIVE: To demonstrate the count sequence of a 4-bit binary.

EXPT. NO. 2: CODE CONVERTER

OBJECTIVE: To construct and verify the operation of code converter circuits.

EXPT. NO. 3: DIODES AND TRANSISTORS AS SWITCHES

OBJECTIVES:

1. To verify the operation of a diode and transistor as switches.

2. To use the transistor switch as a light emitting diode (LED) driver.

3. To use the transistor switch as a relay driver.

EXPT. NO. 4: BASIC LOGIC OPERATIONS AND GATES

OBJECTIVES:

1. To verify the logical properties of basic logic operators using discrete

diode-transistor logic circuits and Transistor-Transistor Logic (TTL) IC

logic gates.

2. To introduce the concepts of duality.

EXPT. NO. 5: EXCLUSIVE-OR (XOR) GATES

OBJECTIVES:

1. To verify the operation of an XOR Gate

2. To use an XOR Gate as a controlled inverter.

3. To demonstrate the use of an XOR Gate in controlling a lamp from two

different locations.

EXPT. NO. 6: DIGITAL IC FAMILIES

OBJECTIVES:

1. To determine the basic characteristics of TTL and CMOS ICs.

2. To verify the operation and applications of open collector and three-

state gates.

EXPT. NO. 7: BOOLEAN FUNCTION FORMS

OBJECTIVE: To introduce the standard Boolean Function forms, namely: the Standard

AND-OR (SAO), also known as sum of Minterm form; Standard AND-OR-

Invert (SAOI) and Standard OR-AND-Invert (SOAI).

EXPT. NO. 8: SIMPLIFICATION OF BOOLEAN FUNCTIONS

OBJECTIVE: To simplify Boolean functions by Karnaugh-mapping.

EXPT. NO. 9: COMBINATIONAL logic circuits

OBJECTIVE: To design, construct and test combinational logic circuits using basic gates.

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EXPT. NO. 10: MULTIPLEXER

OBJECTIVES:

1. To verify the operation of a multiplexer (MUX).

2. To implement a Boolean function using a MUX Medium Scale

Integration (MSI) device.

3. To connect two MUX ICs together to form a digital MUX with a larger

number of inputs.

EXPT. NO. 11: DECODER AND MULTIPLEXER

OBJECTIVES:

1. To verify the operation of a decoder and a demultiplexer (deMUX).

2. To connect a decoder/deMUX together to form a larger decoder circuit.

3. To implement a Boolean function using decoder IC and (NAND) gates.

EXPT. NO. 12: ARITHMETIC CIRCUITS

OBJECTIVES:

1. To construct and verify the operation of a half-adder circuit.

2. To construct and verify the operation of a half-subtractor circuit.

3. To construct and verify the operation of a full-adder circuit.

4. To verify the operation of a 4-bit binary full-adder IC-74LS83.

5. To construct and test a 4-bit binary parallel adder-subtractor circuit

using two 4-bit binary full adder IC- 74LS83 and one quad two-input

XOR IC- 74LS86.

EXPT. NO. 13: BASIC FLIP-FLOPS

OBJECTIVE: To construct, test and investigate the operation of various flip-flop circuits

and devices.

EXPT. NO. 14: 8-BIT LATCH

OBJECTIVE: To verify the operation of an 8-bit latch using 74LS373.

EXPT. NO. 15: ASYNCHRONOUS OR RIPPLE COUNTERS

OBJECTIVES:

1. To construct and test a 4-bit binary ripple counter using flip-flop ICs.

2. To construct and test a Binary-Coded-Decimal (BCD) ripple counter

using flip-flop ICs.

3. To construct and test a 4-bit binary ripple counter using 74LS93.

4. To construct and test a BCD ripple counter using 74LS93.

EXPT. NO. 16: SYNCHRONOUS COUNTERS

OBJECTIVES:

1. To construct and test binary and BCD synchronous counters using flip-

flop.

2. To construct and test binary and BCD synchronous counters using

74LS193

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EXPT. NO. 17: SHIFT REGISTER

OBJECTIVE: To verify the different modes of operation of a shift register using a 4-bit

universal shift register IC-74LS194.

EXPT. NO. 18: MEMORY DEVICES

OBJECTIVES:

1. To verify the behavior of a random access memory (RAM) unit and its

storage capability using a 4x4 file register IC (74LS670).

2. To construct and test a read only memory (ROM) circuit using a decoder

IC and diodes.

3. To expand the memory location of a RAM device.

4. To use a memory device to implement a Boolean function in

combinational logic design.

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2.2 Summary List of Required Materials

1. Digital Trainer (see DTL-05 functional specs. on page)- 1 2. Multitester – 1 3. ICs:

4. Transistor: PNP: 9012 - 1

NPN: 9013 - 2

5. Diodes: 1N4148 - 7

1N4000 - 1

6. Resistors (1/4W): 150 Ω - 1

330 Ω - 3

1k Ω - 2

4.7k Ω - 2

10k Ω - 2

100k Ω - 2

7. Trimmer Resistor: 500 Ω - 1

8. LED - 1

9. SPDT Relay, coil source: 6Vdc - 1

10. Set of Breadboarding/ solid wire - 1

74LS07 - 1 74LS83 - 1

74LS00 - 3 74LS86 - 1 74LS02 - 1 74LS125 - 1 74LS04 - 2 74LS138 - 1 74LS08 - 1 74LS139 - 1 74LS10 - 2 74LS153 - 1 74LS20 - 2 74LS192 - 1 74LS27 - 3 74LS193 - 1 74LS32 - 1 74LS60 - 1 74LS47 - 1 74LS73 - 1 74LS74 - 1 74LS670 - 2

74LS76 - 2 74HC04 - 1

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2.3 DTL-05 Digital Trainer Functional Features

+5V DC Regulated Voltage Source

Variable Clock Generator with True and Complement Output:

CLK

8-bit Data Switches with True and Complement Output:

D7, D6, D5, D4, D3, D2, D1, D0

2-bit Control Switches With True And Complement Output:

K1, K0

8-bit Two Color LED Logic Indicators:

Red Indicator = High Level

Green Indicator = Low Level

Dual Common Anode 7- Segment Display

Breadboard System

Male DB-25 Connector

Female DB-25 Connector

For details on its specifications and operations, refer to its User’s Manual.

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2.4 Definition of Terms and Variables Used in the Experimental

Circuits

AC = alternating current

BCD = binary coded decimal

C = reference variable for capacitor

CE = collector-emitter

CLK= clock

CMOS = complimentary metal oxide semiconductor

CPR = cardiopulmonary resuscitation

Control Switch = the switch found on DTL-05 that generates the necessary control

signal for the experimental circuits.

D = reference variable for diode unless otherwise specified

Data Switch = refers to the switch found on DTL-05 that generates the necessary digital

data for the experimental circuits.

D0, D1, D2, D3, D4, D5, D6, D7 = the Data Switches of DTL-05. These are used to

provide the necessary digital data to the experimental circuits.

DC = direct current

deMUX = demultiplexer

GND = ground

HI= refers to a HIGH level voltage

IC = integrated circuit

K0, K1 = the Control Switches of DTL-05 used to provide the necessary control signal to

the experimental circuits.

LED = light emitting diode

LO = a LOW level voltage

LSTTL = low power schottky transistor-transistor-logic

L0, L1, L2, L3, L4, L5, L6, L7 = the Logic Indicators of DTL-05 used to monitor the

logic state of digital signals in the experimental circuits.

mA = milliampere

MUX = multiplexer

Q = reference variable for transistor

R = reference variable for fixed resistor; used to represent the unit ohm in a circuit

diagram (example: 150R means 150-ohms, 1kR means 1k-ohms, 4k7R, means

7.7k ohms).

RAM = random access memory

RLY = relay

ROM = read only memory

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SAO = standard AND-OR

SOA = standard OR-AND

SOAI = standard OR-AND-Invert

SAOI = standard AND-OR-Invert

SOP = sum of products

SPDT = single-pole-double-throw

SD = reference variable for switching signal diode

Vcc = supply voltage for TTL (74LSXX) device

Vce = collector- emitter voltage

VDD = supply voltage for CMOS (74HCXX) device

VR = reference variable for variable resistor

XOR = exclusive- OR

0 = a LOW level voltage unless otherwise specified

1 = a HIGH level voltage unless otherwise specified

P = pico, x 1012

µ = micro, x10-6

m = milli, x10-3

k = kilo, x103

M = Mega, x106

http://en.wikipedia.org/wiki/Mu_(letter)

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PART 3

EXPERIMENTS

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EXPT. NO. 1: NUMBER SYSTEM

OBJECTIVE: To demonstrate the count sequence of a 4-bit binary.

SUGGESTED READINGS: Discussion about the different number systems like decimal,

binary, octal, hexadecimal, etc. Digital Computer Electronics by Malvino &

Brown, pp. 1-15; Digital Design by Mano, pp.4-20.

REQUIRED SKILLS: To proceed smoothly, the students must be familiar with the use of

DTL-05 or any similar digital trainer.

MATERIALS REQUIRED:

Description Qty.

DTL-05 (Digital trainer) 1

ICs: 74LS47 1

74LS192 1

74LS193 1

Resistor: 150-Ω 1

Breadboarding wire 1 set

WARNING:

1. Do all wiring with power OFF.

2. Make sure you are using the correct power supply voltage as specified.

3. Never reverse the polarity of the power supply to prevent damage to the IC.

Refer to Appendix B for the IC’s and other components’ pin configurations.

PROCEDURE: 1. With power switch OFF, connect the 74FS47 IC as shown in circuit of Fig. 1-1.

Fig. 1-1:

2. Turn the power switch ON and set the data switches D3-D0 to sixteen (16) different

combinations (1=III. 0=LO) given in Table 1-1. Draw the actual 7-segment display

pattern of each of the 16 given combinations under the column 7-segment Display Pattern

of Table 1-1.

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3. Turn OFF the power and connect the circuit shown in Fig. 1-2

Fig. 1-2

4. Turn the power ON and set the CLK frequency to minimum for easy monitoring of the

Count sequence on the Logic Indicators and the 7-segment display.

5. Record the binary count sequence, as it starts from 0000, and its corresponding decimal

equivalent in Table 1-2.

6. Turn the power OFF and replace the IC (74LS192) with 74LS193 without changing any

connection in the circuit.

7. Turn the power ON and record the binary count sequence, as it stars from 0000, and its

corresponding decimal equivalent in Table 1-3.

Table 1-1: Table for step #2

DATA SWITCHES

D3 D2 D1 D0

7- SEGMENT

DISPLAY

PATTERN

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

DATA SWITCHES

D3 D2 D1 D0

7- SEGMENT

DISPLAY

PATTERN

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

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Table 1-2: for step #5


LOGIC

INDICATORS

L3 L2 L1 L0

7- SEGMENT

DISPLAY

PATTERN

LOGIC

INDICATORS

L3 L2 L1 L0

7- SEGMENT

DISPLAY

PATTERN

LOGIC

INDICATORS

L3 L2 L1 L0

7- SEGMENT

DISPLAY

PATTERN

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OBSERVATION AND ANALYSIS:

CONCLUSION:

When you have completed all of the above, have your laboratory instructor sign below:

QUESTIONS:

1. In Fig. 1-1.

1-1. What number system is being represented by the output of the 7-segment display?

a) binary b) BCD c) hexadecimal d) none of the above

1-2. What maximum valid number has the 7-segment display for the binary input of

0000 to 1111? Why?

1-3. How do you describe the function of the IC used in the circuit of Fig. 1-1?

2. In Fig. 1-2.

2-1. What count sequence is demonstrated using 74LS192?

a)binary b)BCD c) Hexadecimal d) none of the above

2-2. How do you describe the function of this IC?

2-3. What count sequence is demonstrated using 74LS193?

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a)binary b)BCD c) Hexadecimal d) none of the above

2-4. How do you describe the function of 74LS193?

3. Convert the binary number 101010110110 to decimal and hexadecimal numbers.

4. In writing a number, the number system being used can be determined by placing a letter,

‘b’ for binary and ‘d’ for decimal, right after the rightmost digit. What letter is used to

Indicate that the number is octal? hexadecimal?

5. Define the following terms: bit byte nibble LSB

binary hex BCD MSB

ANSWERS TO QUESTIONS:

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EXPT. NO. 2: CODE CONVERTER

OBJECTIVE: To construct and test code converter circuits.

SUGGESTED READINGS: Topics covering different codes used in digital systems such as

BCD, gray code, excess three codes, etc. Digital Computer Electronics by

Malvino & Brown, pp. 1-15; Digital Design by Mano, pp. 17-24.

REQUIRED SKILLS: To proceed smoothly, the student must be familiar with the use of


MATERIALS REQUIRED:

Description Qty.

Digital trainer 1

IC’s: 74LS00 3

74LS10 2

74LS47 1

74LS86 1


WARNING:

1. Do all wiring or any change in wiring with the power OFF unless

Otherwise specified in the procedure.

2. Make sure you are using the correct supply voltage as specified.


Refer to appendix V for the IC’s and other components’ pin

configurations.

PROCEDURE:

Part 1: Gray code-to-Binary converter

1. The logic diagram for Fig. 2-1 is a 3-bit Gray code-to-binary converter circuit. Table 2-1

gives the corresponding output in binary for every gray code input. Verify the conversion

from gray code to binary of Fig. 2-1 by completing the columns L2, L1 and L0.

Fig. 2-1: Gray code-to-binary converter

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Table 2-1: Truth table for a Gray code-to-binary converter

GRAY BINARY LOGIC

INDICATORS

C B A X Y Z L2 L1 L0

0 0 0 0 0 0

0 0 1 0 0 1

0 1 1 0 1 0

0 1 0 0 1 1

1 1 0 1 0 0

1 1 1 1 0 1

1 0 1 1 1 0

1 0 0 1 1 1

Part 2: BCD-to-excess three code converter

2. The diagram of a BCD-to-excess three code converter is given in Fig. 2-2. Verify the

code conversion by completing the data on Table 2-2.

Table 2-2: Truth table for BCD-to-excess three code converter

BCD EXCESS THREE LOGIC

INDICATORS

C B A X Y Z L2 L1 L0

0 0 0 0 0 0

0 0 1 0 0 1

0 1 1 0 1 0

0 1 0 0 1 1

1 1 0 1 0 0

1 1 1 1 0 1

1 0 1 1 1 0

1 0 0 1 1 1

25

Fig. 2-2: BCD-to-excess three code converter


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CONCLUSION:


QUESTIONS:

1. In the given code of Table 2-1, how many hits in the code group changed from one

Number to the next?

2. When using BCD, what is the next higher number to 1001?

3. Represent a decimal 386 in BCD and excess three code.

4. What is the standard 7-bit code used by the computer to represent numbers, letters and

Other symbols?

5. With an ACSCII keyboard, each stroke produces the ASCII equivalent of the designated

character. Suppose you type GERALD. What is the output of the ASCII keyboard?


27

EXPT NO. 3: DIODES AND TRANSISTORS AS SWITCHES

OBJECTIVES: 1. To verify the operation of a diode and transistor as switches.

2. To use the transistor switch as a LED driver.

3. To use the transistor switch as a relay driver.

SUGGESTED READINGS: Discussion on the basic operation and characteristic of a diode

and transistor as switches. Electronic principles by Malvino, pp. 62-65,

158-171, 211-213, 258-263.

REQUIRED SKILLS: To proceed smoothly, the student must be familiar with the use of a

multitester and the DTL-05 or any similar digital trainer.

MATERIALS REQUIRED:

Description Qty.

Digital trainer 1

Multitester 1

1N4148 Signal diode 1

1N4000 Rectifier diode 1

9013 NPN Transistor 1

9012 PNP Transistor 1

LED 1

Resistors, 1/4W: 330Ω 1

1k Ω 1

4.7K Ω 1

10K Ω 1

Relay, SPDT, coil 6Vdc 1


WARNING:




Refer to Appendix B for IC’s and other components’ pin

configurations.

PROCEDURE:

Part 1: diode as a Switch 1. Construct the circuits shown in Fig. 3-1. Test each circuit and record the results on the

space provided.

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Fig. 3-1a: Fig.c3-1b:

Measured voltage = Measured voltage =

Part 2: Transistor as a Switch

2. Construct the circuit as shown in Fig. 3-2. Verify the circuit and record the results in

Table 3-1.

Fig. 3-2:

Table 3-1: Table for the circuit of Fig. 3-2.

DATA SWITCH MEASURED VOLTAGE

D0 VBE VCE VOUT

L0

H1

3. Construct the circuit shown in Fig. 3-3. Verify the circuit and record the results in Table 3-2.

Fig. 3-3:

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DATA SWITCH MEASURED VOLTAGE

D0 VBE VCE VOUT

L0

H1


Fig. 3-4:


DATA SWITCH OUTPUT

D0 VCE LED (ON/OFF)

L0

H1


Fig. 3-5:

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DATA SWITCH OUTPUT

D0 VCE L0

(H1/L0)

L1

(H1/L0)

RELAY

(ENERGIZED/

DEENERGIZED)

L0

H1


CONCLUSION:

When you have finished all of the above, have your laboratory instructor sign below:

31

QUESTIONS:

1. Consider the diode on the circuit of Fig. 3-1a as ideal diode. What should be your

measured voltage?

2. Draw the switch equivalent circuit of Fig. 3-1a and 3-1b.

3. In the circuit of Fig. 3-2, what Data Switch setting causes a maximum flow of collector

current?

4. Draw the switch equivalent circuit of the collector-emitter (CE) junction of the transistor

in Fig. 3-3 when the Data Switch is set to H1.

5. The Cut-Off method is one way of testing a saturated transistor in circuit, to determine if

it operates normally as a switch by shorting the base-emitter junction. What should be the

normal collector-emitter voltage (VCE) reading if we apply the Cut-Off method to the

transistor of Fig. 3-2?

6. If we describe the output of the circuit in Fig. 3-4 as active HIGH, how would you

describe

Its input, active HIGH or active LOW?

7. In the circuit of Fig. 3-4, compute for the amount of current flowing to the LED using

your result in Table 3-3. Assume the LED has a voltage drop of 1.7V.

8. Draw the switch equivalent circuit of the transistor in Fig. 3-5 when the relay is energized

and deenergized.


32

EXPT. NO. 4: BASIC LOGIC OPERATIONS AND GATES

OBJECTIVES: 1. To verify the logical properties of basic logic operators using discrete

Diode-transistor logic circuits and TTL IC logic gates.

2. To introduce the concepts of duality.

SUGGESTED READINGS: Discussion on the basic operation and characteristics of a diode

and transistor as switches, the basic logic functions and gates, and the positive

and negative logic. Electronic Principles by Malvino, pp. 62-65, 158-171,

211-213, 258-263, Digital Computer Electronics by Malvino & Brown, pp.

19-36; Digital Design by Mano, pp. 36-68.


multitester and the DTL-05 or any similar digital trainer.

MATERIALS REQUIRED:

Description Qty.

Digital trainer 1

1N4148 Signal diode 3

9013 NPN Transistor 3

IC’s: 74LS00 3

74LS02 1

74LS04 1

74LS08 1

74LS32 1

74LS08 1

Resistors: 4.7K Ω 2

10K Ω 2


WARNING:




Refer to Appendix B for IC’s and other components’ pin

configurations.

PROCEDURE:

Part 1. Transistor Inverter


Table

4-1.

33

Fig. 4-1:


Part II. Resistor-Transistor Gate


Table 4-2.

Fig. 4-2:


INPUT

DATA

OUTPUT

INDICATOR

POSITIVE LOGIC

NEGATIVE LOGIC

INPUT OUTPUT INPUT OUTPUT

D0 L0 A Q A Q

L0

H1

INPUT

DATA

OUTPUT

INDICATOR

POSITIVE LOGIC NEGATIVE LOGIC

INPUT OUTPIT INPUT OUTPUT

D1 D0 L0 B A Q B A Q

L0 L0

L0 H1

H1 L0

H1 H1

34

Part III. Diode Gates

3. Construct the circuit as shown in Fig. 4-3A. Verify the circuit and record the results in

Table 4-3A

Fig. 4-3A

Table 4-3A: Table for the circuit of Fig. 4-3A.

4. Construct the circuit shown in Fig. 4-3B. verify the circuit and record the results in

Table 4-3B.

Fig. 4-3B:

Table 4-3B: Table for the circuit of Fig. 4-3B.

INPUT

DATA

OUTPUT

INDICATOR




L0 L0

L0 H1

H1 L0

H1 H1

INPUT

DATA

OUTPUT

INDICATOR




L0 L0

L0 H1

H1 L0

H1 H1

35

Part IV. Diode-Transistor Logic Gate

1. Construct a circuit as shown in Fig. 4-4. Verify the circuit and record the result in Table 4-4.

Fig. 4-4:

Table 4-4: Table for the circuit of Fig. 4-4:

INPUT

DATA

OUTPUT

INDICATOR


INPUT OUTPUT INPUT OUTPUT

D1 D0 LO B A Q B A Q

LO LO

LO HI

HI LO

HI HI

2. Open the circuit effects: For the circuit shown in Fig. 4-4, set input B to HI and record the

effects of the following on the output:

Q (input A= HI) =____________________

Q (input A= LO) =____________________

Q (input A= open circuit) =____________________

Part V. IC Logic Gates

1. Use one gate from each IC listed above and obtain the truth table of the gate using the

positive and negative logic. Refer to appendix B for pin configuration of each IC. Never

reverse the polarity of the supply voltage.

2. Open circuit effects: for the 74LS00 IC, set one input pin of the gate open and record the

effects of the following on the output:

OUTPUT (other input = HI) = _______________

OUTPUT (other input = LO) = _______________

OUTPUT (other input = open circuit) = _______________

36


________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

CONCLUSION:

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

When you have completed the entire above, have your laboratory instructor sign below:

37

QUESTIONS:

1. What will be the resulting logic operations if we connect the output of the circuit in fig.4-2

to the input of the circuit in figure 4-1? Show the truth table of the combined circuits.

2. Draw the equivalent circuit of a NOR gate using diode-transistor logic.

3. When you need only one gate, which is more economical to use, discrete devices or IC’s?

4. What will be the resulting output of a 74LS32 gate if you apply power to the IC without

applying any signal to its input?

5. Using one 74LS00 IC, draw the circuit that can perform the logic operation of a two-input

OR-gate.

6. What is a universal gate? Give two examples.


38

EXPT. NO.5: EXCLUSIVE-OR (XOR) GATES

OBJECTIVES: 1. To verify the operation of an XOR Gates.

2. To use an XOR Gate as a controlled inverter

3. To demonstrate the use of an XOR Gate in controlling a lamp from two

different locations.

SUGGESTED READINGS: Discussion about XOR Gate, Digital Computer Electronics by

Malvino & Brown, pp.37-43; Digital Design by Mano, pp. 59, 142-148.

REQUIRED SKILLS: To proceed smoothly, the student must be familiar with the use of DTL-

05 or any similar digital trainer.

MATERIALS REQUIRED:

Description Qty.

Digital trainer 1

IC: 74LS86 1

LED 1

Resistors: 330Ω 1

10KΩ 1

Transistor: 9013 1

Bread boarding wire 1 set

WARNING:

1. Do all with power OFF.


3. Never reverse the polarity of the power supply to prevent damage to the

IC.

Refer to appendix B for the IC’s and other components’ pin

configurations.

PROCEDURE:

Part 1. XOR Basic Operation

1. With power switch OFF, construct the circuit as shown in Fig, 5-1.

Fig. 5-1:

39

2. Turn the power ON and verify the circuit operation. Record the result in Table 5-1.

Table 5-1: Table for Step #2.

3. From the result recorded in Table 5-1, derive the Boolean equation of the circuit of Fig.

5-1.

4. Turn the power off and construct the circuit as shown in Fig. 5-2.

Fig. 5-2:

5. Turn the power switch ON, verify the circuit operation and record the results in Table 5-2.

6. Construct the circuit as shown in Fig. 5-3. Verify the circuit operation and record the

results in Table 5-3.

Fig. 5-3:

DATA SWITCHES OUTPUT

D1 D0 L0

LO LO

LO HI

HI LO

HI HI

40

Table 5.2: Table for step #5

CONTROL

SWITCH DATE SWITCHES LOGIC INDICATORS

K0 D3 D2 D1 D0 1.3 1.2 1.1 1.0

LO LO LO LO LO

HI LO LO LO LO

LO LO LO LO HI

HI LO LO LO HI

LO LO LO HI LO

HI LO LO HI LO

LO LO LO HI HI

HI LO LO HI HI

LO LO HI LO LO

HI LO HI LO LO

LO LO HI LO HI

HI LO HI LO HI

LO LO HI HI LO

HI LO HI HI LO

LO LO HI HI HI

HI LO HI HI HI

LO HI LO LO LO

HI HI LO LO LO

LO HI LO LO HI

HI HI LO LO HI

LO HI LO HI LO

HI HI LO HI LO

LO HI LO HI HI

HI HI LO HI HI

LO HI HI LO LO

HI HI HI LO LO

LO HI HI LO HI

HI HI HI LO HI

LO HI HI HI LO

HI HI HI HI LO

LO HI HI HI HI

HI HI HI HI HI

41

Table 5-3: Table for Step #6


________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

CONCLUSION:

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________


____________________________________

DATA SWITCHES OUTPUT

(ON/OFF) D1 D0

LO LO

LO HI

HI LO

HI HI

42

QUESTIONS:

1. Draw the equivalent logic circuit of Fig. 5-1 using AND & OR Gates. Assume that the

complements of D0 & D1 are available.

2. In Fig. 5-2, what is the function of K0?

3. Modify the circuit of fig. 5-3 to control the LED (ON/OFF) by the three digital data D0,

D1 & D2.

4. What electromechanical device can be added to the circuit of fig. 5-3 to practically

control the ON & OFF of a 220-Vac incandescent bulb two different locations?

5. Give two other applications of the XOR-gate.


43

EXPT. NO.6: DIGITAL IC FAMILIES

OBJECTIVES: 1. To determine by experiment the basic characteristics of TTL and CMOS

IC’s.

2. To verify the operation and applications of open collector and three- state

gates.

SUGGESTED READINGS: Discussions on digital ICs’ fan-in/fan-out, noise margin. Valid

HIGH and LOW voltage level, propagation delay, and other electrical ratings

found on a device data sheet. Digital Computer Electronics by Malvino &

Brown, pp.48-58; Digital Design by Mano, pp.62-67.

REQUIRES SKILLS: To proceed smoothly, the student must be familiar with the used of the

digital trainer and be able to understand a device databook.

MATERIALS REQUIRED:

Description Qty.

Digital tester 1

Multitester 1

ICs: 74LS04 2

74LS125 1

74LS07 1

74HC04 1

Resistors, ¼ W: 4.7KΩ 1

47KΩ 2

Trimmer resistor: 500Ω 1

Ceramic capacitor 20pF 2

Bread boarding wire 1 set

WARNING:

1. Do all writing or any change in writing with the power OFF unless otherwise

specified in the procedure.


3. Never reverse the polarity of the power supply to prevent the damage to the IC.

Refer to Appendix B for the IC’s and the other components’ pin configuration.

PROCEDURE:

Part 1 Noise Margin

1. Construct the circuit as shown in Fig. 6-1.

2. Adjusting the trimmer resistor VR, set VI to 2.0V and record the measured output

voltage V2 under the column 𝑉𝑜𝐻 of Table 6-1.

Set VI to 0.8V and record the measured output voltage V2 under the column of 𝑉𝑜𝐿

of the table 6-1.

44

Fig. 6-1:


VI V2

𝑉𝑇𝐻 𝑉𝐼𝐿 𝑉𝑂𝐻 𝑉𝑂𝐿

2.0 V xxx Xxx

xxx 0.8V xxx

3. Using the given 𝑽𝑰𝑯 and 𝑽𝑰𝑳 and recorded the 𝑽𝒐𝑯 and𝑽𝑶𝑳of the table- 6-1, determine the

high level and low-level noise margin of a circuit when the output of an LSTTL device is

used to drive another LSTTL device. Refer to Fig.6-2 in determining the noise margin of a

circuit and write your answers on the spaces provided below.

Fig. 6-2: Signals for evaluating noise margin.

Noise margin for LSTTL to LSTTL logic:

Low-level noise margin: 𝑉𝑁𝐿 = ____________

High-level noise margin: 𝑉𝑁𝐻 = ____________

45

4. Replace the 74LS04-TTL inverter gate of Fig. 6-1 with a 74HC04-CMOS inverter gate and

determine the noise margin for CMOS to CMOS logic using using the same steps used on

LSTTL logic. However, refer to table 6-2 for the setting of VI and recoer the responsive

measured voltage under 𝑉𝑂𝐻 and 𝑉𝑂𝐿 of column V2.

Table 6-2: table foe step #4

VI V2

𝑉𝑇𝐻 𝑉𝐼𝐿 𝑉𝑂𝐻 𝑉𝑂𝐿

70%𝑉𝐷𝐷 xxx Xxx

xxx 30%𝑉𝐷𝐷 xxx

Note: 𝑉𝐷𝐷 refers to the supply voltage of a CMOS device.

Noise Margin for CMOS to CMOS logic:

Low-level noise margin: 𝑉𝑁𝐿 = ____________

High-level noise margin: 𝑉𝑁𝐻 = ____________

Part 2: Fan-in/Fan-out

5. Refer to the data sheets of the 74LS04 TTL-inverter and the 74HC04 CMOS-inverter (or

appendix C) and complete Table 6-3.

Table 6-3: Table foe step 5

Driving

device

Parameter Number of loads given

𝐼𝑂𝐿 (mA) 𝐼𝑂𝐻 (µA) 𝐼𝐼𝐿 (mA) 𝐼𝐼𝐻 (µA) 74LSXX 74HCXX

74LS04

74HC04

Part 3: OPEN COLLECTOR GATES


Fig. 6-3:

46

7. Set D0 specified below and record the output voltage for each setting.

D0= LO : Vo = ___________________

D0= HI : Vo = ___________________

8. Add a 1-k-ohm resistor between the =5V terminal and the output terminal of the gate in

Fig.6-3. Set D0 as specified below and record the output voltage for each setting.

D0= LO : Vo = ___________________

D0= HI : Vo = ___________________


Fig. 6-4:

10. Using positive logic, derive the truth table and the logic function of the circuit in Fig. 6-4.

Use Table. 6-4.

Table. 6-4.: Table for step #10.

Part 4: Three-State Gates

11. Construct the circuit as shown in Fig.6-5. Verify the circuit operation and complete

Table 6-5.

Fig. 6-5:

INPUT

D1 D0

OUTPUT

L0

LO LO

LO HI

HI LO

HI HI

47

Table 6.5: Table for step #11

Part 5: Propagation Delay (optional)


Fig. 6-6.

13. Set the oscilloscope to dual mode and adjust the volts/div. and time/div. setting for proper

display of the input and output waveforms.

14. Determine the total propagation delay from the input of the first inverter to the output of the

sixth inverter during the upswing (𝑡𝑃𝐿𝐻 And again during the downswing 𝑡𝑃𝐻𝐿 of the pulse.

INPUT OUTPUT

ENABLE

(K0)

DATA

(D0) L0

LO LO

LO HI

HI LO

HI HI

48

15. Compute the propagation delay of each gate using the formula below.

𝑡𝑃𝐿𝐻 per gate =𝑡𝑜𝑡𝑎𝑙 𝑡𝑃𝐿𝐻

𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑔𝑎𝑡𝑒𝑠

𝑡𝑃𝐻𝐿 per gate =𝑡𝑜𝑡𝑎𝑙 𝑡𝑃𝐻𝐿

𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑔𝑎𝑡𝑒𝑠

𝑡𝑃𝐿𝐻 per gate = _________________

𝑡𝑃𝐻𝐿 per gate = _________________


____________________________________________________________________________

____________________________________________________________________________

____________________________________________________________________________

____________________________________________________________________________

____________________________________________________________________________

____________________________________________________________________________

____________________________________________________________________________

____________________________________________________________________________

____________________________________________________________________________

____________________________________________________________________________

____________________________________________________________________________

____________________________________________________________________________

____________________________________________________________________________

____________________________________________________________________________

CONCLUSION:

____________________________________________________________________________

____________________________________________________________________________

____________________________________________________________________________

____________________________________________________________________________

____________________________________________________________________________

When you have completed all of the above, have your laboratory instructor sign below.

_________________________________________

49

QUESTIONS:

1. What is a noise margin?

2. What will be the noise margin of the circuit if the 74LS20 is taking its inut signal from a

device which has a HIGH output voltage of 4.V and a LOW output voltage of 0.2V?

3. Can we use the 74LS04 as a driver to LED indicator with the current through the LED

limited to 10 mA? Why?

4. How many 74LS10 inputs can be connected to a 7400 output?

5. Can we connect directly connect the output of TTL logic device to the input of a CMOS

device provided they are both using +5V supply? Why?

6. What type of TTL device is usully used as an interface between a TTL logic IC and a

CMOS logic IC?

7. What are the states that a three-state gate exhibits?

8. How many standard TTL inverter gates should be connected to produce a delay of 0.242

microseconds?


50

EXPT NO. 7: BOOLEAN FUNCTION FORMS

OBJECTIVE: To introduce the four standard Boolean function forms, namely: sum of minterm

(SAO) product of maxterm (SOA), Standard-AND-OR-invert (SAOI), and

Standard OR-AND-LNVERT (SOAI).

SUGGESTED READINGS: Canonical and standard Boolean expressions, duality theorem, and

Boolean minimization. Digital Computer Electronics by malvino & Brown,

pp.23-25, 33-36, 64-70; Digital Design by Mano, pp. 49-58, 67-68, 88-98.

REQUIRED SKILLS: To proceed smoothly, the student must be familiar with the use DTL-05

or any similar digital trainer.

Materials required:

Description Qty.

digital trainer 1

IC: 74LS10 2

74LS27 3

74LS260 1


WARNING:

1. Do all wiring or any change in wiring with the power OFF unless otherwise




Refer to Appendix B for the IC’s and other components’ pin configurations.

PROCEDURE:

1. Convert the function F=AC + AB to a standard truth table (column F) as given in

Table 7-1.

51

Table 7-1: Boolean Functions Forms

INPUT OUTPUT

C B A F SAO SOA SOAI

1

2

3

4

5

6

7

2.Write the F in the Boolean function form given below and draw the logic diagram using the

basic gates on the space provided below:

A. F(SAO)

52

B. F(SAOI)

C. F(SOA)

53

D. (SOAI):

3. Verify the circuit implementation for each form in step #2 by completing the data in Table 7-1.

4. Draw the circuit implementation of function F in the SAO form using the available NAND

gates IC (see materials required) only. Assume that all the complements are available.

5. Construct the circuit implementation of step #4 and test if it allows the data under column SAO

of Table 7-1.

6. Draw the circuit implementation of function F in the SAOI from using the available NOR gates

IC (see materials required. Assume that all the complements are available.

54

7. Construct the circuit implementation of step #4 and test if it follows the data under column

SOAI of Table 7-1.


________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

CONCLUSION:

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________


______________________________

QUESTIONS:

1.] Express the function given in step #1 in

a. sum of minterm notation

b. product of maxterm notation

2.] How do you call the logical product of variables and complements that produces a high

output for a given input condition?

55

3.] A majority function is generated in a combinatorial logic circuit when the output is equal

to 1 of the input variables have more 1s than 0s. The output is 0 otherwise. Design a

three-input majority function by following the steps and conditions given below:

1. Derive the truth table.

2. Express the function in the SAO form.

3. Implement the function using only NAND gates. Assume that all the complements

are available.


56

EXPT. NO 8: SIMPLIFICATION OF BOOLEAN FUNCTIONS

OBJECTIVE: To simplify Boolean functions by Karnaugh-mapping (K-mapping).

SUGGESTED READINGS: Boolean Minimization using K-mapping techniques up to four

variable functions. Digital Computer Electronics by Malvino & Brown,

pp. 70-77; Digital Design by Mano, pp 72-82.



MATERIALS REQUIRED:

Description Qty.

Digital trainer 1

IC’s: 74LS00 2

74LS10 1

74LS20 1


WARNING:


otherwise specified in the procedure.

2. Make sure you are using the correct supply voltage specified.


Refer to appendix B for the IC’s and other components’ pin configurations.

PROCEDURE:

Part 1: Logic Diagram Implementation

1. Obtain the truth table of the circuit shown in Fig. 8-1 by completing column F1 of

Table 8-1.

Table 8-1:

INPUT OUTPUT

X Y Z F1 L0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

57

Fig. 8-1: Logic Diagram to be simplified.

2. Obtain the Boolean function, F1, in sum of minterm form. Write your answer on the

space provided below.

F1(X, Y, Z) = ∑(__________)

3. Simplify the obtained Boolean function, F1, from step #2 by K-mapping. In the sum of

products (SOP) form, write the simplified expression of F1, as F2 on the space provided

below.

F2(X, Y, Z) = ______________________

4. Assuming that the complement of each variable (X,Y,Z) is not available; implement the

simplified expression of step #3 using a single 74LS00-QUAD 2-input NAND gate IC.

Draw your circuit implementation on the space provided below.

Circuit implementation of Boolean function F1 using a single 74Ls00-Quad 2-input

NAND gate IC.

58

5. Construct your circuit implementation by connecting the inputs X, Y and Z to Data

Switches D2, D1 and D0 respectively, and the output F2 to the Logic Indicator L0 as

illustrated in the block diagram of Fig 8-2.

6. Test the circuit and record the results by completing the column L0 of Table 8-1.

Fig. 8-2: Block diagram showing where the inputs and output should be connected.

Part 2: Boolean Functions

7. Simplify the two Boolean functions given below by K-mapping. Write the simplified

functions in SOP form on the space provided below.

F1(K, L, M, N) = ∑(0,1,4,5,9,11,13,15)

simplified SOP form of F1(K,L,M,N) = ________________________________

F2(K, L, M, N) = KLN + KLM + LN + KLN + KLM

simplified SOP form of F2(K,L,M,N) = ________________________________

8. Using a minimum number of NAND gates, draw the logic implementation of the

simplified expressions of functions F1 &F2, from step #7, on the space provided below.

Assume that the complement of each variable (K,L,M,N) is not available.

Circuit implementation of the simplified F1 & F2 using a minimum number of NAND

gates.

59

9. Construct and test your simplified circuit from step#8 by connecting the inputs K,L,M,N

to Data Switches D3,D2,D1.D0 and the outputs F1, F2 to Logic Indicators L1, L0,

respectively. Record the results in Table 8-2.

Table 8-2:

where 0 = LO, and 1 = HI


________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

INPUT OUTPUT

K

(D3)

L

(D2)

M

(D1)

N

(D0)

F2

(L1)

F1

(L0)

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

60

CONCLUSION:

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________


_______________________________

QUESTIONS:

1. What does each square on a Karnaugh map represent?

2. Describe the following:

a. pair

b. quad

c. octet

3. Write a procedure on how to use the Karnaugh map to simplify logic circuits.

4. Simplify the following functions by using the Karnaugh map:

a. S= BD + BCD + ABCD

b. Y(ABCD) = sum of minterms (0,2,5,7,10,13)


61

EXPT. NO 9: COMBINATIONAL LOGIC CIRCUITS

OBJECTIVE: To design, construct and test combinational logic circuits using basic gates.

SUGGESTED READINGS: Basic logic gates and Boolean function simplification,

combinatorial logic circuits. Digital Computer Electronics by Malvino &

Brown, pp. 64-75; Digital Design by Mano, pp 72-110 or 72,110-148.



MATERIALS REQUIRED:

Description Qty.

Digital trainer 1

IC’s: 74LS00 2

74LS10 2

74LS20 2

74LS86 1


WARNING:



2. Make sure you are using the correct supply of voltage as specified.


Refer to appendix B for the IC and other components’ pin configurations.

PROCEDURE:

Step-by-Step Design Procedure for the Combinatorial Circuits

1. Go over the Step-by-Step Design Procedure stated below and apply it to design the three

combinatorial circuits described in the given problems.

A. Obtain the truth table of the circuit.

B. Simplify the output function.

C. Draw the circuit diagram using a minimum number of NAND gates.

D. Construct the circuit and test it for proper operation by verifying the input/output

relationship.

2. After testing and verification of your designed combinatorial logic circuit, have your

laboratory instructor check it.

62

PROBLEMS:

Design Problem #1:

Design a combinatorial circuit with four inputs A,B,C and D and one output, F. F is equal

to logic 1 when A = 1, provided that B = 0, or when B = 1 provided that either C or D is

also equal to 1. Otherwise, the output is equal to 0.

Answer to Design Problem #1:

Design Problem #2:

A majority logic is a digital circuit whose output is equal to logic 1 if the majority inputs

are 1s. The output is 0 otherwise. Design and test a three-input majority circuit using

NAND gates with a minimum number of ICs.

Answer to Design Problem #2:

63

Design Problem # 3:

Design, construct and test a circuit that penetrates an even parity bit from four-message

bits. Use gates.

Answer to Design Problem # 3:


_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

64

CONCLUSION:

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________


_________________________________

QUESTIONS:

1. Describe a combinatorial logic circuit.

2. Why do we always use the NAND gates in most combinatorial logic circuits?


65

EXPT. NO 10: MULTIPLEXER

OBJECTIVE: 1. To verify the operation of a multiplexer (MUX).

2. To implement a Boolean function using an MUX (MSI) device.

3. To connect two MUX ICs together to form a digital MUX with a larger

number of inputs.

SUGGESTED READINGS: Discussions on multiplexer’s operation and applications. Digital

Computer Electronics by Malvino & Brown, pp. 58-60; Digital Design by

Mano, pp 72-110 or 72,110-148.



MATERIALS REQUIRED:

Description Qty.

Digital trainer 1

IC’s: 74LS00 1

74LS32 1

74LS153 1


WARNING:






PROCEDURE:

Part 1: Multiplexer Operation

1. 74LS153 IC is a dual 4-line to 1-line multiplexer. Verify its operation by constructing the

circuit shown in Fig. 10-1 and record the results by completing column L0 of Table 10-1.

66

Fig. 10-1: 4-line to 1-line multiplexer experiment circuit

Table 10-1: Truth table of a 4-line to 1-line multiplexer

SELECT LINES ENABLE INPUT DATA OUTPUT

S1

(K1)

S0

(K0)

E

C3

(D3)

C2

(D2)

C1

(D1)

C0

(D0)

DATA

Y

LOGIC

INDICATOR

LO

x x 1 x x x x HI-Z

0 0 0 x x x 0 0

0 0 0 x x x 1 1

0 1 0 x x 0 x 0

0 1 0 x x 1 x 1

1 0 0 x 0 x x 0

1 0 0 x 1 x x 1

1 1 0 0 x x x 0

1 1 0 1 x x x 1

Note: x means don’t care

HI-Z means high impedance

Part 2: Multiplexer as a Universal Logic Circuit

2. For a given function F, F = AB + AB, implement the logic circuit using the two different

circuits shown in Fig. 10-2a and Table 10-2b. Verify that the circuits produce the same

output. Record the results in table 10-2a and Table 10-2b.

Fig. 10-2a: Logic circuit implementation of the given Function F of step #2 using discrete

NAND gates only.

67

Fig. 10-2b: Logic circuit implementation of the given Function F of step #2 using discrete a

74LS153 multiplexer IC.

Part 3: Multiplexer Expansion

The block diagram of Fig, 10-3 shows the expansion of 2 four-line to 1-line

multiplexers to an 8-line to 1-line multiplexer. Realize the given block diagram by

constructing the circuit shown in Fig. 10-4. Verify the circuit operation by completing

the data on Table 10-3.

Table 10-2a: Table for step #2,

logic circuit implementation

using NAND gates

INPUT OUTPUT

B

(D1)

A

(D0) LO

0 0

0 1

1 0

1 1

Table 10-2b: Table for step #2, logic

circuit implementation using

NAND gates

INPUT OUTPUT

B

(D1)

A

(D0) LO

0 0

0 1

1 0

1 1

68

Fig. 10-3: Block diagram for MUX expansion.

Fig. 10-4: Experimental circuit for MUX expansion.

69

Table 10-1: Truth table of a 4-line to 1-line multiplexer

SELECT LINES INPUT DATA OUTPUT

K2 K1 K0 D7 D6 D5 D4 D3 D2 D1 D0 L0

0 0 0 x x x x x x x 0

0 0 0 x x x x x x x 1

0 0 1 x x x x x x 0 x

0 0 1 x x x x x x 1 x

0 1 0 x x x x x 0 x x

0 1 0 x x x x x 1 x x

0 1 1 x x x x 0 x x x

0 1 1 x x x x 1 x x x

1 0 0 x x x 0 x x x x

1 0 0 x x x 1 x x x x

1 0 1 x x 0 x x x x x

1 0 1 x x 1 x x x x x

1 1 0 x 0 x x x x x x

1 1 0 x 1 x x x x x x

1 1 1 0 x x x x x x x

1 1 1 1 x x x x x x x

Note: For the select line “K2”, 1 = +5V and 0 = GND.


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70

CONCLUSION:

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_________________________________

QUESTIONS:

1. Describe a digital multiplexer.

2. What is another term for MUX??

3. An 8-line to 1-line MUX has inputs A, B and C connected to the select inputs S2, S1 and

S0, respectively. The data inputs, I0 and I7 are as follows: I1 = I2 = I7 = 0; I3 = I5 = 1;

and I6 = D. Determine the Boolean function that the MUX implements.

4. A 74LS152 is an 8-line to 1-line MUX. However, it cannot be used to produce an MUX

with 16 input lines. Why?

5. Draw the circuit showing hot two 72LS151 (8-input MUX) ICs can be connected to

produce a 16-input MUX.


71

EXPT. NO 10: DECODER AND DEMULTIPLEXER

OBJECTIVE: 1. To verify the operation of a decoder and a demultiplexer (deMUX).

2. To connect a decoder and a deMUX together to form a larger decoder

circuit

3. To implement a Boolean function using a deMUX MSI device and NAND

gates.

SUGGESTED READINGS: Topics about the basic operation and applications of MSI devices

such as decoder and demultiplexer. Digital Design by Mano, pp 166-170.

REQUIRED SKILLS: To proceed smoothly, the student must be familiar with the use of digital

trainer and be able to read and interpret a device data sheet.

MATERIALS REQUIRED:

Description Qty.

Digital trainer 1

IC’s: 74LS00 1

74LS139 1

74LS86 1


WARNING:





PROCEDURE:

Part 1: Decoder/Demultiplexer Operation

1. Construct the circuit as shown in Fig. 11-1. Verify the circuit operation and record the results

in Table 11-1.

Fig. 11-1:

72

Table 11-1: Truth Table of a decoder with enable input (step #1)

2. Construct the circuit as shown in Fig. 11-2. Verify the circuit operation and record the results

in Table 11-2.

Fig. 11-2: Experimental circuit for decoder/de MUX operation

Table 11-2: Truth table of demultiplexer (Step #2)

INPUT OUTPUT

ENABLE SELECT

LINES LOGIC INDICATORS

K0 D1 D0 L3 L2 L1 L0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

INPUT OUTPUT

SELECT LINES DATA LOGIC INDICATORS

K1 K0 D1 L3 L2 L1 L0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

73

Part 2: Decoder Expansion

3. Construct a 3-o-8 line decoder using two 2-to-4 line decoders of the 74LS139 as shown in

Fig. 11-3. Test the validity of the given circuit and record the results in Table 11-3.

Fig. 11-2: Decoder Expansion


Part 3: Implementation of Boolean Function using a Decoder

4. For the given function F = AB + AB, construct and test each logic implementation given

in Fig. 11-4a, -4b and -4c. Record the results by completing Table 11-4.

INPUT OUTPUT

ENABLE SELECT

LINES

LOGIC INDICATORS

K0 D1 D0 L3 L2 L1 L0 L0 L0 L0 L0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Fig. 11-4a:

74

CONCLUSION: ______________________________________________________________________________

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________________________

QUESTIONS:

1. Describe a digital multiplexer.

2. What is another term for MUX?

3. An 8-line to 1-line MUX has inputs A, B and C connected to the select inputs S2, S1 and

S0 respectively. The data inputs, I0 trough I7 are as follows: I1 = I2 = I7 = 0; I3 = I5 = 1;

I6 = D. Determine the Boolean function that the MUX implements.

4. A 74LS152 is an 8-line to 1-line MUX. However, it cannot be used to produce an MUX

with 16 input lines. Why?

5. Draw the circuit showing how to 74LS151 (8-line MUX) ICs can be connected to

produce a 16-input MUX.


75

EXPT. NO. 11: DECODER AND DEMULTIPLEXER

OBJECTIVES: 1. To verify the operation of a decoder and a demultiplexer (deMUX).

2. To connect a decoder and a deMUX together to form a larger decoder

circuit.

3. To implement a Boolean function using deMUX MSI device and NAND

gates.

SUGGESTED READINGS:

Topics about the basic operation and applications of MSI devices such as

decoder and demultiplexer. Digital Design by Mano, pp. 166-170.

REQUIRED SKILLS:

To proceed smoothly, the student must be familiar with the use of a digital

trainer and be able to read and interpret a device datasheet.

MATERIALS REQUIRED:

Description Qty.

Digital Trainer 1

ICs: 74LS00 1

74LS139 1

74LS86 1

Breadboarding Wire 1 set

WARNING:

1. Do all wiring with power off.


3. Never reverse the polarity of the power supply to prevent damage on the IC,

Refer to Appendix B for the ICs and other components’ pin configuration.

PROCEDURE:

Part 1: Decoder/Demultiplexer Operation

1. Construct the circuit as shown in the Fig. 11-1. Verify the circuit operation and record the

results of Table 11-1.

76

Fig, 11-1:

Table 11-1: Truth table of a decoder with enable input (step #1)

INPUT OUTPUT

ENABLE SELECT LINES LOGIC INDICATORS

K0 D1 D0 L3 L2 L1 L0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

2. Contract the circuit as shown in Fig. 11-2. Verify the circuit operation and record the

results in Table 11-2.

Fig. 11-2: Experimental circuit for decoder/deMUX operation

SELECT LINES

ENABLE

OUTPUTS

LOGIC INDICATORS

SELECT LINES

ENABLE

LOGIC INDICATORS

OUTPUTS

77


INPUT OUTPUT

SELECT

LINES DATA LOGIC INDICATORS

K1 K0 D1 L3 L2 L1 L0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Part 2: Decoder Expansion

3. Construct a 3-to-8 line decoder using two 2-to-4 line decoder of the 74LS139 as shown in

Fig. 11-3. Test the validity of the given circuit and record the results in Table 11-3.

Fig. 11-3:

LOGIC INDICATORS

LOGIC INDICATORS

OUTPUTS

SELECT LINES

78

Table 11-3: Truth Table of a 3-to-8 line decoder (step #3)

INPUT OUTPUT

SELECT LINES LOGIC INDICATORS

K0 D1 D0 L3 L2 L1 L0 L0 L0 L0 L0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Part 3: Implementation of Boolean Function using a Decoder

4. For the given function F = AB + AB, construct and test each logic implementation given

in Fig. 11-4a, -4b and -4c. Record the results by completing Table 11-4.

Fig. 11-4a:

Fig. 11-4b:

LOGIC INDICATOR

OUTPUT

INPUT DATA

INPUT DATA

OUTPUT

LOGIC INDICATOR

79

Fig. 11-4c:

Table 11-4: Truth table for the function F (step #4)


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INPUT OUTPUT

B A F LOGIC

INDICATORS

D1 D0 L0 LO LO

0 0

0 1

1 0

1 1

INPUT DATA

OUTPUT

LOGIC INDICATOR

80

CONCLUSION:

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______________________________________________________________________________


________________________

QUESTIONS:

1. What is the difference between a decoder and a demultiplexer?

2. A 74LS138 is a 3-to-8 line decoder demultiplexer IC. Use two 74LS138s to produce a 4-

to-16 line decoder.

3. Write a step-by-step procedure on how to implement a Boolean function using a decoder

and NAND gates.

4. A combinational circuit is defined by the following two Boolean functions. Design the

circuit with a 74LS138 and NAND gates.

F1 = XYZ + XZ

F2 = XYZ + XY

F3 = XYZ + XY

ANSWERS TO QUESTION:

81

EXPT. NO. 12: ARITHMETIC CIRCUITS

OBJECTIVES: 1. To construct and verify the operation of a half-adder circuit.

2. To construct and verify the operation of a half-subtractor circuit.

3. To construct and verify the operation of a full-adder circuit.

4. To verify the operation of a 4-bit binary full-adder IC 74LS83.

5. To construct and test a 4-bit binary parallel adder-subtractor circuit using one

74LS83 and one 74LS86.

SUGGESTED READINGS: Topics covering half-adder, full-adder, parallel-adder,

adder/subtartor. Digital Computer Electronics by Malvino & Brown, pp. 79-

89; Digital Design by Mano, pp. 116-123, 154-163.

REQUIRED SKILLS: To proceed smoothly, the students must be familiar, with the use of

DTL-05 or any similar digital trainer, and be able to read and interpret the TTL

databook.

MATERIALS REQUIRED:

Description Qty.

Digital trainer 1

ICs: 74LS08 1

74LS86 1

74LS83 1


WARNING:

1. Do all wiring or any change in wiring with power OFF unless otherwise



3. Never reverse the polarity of the power supply to prevent damage on the IC.

Refer to appendix B for the ICs pin configuration.

PROCEDURE:

Part 1: Half-adder

1. Construct the half-adder circuit in Fig. 12-1. Test the logical operation by completing the

date in Table 12.1.

82

Fig. 12-1 Logic Diagram of a half-adder circuit

Table 12-1: Truth table for a half-adder circuit

Part2: Half-subtractor

2. Construct the half-subtractor of Fig. 12-2. Test the logical operation by completing the

data in Table 12-2.

Fig. 12-2: Logic diagram of a half-subtractor circuit

INPUT OUTPUT

D1 D0 CARRY

(L1)

SUM

(L0)

0 0

0 1

1 0

1 1

OUTPUTS INPUT DATA

OUTPUTS

INPUT DATA

MINUEND

SUBTRAHEND

83

Table 12-2: Truth table for a half-subtractor circuit

Part 3: Full-adder

3. Construct the full-adder of Fig. 12-3. Test its logical operation by completing the data in

Table 12-3.

Fig. 12-3: Logic diagram of a full-adder circuit

Table 12-3: Truth table for a full-adder circuit

INPUT OUTPUT

D2 D1 D0 CARRY

(L1)

SUM

(L0)

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

INPUT OUTPUT

A

(D1)

B

(D0)

BORROW

(L1)

DIFFERENCE

(L0)

0 0

0 1

1 0

1 1

84

Part 4: 4-Bit Parallel Adder

4. Construct the logic diagram of Fig. 12-4. Test its arithmetic operation by completing the

data in Table 12-4.

Fig. 12-4: 4-bit parallel adder using a 74LS83 MSI device

Table 12-4: 4-bit parallel adder using a 74LS83

INPUT OUTPUT

CARRY IN DATA GROUP B DATA GROUP A CARRY-OUT SUM

K0 D7 D6 D5 D4 D3 D2 D1 D0 L4 L3 L2 L1 L0

0 0 0 0 0 0 0 0 0

0 0 0 0 1 0 0 0 0

0 0 0 0 1 0 0 0 1

1 1 1 1 0 0 0 0 0

1 1 1 1 0 0 0 0 1

Part 5: 4-Bit Binary Adder and Subtractor using 74LS83 MSI

5. Construct the logic diagram of Fig. 12-5. Verify its arithmetic operation by performing

the following operations in binary. Record the results by completing the data in Table

12-5.

9 + 5, 9 – 5

9 + 9, 9 – 9

9 + 15, 9 – 15

DATA

GROUP A

DATA

GROUP B

CARRY - IN

85

Fig. 12-5: Binary adder and subtractor using 74LS83 and 74LS86 ICs

Table 12-5: Simple arithmetic operation using 74LS83

Add/Subtract

K0

ARTIHMETIC

OPERATION

(A± B)

OUTPUT

Carry/Borrow Sum/Difference

L4 L3 L2 L1 L0

0 9+5

0 9+9

0 9+15

1 9-5

1 9-9

1 9-15


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DATA

GROUP B

ADD / SUBTRACT

DATA

GROUP A

CARRY / BORROW

SUM / DIFFERENCE

86

CONCLUSION:

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________________________

QUESTIONS:

1. What is the main difference between a half-adder and a full-adder?

2. Is the logic circuit that adds 4-bits a full-adder?

3. What is the function of the XOR gates in the circuit of Fig. 12-5?

4. What method does the circuit of Fig. 12-5 apply to subtract binary numbers?


87

EXPT. NO. 13: BASIC FLIP-FLOPS

OBLECTIVES: To construct and investigate the operation of various flip-flop circuits and

devices.

SUGGESTED READINGS: Introduction to sequential circuits, basic memory cell, types of

flip-flop, triggering of flip-flops, IC flip-flops. Digital Computer Electronics

by Malvino & Brown, pp. 90-102, Digital Design by Mano, pp. 202-218.

REQUIRED SKILLS: To proceed smoothly, the students must be familiar with the use of

DTL-05 or any similar digital trainer, and be able to read and interpret the

TTL databook.

MATERIALS REQUIRED:

Description Qty.

Digital Trainer 1

ICs: 74LS00 1

74LS02 1

74LS04 1

74LS10 1

74LS74 1

74LS76 1

Resistors: 1k 2

Breadbording wire 1 set

WARNING:




3. Never reverse the polarity of the power supply to prevent damage on the IC.

Refer to appendix B for the ICs pin configuration.

PROCEDURES:

Part 1: NAND RS Latch

1. Construct the NAND RS Latch of Fig. 13-1.

88

Verify the logical property of the NAND RS Latch by completing the data in Table 13-1.

Fig. 13-1: NAND RS Latch

Table 13-1: Truth table for NAND RS Latch

INPUT OUTPUT

S R

Q

(L0)

Q

(L1)

1 1

0 1

1 0

0 0

Part 2: NOR RS Latch

2. Construct the NOR RS latch of Fig. 13-2 and verify its logical property by completing

the data in Table 13-2.

Fig. 13-2: NOR RS Latch

89

Table 13-2: Truth Table for NOR RS Latch

INPUT OUTPUT

S R

Q

(L0)

Q

(L1)

1 1

0 1

1 0

0 0

Part 3: Clocked RS Flip-Flop

3. Construct the logic diagram of Fig. 13-3. Verify its logical property by completing the

data in Table 13-3. Take note of the effect of CLOCK on the output.

Fig. 13-3: Clocked RS Flip-Flop

Table 13-3: Truth table of a clocked RS Flip-Flop

INPUT OUTPUT

S R CLOCK

Q

(L0)

Q

(L1)

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

CLOCK

90

Part 4: D Flip-Flop

4. Construct the logic diagram of Fig. 13-4. Verify the logical property of the D Flip-Flop

by completing the data in the Table 13-4. Take note of the effect of CLOCK on the

output.

Fig. 13-4: Clocked D Flip-Flop

Table 13-4: Truth table of clocked D flip-flop

INPUT OUTPUT

D CLOCK

Q

(L0)

Q

(L1)

1 1

0 1

1 0

0 0

Part 5: IC type Dual JK Flip-Flop

5. Construct the experimental circuit of Fig. 13-5 and verify its truth table given in Table

13-5.

CLOCK

91

Fig. 13-5: 74LS76 IC type Dual JK flip-flop

Table 13-5: Truth table of the 74LS76 Dual JK flip-flop

INPUT OUTPUT

CLOCK PRESET CLEAR J K Q Q L1 L0

x x x x x 1 0

x x x x x 0 1

x x x x x 1 1

0 0 0 0 q q

1 1 0 1 1 1

0 0 1 0 0 0

1 1 1 1 q q

Note: means clock transition from HIGH to LOW level.

Part 6: IC type Dual D-type Flip-Flop

6. Construct the experimental circuit of Fig. 13-6 and verify its truth table given in Table

13-6.

Fig. 13-6: 74LS74 dual D-type flip-flop

92

Table 13-6: Truth table of the 74LS74 dual D-type flip-flop

INPUT OUTPUT

CLOCK PRESET CLEAR D Q Q L1 L0

x 0 1 x 1 0

x 1 0 x 0 1

x 0 0 x 1 1

1 1 1 1 0

1 1 0 0 1

0 1 1 x q q

1 1 1 x q q

Note: means clock transition from LOW to HIGH level.


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CONCLUSION:

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93

QUESTIONS:

1. What is race condition?

2. Is a flip-flop a bi-state device? Why?

3. Do all available flip-flops have two complementary outputs?

4. What is the difference between a level-triggered and an edge-triggered device?

5. What is a T flip-flop? Draw the circuit implementation of a flip-flop using a 74LS76 IC.

6. The output of a flip-flop can be cleared or set automatically upon initial application of

power to the circuit. Draw the circuit to show how to initially clear the output of the

74LS76 flip-flop IC upon application of power to it by adding resistor and capacitior.


94

EXPT. NO. 14: 8-BIT LATCH

OBJECTIVE: To verify the operation the operation of an 8-bit latch using 74LS373.

SUGGESTED READINGS: Discussion about latches and tri-state gates. Digital Computer

Electronics by Malvino & Brown, pp. 95-98; Digital Design by Mano, pp.

207-208.

REQUIRED SKILLS: To proceed smoothly, the student must be familiar with the use of DTL-

05 or any digital trainer.

MATERIALS REQUIRED:

Description Qty.

Digital trainer 1

IC: 74LS373 1


WARNING:



3. Never reverse the polarity of the power supply to prevent damage on the

IC. Refer to Appendix B for the IC’s and other components in pin

configurations.

PROCEDURE:

1. With power OFF, construct the circuit as shown in Fig. 14-1.

Fig. 14-1:

2. Set all the DATA (D7-D0) and CONTROL (K1, K0) switches to LO before applying power

to the circuit.

95

3. Apply power to the circuit and record the output states of the logic indicators in Table 14-1.

4. Change the DATA (D7-D0) switch settings to 10101010 and record the resulting logic

indicator output in the Table 14-1.

Table 14-1: table for step #4

STEP

NO.

INPUT OUTPUT

CONTROL

SWITCHES DATA SWITCHES LOGIC INDICATORS

K1 K0 D7 D6 D5 D4 D3 D2 D1 D0 L7 L6 L5 L4 L3 L2 L1 L0

3 0 0 0 0 0 0 0 0 0 0

4 0 0 1 0 1 0 1 0 1 0

5 0

1 0 1 0 1 0 1 0

6 1 0 1 0 1 0 1 0 1 0

7 0 0 1 0 1 0 1 0 1 0

8 1

1 1 0 0 0 1 1 0

9 0 0 1 1 0 0 0 1 1 0

Note: means momentary HIGH state.

5. Using the same setting of DATA switches as in step 4, set the CONTROL switch K0

momentary, to H1 and record the resulting logic indicator output in Table 14-1.

6. Then set the CONTROL switch K1 to H1 and record the results in Table 14-1.

7. Return the CONTROL switch K1 to L0 and record the results in the Table 14-1.

8. Again, set the CONTROL switch K1 to H1, then change the DATA (D7-D0) switches to

11000110 and set the CONTROL switch K0 momentary to H1. Record the results in Table 14-1.

9. Set the CONTROL switch K1 to L0 and record the results in Table 14-1.

10. Set the DATA switches (D7-D0) to any combination and observe what happens to the output

display by the logic indicator.

11. Repeat step # 10 with the CONTROL switch K0 set to H1.

96


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CONCLUSION:

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________________________________

QUESTIONS:

1. Describe the functions of the two input pins G and OC of the 74LS373.

2. What specific type of triggering does the 74LS373 used?

3. Can we tie respective inputs of two or more 74LS373 as in the so called bus sharing?

How about the outputs? Why?

4. In the Signetics TTL Data Manual, the 74LS373 is described as an “octal transparent

latch with 3-state outputs” while the 74LS374 is described as an “octal D flip-flop

with 3-state outputs”. Can we always use the 74LS374 as a substitute for 74LS373 and

vice versa? Why?


97

EXPT. NO. 15: ASYNCHRONOUS OR RIPPLE COUNTERS

OBJECTIVES: 1.To construct and test a 4-bit binary ripple counter using flip-flop ICs.

2. To construct and test a BCD ripple counter using flip-flop ICs.

3. To construct and test a 4-bit binary ripple counter using 74LS93.

4. To construct and test a BCD ripple counter using 74LS93.

SUGGESTED READINGS: Design and construct of ripple counters and their characteristics,

divide-by-n counters and frequency dividers. Digital Computer Electronics

by Malvino & Brown, pp. 110-120; Digital Design by Mano, pp. 272-277.


digital trainer and an oscilloscope, and be able to read and interpret the TTL,

data book.

MATERIALS REQUIRED:

Description Qty.

Digital trainer 1

Oscilloscope 1

ICs: 74LS00 1

74LS93 1

74LS76 2

74LS08 1

Breadboarding wires 1 set

WARNING:





Refer to Appendix B for the IC’s and other components’ pin configuration.

PROCEDURE:

Part 1: 4-Bit Binary Ripple Counter using Flip-flop ICs

1. Construct the circuit as shown in Fig. 15-1. Clear the counter’s output by referring to the

function table shown in Table 15-1.

2. Set the CLK output to approximately 1 Hz and verify the circuits count sequence by

completing the data in Table 15-2.

98

Fig. 15-1: 4-bit ripple counter using flip-flops

Table 15-1: Function table of the circuits of Fig. 15-1 and Fig. 15-2

Note: x means don’t care.

means CLK transition from HIGH to LOW level.

3. Set clock frequency to 500Hz and measure the frequency of all the outputs Q1, Q2, Q4

and Q8 using an oscilloscope. Record your answers on the spaces provided below.

Output Frequency

Q8 = _________

Q4 = _________

Q2 = _________

Q1 = _________

INPUT

FUNCTION START/STOP CLEAR CLK

x 0 x clear output

1 1

count up

0 1

no change

99

Table 15-2: Count Sequence for counter of step #2

Part 2: BCD ripple counter using flip-flop ICs

4. Construct the circuit as shown in Fig.15-2. Verify its count sequence by repeating steps

#1 and #2; however, record the data in Table 15-3.

Fig. 15-2: BCD ripple counter using flip-flop ICs

Q8

(L3)

Q4

(L2)

Q2

(L1)

Q1

(L0)

DECIMAL

EQUIVALENT

100

Table 15-3: Count Sequence for the counter of step #4

Q8

(L3)

Q4

(L2)

Q2

(L1)

Q1

(L0)

DECIMAL

EQUIVALENT

Part 3: 4-Bit Binary Ripple Counter using 74LS93 IC

5. Construct the circuit of Fig. 15-3.

Fig. 15-3: 4-bit binary ripple counter using 74LS93 IC

6. Clear counter by momentarily switching K0 to a H1 condition. Verify its count sequence

by repeating step #2; however, record the data in Table 15-4.

7. Set clock frequency to 500 Hz and measure the frequency of all the outputs Q1, Q2, Q4

and Q8 using an oscilloscope. Record your results on the spaces provided below.

Output Frequency

Q8 = _________

Q4 = _________

Q2 = _________

Q1 = _________

101

Table 15-4: Count Sequence for the counter of step 6

Part 4: BCD Ripple Counter using 74LS93 IC

8. Construct the circuit of Fig. 15-4. Repeat step #6 and record your results in Table 15-5.

Fig. 15-4: BCD ripple counter using 74LS93 IC.

Q8

(L3)

Q4

(L2)

Q2

(L1)

Q1

(L0)

DECIMAL

EQUIVALENT

102

Table 15-5: Count Sequence for the counter of step #8

Q8

(L3)

Q4

(L2)

Q2

(L1)

Q1

(L0)

DECIMAL

EQUIVALENT


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________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

CONCLUSION:

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

When you have completed all of the above, have your laboratory sign below:

____________________________

103

QUESTIONS:

1. Basically, each can JK flip-flop in the circuit of Fig. 15-1 is configured as ______flip-

flop.

2. Referring to the results of step #3, what is the function of each stage of JK flip-flop in the

circuit of Fig. 15-1?

3. How many T flip-flop are needed to generate a 4-Hz clock signal from a clock source of

256 Hz?

4. A divide-by-6 counter divides the input clock’s frequency by 6. Draw the circuit showing

how a 74LS93 ripple counter IC can be used to construct a divide-by-6 counter.

5. A real-time clock can be constructed by cascading ripple counters. From a 1-Hz clock

source, determine the numbers of divide-by 10 and divide-by-6 counters needed to

construct a real-time clock. Draw its block diagram.


104

EXPT. NO. 16: SYNCHRONOUS COUNTERS

OBJECTIVES: 1. To construct and test a 4-bit binary synchronous counter using flip-flop ICs.

2. To construct and test a BCD synchronous counter using flip-flop ICs.

3. To verify the operation of 74LS193-presettable 4-bit binary up/down

synchronous counter IC.

4. To construct and test a BCD synchronous counter using 74LS193 IC and

NAND gate.

SUGGESTED READINGS: Discussions on construction and analysis of synchronous counters

with up/down count sequence and parallel loading.

REQUIRED SKILLS: To proceed smoothly, the student must be familiar with the use of the

digital trainer, and be able to read and interpret the TTL data book.

MATERIALS REQUIRED:

Description Qty.

Digital trainer 1

ICs: 74LS76 2

74LS193 1

74LS08 1

74LS10 1


WARNING:

1. Do all wiring or any change in wiring with power OFF unless



3. Never reverse the polarity of the power supply to prevent damage

on the IC. Refer to Appendix B for the IC’s and other components

pin configurations.

PROCEDURE:

Part 1: 4-Bit Binary Synchronous Counters using Flip-flop IC’s

1. Construct the circuit as shown in Fig. 16-1. Clear the counters output by referring to the

function table shown in Table 16-1.

2. Set the CLK output to approximately 1 Hz and verify the circuits count sequence by

completing the data in Table 16-2.

105

Fig. 16-1: 4-bit binary synchronous counter using flip-flops

Table 16-1: Functions table of the circuits of Fig. 16-2

INPUT

FUNCTION START/STOP

(K1)

CLEAR

(K0)

CLK

x 0 x Clear output

1 1

Count up

0 1

No change


Means CLK transition from HIGH to LOW level.

106

Table 16-2: Count Sequence for counter of step #2

Part 2: BCD Synchronous Counter using Flip-flop ICs

3. Construct the circuit as shown in Fig. 16-2. Verify its count sequence using the same

function table shown in Table 16-1, and record the results in Table 16-3.

Table 16-3: Count sequence for the counter of step #3

Q8

(L3)

Q4

(L2)

Q2

(L1)

Q1

(L0)

DECIMAL

EQUIVALENT

Q8

(L3)

Q4

(L2)

Q2

(L1)

Q1

(L0)

DECIMAL

EQUIVALENT

107

Fig. 16-2: BCD synchronous counter using flip-flop ICs

Part 3: Functional Operation of 74LS193 IC

4. Construct the circuit of Fig. 16-3.

Fig. 16-3: 4-bit binary synchronous counter using the 74LS193 IC counter

5. Verify the function table of the 74LS193 IC counter given in Table 16-4. Adjust the

CLK frequency for an easy monitoring of its count sequence. Record its count-up

sequence that starts from 0000 in Table 16-5.

108

Table 16-4: Function table of the 74LS193 IC counter

INPUT FUNCTIONS

CLR

(K0)

LOAD

(K1)

UP

(CLK)

DN

(CLK)

1 x x x Clear counter output

0 0 x x Load input data

0 1

NC Count up

0 1 NC

Count down

Note: x means don’t care.

NC means no connection.

Means CLK transition from LOW to HIGH level.

Table 16-5: Count-up sequence of the 74LS193 circuit of step #5

Q8

(L3)

Q4

(L2)

Q2

(L1)

Q1

(L0)

DECIMAL

EQUIVALENT

Part 4: 74LS193 IC Counter Applications

6. Construct the circuit of Fig. 16-4. Using the functions table of Table 16-4, verify the

circuit operation and record your results in Table 16-6.

109

Fig. 16-4: 74LS193 IC application circuit as a BCD counter

Table 16-6: Count Sequence for the counter circuit of step #7

Q8

(L3)

Q4

(L2)

Q2

(L1)

Q1

(L0)

DECIMAL

EQUIVALENT


________________________________________________________________________

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________________________________________________________________________

________________________________________________________________________

110

CONCLUSION:

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________


___________________________

QUESTIONS:

1. What do you mean by synchronous clocking?

2. What is decade counting?

3. Why is the 74LS193 described as presettable?

4. Referring to the TTL Data Manual, what single IC can we use to implement the BCD

counter circuit of Fig. 16-4?

5. Draw the circuit that implements a mod-12 counter using 74LS193 and external gates.


111

EXPT. NO. 17: SHIFT REGISTERS

OBJECTIVE: To verify the different modes of operation of a shift register using a 4-bit

universal shift register IC – 74LS194.

SUGGESTED READINGS: Shift registers types, operations and applications. Digital Computer

Electronics by Malvino & Brown, pp. 106-110; Digital Design by Mano, pp.

257-271.

REQUIRED SKILLS: The students must be familiar with the use of digital trainer and be able

to read and interpret a device function table.

MATERIALS REQUIRED:

Description Qty.

Digital trainer 1

ICs: 74LS194 1


WARNING:




3. Never reverse the polarity of the power supply to prevent any damage to

the IC. Refer to Appendix B for the IC’s and other components pin

configurations.

PROCEDURE:

Part 1: Parallel Loading

1. Study the functions table of the 74LS194 IC shown in Table 17-1 and construct the

circuit as shown in Fig. 17-1. Do not disconnect this circuit after you are through with

this part. You will be using this circuit all throughout the experiment.

2. Verify its parallel load operation using the data given in Table 17-2 and record your

results under the OUTPUT column. Take note that the CLK is manually controlled by

the DATA Switch D7. You should set the required CONTROL and DATA inputs given

in Table 17-2 before activating the said CLK (D7).

112

Fig17-1: Shift register using 74LS194 IC

DATA &

CONTROL

SWITCHES NOTE:

D3, D2, D1, D0 = PARALLEL INPUT DATA (D, C, B, A)

L3, L2, L1, L0 = PARALLEL OUTPUT DATA (QD, QC, QB,

QA)

L0 = SHIFT LEFT SERIAL DATA OUTPUT

L3 = SHIFT RIGHT SERIAL DATA OUTPUT

D5 = SHIFT RIGHT SERIAL DATA INPUT (SR)

D4 = SHIFT LEFT SERIAL DATA INPUT (SL)

D6 = CLEAR INPUT (CLR)

D7 = MANUAL CLOCK INPUT (CLK)

K1-K0 = MODE SELECT INPUTS (S1-S0)

Table 17-1: Function Table of 74LS194IC

OPERATING

MODE

INPUT OUTPUT

CONTROL SIGNALS SERIAL

DATA PARALLEL DATA PARALLEL DATA

CLK CL

K

S

1 S0

DS

L

DS

R A B C D QA QB QC QD

Reset 0 L X X X x X x X x L L L L

Hold

H l l X X X X X X qA qB qC qD

Parallel load

H L h X X dA dB dC dD qA qB qC qD

Shift left

H h l X l X X X X QB qC qD L

H l l X h X X X X qB qC qD H

Shift right

H l h l X X X X X L qA qB qC

H l h H X x X x X H qA qB qC

Note: H = HIGH voltage level

L = LOW voltage level

h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition.

l = LOW voltage level one setup prior to the LOW-to-HIGH clock transition.

X = don’t care

d (q) = lower case letter indicates the state of the referenced input(output) one setup

time prior to the LOW-to-HIGH clock transition

= LOW-to-HIGH clock transition

113

Table 17-2: Parallel load mode

CLK

NO.

INPUT OUTPUT


DATA PARELLEL DATA PARELLEL DATA

CLK

D7

CLK

D6

S1

K1

S0

K0

DSR

D5

DSL

D4

A

D0

B

D1

C

D2

D

D3

QA

L0

QB

L1

QC

L2

QD

L3

1 X L X X X x X X X X

2

H h h X X h l h l

3

H h h X X l h l h

4

H l l X X l l h h

5

H h h X X l l h h

6

H h h x X h h l l

Note: means momentary HIGH state of D7

See note below Table 17-1 about other variables.

3. Verify its shift left operation using the data given in Table17-3 and record your results under

the OUTPUT column. As in part 1, you should set the required CONTROL and DATA inputs

before activating the CLK (D7).

Part 2: Shift Left Operation

Table 17-3: Shift left Mode

CLK

NO.

INPUT OUTPUT


DATA PARALLEL DATA PARALLERL DATA

CLK

D7

CLK

D6

S1

K1

S0

K0

DSR

D5

DSL

D4

A

D3

B

D2

C

D1

D

D0

QA

L0

QB

L1

QC

L2

QD

L3

1

H h h X X l h l h

2

H l l X X X X X X

3

H h l X l X X X X

4

H h l X l X X X X

5

H h l X l X X X X

6

H h l X l X X X X

7

H h h X X h l h l

8

H h l X h X X X X

9

H h l X h X X X X

10

H h l X h X X X X

11

H h l x h X X x X

Note: means momentary HIGH state of D7.


114

Part 3: Shift Right Operation

4. Verify its shift right operation using the data given in Table 17-4 and record your results

under the OUTPUT column. As in part 1, you should set the required CONTROL and DATA

inputs before activating the CLK (D7).

Table 17-4: Shift Right Mode

CLK

NO.

INPUT OUTPUT


DATA PARALLEL DATA PARALLEL DATA

CLK

D7

CLK

D6

S1

K1

S0

K0

DSR

D5

DSL

D4

A

D0

B

D1

C

D2

D

D3

1

H h h x X h l h l

2

H L l x X x x x x

3

H H l l X x x x x

4

H H l l X x x x x

5

H H l l X x x x x

6

H H l l X x x x x

7

H H H x X l h l h

8

H H l h X x x x x

9

H H l h X x x x x

10

H H l h X x x x x

11

H H l h x x x x

Note: means momentary HIGH state of D7.



________________________________________________________________________

115

CONCLUSION:


_________________________________

QUESTIONS:

1. Define the following : PISO SIPO

PIPO SISO

2. What is a controlled shift register?

3. Why is a 74LS194 IC described as a universal shift register?

4. Can we consider a shift register a storage register?

5. Give at least two applications of a shift register.


116

EXPT. NO. 18: MEMORY DEVICES

OBJECTIVES: 1. To verify the behavior of a random access memory (RAM) unit and its

Storage capability using a 4×4 file register IC (74LS670).

2. To construct and test a read only memory (ROM) circuit using a

decoder IC and diodes.

3. To expand the memory location of a RAM device

4. To use a memory device to implement a Boolean function in

combinational logic design.

SUGGESTED READINGS: Topics converting RAM? ROM devices, file registers,

combinational logic design. Digital Computer Electronics by Malvino

&Brown, pp. 130-137: Digital Design by Mano,pp. 180-186,289-299.

REQUIRED SKILLS: The student must be familiar with the use of a digital trainer and be able

to read and interpret a device function table.

MATERIALS REQUIRED:

Description Qty.

Digital Trainer 1

IC’s: 74LS86 1

74LS138 1

74LS670 2

Diodes: IN4148 7

Resistors: 4.7KΩ 4

Breadboarding wire 1set

WARNING:

1. Do all wiring or any change in wiring with the power OFF unless otherwise specified

in the procedure.


3. Never reverse the polarity of the power supply to prevent damage on the IC. Refer to

Appendix B for the IC’s and other component’s pin configurations

PROCEDURE:

Part 1: RAM Functional Operation

1. Connect the circuit as shown in the Fig. 18-1 and verify its function table, shown in Table

18-1, by writing and reading the data in the corresponding memory location give in Table

18-2.

2. Ask your instructor to check that you have already stored the data given in Table 18-2.

117

FIG. 18-1: RAM Experimental Circuit

DATA

LINE LOGIC

INDICATIONS

ADDRESS

LINE

ENABLE

Table 18-1: 74LS670 function tables; read and write mode

A. Write Mode:

OPERATING

MODE

INPUT INTERNAL

LATCHES WE Dn

Write Data L L L

L H L

Data latched H X No change

B. Read Mode:

OPERATING

MODE

INPUT OUTPUT

RE INTERNAL

LATCHES

Qn

Write data L L L

L H H

Data latched H x (z)


Z means high impedance


ADDRESS DATA

B A D3 D2 D1 D0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

118

Part 2: Read Only Memory (ROM)

3. Connect the circuit as shown in Fig.18-2 and verify its function table, shown in Table18-3,

by and reading the stored data in the corresponding memory location given in Table18-4.

Fig.18-2: ROM experimental circuit

Table 18-3: ROM circuit function table

MODE OF

OPERATION

READ

ENABLE

(K0)

OUTPUT

(Q3-Q0)

Read L Content of selected address

Disabled H H

Table 18-4: Table for step #3.

ADDRESS OUTPUT

D2 D1 D0 Q3

(L3)

Q2

(L2)

Q1

(L1)

Q0

(L0)

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

119

Part 3: Memory Expansion

4. Construct the circuit as shown in Fig. 18-3. This circuit also follows the function table

shown in Table 18-1.

5. Verify its operation by writing and reading the data in the corresponding memory

location given in Table 18-5. Do not disconnect the circuit after finishing this part.

You will be using it on the next part of this experiment.

6. Ask your instructor to check that you have already stored the data given in Table 18-5.

Fig.18-3: 4×4 memory device expanded to 8×4

120


ADDRESS OUTPUT

D2 D1 D0 Q3 Q2 Q1 Q0

0 0 0 0 0 0 1

0 0 1 0 0 1 0

0 1 0 0 1 0 0

0 1 1 1 0 0 0

1 0 0 1 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 1 0

Part 4: Boolean Function Implementation

7. Using Table 18-6, derive the truth table of the given Boolean functions below:

F1 (A2, A1, A0) = Σ (3, 5, 7)

F2 (A2, A1, A0) =Σ (2, 5, 6, 7)

F3 (A2, A1, A0) =Σ (1, 4, 7)

F4 (A2, A1, A0) = Σ (0, 1, 3, 6)

8. Implement the Boolean FUNCTIONS GIVEN IN STEP #5 USIG THE

EXPERIMENTAL CIRCUIT OF Fig.18-3 and derive the truth table in Table 18-6.

Assign the four given Boolean functions to the four logic indicators as follows:

F1=L0, F2=L1, F3=L2, F4=L3.

9. Test your implementation and record the results by completing the column under the

logic indicators, L3-L0, in Table 18-6.

Table 18-6: Table for steps #7 to #9

INPUT OUTPUT

A2 A1 A0 FUNCTIONS LOGIC INDICATOR

F4 F3 F2 F1 L3 L2 L1 L0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

121


________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

CONCLUSION:

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________


_____________________________________

122

QUESTIONS:

1. What is a RAM?

2. What are volatile and non-volatile memory devices?

3. Classify the circuits of Fig. 18-2 and fig. 18-2 as volatile or non-volatile.

4. Define the organizational structure of the circuit of Fig. 18-2.

5. What is the difference between the memory capacity and memory organization?


123

4.1 Appendix A: Electrical/electronic Symbols

No. Component Symbol Reference Variable

1 FIXED RESISTOR R

2 TRIMMER RESISTOR VR

3 POTENTIOMETER VR or POT

4 LDR (Light dependent Resistor) LDR

5 THERMISTOR R, TH

6 NON-POLARIZED CAPACITOR C

7 POLARIZED CAPACITOR C

8 INDUCTOR L

9 TRANSFORMER T

10 DIODE D

11 LED D, LED

12 ZENER DIODE D, ZD

13 PHOTODIODE D, PD

124


14 NPN TRANSISTOR B Q

15 PNP TRANSISTOR B Q

16 DARLINGTON Q

TRANSISTOR

17 PHOTOTRANSISTOR Q, PT

18 n-CHANNEL JFET Q

19 P-CHANNEL JFET Q

20 N-CHANNEL DEPLETION Q

TYPE MOSFET

21 p-CHANNEL DEPLETION Q

TYPE MOSFET

22 SCR D, Q, SCR

23 TRIAC Q

24 n-CHANNEL UJT Q

25 p-CHANNEL UJT Q

26 SPEAKER SPK

27 MICROPHONE MIC

125


28 SPST SWITCH SW

29 SPDT SWITCH SW

30 PUSH BUTTON SWITCH SW

NORMALLY OPEN

31 PUSH BUTTON SWITCH SW

NORMALLY CLOSED

32 FUSE F

126

4.2 Appendix B: Component Pin Configurations

I. Digital Integrated Circuits

74LS00 74LS08

74LS02 74LS10

74LS04, 74HC04 74LS20

74LS07 74LS27

127

74LS32 74LS83

74LS47 74LS86

74LS74 74LS125

74LS76 74LS138

128

74LS139 74LS373

74LS153 74LS670

74LS193, 74LS192 74LS260

II. Transistors:

NPN PNP

III. Diode:

129

4.3 Appendix C: Functional Description and Electrical Specifications of Selected

Devices

I Discrete Devices Maximum Rating

Diodes: 1N4148 Switching Signal Diode - 200mA, 100V

1N4000 Rectifier Diode - 1A, 50V

Transistors: 9013 NPN General Purpose 0.625 W, 25V, 0.8A

9012 PNP General purpose 0.625 W, 25V, 0.8A

Relay: SPDT, Coil-6V DC, and Contact-any rating

Resistors: 1/4 Watt, 5% tolerance

II. Integrated Circuits Functional Description

7407 - Hex Buffer/driver (open collector)

74C04 - Hex Inverter (CMOS version)

74LS00 - Quad 2-Input NAND Gate

74LS02 - Quad 2-Input NOR Gate

74LS04 - Hex Inverter

74LS08 - Quad 2-Input AND Gate

74LS10 - Triple 3-Input NAND Gate

74LS20 - Dual 4-Input NAND Gate

74LS27 - Triple 3-Input NOR Gate

74LS32 - Quad 2-Input OR Gate

74LS47 - BCD to 7-Segment Decoder/Drivers

74LS76 - Dual JK Flip-Flop

74LS83 - 4-Bit Full Adder

74LS86 - Quad 2-Input XOR Gate

74LS93 - 4-Bit Binary Ripple Counter

74LS125 - Quad 3-State Buffer

74LS139 - Dual 1-of-4 Decoder/Demultiplexer

74LS153 - Dual 4-Line to 1-Line Multiplexer

74LS192 - Presettable BCD Decade Up/Down Counter

74LS193 - Presettable 4-Bit Binary Up/Down Counter

74LS194 - 4-Bit Bidirectional Universal Shift Register

74LS373 - Octal Transparent Latch with 3-State Outputs

74LS670 - 4x4 Register File (3-State)

74LS260 - Dual 5-Input NOR Gate

130

III. Important DC Characteristics of 74LS Family

Parameter

Input HIGH voltage Vih = 2.0V minimum

LOW voltage Vil = 0.8V maximum

Input Output LOW voltage Vol = 0.5V maximum

Output HIGH voltage Voh = 2.7V minimum

Output HIGH current Ioh = -400mA maximum

Input HIGH current Iih = 20uA maximum

Input LOW current Iil = -0.4mA maximum

Output LOW current Iol = -8.0mA maximum

Output short circuit current Ios = -100mA maximum

IV. Important DC Characteristics of 74HC04

Parameter

Input HIGH voltage Vih = 70 Vdd minimum

Input LOW voltage Vil = 30 Vdd

Output LOW voltage Vol = 0.1V maximum

Output HIGH voltage Voh = 97 Vdd minimum

Input HIGH current Iih = 0.1uA maximum

Input LOW current Iil = -0.1uA maximum

Output HIGH current Ioh = -200uA maximum

Output LOW current Iol = 4mA maximum

131

4.4 Appendix D: Steps in Troubleshooting Electrical/Electronic Equipment

Troubleshooting is the process of narrowing down the possible reasons for a failure until you

pinpoint the cause. Effective troubleshooting follows a systematic approach in solving a

problem. Troubleshooting any electrical/electronic circuit or equipment requires that you:

1. KNOW THE SYSTEM. This means understanding the detailed operation of the system

by knowing:

- The supposed sequence of events.

- What components cause each event.

Knowing the system's detailed operation may require studying its block-schematic- and

even wiring-diagram.

A block diagram shows the different sections that compromise the whole system.

A schematic diagram shows the electrical/electronic circuits used in each block/section

of the whole system.

A wiring diagram is like a simple road map that shows where the components are, and

where the wires go between them.

2. INVESTIGATE THE SYMPTOMS OF FAILURE. The symptoms of failure will

often indicate which section of the machine is in real trouble. This step usually provides

you with important clue in fixing the defective machine.

3. LIST PROBABLE CAUSES OF TROUBLE. Based on what you know and the clues

uncovered, list the probable or likely causes of trouble. Usually, this can be done in your

head. But if a machine is complicated, it helps to write it down.

4. ELIMINATE POSSIBILITIES SYSTEMATICALLY. This means performing tests

on the machine in logical order. Usually, you are trying to eliminate a whole group of

possibilities with one test, narrowing down the choices as quickly as possible until you

are left with actual cause of trouble.

5. DETERMINE THE ROOT CAUSE OF TROUBLE. Getting the equipment running

again is often not the end of the troubleshooting procedure. You may be able to discover

why the trouble happened, and do something to keep it from happening again.

132

4.5 Appendix E: Application Circuits

TTL COMPATIBLE LOGIC PROBE

133

SHORT CIRCUIT PROTECTION

In this circuit the diodes D1, D2 and D3 are configure as an AND gate. When any of the

three voltage regulator's output goes LOW, due to a short circuit from any of the regulator's

positive terminal and the ground, the diode-AND-gate's output goes LOW and turn the

transistors Q1 and Q2 off, thus cutting the power applied to the three voltage regulators

LIGHT ACTIVATED TOGGLE SWITCH

The circuit can be used to practically turn on/off any electrical device by just triggering the

phototransistor (FPT-100) with a visible light. It can be used as an on/off remote control or in an

alarm circuit. Trimmer resistor VR is used to adjust the circuit's sensitivity to light intensity.

134

TRANSISTOR SWITCH/DRIVER

The circuit is very useful in multiplexing LED 7-Segment or Matrix display

LED SEQUENTIAL

135

4.6 Appendix F: Suggested Laboratory Grading System

LABORATORY GRADE 40%

Attendance 10%

Attitude 15%

Projects 35%

Expt. Average 40%

Total 100%

DETAILS OF LABORATORY GRADE:

EXPERIMENTAL GRADE

Group Preliminary Report Grading System: 50%

Group Performance 20%

Accuracy of Data 35%

Speed of Performance 20%

Circuit Construction 25%

Total 100%

Individual Report Grading System: 50%

Individual Performance

Attitude 15%

Punctuality 15%

Observation 20%

Analysis 25%

Conclusion 25%

Total 100%

Experiment Grade: 100%

EXPERIMENT AVERAGE = Sum of Experiment Grade divided by the number of

experiments performed

PROJECT GRADE

Presentation 15%

Overall Appearance 15%

Functionality 20%

Oral Defense 30%

Documentation 10%

Total: 100%

136

4.7 Appendix G: Summary of Experiment Grades

EXPT.NO GRADE

1 -

2 -

3 -

4 -

5 -

6 -

7 -

8 -

9 -

10 -

11 -

12 -

13 -

14 -

15 -

16 -

17 -

18 -

AVERAGE

137

4.8 Appendix H: Student’s Accountability Record

Student’s Name: _______________________________________________________________

Item

No. Particulars Qty. Date Remarks

Verified by:

Cleared by:

138

4.9 Appendix I: Resistor Color Coding

ece compilation 190

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