복합칩 (sip, mcp, tsv)에서 의test challenge · 2009-06-30 · "복합칩(sip, mcp,...
TRANSCRIPT
"복합칩 (SIP, MCP, TSV)에서의 Test Challenge"
Prepared by MY Cha
Date : 24.June.2009.
미래 사회는 ?어떤 사회 ?
What’s the complex Chip(SoC) ?
What’s the complex Package(SoP) ?
What is SOC and SOP ?
Why System on Package ?
What kind of SIP ?
Stacked or
Side-by-Side
Wirebond or
FlipChip
Package-in-Packageor
Package-on-Package
withDiscreet Passives & TSV
or Integrated Passive Devices
Focused on test solutions for Application complex's
How we Can test for SIP ?
• Increasing product complexity, integration & density challenges cost effective single tester platform capabilities– Mixed signal, RF, Mixed technology– Multi die (Logic,analog/digital/memory)– Higher frequency
• Cost reduction requirements dominate– Yield characterization / test time reduction– Test insertion elimination using advanced data collection
tools– Cheaper cost/unit ATE solution– Handler - multi-site (Mass parallel)
How we Can test for SIP ?
Application Conversion Status
Why we need the Challenge for SIP test ?
Why we need the Challenge for SIP test ?
1. Cost 증가2. Coverage rate 감소3. Higher cost due to multi
process.
1. Equipment cost increase2. Need 2 more test process3. Test time increasing to
multi die test with conversion application
Test process Flow
Fab Process
Wafer out
Optical Wafer inspection
Wafer Sort
Packing
To Assembly site
Ass’y
Logic test
Memory Test
E/L QA for Memory
Return to Ass’y
⊙ 100% testing
⊙ 100% Testing
⊙ Sample plan: AQL 0.1%, A/R=0/1
System Level Test ⊙ 100% Testing (Optional : Based on Customer requirement for Their SiP and SoP)
Package stacking
⊙ Return to assembly after Logic test & Memory test under each tester.⊙To stacking process between top and Bottom package.
To BackendProcess
Back End Process Flow
The “Backend” - after test, other processsteps may be required:
Lead Scan
Baking
Dry Pack
Tape & Reel (Optional)
Pack, Label & Ship
Finished Goods
Semiconductors
FVI (Optional)
FVI L/A
Thank you!