FinFET and other New Transistor Technologies
Chenming HuUniv. of California
Chenming Hu, July 2011
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NY Times news article:
• Intel will use 3D FinFET for 22nm
• Most radical change in decades• There is a competing SOI technology
May 4 2011 NY Times Front Page
Chenming Hu, July 2011
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• TSMC, IBM…new transistors soon
• Since 2001 ITRS shows FinFET and ultra-thin-body UTB-SOI as the two successor MOSFETs
• SOITEC UTB-SOI recently available
• IBM 2009 5nm UTB SOI paper
Other Background Info
Chenming Hu, July 2011
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New MOSFET Structures
Chenming Hu, July 2011
Cylindrical FET
Ultra Thin Body SOI
5
Vt, S (swing) and Ioffare sensitive to Lg &dopant variations.
• high design cost• high Vdd, hence
high power usage
Good Old MOSFET Nearing Limits
Finally painful enough for change.Chenming Hu, July 2011
Power Consumption Problems 1.Not just a chip and package thermal
issue.2.ICs use a few % of world’s electricity
today and • Power per chip is growing.• IC units in use also growing.
3.If power consumption is not reduced, industry future growth is at risk.
Chenming Hu, July 2011
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Want Low Vt and Low Ioff
Need smaller S and less variations of S and Vt
Chenming Hu, July 2011
MOSFET becomes “resistor” at very small L –- Drain competes with Gate to control the channel barrier.
0.0 0.3 0.6 0.910-11
10-9
10-7
10-5
10-3
Drai
n Cu
rrent
, IDS
(A/µ
m)
Gate Voltage, VGS (V)
Size shrink
How Vt Variation & S Got So Bad
LGate
Insulator
Source Drain
Cg
Cd
Gate
or larger Vd
Smaller size
Chenming Hu, July 2011
Reducing EOT is Not Enough
Gate cannot control theleakage current paths
that are far from the gate.
Gate
Source Drain
Leakage Path
Chenming Hu, July 2011
One of Two Ways to Better Vt and SThe gate controls a thin body from more than one side.
Gate
Gate
Source Drain
FinFET body is a thin fin N. Lindert et al., DRC paper II.A.6, 2001
Sour
ce
Dra
in
Fin WidthFin Height
Gate Length
Chenming Hu, July 2011
FinFET- 1999Undoped Body. 30nm etched thin fin. Vt set with gate work-function (SiGe).
X. Huang et al., IEDM, p. 67, 1999
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0 10 20 30 40 50Lg [nm]
ΔV
t [V
]
Vt at 100 nA/μm, Vd = 0.05 V
Fin width: 20 nm
Chenming Hu, July 2011
STI
Gate
SiSTISTI
Gate
SiSTI
State-of-the-Art FinFET on Buk Si20nm Hi PerfC.C. Wu et al., 2010 IEDM
28nm SoC C.C. Yeh et al., 2010 IEDM
Chenming Hu, July 2011
FinFET is “Easy” to Scale
because leakage is well suppressed if Fin thickness =or< Lg
• Thin fin can be made with the same Lg patterning/etching tools.
Chenming Hu, July 2011
Lg = 5 nm
5nm Lg TSMC2004 VLSI Symp
10nm Lg AMD2002 IEDM
3nm Lg KAIST2006 VLSI Symp
Second Way to Better Vt and SUltra-thin-body SOI (UTB-SOI)No leakage path far from the gate.
1.E-12
1.E-10
1.E-08
1.E-06
1.E-04
1.E-02
0 0.2 0.4 0.6 0.8 1
Gate Voltage [V]
Dra
in C
urre
nt [A
/um
]Tsi=8nmTsi=6nmTsi=4nm
Y-K. Choi, IEEE EDL, p. 254, 2000
Gate
Source DrainUTBSiO2
Si
Chenming Hu, July 2011
Most Leakage Flows >5nm Below Surface
Y-K. Choi et al., IEEE Electron Device Letters, p. 254, 2000Chenming Hu, July 2011
Silicon Body Needs to be <Lg/3For good swing and device variation
Y-K. Choi et al., IEEE Electron Device Letters, p. 254, 2000Chenming Hu, July 2011
Y-K. Choi et al, VLSI Tech. Symposium, p. 19, 2001
3nm Silicon Body, Raised S/DUTB-SOI
Chenming Hu, July 2011
State-of-the-Art 5nm Thin-Body SOI
ETSOI, IBM K. Cheng et al, IEDM, 2009
Chenming Hu, July 2011
Both Thin-Body Transistors Provide
• Better swing. • S & Vt less sensitive to Lg and Vd.• No random dopant fluctuation. • No impurity scattering. • Less surface scattering (lower Eeff).
•Higher on-current and lower leakage•Lower Vdd and power consumption•Further scaling and lower cost
Chenming Hu, July 2011
Back-Gate Bias Option
UTB-SOI FinFET
STI
STI
Si
Gate 1Gate 2
Chenming Hu, July 2011
Similarities• 1996: UC Berkeley proposed to DARPA two “25nm Transistors”. Both of them•use body thickness as a new scaling parameter•can use undoped body for high µ and no RDF• 1999: demonstrated FinFET2000: demonstrated UTB-SOI (Ultra-Thin Body)
• Since 2001: ITRS highlights FinFET and UTBSOI• Now: Intel will use Trigate FinFET.
Soitec readies +-0.5nm substrates for UTBSOI• Both FinFET & UTBSOI better than planar bulk!
Chenming Hu, July 2011
Main Differences• FinFET body thickness ~ Lg. Investment by fabsUTBSOI thickness ~1/3 Lg. Investment by Soitec• FinFET has clear long term scalability. UTBSOImay be ready sooner depending on each firm’s readiness with FinFET.• FinFET has larger Ion or can use lower Vdd. UTBSOI has a good back-gate bias option.
STISTI
SiGate 1 Gate 2
UTBSOI
FinFETChenming Hu, July 2011
What May Happen• FinFET will be used at 22nm by Intel and later by more firms through and beyond 10nm.• Some firms may use UTBSOI to gain/protect market at 20 or 18nm if FinFET is not option.
If so, competition between FinFET and UTBSOIwill bring out the best of both.
If not----- back to first bullet.
Chenming Hu, July 2011
Chenming Hu, July 2011
FinFET BSIM Compact Model Verified
FinFET Fabricated at TSMC. Lg = 30 nm-10um
0.0 0.4 0.8 1.20
25µ
50µ
Vd = 1.2V
Vd = 50mV
Lg = 50nm
Drai
n Cu
rrent
(A)
Gate Voltage (V)1p
1n
1µ
1m
0.0 0.4 0.8 1.21p
10p
100pVd = 1.2V
Lg = 50nm
Bulk
Curre
nt (A
)
Gate Voltage (V)
Id-Vd
0.0 0.4 0.8 1.20
25
50Vg = 1.2 - 0.4V
Lg = 50nm
Drai
n Cu
rrent
(µA)
Drain Voltage (V)
Id-Vg Ibulk Id-Vd
Chenming Hu, July 2011
M. Dunga, 2008 VLSI Tech Sym
Chenming Hu, July 2011
Chenming Hu, July 2011
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Reduce all capacitances.
Reduce C
2ddVCf ⋅⋅
Chenming Hu, July 2011
Vacuum-Sheath Interconnect
Etch Stop layer
Metal
Dielectric Beam
Mutual Capacitance : CM
Total Capacitance : CTOTAL
Load Capacitance : CO
CTOTAL ∝ Delay, CM ∝ Crosstalk Noise
J. Park, Electronics Letters, p. 1294, 2009
Chenming Hu, July 2011
Effective k of Vacuum-Sheath Interconnects
No Solution
Bea
m D
iele
ctri
c Con
stan
t
20 30 40 50 60 70 80
Air Percentage (%)
2.25
2.9
3.3
3.6
3.9
1.31.4
1.51.6
1.71.8
1.92.0
2.12.22.3
2.42.5
2.6No Solution
J. Park, Electronics Letters, p. 1294, 2009 Chenming Hu, July 2011
Vacuum Spacer to Reduce CGC
CGCCGOX
Gate
Contacts» CGC<
CGOX : Gate Oxide Capacitance
CGC : Gate-to-Contact Capacitance
Scale Down
CGOX
Chenming Hu, July 2011
OxideSpacer
Vacuum Spacer Self-
aligned contact (SAC)
Inverter Delay, ps
6.15(1)
5.05(0.82)
Inverter switching energy, fJ
24.2(1)
18.8(0.78)
Relative Area 1 0.7
20nm MOSFET comparisonVacuum Spacer Self-Aligned Contact
OxideVacuum
J. Park, IEEE EDL, p.1368, 2009
Chenming Hu, July 2011
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Log
Drai
n Cu
rren
t Id
Gate Voltage Vg
S<60mV/dec
S>60mV/dec
Future Low Voltage Green Transistor
Chenming Hu, July 2011
How to reduce Vdd to 0.15V?
1.Reduce Vdd – Vt to < 0.1V with high-mobility-channel material, or sub-threshold circuits.
2. Reduce Vt to 50mV. Need a device that is free of the 60mV/decade turn-off limit.
Chenming Hu, July 2011
Origin of the 60mV/decade Limit
Leakage current is determined by Boltzmann distribution or 60 mV/decade, limiting MOSFET, bipolar, graphene MOSFET…
So, let electrons go through, not over, the energy barrier semiconductor tunneling or MEMS
Ec
Ev
COX
VG
Source Channel Drain
A potential barrier controls the electron flow.
Chenming Hu, July 2011
Semiconductor Band-to-Band Tunneling: generating electron/hole pairsEC
EV
A known mechanism of leakage current since 1985.
J. Chen, P. Ko, C. Hu, IEDM 1985
Called Gate Induce Drain Leakage (GIDL).
N+ N+ P-
Chenming Hu, July 2011
Abrupt turn-on due to over-lap of valence/conduction bands; adjustable turn-on voltage.
Green Transistor --Simulation
Energy band diagram
Simulated carrier generation rates
Hole flow
Electron flow
N+ Source
P+ Pocket
Gate
P+ Drain
C. Hu, 2008 VLSI-TSA, p.14, April, 2008
N+ P+
Buried Oxide
P+ Pocket
N--
G
DS
Chenming Hu, July 2011
C. Hu, 2008 VLSI-TSA, p.14, April, 2008
Reduce Vdd by Reducing Eg
1E-11
1E-10
1E-09
1E-08
1E-07
1E-06
1E-05
1E-04
1E-03
1E-02
0.0 0.2 0.4 0.6 0.8 1.0
Eg=0.36eV
Eg=0.69eV Eg=1.1eV
Eg=0.36eV, Vdd=0.2V, EOT=5 Å, CV/I=0.42pS
Eg=0.69eV, Vdd=0.5V, EOT=7 Å, CV/I=2.2pS
Eg=1.1eV, Vdd=1V, EOT=10 Å, CV/I=4.2pS
Gate Voltage, VGS (V)
I DS
(µ/µ
m)
Lg=40nm
Simulated impact of Eg scaling
Vdd scales down faster than Eg.C. Hu, 2008 VLSI-TSA, p.14, April, 2008
Chenming Hu, July 2011
Simulated gFET Inverter VTCGood voltage gain at 0.1V
0
50
100
150
200
0 50 100 150 200
VDD: 0.2 V
VDD: 0.15 V
VDD: 0.1 V
Input Voltage, VIN (mV)
Out
put V
olta
ge, V
OU
T(m
V)
.
Chenming Hu, July 2011
C. Hu, 2008 VLSI-TSA, p.14, April, 2008
P+ Source N+ Drain
Ge Substrate
Gate
Si
Gat
e O
xide
Ge tFET
Si-Ge HtFET
~~~~EC
EV
~~~~
~~~~~~~~
Gate
Si Ge
EC offset
Hetero-junction gFET• Strained Si on Ge has 0.18eV “effective tunneling Eg”.
• III-V.
A. Bowonder, Intern’l Workshop Junction Tech., 2008
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• FinFET and UTB-SOI are viable new sub-22nm transistors.
• Different performances, investment costs, wafer costs, scaling barriers.
• Their BSIM SPICE models are available – free
• Capacitance and tunnel gFET are potential opportunities.
Summary
Chenming Hu, July 2011