EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 1
EE247Lecture 10
• Switched-capacitor filters– Switched-capacitor network electronic noise– Switched-capacitor integrators
• DDI integrators• LDI integrators• Effect of parasitic capacitance• Bottom-plate integrator topology
– Resonators– Bandpass filters– Lowpass filters
• Termination implementation• Transmission zero implementation
– Switched-capacitor filter design considerations– Switched-capacitor filters utilizing double sampling technique – Effect of non-idealities
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 2
Summary of last lecture• Continuous-time filters continued
– Various Gm-C filter implementations– Comparison of continuous-time filter topologies
• Switched-capacitor filters– Emulating resistor via switched-capacitor network– 1st order switched-capacitor filter– Switch-capacitor filter considerations:
• Issue of aliasing and how to avoid it– Sample at high enough frequency so that the entire range of
signals including the parasitics are at freqs < fs /2– Use of anti-aliasing prefilters
• Effect of sample and hold
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 3
Switched-Capacitor Network Noise
• During φ1 high: Resistance of switch S1 (Ron
S1) produces a noise voltage on C with variance kT/C (lecture 1- first order filter noise)
• The corresponding noise charge is:
Q2 = C2V2 = C2. kT/C = kTC
• φ1 low: S1 opens This charge is sampled
vIN vOUT
CS1 S2
φ1 φ2
RonS1
C
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 4
Switched-Capacitor Noise
vIN vOUT
CS1 S2
φ1 φ2
RonS2
C
• During φ2 high: Resistance of switch S2 contributes to an uncorrelated noise charge on C at the end of φ2 : with variance kT/C
• Mean-squared noise charge transferred from vIN to vOUT per sample period is:
Q2=2kTC
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 5
• The mean-squared noise current due to S1 and S2’s kT/C noise is :
• This noise is approximately white and distributed between 0 and fs /2 (noise spectra single sided by convention) The spectral density of the noise is:
S.C. resistor noise = a physical resistor noise with same value!
Switched-Capacitor Noise
( )2Q 2 2S ince i then i Qf 2k TCfs B st= → = =
22 2k TCfi B s 4k TCf B sf fs2
2 4k T1 i BSince R then : EQ f C f Rs EQ
= =Δ
= =Δ
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 6
Periodic Noise AnalysisSpectreRF
PSS pss period=100n maxacfreq=1.5G errpreset=conservativePNOISE ( Vrc_hold 0 ) pnoise start=0 stop=20M lin=500 maxsideband=10
SpectreRF PNOISE: checknoisetype=timedomainnoisetimepoints=[…]
as alternative to ZOH.noiseskipcount=large
might speed up things in this case.
ZOH1T = 100ns
ZOH1
T = 100ns
S1R100kOhm
R100kOhm
C1pFC1pF
PNOISE Analysissweep from 0 to 20.01M (1037 steps)
PNOISE1
Netlistahdl_include "zoh.def"ahdl_include "zoh.def"
Vclk100ns
Vrc Vrc_hold
Sampling Noise from SC S/H
C11pFC11pFC11pFC11pF
R1100kOhm
R1100kOhm
R1100kOhm
R1100kOhm
Voltage NOISEVNOISE1
NetlistsimOptions options reltol=10u vabstol=1n iabstol=1psimOptions options reltol=10u vabstol=1n iabstol=1psimOptions options reltol=10u vabstol=1n iabstol=1psimOptions options reltol=10u vabstol=1n iabstol=1p
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 7
Sampled Noise Spectrum
Density of sampled noise including sinc distortion
Sampled noise normalized density corrected for sinc distortion
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 8
Total Noise
Sampled simulated noise in 0 … fs/2: 62.2μV rms
(expect 64μV for 1pF)
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 9
Switched-Capacitor Integrator
-
+
Vin
Vo
φ1 φ2CI
Css
s ignal sampling
s0 I
s0 s I
for f f
f CV V dtinC
Cf Cω
×=
<<
→
= ×
∫
-
+∫ φ1
φ2
T=1/fs
Main advantage: No tuning needed critical frequency function of ratio of capacitors & clock freq.
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 10
Switched-Capacitor Integrator
-
+
Vin
Vo
φ1 φ2CI
Cs
-
+
Vin
Vo
φ1CI
Cs
-
+
Vin
Vo
φ2CI
Cs
φ1
φ2
T=1/fs
φ1 High Cs Charged to Vin
φ2 HighCharge transferred from Cs to CI
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 11
Continuous-Time versus Discrete Time Analysis Approach
Continuous-Time
• Write differential equation• Laplace transform (F(s))• Let s=jω F(jω)
• Plot |F(jω)|, phase(F(jω)
Discrete-Time
• Write difference equation relates output sequence to input sequence
• Use delay operator z -1 to transform the recursive realization to algebraic equation in z domain
• Set z= e jωT
• Plot mag./phase versus frequency
[ ]
( ) ( )
o s i s
1o i
V ( nT ) V . . . . . . . . . .( n 1)T
V z V . . . . . . .Z z−
= −−
=
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 12
Discrete Time Design Flow• Transforming the recursive realization to algebraic
equation in z domain:– Use delay operator z :
s1s1/ 2s1s1/ 2s
nT ..................... 1............. z( n 1)T
.......... z( n 1/ 2 )T............. z( n 1)T
.......... z( n 1/ 2 )T
⎡ ⎤⎣ ⎦⎡ ⎤⎣ ⎦⎡ ⎤⎣ ⎦⎡ ⎤⎣ ⎦
−
−
+
+
→→−→−→+→+
* Note: z = e jωTs = cos(ωTs )+ j sin(ωTs )
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 13
Switched-Capacitor IntegratorOutput Sampled on φ1
φ1 φ2 φ1 φ2 φ1
Vin
Vo
Vs
Clock
Vo1
-
+
Vin
Vo1
φ1 φ2 CI
Cs
φ1
Vo
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 14
Switched-Capacitor Integrator
φ1 φ2 φ1 φ2 φ1
Vin
Vo
Vs
Clock
Vo1
Φ1 Qs [(n-1)Ts]= Cs Vi [(n-1)Ts] , QI [(n-1)Ts] = QI[(n-3/2)Ts]
Φ2 Qs [(n-1/2) Ts] = 0 , QI [(n-1/2) Ts] = QI [(n-3/2) Ts] + Qs [(n-1) Ts]
Φ1 _ Qs [nTs ] = Cs Vi [nTs ] , QI [nTs ] = QI[(n-1) Ts ] + Qs [(n-1) Ts]Since Vo1= - QI /CI & Vi = Qs / Cs CI Vo1(nTs) = CI Vo1 [(n-1) Ts ] -Cs Vi [(n-1) Ts ]
(n-1)Ts nTs(n-1/2)Ts (n+1)Ts(n-3/2)Ts (n+1/2)Ts
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 15
Switched-Capacitor IntegratorOutput Sampled on φ1
sIsI
1s1I
o s o ss sI I inCo s o s sinCC1 1o o inC
CC 1in
C V (nT ) C V C V(n 1)T (n 1)T
V (nT ) V V(n 1)T ( n 1)T
V ( Z ) Z V ( Z ) Z V ( Z )
Vo Z( Z )ZV
⎡ ⎤ ⎡ ⎤⎣ ⎦ ⎣ ⎦
⎡ ⎤ ⎡ ⎤⎣ ⎦ ⎣ ⎦
−−
− −
−
= −− −
= −− −
= −
= − ×
DDI (Direct-Transform Discrete Integrator)
-
+
Vin
Vo1
φ1 φ2 CI
Cs
φ1
Vo
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 16
z-Domain Frequency Response•LHP singularities in s-plane map into inside of unit-circle in z-domain
•RHP singularities in s-plane map into outside of unit-circle in z-domain
•The jω axis maps onto the unit-circle
•Particular values:
– f = 0 z = 1– f = fs/2 z = -1
f = 0
f = fs /2
LHP in s-domain
imag. axis in s-domain z-plane
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 17
z-Domain Frequency Response
• The frequency response is obtained by evaluating H(z) on the unit circle at:
z = e jωT = cos(ωTs) + j sin(ωTs)
• Once z=-1 (fs /2) is reached, the frequency response repeats, as expected
• The angle to the pole is equal to 360° (or 2πradians) times the ratio of the pole frequency to the sampling frequency
(cos(ωTs),sin(ωTs))
2πffS
z-plane
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 18
Switched-Capacitor Direct-Transform Discrete Integrator
1s1I
s 1I
CC 1in
CC 1
Vo z( z )zV
z
−−−
= − ×
= − × −
-
+
Vin
Vo
φ1 φ2CI
Cs
φ1
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 19
DDI IntegratorPole-Zero Map in z-Plane
z -1=0 z = 1on unit circle
Pole from f 0in s-plane mapped to z =+1
As frequency increases zdomain pole moves on unit circle (CCW)
Once pole gets to:z=-1 (f=fs /2)
frequency response repeatsz-plane
f = fs /2
f
f1
1
(z-1)increasing
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 20
DDI Switched-Capacitor IntegratorCI
Ideal Integrator Magnitude Error Phase Error
( )
( )
1s1I
j T / 2s sj T j T / 2 j T / 2I I
sI
sI
C j TC 1in
j jC CC C1
C j T / 2C
C j T / 2C j T
Vo z( z ) , z ezV
e ee1 since : s in 2 je e e
1j e 2 sin T / 2
T / 21 esin T / 2
ωω ω ω
ω
α α
ω
ω
α
ω
ωω ω
−−
−−
−
−
− −
−
−
= − × =
−= × = × =
= − × ×
= − × ×
-
+
Vin
Vo
φ1 φ2CI
Cs
φ1
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 21
DDI Switched-Capacitor Integrator
Example: Mag. & phase error for:1- f / fs=1/12 Mag. error = 1% or 0.1dB
Phase error=15 degreeQintg = -3.8
2- f / fs=1/32 Mag. error=0.16% or 0.014dBPhase error=5.6 degreeQintg = -10.2
CI
-
+
Vin
Vo
φ1 φ2CI
Cs
φ1
DDI Integrator:magnitude error no problemphase error major problem
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 22
5th Order Low-Pass Switched Capacitor Filter Built with DDI Integrators
Example: 5th Order Elliptic FilterSingularities pushed towards RHP due to integrator excess phase
s-planeFine View
jω
σ
Ideal PoleIdeal Zero
s-planeCoarse View
jω
σ
ωs
-ωs DDI PoleDDI Zero
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 23
Frequency (Hz)
Switched Capacitor Filter Build with DDI Integrator
( )ωjH
sf / 2 sf 2fs fContinuous-TimePrototype
SC DDI basedFilter
PassbandPeaking
Zeros lost!
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 24
Switched-Capacitor Integrator Output Sampled on φ2
CI
-
+
Vin
Vo2
φ1 φ2CI
Cs
φ2
Sample output ½ clock cycle earlierSample output on φ2
Vo
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 25
Φ1 Qs [(n-1)Ts]= Cs Vi [(n-1)Ts] , QI [(n-1)Ts] = QI[(n-3/2)Ts]
Φ2 Qs [(n-1/2) Ts] = 0 , QI [(n-1/2) Ts] = QI [(n-3/2) Ts] + Qs [(n-1) Ts]
Φ1 _ Qs [nTs ] = Cs Vi [nTs ] , QI [nTs ] = QI[(n-1) Ts ] + Qs [(n-1) Ts]
Φ2 Qs [(n+1/2) Ts] = 0 , QI [(n+1/2) Ts] = QI [(n-1/2) Ts] + Qs [n Ts]
φ1 φ2 φ1 φ2 φ1
Vin
Vo2
Vs
Clock
(n-1)Ts nTs(n-1/2)Ts (n+1)Ts(n-3/2)Ts
Switched-Capacitor Integrator Output Sampled on φ2
(n+1/2)Ts
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 26
QI [(n+1/2) Ts] = QI [(n-1/2) Ts] + Qs [n Ts]Vo2= - QI /CI & Vi = Qs / Cs CI Vo2 [(n+1/2) Ts] = CI Vo2 [(n-1/2) Ts ] -Cs Vi [n Ts ]Using the z operator rules:
CI Vo2 z1/2 = CI Vo2 z-1/2 - Cs Vi
1 / 2s1I
CC 1in
Vo2 z( z )zV
−−−
= − ×
Switched-Capacitor Integrator Output Sampled on φ2
φ1 φ2 φ1 φ2 φ1
Vin
Vo
Vs
Clock
(n-1)Ts nTs(n-1/2)Ts (n+1)Ts(n-3/2)Ts
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 27
LDI Switched-Capacitor Integrator
( )
( )
1/ 2s1I
j T / 2s e s 1j T j T / 2 j T / 2I I
sI
sI
C j TC 1 zin
C CC C1
CC
CC j T
Vo2 z( z ) , z eV
e e e
1j 2 sin T / 2
T / 21sin T / 2
ωω ω ω
ω
ω
ωω ω
−−
−− − +
−
− −
= − × =
= − × = ×
= − ×
= − ×
CI
Ideal Integrator Magnitude Error
No Phase Error! For signals at frequencies << sampling freq.
Magnitude error negligible
-
+
Vin
Vo2
φ1 φ2CI
Cs
φ2
LDI
LDI (Lossless Discrete Integrator) same as DDI but output is sampled ½clock cycle earlier
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 28
Frequency Warping• Frequency response
– Continuous time (s-plane): imaginary axis– Sampled time (z-plane): unit circle
• Continuous to sampled time transformation– Should map imaginary axis onto unit circle– How do S.C. integrators map frequencies?
12s
S.C. 11
1s2
C zH ( z )C zint
C
C j sin f Tint π
−= −−
= −
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 29
CT – SC Integrator ComparisonCT Integrator SC Integrator
int
s s
CRCf C
τ = =Identical time constants:
Set: HRC(fRC) = HSC(fSC)
⎟⎟⎠
⎞⎜⎜⎝
⎛=
s
SCsRC f
fff ππ
sin
12s
SC 11
1s2 s
C zH ( z )C zint
C
C j sin f Tint SCπ
−= −−
= −
RC1
12 RC
H ( s )s
jf
τ
π τ
= −
= −
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 30
LDI Integration
⎟⎟⎠
⎞⎜⎜⎝
⎛=
s
SCsRC f
fff ππ
sin
• “RC” frequencies up to fs /πmap to physical (real) “SC”frequencies
• Frequencies above fs /π do not map to physical frequencies
• Mapping is symmetric about fs /2 (aliasing)
• “Accurate” only for fRC << fs0 0.1 0.2 0.30
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
fRC /fs
f SC/f s
1/π
Slope=1
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 31
Switched-Capacitor Filter Built with LDI Integrators( )ωjH
Zeros Preserved
Frequency (Hz) 2fs ffsfs /2
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 32
Switched-Capacitor IntegratorParasitic Sensitivity
Effect of parasitic capacitors:
1- Cp1 - driven by opamp o.k.
2- Cp2 - at opamp virtual gnd o.k.
3- Cp3 – Charges to Vin & discharges into CI
Problem parasitic sensitivity
-
+
VinVo
φ1 φ2CI
CsCp3
Cp2
Cp1
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 33
Parasitic InsensitiveBottom-Plate Switched-Capacitor Integrator
Sensitive parasitic cap. Cp1 rearrange circuit so that Cp1 does not charge/discharge
φ1=1 Cp1 grounded
φ2=1 Cp1 at virtual ground
Solution: Bottom plate capacitor integrator
Vi+
Cs-
+ Vo
CI
Cp1
Cp2
φ1 φ2
Vi-
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 34
Bottom Plate Switched-Capacitor Integrator
12
12
1s s1 1I I
s s1 1I I
C Cz zC C1 z 1 z
C Cz 1C C1 z 1 z
−−
− −
−
− −
− −
− −− −
Note: Different delay from Vi+ &Vi- to either output
Special attention needed for input/output connections
Vi+
Cs-
+ Vo
CIφ1 φ2
Vi-
Vi+on φ1
Vi-on φ2
Vo1on φ1
Vo2on φ2
φ1
φ2
Vo2
Vo1
Output/Inputz-Transform
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 35
Bottom Plate Switched-Capacitor Integratorz-Transform Model
12
12
11 1
1 1
z z1 z 1 z
z 11 z 1 z
−−− −
−
− −
− −
−− −
121
z1 z
−
−−
12z−
Input/Output z-transformVi+
Cs-
+ Vo
CIφ1 φ2
Vi-
φ1
φ2
Vo2
Vo1
Vi+
Vi- 12z+ Vo2
Vo1
LDI
s IC C
s IC C−
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 36
LDI Switched-Capacitor Ladder Filter
CsCI
12
1z
1 z
−
−−
-+
+ - + -3
1sτ 4
1sτ 5
1sτ
12z
−
12z
+
12z
+12z
+
12z
−
CsCI
−
CsCI
−CsCI
−CsCI
CsCI
Delay around integrator loop is (z-1/2 . z+1/2 =1) LDI function
12
1z
1 z
−
−−
12
1z
1 z
−
−−12z
−
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 37
Switched-Capacitor LDI Resonator
2s
ω
1s
ω−
C1 1f1 sR C Ceq1 2 2C1 3f2 sR C Ceq3 4 4
ω
ω
= = ×
= = ×
Resonator Signal Flowgraph
φ1 φ2
φ2 φ1
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 38
Fully Differential Switched-Capacitor Resonator
φ1 φ2
φ1 φ2
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 39
Switched-Capacitor LDI Bandpass FilterUtilizing Continuous-Time Termination
0s
ω
0s
ω−
C C3 1f0 s sC C4 2C2Q CQ
ω = × = ×
=
Bandpass FilterSignal Flowgraph
CQ
Vi
Vo-1/QVo2Vi
Vo2
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 40
s-Plane versus z-PlaneExample: 2nd Order LDI Bandpass Filter
σ
jωs-plane z-plane
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 41
Switched-Capacitor LDI Bandpass FilterContinuous-Time Termination
0.1 1 10f0
0
-3dBΔf
Frequency
Mag
nitu
de (d
B)
C1 1f f0 s2 C2f0f Q
C C1 Q1 fs2 C C2 4
π
π
= ×
Δ =
= ×
Both accurately determined by cap ratios & clock frequency
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 42
Fifth Order All-Pole LDI Low-Pass Ladder FilterComplex Conjugate Terminations
•Complex conjugate terminations (alternate phase switching)
Termination Resistor
Termination Resistor
Ref: Tat C. Choi, "High-Frequency CMOS Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, May 1983 (ERL Memorandum No. UCB/ERL M83/31).
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 43
Fifth-Order All-Pole Low-Pass Ladder FilterTermination Implementation
Ref: Tat C. Choi, "High-Frequency CMOS Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, May 1983 (ERL Memorandum No. UCB/ERL M83/31).
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 44
Sixth-Order Elliptic LDI Bandpass Filter
TransmissionZero
Ref: Tat C. Choi, "High-Frequency CMOS Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, May 1983 (ERL Memorandum No. UCB/ERL M83/31).
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 45
Use of T-Network
High Q filter large cap. ratio for Q & transmission zero implementationTo reduce large ratios required T-networks utilized
Ref: Tat C. Choi, "High-Frequency CMOS Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, May 1983 (ERL Memorandum No. UCB/ERL M83/31).
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 46
Sixth Order Elliptic Bandpass FilterUtilizing T-Network
•T-networks utilized for:• Q implemention• Transmission zero implementation
Q implementation
Zero
Ref: Tat C. Choi, "High-Frequency CMOS Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, May 1983 (ERL Memorandum No. UCB/ERL M83/31).
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 47
Switched-Capacitor Resonator
Regular samplingEach opamp busy settling only during one of the two clock phases
Idle during the other clock phase
φ1 φ2
φ2 φ1
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 48
Switched-Capacitor Resonator Using Double-Sampling
Double-sampling:
•2nd set of switches & sampling caps added to all integrators
•While one set of switches/caps sampling the other set transfers charge into the intg. cap
•Opamps busy during both clock phases
•Effective sampling freq. twice clock freq. while opamp bandwidth requirement remains the same
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 49
Double-Sampling Issues
fclock fs= 2fclock
Issues to be aware of:- Jitter in the clock - Unequal clock phases -Mismatch in sampling caps.
parasitic passbands Ref: Tat C. Choi, "High-Frequency CMOS Switched-Capacitor Filters," U. C. Berkeley, Department of
Electrical Engineering, Ph.D. Thesis, May 1983 (ERL Memorandum No. UCB/ERL M83/31).
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 50
Double-Sampled Fully Differential S.C. 6th Order All-Pole Bandpass Filter
Ref: Tat C. Choi, "High-Frequency CMOS Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, May 1983 (ERL Memorandum No. UCB/ERL M83/31).
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 51
Sixth Order Bandpass Filter Signal Flowgraph
γ
1Q
− 0s
ω
inV 1−
0s
ω−
1Q
−0s
ω0s
ω−
0s
ω−0
sω
outV1γ−
γγ−
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 52
Double-Sampled Fully Differential 6th Order S.C. All-Pole Bandpass Filter
Ref: B.S. Song, P.R. Gray "Switched-Capacitor High-Q Bandpass Filters for IF Applications," IEEE Journal of Solid State Circuits, Vol. 21, No. 6, pp. 924-933, Dec. 1986.
-Cont. time termination (Q) implementation-Folded-Cascode opamp with fu = 100MHz used-Center freq. 3.1MHz, filter Q=55-Clock freq. 12.83MHz effective oversampling ratio 8.27-Measured dynamic range 46dB (IM3=1%)
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 53
Effect of Opamp Nonidealities on Switched Capacitor Filter Behaviour
• Opamp finite gain• Opamp finite bandwidth• Finite slew rate of the opamp
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 54
Effect of Opamp Non-IdealitiesFinite DC Gain
Input/Output z-transformVi+
Cs-
+ Vo
CIφ1 φ2
Vi-DC Gain = a
sI s 1
I
1
Cs C C
s C a
o
o a
1H( s ) f
s f
H( s )s
Q a
ωω
≈ −+ ×
−≈
+ ×
⇒ ≈ Finite DC gain same effect in S.C. filters as for C.T. filters
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 55
Effect of Opamp Non-IdealitiesFinite Opamp Bandwidth
Input/Output z-transformVi+
Cs-
+ Vo
CIφ1 φ2
Vi-Unity-gain-freq.
= ft
Ref: K.Martin, A. Sedra, “Effect of the Opamp Finite Gain & Bandwidth on the Performance of Switched-Capacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981.
Assumption-Opamp does not slew (will be revisited)Opamp has only one pole exponential settling
Vo
φ2
T=1/fs
settlingerror
time
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 56
Effect of Opamp Non-IdealitiesFinite Opamp Bandwidth
actual idealIk k 1
I s
I t
I s s
t s
C1 e e ZH ( Z ) H ( Z )
C CC f
where kC C f
f Opamp unity gain frequency , f Clock frequency
π
− − −⎡ ⎤− + ×≈ ⎢ ⎥+⎣ ⎦
= × ×+
→ − − →
Ref: K.Martin, A. Sedra, “Effect of the Opamp Finite Gain & Bandwidth on the Performance of Switched-Capacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981.
Input/Output z-transformVi+
Cs-
+ Vo
CIφ1 φ2
Vi-Unity-gain-freq.
= ft
Vo
φ2
T=1/fs
settlingerror
time
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 57
Effect of Opamp Finite Bandwidth on Filter Magnitude Response
Magnitude deviation due to finite opamp unity-gain-frequency
Example: 2nd
order bandpass with Q=25
fc /ft
|Τ|non-ideal /|Τ|ideal (dB)
fc /fs=1/32fc /fs=1/12
Active RC
Ref: K.Martin, A. Sedra, “Effect of the Opamp Finite Gain & Bandwidth on the Performance of Switched-Capacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981.
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 58
Effect of Opamp Finite Bandwidth on Filter Magnitude Response
Example:For 1dB magnitude response deviation:1- fc/fs=1/12
fc/ft~0.04ft>25fc
2- fc/fs=1/32fc/ft~0.022
ft>45fc
3- Cont.-Timefc/ft~1/700
ft >500fc fc /ft
|Τ|non-ideal /|Τ|ideal (dB)
fc /fs=1/32fc /fs=1/12
Active RC
Ref: K.Martin, A. Sedra, “Effect of the Opamp Finite Gain & Bandwidth on the Performance of Switched-Capacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981.
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 59
Effect of Opamp Finite Bandwidth Maximum Achievable Q
fc /ft
Max. allowable biquad Q for peak gain change <10%
C.T. filters
Oversampling Ratio
Ref: K.Martin, A. Sedra, “Effect of the Opamp Finite Gain & Bandwidth on the Performance of Switched-Capacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981.
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 60
Effect of Opamp Finite Bandwidth Maximum Achievable Q
fc /ft
C.T. filters
Example:For Q of 40 required Max. allowable biquad Q for peak gain change <10%
1- fc/fs=1/32fc/ft~0.02
ft>50fc
2- fc/fs=1/12fc/ft~0.035
ft>28fc
3- fc/fs=1/6fc/ft~0.05
ft >20fcRef: K.Martin, A. Sedra, “Effect of the Opamp Finite Gain & Bandwidth on the Performance of Switched-
Capacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981.
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 61
Effect of Opamp Finite Bandwidth on Filter Critical Frequency
Critical frequency deviation due to finite opamp unity-gain-frequency
Example: 2nd
order filterfc /ft
Δωc /ωc
fc /fs=1/32
fc /fs=1/12
Active RC
Ref: K.Martin, A. Sedra, “Effect of the Opamp Finite Gain & Bandwidth on the Performance of Switched-Capacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981.
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 62
Effect of Opamp Finite Bandwidth on Filter Critical Frequency
fc /ft
Δωc /ωc
fc /fs=1/32
fc /fs=1/12
Active RC
Example:For maximum critical frequency shift of <1%
1- fc/fs=1/32fc/ft~0.028
ft>36fc
2- fc/fs=1/12fc/ft~0.046
ft>22fc
3- Active RCfc/ft~0.008
ft >125fc
C.T. filters
Ref: K.Martin, A. Sedra, “Effect of the Opamp Finite Gain & Bandwidth on the Performance of Switched-Capacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981.
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 63
Sources of Distortion in Switched-Capacitor Filters
• Distortion induced by finite slew rate of the opamp
• Opamp output/input transfer characteristic non-linearity
• Capacitor non-linearity• Distortion incurred by finite setting time of the
opamp• Distortion due to switch clock feed-through
and charge injection
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 64
What is Slewing?
oV
Vi+Vi-
φ2
Cs
-
+
Vin
Vo
φ2CI
Cs
CI
CL
Assumption:Integrator opamp is a simple class Atransconductance type differential pairwith fixed tail current Iss
Iss
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 65
oV
Vi+Vi-
φ2
Cs
CI
CL
Iss
What is Slewing?Io
VinVmax
Imax =Iss
Slope ~ gm
VCs > VmaxOutput current constant Io=Iss Vo ramps up/down Slewing
After Vcs is discharged enough to have: VCs <Vmax Io=gm VCs Exponential or over-shoot settling
Io
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 66
Distortion Induced by Opamp Finite Slew Rate
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 67
Ideal Switched-Capacitor Output Waveform
φ1
φ2
Vin
Vo
Vcs
Clock-
+
Vin
Vo
φ1CI
Cs
-
+
Vin
Vo
φ2CI
Cs
φ2 High Charge transferred from Cs to CI
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 68
Slew Limited Switched-CapacitorOutput Settling
φ1
φ2
Vo-real
Vo-ideal
Clock
Slewing LinearSettling
Slewing LinearSettling
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 69
Distortion Induced by Finite Slew Rate of the Opamp
Ref: K.L. Lee, “Low Distortion Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, Feb. 1986 (ERL Memorandum No. UCB/ERL M86/12).
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 70
Distortion Induced by Opamp Finite Slew Rate
• Error due to exponential settling changes linearly with signal amplitude
• Error due to slew-limited settling changes non-linearly with signal amplitude (doubling signal amplitude X4 error)
For high-linearity need to have either high slew rate or non-slewing opamp
( )( )
( )
o s
o s
2T2ok 2r s
2T2o3 r s
8 sinVHD S T k k 4
8 sinVHD S T 15
ω
ω
π
π
=−
→ =
Ref: K.L. Lee, “Low Distortion Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, Feb. 1986 (ERL Memorandum No. UCB/ERL M86/12).
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 71
Distortion Induced by Opamp Finite Slew Rate Example
-120
-100
-80
-60
-40
-20
1 10 100 1000
HD
3 [d
B]
(Slew-rate / fs ) [V]
f / fs =1/32
f / fs =1/12
Vo =1V V
o =2V
Vo =1V V
o =2V
EECS 247 Lecture 10: SC Filters © 2006 H. K. Page 72
Distortion Induced by Finite Slew Rate of the Opamp
• Note that for a high order switched capacitor filter only the last stage slewing will affect the output linearity (as long as the previous stages settle to the required accuracy)
Can reduce slew limited linearity by using an amplifier with a higher slew rate only for the last stageCan reduce slew limited linearity by using class A/B amplifiers
• Even though the output/input characteristics is non-linear the significantly higher slew rate compared to class A amplifiers helps improve slew rate induced distortion
• In cases where the output is sampled by another sampled data circuit (e.g. an ADC or a S/H) no issue with the slewing of the output as long as the output settles to the required accuracy & is sampled at the right time