Download - CMOS Circuits
CONCORDIAVLSI DESIGN LAB
1
CMOS Circuits
CONCORDIAVLSI DESIGN LAB
2
Combination and Sequential
CONCORDIAVLSI DESIGN LAB
3
Static Combinational Network
PMOSNetwork
NMOSNetwork
Inputs Output
VDDCMOS Circuits
• Pull-up network-PMOS• Pull-down network- NMOS• Networks are complementary to each other• When the circuit is dormant, no current flows between supply lines.• Number of the NMOS transistors (PMOS transistors) equals to the number of the inputs.• Output load is capacitive
CONCORDIAVLSI DESIGN LAB
4
NAND Gates
Transistors in Parallel
(W/L)1 (W/L)2 (W/L)eff
1/Rcheff = (1/Rch1) + (1/Rch2)
WL-----
eff
WL-----
1
WL-----
2+=
Transistors in Series
WL-----
eff
WL-----
1
1– WL-----
2
1–+
1–=
Rcheff = Rch1 + Rch2
(W/L)1
(W/L)2
(W/L)eff
CONCORDIAVLSI DESIGN LAB
5
CMOS NAND GateDC Analysis
Two possible scenarios:1. Both inputs are toggling2. One input is toggling, the other one set high
Assumptions: MP2=MP1=MPMN1=MN2=MNW/L for MP = (W/L)pW/L for MN = (W/L)n
InverterVTC
CONCORDIAVLSI DESIGN LAB
6
Gate Sizing
To obtain equal Rise and Fall time,
Size the series / parallel transistors
to have an equivalent of a single PU or PD
inverter transistor in your design
CONCORDIAVLSI DESIGN LAB
7
Sizing the CMOS Gate
CONCORDIAVLSI DESIGN LAB
8
NAND Gates: Analysis
Scenario #1-Both inputs are togglingL-H > (W/L)eff = 2(W/L)pH-L > (W/L)eff = 1/2(W/L)nKR|NAND = 1/4 KR|INV
Scenario #2- One input is togglingL-H > (W/L)eff = (W/L)pH-L > (W/L)eff = 1/2(W/L)nKR|NAND = 1/2 KR|INV
Vout
Vin
VOH
VOLVx2 Vx1
Vin=Vout
InverterOne input toggling
Two inputs toggling
CONCORDIAVLSI DESIGN LAB
9
NAND Gates: Analysis
VDD
MP1MP2
MN1
MN2
A
B
X
CL
Switching AnalysisScenario #1-Both inputs are togglingtPLH |NAND = 1/2tPLH |INVERTER
tPHL |NAND = 2tPHL |INVERTER
Scenario #2- One input is togglingtPLH |NAND = tPLH |INVERTER
tPHL |NAND = 2tPHL |INVERTER
CONCORDIAVLSI DESIGN LAB
10
NAND Gate: Power Dissipation
VDD
MP1MP2
MN1
MN2
A
B
X
CL
Pac= α.f . C VDD2
A B X 0 0 1 1 0 1 0 1 1 1 1 0
α = P (X=1). P (X=0) assuming A and B have equal probabilities for 1 and 0α = (1/4). (3/4)= 3/16C = CL + C parasitic
CONCORDIAVLSI DESIGN LAB
11
Increasing the inputs
CONCORDIAVLSI DESIGN LAB
12
NOR Gate: Analysis
DC Analysis/ AC Analysis
Two possible scenarios:1. Both inputs are toggling (one is set low)2. One input is toggling, the other one set high
Assumptions: AP2=BP1=MP AN1=BN2=MNW/L for MP = (W/L)pW/L for MN = (W/L)n
Compare with a CMOS inverter: MP/MNKR, and the shift in VTC
Propagation delay tPLH and tPHL
CONCORDIAVLSI DESIGN LAB
13
4 INPUT NOR GateVDD
A
B
C
D
A B C D CL
X
Very slow rise time and rise delays
Could be compensated by increasing of PMOS transistor size.
Implications: Silicon Area Input capacitance
CONCORDIAVLSI DESIGN LAB
14
Practical Considerations 1. Minimize the use of NOR gates2. Minimize the fan-in of NOR gates3. Limit the fan-in to 4 for NAND gates4. Use De morgan’s theorem to reduce the number of fan-in per gate
Example:
F = ABCDEFGH = (ABCD) + (EFGH)
CONCORDIAVLSI DESIGN LAB
15
Complex CMOS Gate
CONCORDIAVLSI DESIGN LAB
16
Reducing Output Capacitance
CONCORDIAVLSI DESIGN LAB
17
Pseudo nMOS
CONCORDIAVLSI DESIGN LAB
18
Pseudo nMOS NAND/NOR Gates
From Lecture #4For acceptable operation
WN=1.5 WP for our Process respecting min WP
CONCORDIAVLSI DESIGN LAB
19
Pseudo nMOS Complex Gates
From Lecture #4For acceptable operation
WN=1.5 WP for our Process respecting min WP
CONCORDIAVLSI DESIGN LAB
20
CASCODE LOGIC
Lad is cross coupled pMOS
transistors
Logic is series and parallel
complementary transistors
Input and Output are in
Complementary forms
CONCORDIAVLSI DESIGN LAB
21
CSACODE Inverter/Nand Gate
CONCORDIAVLSI DESIGN LAB
22
CASCODE Complex Gate
CONCORDIAVLSI DESIGN LAB
23
DCVS trees for a full adder Sum and Carry
Pull-Down Networks
S’(A,B,C) = A’BC’ + A’B’C + ABC + AB’C’S (A,B,C) = A’B’C’ + A’BC + ABC’ + AB’C
C(A,B,C) = AB + BC + AC
CONCORDIAVLSI DESIGN LAB
24
Transmission Gate
Bi-directional switch, passes digital signalsLess complex and more versatile than AND gate Passes analog signals
Problems: Large ON resistance during transitions of input signals Large input and output capacitance (useful for data storage applications) Capacitive coupling
Applications:Multiplexers, encoders, latches, registersvarious combinational logic circuits
C
C
A B
BA
C
C
C
C
A B TGA B
C
INV included
CONCORDIAVLSI DESIGN LAB
25
NMOS/PMOS as Pass Transistors
Vi Vo
C
CL
NMOS Transistor Passes weak “1” signal Vo = VDD -VTN
Passes “0” signal undegraded
Vo
Vi
VDD -VTN
Vi Vo
C
CL
VDD -VTN
Vo
Vi
-VTP
-VTP
PMOS Transistor
Passes “1” signal undegraded
Passes weak “0” signal Vo= -VTP
CONCORDIAVLSI DESIGN LAB
26
TX Gate: Characteristics
C
Vin Vo
Vo
Vin
0V |VTP| VDD-VTN VDD
nmos:lin nmos:sat nmos:offpmos:sat pmos:lin pmos:lin
Req,pReq,n
Req,TX
Vo
R
VDD-VTN VDD0
CONCORDIAVLSI DESIGN LAB
27
AND, NAND
A B F
0 0 0
0 1 0
1 0 0
1 1 1
CONCORDIAVLSI DESIGN LAB
28
OR, NOR
A B F
0 0 0
0 1 1
1 0 1
1 1 1
CONCORDIAVLSI DESIGN LAB
29
A multiplexer
C A B F C A B F
0 0 0 0 1 0 0 0
0 0 1 1 1 0 1 0
0 1 0 0 1 1 0 1
0 1 1 1 1 1 1 1
CONCORDIAVLSI DESIGN LAB
30
XOR
A B F
0 0 0
0 1 1
1 0 1
1 1 0
CONCORDIAVLSI DESIGN LAB
31
Four to one multiplexer
CONCORDIAVLSI DESIGN LAB
32
TX Gate: Layout
VDD
VSS
VOVi
C
C C CFor data path structure
P+P+
N+N+
CONCORDIAVLSI DESIGN LAB
33
NAND Gates: Layout
Layout Transistors in Series
Transistors in Parallel
CONCORDIAVLSI DESIGN LAB
34
NAND Gates: Layout
A BX
Metal IIVia
VDD
GND
CONCORDIAVLSI DESIGN LAB
35
NOR Gate: Layout
ABX
VDD
GND
CONCORDIAVLSI DESIGN LAB
36
Analysis and Design of Complex Gate
A B C D E F
A B C D E F
VDD
GND
OUT
active(diffusion)
n+ layermetalpolysilicon
contact
p+ layer
N-well
Analysis
1. Construct the schematic2. Determine the logic function.3. Determine transistor sizes.4. Determine the input pattern to cause slowest and fastest operations.5. Determine the worst case rise delay (tPLH)and fall delay (tPHL)6. Determine the best case rise and fall delays.