Diplomarbeit
900MHz Power AmplifierModule in Multilayer-Laminate
Technology
ausgefuhrt zum Zwecke der Erlangung des akademischen Grades eines
Diplom-Ingenieurs unter Leitung von
Werner Simburger und Arpad L. Scholtz
E389
Institut fur Nachrichtentechnik und Hochfrequenztechnik
eingereicht an der Technischen Universitat Wien
Fakultat fur Elektrotechnik und Informationstechnik
von
Thomas Beles
9226945Hafergrubenweg 22, A-2230 Ganserndorf
Ganserndorf, im Juni 2005
Contents
1 Introduction 11.1 State-of-the-art power amplifier modules . . . . . . . . . . . . . . 1
2 Integrated 900 MHz power amplifier 42.1 A monolithic transformer coupled push-pull type power amplifier
in silicon bipolar technology . . . . . . . . . . . . . . . . . . . . . 42.2 Balanced output matching network . . . . . . . . . . . . . . . . . 6
2.2.1 Transmission-line transformer . . . . . . . . . . . . . . . . 62.3 Optimum load impedance . . . . . . . . . . . . . . . . . . . . . . 9
3 Balun in multilayer-laminate technology 133.1 Functionality of the balun . . . . . . . . . . . . . . . . . . . . . . 143.2 Substrates of the balun . . . . . . . . . . . . . . . . . . . . . . . . 153.3 Simulation and design . . . . . . . . . . . . . . . . . . . . . . . . 193.4 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4 Experimental results 314.1 S-parameter characterization of the balun . . . . . . . . . . . . . 314.2 Power amplifier module . . . . . . . . . . . . . . . . . . . . . . . . 35
Conclusion 41
A Losses of the multilayer balun 43A.1 The dielectric loss . . . . . . . . . . . . . . . . . . . . . . . . . . . 43A.2 The ohmic losses . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
A.2.1 DC loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43A.2.2 Rf loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
B Alternative Implementations 46
Bibliography 54
i
List of Abbreviations
AC Alternating CurrentADS Advanced Design System, CAD software by Agilent TechnologiesB6HF Infineon silicon bipolar technology with fT = 25GHzC Capacity in [F]CMOS Complementary Metal Oxide SemiconductorDC Direct CurrentDCS1800 Digital Cellular System (1800 MHz)εr Relative permittivityESD Electrostatic Sensitive Devicef Frequency [Hz]FR4 Epoxy LaminateGSM Global System for Mobile communicationsGaAs Gallium ArsenideGPRS General Packed Radio ServiceGND GroundIC Integrated CircuitL Inductance in [H]LCP Liquid Crystalline Polymer, substrate material by Rogersλ Wavelength in [m]µ Permeability in [Vs/Am]MMIC Monolithical M icrowave Integrated CircuitMOS Metal Oxide SemiconductorPA Power AmplifierPAC Power Amplifier ControlPAE Power Added EfficiencyPA2SA A power amplifier chip in B6HF by InfineonPCB P rinted Circuit BoardPCS1900 P ersonal Communication System (1900 MHz)RF Radio F requencyρ Reflection coefficientSKY77324 A power amplifier module by SkyworksSi SiliconSMA SubM iniatur A : Standard RF connector up to 18 GHzSMD Surface Mounted Deviceω angular frequencyZ complex impedance in [Ω]
ii
Chapter 1
Introduction
A RF power amplifier is required in every wireless system. However there areseveral ways to design such a power amplifier depending on the requirements. Inthis thesis, a push-pull power amplifier for 900 MHz is characterized including anew balun design for output matching.
Currently power amplifier for GSM are implemented single-ended. One of thereasons for this is that matching is easier, because a balun is not required. On theother hand the single-ended implementation also has disadvantages. For examplethe emitter inductance of the bond wires affects negative to the RF performance.
State of the art modules will be discussed in section 1.1. This work is lookingfor an another solution, which is based on the use of a balanced circuit design insilicon. To match the balanced amplifier to 50 Ω unbalanced output, a balun isrequired.
In chapter 2 the integrated power amplifier chip PS2SA is presented, includingmeasurement results of a reference balun design. These results will be used lateron to be compared with the multilayer balun presented in chapter 3 and 4. Aload pull measurement, which is used for the design of the multilayer balun, ispresented as well.
Chapter 3 shows the design and realization of a new multilayer balun. Function-ality of the balun, used materials and a simulation model is explained in detail.Finally experimental results are presented in chapter 4.
The appendix shows the losses of the balun in detail, and closing with an overviewabout alternative multilayer balun implementations.
1.1 State-of-the-art power amplifier modules
Most of today’s power amplifiers for handsets are hybridmodules which work forall four GSM frequency bands. The enterprices Anadigics, Analog Divices, Hi-tachi, Motorola, Philips, RFMD, Skyworks and TriQuint are offering such quad-
1
CHAPTER 1. INTRODUCTION 2
Figure 1.1: Schematic diagram of the Skyworks 77324 quad-band power amplifiermodule. Source: [Skyworks 03]
band power amplifier modules. From all these we look are up to the SKY77324module from Skyworks. The products from other companies are designed in sim-ilar ways.
The SKY77324 power amplifier module consists of separate GSM850/900 PA andDCS1800/PCS1900 PA blocks, impedance matching circuitry for 50Ω input andoutput impedances, and a power amplifier control (PAC) block with an internalcurrent-sense resistor. The custom CMOS integrated circuit provides the internalPAC function and interface circuitry.
Fabricated on a single Gallium Arsenide die, one heterojunction bipolar transistorPA block supports the GSM850/900 bands and the other supports the DCS1800and PCS1900 bands. The GaAs die, the silicon die, and the passive componentsare mounted on a multilayer laminate substrate. The assembly is encapsulatedwith plastic overmold. Fig. 1.1 and Tab. 1.1 show more details.
CHAPTER 1. INTRODUCTION 3
Applications Class 4 GSM850/900Class 1 DCS1800/PCS1900Class 12 GPRS multi-slot operation
Input Power Range 0 to 6 dBmTypical Output Power GSM850 35 dBm
GSM900 35 dBmDCS 33 dBmPCS 33 dBm
Typical PAE GSM850 49%GSM900 53%DCS 51%PCS 53%
Supply Voltage 2.9 - 4.8 VPackage 6 mm x 8 mm x 1.2 mm, 22-pin MCM
Internal ICC Sense resistor for PACInput/Output matching 50Ω internal with DC blocking
Table 1.1: Features of the Skyworks 77324 quad-band power amplifier module.Source: [Skyworks 03]
Chapter 2
Integrated 900 MHz poweramplifier
This chapter is based on the paper ”Monolithic Integration of Power Amplifier inSilicon-based Technologies” from Werner Simburger [Simburger 99], and presentsthe integrated power amplifier PA2SA for 900MHz.
To evaluate the performance of the power amplifier MMIC an external outputmatching network circuit is required. This circuit consists of a partially dis-tributed impedance transformation network and a semi-rigid line balun. Themeasurement results will be used later on to be compared with the multilayerbalun presented in chapter 3 and 4.
A detailed description of the PA chip PS2SA is also shown in [Heinz 99], includinga load-pull measurement, which is important for the design of the multlayer balun.These measurement results will be presented at the end of this chapter.
2.1 A monolithic transformer coupled push-pull
type power amplifier in silicon bipolar tech-
nology
Fig. 2.1 shows a simplified schematic diagram of a monolithic 2-stage push-pullpower amplifier.
It consists of an on-chip transformer as input-balun, a driver stage, a transformeras interstage matching network and a power output stage. A current mirror isused to set the bias current of the driver stage and the output stage each.
The input-transformer X1 is connected as a parallel resonant device using aMOS-capacitor CIN . The transformer acts as balun as well as input matchingnetwork. On-chip transformers are also used successfully by e.g. J.R. Long andM.A.Copeland [Long 95], J. Zhou [Zhou, J.J. 98], D.Cheung [Cheung, D.T. 98].
4
CHAPTER2. INTEGRATED 900MHZ POWER AMPLIFIER 5
SubstrateVEE
RFIN+
VCC
X1
BIAS BIAS
X2
R1 R2
CIN
CIS
D1 D2
T1
T2
T3
T4
RFIN-
RFOUT-
RFOUT+
Figure 2.1: Basic architecture of a transformer coupled monolithic 2-stage push-pull type power amplifier.
There are several outstanding advantages due to the on-chip transformer at theinput:
• No restrictions to the external dc potential at the input terminals.
• No external input dc blocking capacitor is required.
• The input signal can be applied balanced or single-ended if one input ter-minal is grounded.
The interstage matching network of the power amplifier consists of the transform-ers X2. A MOS capacitor CIS are connected in parallel to the primary windings.
From this basic idea the circuit shown in Fig. 2.2 was developed. Several experi-mental results of this MMIC are presented in [Simburger, 99,a, Simburger, 99,b].The amplifier circuit is designed to meet the requirements to the parasitic be-havior of the on-chip transformers. Therefore, the interstage matching networkof the power amplifier consists of two transformers X2 and X3 with a turn ra-tio of N=5:2. The primary windings are connected in series and the secondarywindings are connected in parallel in order to provide the right values of primaryand secondary inductance and to put high base currents into the output powertransistors.
CHAPTER2. INTEGRATED 900MHZ POWER AMPLIFIER 6
Figure 2.2: Schematic diagram of a monolithic push-pull power amplifier[Simburger, 99,a, Simburger, 99,b].
The chip is fabricated in a standard 25GHz-fT , 0.8µm, 3-layer-interconnect siliconbipolar production technology of Infineon B6HF [Klose, H. 93]. Fig. 2.3 shows across section of a typical 0.8 µm BEC transistor module. The production technol-ogy offers rf npn, high voltage npn, lateral pnp, p+/p−/n+-poly resistors, 2 fF/µm2
MOS capacitors and ESD structures. Fig. 2.4 shows a micrograph of the chip.
2.2 Balanced output matching network
The strong impact of the output matching network and the bias operating pointon the output power and the PAE of a rf power amplifier is a well known subject([Sokal, N. O 75] to [Nishiki 87]). The performance of a power amplifier dependson the circuit design as well on the input/interstage/load-line matching network.
2.2.1 Transmission-line transformer
A transmission-line transformer circuit can be used to evaluate the performanceof a power amplifier MMIC, or as a design basis for a discrete or hybrid-module
CHAPTER2. INTEGRATED 900MHZ POWER AMPLIFIER 7
Base Contact Emitter Contact Collector Contact
2 µm
Channel-Stop Buried-Layer
Buried-LayerContact
Active Transistor
LOCOSPoly n
+Poly p+
Al
Al
Al
Oxide
Poly n+
Figure 2.3: Cross section of a 25GHz-fT , 0.8µm silicon bipolar transistor BECmodule [Klose, H. 93].
implementation [Motorola 94]. The output matching network circuit, which wasused in [Simburger, 99,a] to evaluate the performance of the power amplifierMMIC consists of a partially distributed impedance transformation network anda semi-rigid line balun. Fig. 2.5 shows the schematic diagram of the test circuit.
The input of the amplifier MMIC is connected via a 50Ω micro-strip line to theinput signal. The supply-voltage line of the output stage consists of two 50Ωλ/4-length lines (at the frequency of operation f1) translating a low impedanceat 2f1 to the output transistors. The optimum load impedance at the frequencyof operation f0 is translated by 25 Ω λ/8-length micro-strip lines. CM determinesmainly the real part and CE determines nearly orthogonal the imaginary part ofthe load impedance at f1. CA determines the impedance at 3f1 which should beas high as possible. CK are DC blocking capacitors. A λ/4-length 50Ω semi-rigidline acts as balun.
Fig. 2.6 shows a photograph of a test circuit, which was designed at 900 MHz[Simburger, 99,b]. The printed circuit board (PCB) measures 70mm×78mm. AFR4 substrate with a height of h = 0.8mm is used.
Transmission-line transformer experimental Results
Fig. 2.7 shows the output power and PAE versus input power, of the power am-plifier (Fig. 2.2), at 900MHz and T = 27C depending on the supply-voltage at2.5V, 3.5V, 4V and 4.5 V. The maximum PAE is about 57% at 3.5V and 4V.37 dBm (5W) output power is achieved at 4.5 V supply voltage and 900MHz.The linear gain is 36 dB.
CHAPTER2. INTEGRATED 900MHZ POWER AMPLIFIER 8
Figure 2.4: Micrograph of the rf power amplifier IC [Simburger, 99,b]. Size:2×2mm2.
Fig. 2.8 shows the output power and PAE versus frequency and supply-voltage atT = 27 C. The input power is +10 dBm. 37 dBm (5W) is achieved at 800MHzto 910MHz and 4.5V supply voltage. The PAE at the maximum output power is57%. At 3.5V and 4 V the maximum PAE is about 59%. The collector efficiencyof the output stage is 67% in this case. In general the PAE is > 50% from800MHz to 960MHz. The driver stage and the output stage forms a push-pullClass AB stage each. At 2.5V supply voltage the bias current of the driver stageis about 30mA per transistor. The bias current of the output stage is 260 mA perTransistor. At 4.5 V supply voltage the bias current of the output stage goes upto near 400mA due to breakdown conditions.
CHAPTER2. INTEGRATED 900MHZ POWER AMPLIFIER 9
CA P
OUTP
IN
25 W
50
W50
W
50 W
l/8
l/4
l/4
25 W
25 W 25 W
BALUN
Power-Down
Power Amplifier Chip
mounted in a TSSOP-16 package
with heat sink.
VCC
VCC
VCC
CM
CE
CK
CK
Figure 2.5: Schematic diagram of the transmission-line transformer output match-ing network.
2.3 Optimum load impedance
To achieve the best performance of the power amplifier, the right load impedanceat the output is required. This process is called power matching. Here, the load isdimensioned exactly conjugate complex to the impedance of the amplifier circuit.As [Gonzales 84] has shown, this strategy warrants the maximum output power.
However, power amplifier in most cases do not work in the linear range. This non-linearity makes the system time variant. Thus, the linear power matching methodis not correct any more. In fact, [Jochen 95] showed that the maximum outputpower for nonlinear power amplifiers is maximized if a certain load impedanceis attached to the fundamental frequency and the second and third harmonicfrequency. For the second harmonic frequency the load should be close to a shortcircuit, while for the third harmonic frequency an open circuit is desired.
While the real part of the load for the fundamental frequency depends mainlyon the power supply voltage and the desired power output the imaginary part iscaused by parasitic substrate and transistor capacities, not to forget the induc-tances of the bonding wires and interconnections.
For the design of the multilayer balun the optimum load impedance of the PA2SAis necessary. However, Alexander Heinz [Heinz 99] and W. Balkalski [Bakalski 01]have explained the load-pull measurement setup in detail, therefore this paperonly shows the results of these measures based on Alexander Heinz in short: Asthe limits of the two different measurements differ slightly, one can say that themaximum Pout (Fig. 2.9) and the maximum PAE (Fig. 2.10) are achieved at anoptimum load impedance of around 6 Ω.
CHAPTER2. INTEGRATED 900MHZ POWER AMPLIFIER 10
Figure 2.6: Power amplifier test circuit with a transmission-line transformer. FR4PCB size: 70×78mm2. [Bakalski 01]
CHAPTER2. INTEGRATED 900MHZ POWER AMPLIFIER 11
Figure 2.7: Transmission-line transformer output power and PAE versus inputpower and supply voltage. [Heinz 99]
Figure 2.8: Transmission-line transformer output power and PAE versus frequencyand supply voltage. [Heinz 99]
CHAPTER2. INTEGRATED 900MHZ POWER AMPLIFIER 12
0
5
10
15
20
4
2
0
-2
-4
27
28
29
30
31
32
33
34
Realteil (single ended) in Ohm
Imaginärteil (single ended) in Ohm
Pout in
dB
m
28
28.5
29
29.5
30
30.5
31
31.5
32
32.5
33
Figure 2.9: Output power versus complex load impedance measured at 900MHz.[Heinz 99]
0
5
10
15
20
4
2
0
-2
-4
5
10
15
20
25
30
35
40
45
Realteil (single ended) in Ohm
Imaginärteil (single ended) in Ohm
PA
E in
%
10
15
20
25
30
35
40
Figure 2.10: Power added efficiency versus complex load impedance measured at900 MHz. [Heinz 99]
Chapter 3
Balun in multilayer-laminatetechnology
In this chapter a new multilayer balun is presented. The balun has to meet severalrequirements: It provides a matching for the 6 Ω balanced output (optimum load)of the power amplifier PA2SA to an 50 Ω unbalanced load. The balun is realizedin a multilayer laminate board which acts as a carrier for the PA chip as well. Thecarrier function of the board implies feeding control and power lines to the chipas well as leading the produced heat away from the chip. The schematic diagramof the power amplifier module (power amplifier and balun) is shown in Fig. 3.1.
CIN
RFIN+
RFIN-
X1
R1
D1
T1
T2
CIS
X2
R2
D2
T3
T4
Bias VCC
VCC
RFOUT
Power Amplifier PS2SA Multilayer Balun
Bias
Figure 3.1: Schematic diagram of the power amplifier module.
13
CHAPTER3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 14
VCC
RFOUT50 Ohm
RFIN+6 Ohm
RFIN-6 Ohm
Coupler 2 Coupler 1
CL2botton
CL2up
CL1up
CL1botton
broadside coupled striplines
l/4 l/4
Figure 3.2: Schematic diagram of the multilayer balun.
3.1 Functionality of the balun
The basic circuit of the balun is shown in Fig. 3.2. It consist of two λ/4 - cou-plers which are implemented as broadside coupled striplines. Each of the couplershifts the phase by 90 degrees. Basic Information concerning of broadside coupledstriplines can be found in [Mongia, R. 99] and [Wadell 91]. V CC is the supplyfor the output circuit of the power amplifier.
For the design it is necessary to understand the wave propagation on the striplines.Fig. 3.3 shows the two propagation modes. For a good coupler the ODD mode isdesired and the EVEN mode is undesired. This will be reached by a small spacingS and a large spacing B, so that the ODD mode dominates.
S B
EVEN - Mode ODD - Mode
tan d2
tan d2
tan d1
tan d2
tan d2
tan d1
Figure 3.3: The two propagation modes of broadside coupled striplines.
CHAPTER3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 15
Product Property R/flex 3600 R/flex 3850 R/flex 3958(R/flex 3800)
Construction Type single clad double clad bond filmlaminate laminate
Dielectric Constant, εr 2.9 (1-10GHz)Dielectric Loss Factor, tan δ 0.002 (1-10GHz)Moisture Absorption, % 0.04LCP Thickness, µm 25, 50, 100Copper Thickness, µm 18, others upon request N/AMelting Temperature, C 290 315 280 (315)Solder Float, C 260 288 260 (288)
Table 3.1: R/flex 3000 LCP product family. Source: [Rogers 03]
The main part of the electrical field is captured between the striplines. This willbe improved by a large εr1 and a small εr2. For a good performance of the couplerit is important that the dielectric loss tan δ1 is small, whereas the influence of thedielectric loss tan δ2 is not so relevant.
3.2 Substrates of the balun
In reference to previous explanation the basic construction of the multilayerbuildup of the balun results as is shown in Fig. 3.4. Metal 2 and 5 serve as ground-planes for coupler 1; metal 6 and 9 for coupler 2. Metal 3 and 4 as well as metal 7and 8 are the broadside coupled striplines. The top and the bottom metal layersare used for the power and control lines. The dielectric layers εr2 and εr3 are madeof cheap FR4. Between the striplines a very thin high quality layer is necessary.
There are two reasons to use high quality layers instead of FR4. Firstly thedielectric loss of FR4 is higher than the loss of the high quality material. Secondlythe minimum thickness of FR4 is 100 µm, whereas the high quality materials areavailable with a minimum thickness of 25 µm. If the module was fabricated onlyin FR4, the overall size would be significanty larger as the composite buildupwith FR4 and high quality materials.
The following two high quality substrates were investigated:
• Rogers R/flex 3000 LCP by Rogers
• Gores Speedboard C by Gore
The Rogers R/flex 3000 LCP is a new substrate by Rogers for high frequencyapplications. LCP is equivalent for ‘Liquid Crystalline Polymer’. It has a dielectricconstant εr of 2.9, and a very small dielectric loss factor tan δ of 0.002. Both values
CHAPTER3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 16
SiIC
Me
tal1
(Sig
na
l)
Me
tal2
(GN
DP
lan
e)
Me
tal3
(Co
up
led
Lin
es)
Me
tal4
(Co
up
led
Lin
es)
Me
tal5
(GN
DP
lan
e)
Me
tal6
(GN
DP
lan
e)
Me
tal7
(Co
up
led
Lin
es)
Me
tal8
(Co
up
led
Lin
es)
Me
tal9
(GN
DP
lan
e)
Me
tal1
0(S
ign
al)
Bo
nd
Wire
Ep
oxy
Glu
e
Coupler1 Coupler2
r22
,ta
n2
00
-30
0M
icro
n
CL2up
CL2bottom
CL1up
CL1bottom
VC
CR
fou
t
Rfin
+R
fin
-
CL
1u
p
CL1bottom
CL2bottom
CL2up
/4
r22
,ta
n2
00
-30
0M
icro
n
r22
,ta
n2
00
-30
0M
icro
n
r22
,ta
n2
00
-30
0M
icro
n
r1,ta
n2
5M
icro
n
r1,ta
n2
5M
icro
n
r3,ta
n1
00
Mic
ron
r3,ta
n1
00
Mic
ron
(~4
6m
mat9
00
MH
z)
r3,ta
n1
00
Mic
ron
Figure 3.4: Basic construction of the multilayer buildup and schematic diagramof the balun.
CHAPTER3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 17
Copper
Copper
R/flex 3850 double clad
R/flex 3858 bonding film
Copper
R/flex 3600 single clad
Figure 3.5: Rogers R/flex 3850 double clad laminates can be multilayer bondedwith the Rogers R/Flex 3958 bondply or Rogers R/flex single clad laminatesto make all-LCP multilayer boards. Rogers R/flex circuite materials can also becombined with epoxy, acrylic or cyanate ester to enhanced the properties of amultilayer design as needed.
Dielectric constant εr at 1-40GHz 2.6Dielectric Loss Factor, tan δ at 1-40GHz 0.0036Glass transition Temperature Tg, C 220Thickness of dielectric, µm 38, 51, 57, 86Moisture Absorption, % (w/w) 0.31 - 0.46
Table 3.2: Material Properties of Gores Speedboard C. It’s only available asprepreg. Source: [Gore 02]
are nearly constant in a wide range of frequency. The LCP is available as a singlecopper-clad laminate, as a double copper-clad laminate and as a bonding film,too. Tab. 3.1 and Fig. 3.5 shows more details.
The other high frequency substrate is the Speedboard C by Gore. In contrast tothe LCP it is only available as prepreg. A prepreg is a dielectric layer withouta copper-clad to combine multilayer buildups, such as the bonding film in thecase of Rogers R/flex. Gores Speedboard C has a dielectric constant εr of 2.6,and a dielectric loss factor tan δ of 0.0036, which is also nearly constant in awide range of frequency. Tab. 3.2 shows the material properties: The thinnestavailable thickness is the 38 µm speedboard. In contrast to the LCP single anddouble clad laminate the thickness is becoming smaller after pressing. For thebalun application, in which copper laminated cores are pressed from both sides,the thickness decreases to about 25 µm, which is illustrated in Fig. 3.6.
We used the following companies as suppliers for test module fabrication:
• Aspocomp Group, Ayritie 12 a, P.O. Box 230, 01511 Vantaa, Finland
CHAPTER3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 18
Speedboard C - Prepeg
Copper
Copper
After Pressing
Speedboard C - Prepeg
Copper
Copper
Before Pressing
Copper
Copper
LCP - Core, double clad
FR4 - Core
FR4 - Core
FR4 - Core
FR4 - Core
FR4 - Prepeg
Copper
Copper
LCP - Core, double clad
FR4 - Prepeg
FR4 - Prepeg
FR4 - Prepeg
25
m
25
m
~25
m
38
m
Figure 3.6: Comparison of Rogers double clad LCP core and Gores SpeedboardC prepeg.
Sales Manager: Fernando MirandaPhone: +358 9 7597 0720Fax: +358 9 7597 0720email: [email protected]
• Optiprint, SwitzerlandSales Manager: Gerhard PoppPhone: +49 7129 922783Fax: +49 7129 922784email: [email protected]
• R&D Ciruits, NJ, USAEngineering Manager: Tom SmithPhone: +1 732 549 4559 Ext. 26Fax: +1 732 549 1388email: [email protected]
• Ruwel, Marburger Strasse 65, D-35083 Wetter/Hessen, GermanyProduct Manager: Henk BerkelPhone: +49 64 2381 246Fax: +49 64 23 4385email: [email protected]
CHAPTER3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 19
3.3 Simulation and design
To describe the balun with S-parameters we have used the mixed mode concept.The basics of mixed mode S-parameters can be found in [Agilent 01], [Agilent 97],[Maxim 01] and in [Stengel 99].
In the case of a balun there is a combination of balanced and single ended ports. Todefine the S-parameters of this device, three modes must be included: differential-and common modes on the balanced port, and a single ended mode on the singleended port (Fig. 3.7).
Three-Terminal Devices(3 Modes of Propagation)
Single-Ended ModeDifferential ModeCommon Mode
Port 1
(unbalanced)
Port 2
(balanced)
Single Ended
Response
Differential
Mode Response
Common Mode
Response
Port 1
Port 2
Port 2
Port 1 Port 2 Port 2
Single
Ended
Stimulus
Differential
Mode
Stimulus
Common
Mode
Stimulus
Sss11
Ssd12
Ssc12
Sds21
Sdd22
Sdc22
Scs21
Scd22
Scc22
Balun1
2
3
Figure 3.7: To characterise a balun the mixed mode concept is to consider.
For a characterization of the balun the single ended S-parameters must be ex-tended by mixed mode S-parameters. For a full description of the balun, with itsdifferent modes at input and output, following terms are necessary:
• One single-ended port reflection term - Sss11
• Four balanced port reflection terms - Sdd22, Scc22, Sdc22, Scd22
• Two forward transmission terms - Sds21, Scs21
CHAPTER3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 20
• Two reverse transmission terms - Sds12, Scs12
The S-matrix for such a device is arranged with the stimulus conditions in thecolumns, and the response conditions in the rows. Notice that two columns andtwo rows describe each balanced port, and one column and one row describe eachsingle-ended port.
In this case the four parameters in the lower right corner describe the four types ofreflection that are possible on a balanced port, the single parameter in the upperleft describes the reflection on the single ended port, and the other four parametersdescribe the differential and common mode transmission characteristics in theforward and reverse directions.
To receive the mixed mode parameters from a 3 port single ended measurement,the following transformation equations are used:
Sss11 = S11 (3.1)
Ssd12 =1√2· (S12 − S13) (3.2)
Ssc12 =1√2· (S12 + S13) (3.3)
Sds21 =1√2· (S21 − S31) (3.4)
Scs21 =1√2· (S21 + S31) (3.5)
Sdd22 =1
2· (S22 − S23 − S32 + S33) (3.6)
Scc22 =1
2· (S22 + S23 + S32 + S33) (3.7)
Sdc22 =1
2· (S22 + S23 − S32 − S33) (3.8)
CHAPTER3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 21
Scd22 =1
2· (S22 − S23 + S32 − S33) (3.9)
In this work we primarily look upon a multilayer balun made of a combinationof LCP and FR4 in work with the board producer Ruwel. For the simulation theprogram ADS 2003A from Agilent Technologies is used. ADS is an abbreviationfor ”Advanced Design System”. We start with an estimation of the line widthand the line length. They will be calculated with the ADS tool ”LineCalc”. Forthis calculation the characteristic impedance Z0 of the λ/4 - coupler is required,and can be determined by
Z20 = Zin · Zout = Zeven · Zodd. (3.10)
With Zin = 6 Ω and Zout = 50Ω the result is Z0 = 17.32Ω. So the line widthbecomes about 500 µm, the line length of the λ/4 - line about 46mm, Zeven ≈ 65Ωand Zodd ≈ 4.5Ω. Next we create a simulation model. For this we start with theschematic tool, where the basic circuit will be assembled. To save space the linesare arranged in spiral structures. Fig. 3.8 shows the details of the schematic.
For the simulation we change to the layout tool. There is an efficient 3D-Simulatorcalled ”Momentum” available. Furthermore, in the layout tool there is a possibil-ity to generate composite substrate stacks, which is a problem in the schematictool. To export the structure from the schematic tool to the layout tool the func-tion ”Generate/Update Layout...” is used. For a successful export, the groundand the port components must be erased.
After export the structure is available in the layout tool. At first the layers canbe named or renamed with the ”Layer Editor”. Next the substrate stack andthe assignment of the layers will be defined. This is possible with the function”Momentum - Substrate - Create/Modify...”. Furthermore, the structure must beexpanded with the ground planes, interlayer connections and the ports for thesimulation. One interlayer connection is necessary for coupling the two striplines.Some others are necessary to couple the ground planes. To facilitate the simulationall interlayer connections will be implemented in quadratic structures.
With the ”Port Editor...” the three input/output-ports will be defined as singletype ports with 50Ω. The ground reference ports on the ground planes must beassigned to the input/output-ports, and also in alignment with them. Fig. 3.9shows the layout of the balun for the simulation. However, both the single endedand the balanced port are defined with 50 Ω single ended. For this it is possibleto export the S-parameter data to a 3-port blackbox in ADS or into anotherprogram. Now the S-parameter is displayed from case to case normalized to 50Ωfor all ports or normalized to 50 Ω for the single ended port and 6 Ω for thebalanced port.
CHAPTER3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 22
SBCLINCLin9
P1Layer=cond1
L=C umS=s um
W=w um
Subst="MMix1"
Term
Term1
Z=50 Ohm
Num=1
Term
Term3
Z=50 OhmNum=3
Term
Term2
Z=50 OhmNum=2
SBCLIN
CLin3
P1Layer=cond1
L=J um
S=s umW=w um
Subst="MMix1"
SBCLIN
CLin16
P1Layer=cond1
L=C um
S=s um
W=w umSubst="MMix2"
SBCLIN
CLin11
P1Layer=cond1L=J um
S=s um
W=w um
Subst="MMix2"
SMITER
Bend17
Layer=cond2W=w um
Subst="MMix2"SBCLIN
CLin17
P1Layer=cond1
L=G umS=s um
W=w um
Subst="MMix2"
SBCLIN
CLin5
P1Layer=cond1L=G um
S=s um
W=w um
Subst="MMix1"
SMITER
Bend12
Layer=cond1
W=w um
Subst="MMix1"
SMITER
Bend14
Layer=cond1
W=w um
Subst="MMix1"
SMITERBend13
Layer=cond2W=w um
Subst="MMix1"
SMITERBend11
Layer=cond2
W=w um
Subst="MMix1"
SMITER
Bend5
Layer=cond2
W=w umSubst="MMix1"
SBCLIN
CLin10
P1Layer=cond1
L=B umS=s um
W=w um
Subst="MMix1"
SBCLIN
CLin6
P1Layer=cond1
L=F umS=s um
W=w um
Subst="MMix1"
SMITER
Bend3
Layer=cond2
W=w umSubst="MMix1"
SBCLIN
CLin4
P1Layer=cond1L=H um
S=s um
W=w um
Subst="MMix1"
SMITERBend2
Layer=cond2
W=w um
Subst="MMix1"
SMITERBend1
Layer=cond1W=w um
Subst="MMix1"
SMITER
Bend9
Layer=cond2
W=w umSubst="MMix1"
SMITER
Bend10
Layer=cond1W=w um
Subst="MMix1"
SBCLIN
CLin7
P1Layer=cond1L=E um
S=s um
W=w umSubst="MMix1"
SMITERBend7
Layer=cond2W=w um
Subst="MMix1"
SMITER
Bend8
Layer=cond1
W=w umSubst="MMix1"
SMITER
Bend26
Layer=cond1
W=w um
Subst="MMix2"
SMITER
Bend25
Layer=cond2W=w um
Subst="MMix2"
SMITER
Bend19
Layer=cond1W=w um
Subst="MMix2"
SMITER
Bend24
Layer=cond2
W=w umSubst="MMix2"
SMITER
Bend27
Layer=cond1
W=w umSubst="MMix2"
SBCLINCLin12
P1Layer=cond1
L=H umS=s um
W=w um
Subst="MMix2"
SMITER
Bend20
Layer=cond2
W=w umSubst="MMix2"
SBCLIN
CLin13
P1Layer=cond1L=F um
S=s um
W=w umSubst="MMix2"
SMITERBend18
Layer=cond1
W=w um
Subst="MMix2"
SBCLIN
CLin15
P1Layer=cond1
L=D umS=s um
W=w um
Subst="MMix2"
SMITER
Bend16
Layer=cond2
W=w um
Subst="MMix2"
SMITERBend15
Layer=cond1
W=w um
Subst="MMix2"
SMITER
Bend21
Layer=cond1W=w um
Subst="MMix2"SMITER
Bend22
Layer=cond2
W=w umSubst="MMix2"
SMITERBend23
Layer=cond2W=w um
Subst="MMix2"
SMITER
Bend28
Layer=cond1
W=w umSubst="MMix2"
SMITER
Bend44
Layer=cond1
W=w um
Subst="MMix2"
SMITER
Bend43
Layer=cond2
W=w umSubst="MMix2"
SMITER
Bend45
Layer=cond2
W=w um
Subst="MMix1"
SBCLIN
CLin28
P1Layer=cond1L=A um
S=s um
W=w umSubst="MMix1"
SMITERBend46
Layer=cond1
W=w um
Subst="MMix1"
SMITERBend6
Layer=cond1W=w um
Subst="MMix1"
SMITER
Bend4
Layer=cond1W=w um
Subst="MMix1"
SBCLINCLin8
P1Layer=cond1
L=D umS=s um
W=w um
Subst="MMix1"
SBCLIN
CLin18
P1Layer=cond1
L=B umS=s um
W=w um
Subst="MMix2"
SBCLIN
CLin14
P1Layer=cond1
L=E um
S=s umW=w um
Subst="MMix2"
SBCLIN
CLin27
P1Layer=cond1L=A um
S=s um
W=w umSubst="MMix2"
S_Param
SP1
Step=0.01 GHz
Stop=1.5 GHz
Start=0.5 GHz
S-PARAMETERS
SSUB
MMix2
Cond2="metal4"
Cond1="metal3"
TanD=0.002Cond=5.7E7
T=18 um
B=361 umMur=1
Er=2.9
SSub
SSUBMMix1
Cond2="metal8"
Cond1="metal7"
TanD=0.002Cond=5.7E7
T=18 um
B=361 umMur=1
Er=2.9
SSub
VAR
VAR1
d=3150w=600
J=2036
H=2583G=5020
F=4945
E=6562
D=6437C=8106
B=8087
A=2854s=25
EqnVar
Figure 3.8: Schematic of the balun assembled in ADS2003A schematic tool.
CHAPTER3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 23
RFIN+RFIN- RFOUTCL1
(Metal 3 + 4)
CL2
(Metal 6 + 7)
13.4 mm
11.8
mm
Metal 3 - CL1up
Metal 6 - CL2up
Metal 7 - CL2bottom
460um
Figure 3.9: Simulation with the layout tool - top view of the Ruwel multilayerbalun version D1. Line length = 46.62mm, line width = 460 µm.
With this information it is possible to determine the exact buildup of the mul-tilayer. To achieve a good performance of the coupled lines, the insertion loss ofthe differential mode to single ended mode transmission Sds21 should be less than0.2 to 0.3 dB - for operating conditions (50 Ω single ended port, 2 x 6Ω balancedport). The simulation shows that with a spacing of 300 µm between the striplinesand the ground planes the goal for the insertion loss of Sds21 will be exceeded.It also shows that the reflection coefficients of the balanced port are small incase of differential mode and large for the common mode. Three FR4 prepegs,each with 115 µm thickness, decrease to about 300 µm after pressing. With only
CHAPTER3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 24
-2.5
-2.0
-1.5
-1.0
-0.5
-3.0
0.0
dB(Sds21)
0.7 0.8 0.9 1.0 1.10.6 1.2
-38
-36
-34
-32
-30
-40
-28
freq, GHz
dB(Scs21)
m2
-30
-25
-20
-15
-10
-5
-35
0
dB(Sdd22)
m3
0.7 0.8 0.9 1.0 1.10.6 1.2
-0.14
-0.12
-0.10
-0.08
-0.16
-0.06
freq, GHz
dB(Scc22)
m4
Transmission: Balanced -> single ended Balanced port reflection
Result of Simulation - Ruwel Version D1
Eqn Sds21 = 0.707*(S(2,1)-S(3,1))
Eqn Scs21 = 0.707*(S(2,1)+S(3,1))
Eqn Sdd22 = 0.5*((S(2,2)+S(3,3))-(S(2,3)+S(3,2)))
Eqn Scc22 = 0.5*((S(2,2)+S(3,3))+(S(2,3)+S(3,2)))
(Differential mode --> single ended mode transmission)
(Common mode --> single ended mode transmission)
(Common mode reflection)
(Differential mode reflection)
m1freq=dB(Sds21)=-0.125
900.0MHz
m2freq=dB(Scs21)=-29.958
900.0MHz
m4freq=dB(Scc22)=-0.129
900.0MHz
m3freq=dB(Sdd22)=-32.660
900.0MHz
m1
Figure 3.10: Simulation result for operating contitions (50Ω single ended port,2 x 6Ω balanced port) of the balun with 300 µm spacing between the striplinesand the groundplanes. The line width is 460 µm and the line length is 46.62 mm.LCP and FR4 are used for the substrates. The insertion loss of the differentialmode to single ended mode transmission Sds21 amounts to 0.125 dB.
two prepegs the insertion loss would be significantly larger because the unwantedEVEN mode could be propagated better.
Fig. 3.11 shows the resulting multilayer buildup. For the functionality of the baluna separation of metal 5 and 6 would not be necessary. An advantage of this imple-mentation, where metal 5 and 6 are separated, is the symmetrically structure ofthe buildup. With the specified multilayer buildup now it is possible to determinethe line width and the line length exactly. The result of the simulation, which isillustrated in Fig. 3.10, is achieved with a line width of 460 µm and a line lengthof 46.62mm.
In Fig. 3.12 the 3D view of the simulation is shown.
CHAPTER3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 25
SiIC
Via
1
Pro
ject:
GS
MP
A-
Ruw
el
Pro
cess:
Meta
lization:18
Mic
ron
Copper
Foil
Fin
ish:M
eta
l1
and
Meta
l10
-G
old
pla
ting
r=4.3
,ta
n=
0.0
02
FR
4-
100
Mic
ron
Co
red
ou
ble
cla
d
FR
4-
(3x
115
Mic
ron)
300
Mic
ron
Pre
peg
211
6
ab
ou
tafte
rp
ressin
g
r=2.9
,ta
n=
0.0
2LC
P-
25
Mic
ron
38
50
Co
red
ou
ble
cla
d
FR
4-
(3x
115
Mic
ron)
300
Mic
ron
Pre
peg
211
6
ab
ou
tafte
rp
ressin
g
FR
4-
(3x
115
Mic
ron)
300
Mic
ron
Pre
peg
211
6
ab
ou
tafte
rp
ressin
g
r=4.2
,ta
n=
0.0
02
FR
4-
(3x
115
Mic
ron)
300
Mic
ron
Pre
peg
211
6
ab
ou
tafte
rp
ressin
g
Meta
l1
(Sig
nal)
Meta
l2
(GN
DP
lane)
Meta
l3
(Couple
dLin
es)
Meta
l4
(Couple
dLin
es)
Meta
l5
(GN
DP
lane)
Meta
l6
(GN
DP
lane)
Meta
l7
(Couple
dLin
es)
Meta
l8
(Couple
dLin
es)
Meta
l9
(GN
DP
lane)
Meta
l10
(Sig
nal)
Bond
Wire
Epoxy
Glu
e
0.4
mm
(befo
repla
ting)
Desig
nru
les
used
inth
ela
yout:
min
125um
meta
lto
meta
ldis
tance
min
100um
annualring
for
the
catc
hpads
r=4.3
,ta
n=
0.0
02
FR
4-
100
Mic
ron
Co
red
ou
ble
cla
d
r=4.3
,ta
n=
0.0
02
FR
4-
100
Mic
ron
Co
red
ou
ble
cla
d
r=4.2
,ta
n=
0.0
02
r=4.2
,ta
n=
0.0
02
r=4.2
,ta
n=
0.0
02
r=2.9
,ta
n=
0.0
2LC
P-
25
Mic
ron
38
50
Co
red
ou
ble
cla
d
Figure 3.11: The detailed multilayer buildup from Ruwel with LCP and FR4.
CHAPTER3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 26
CL1
(Metal 3 + 4)
CL2
(Metal 7 + 8)
Vias
GND Plane
(Metal 5 + 6)
Figure 3.12: Simulation with the ADS layout tool - 3D view.
3.4 Layout
Now the simulation model in ADS will be upgraded to a complete layout. Thefirst step is to design the connection area for the chip. The chip will be glued ongrounded metal areas. Vias below the chip lead the heat which is produced away.In this design only through vias are in use. The electrical connection betweenthe chip and the board will be achieved with bond wires. There are separatedgrounds for the driver stage and the output stage.
All control and power lines lead to the outside of the board, where they are routed
CHAPTER3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 27
D
D
d
GND via
GND via
GND via
GND via
Impedance
controlled via
Figure 3.13: To control the impedance of a via a coaxial structure is necessary.
with vias to the bottom side of the multilayer. To compensate the inductivity ofthe power lines pads are provided for capacitors. The RFin and the RFout linesare performed in 50Ω lines. The vias for this lines are implemented in 50Ω coaxialvias. They are calculated with the following equation (Fig. 3.13):
Z =173√
ε· log D
0.933 · d (3.11)
On the bottom side V CC and RFout are leading to the pads on the outside,whereas V CC has a line length of λ/4. So unwanted crosstalk at fundamentalfrequency is suppressed due to the transformation characteristic of the λ/4 line.The spacing between the V CC line and the RFout line is maximized, so thatcrosstalk is minimized. It is important that the groundplanes are cutting outbehind the RF -pads, otherwise the pads will work as capacitors. In Fig. 3.14 thetop and the bottom view of the Ruwel multilayer balun is shown.
The balun was produced in various versions. So the line length and the line widthare varying. For S-parameter measurements all versions are also produced withtest pads. An overview of the different versions is shown in Tab. 3.3.
In Fig. 3.15 a section of the profile of the Ruwel multilayer balun is shown. Thefour groundplanes and the coupled lines are clearly identifiable. Also, a via isshown in its profile. In the picture we recognize that a small lateral off-set of thelayers exists. Important is that the spacing between the line is only about 18 µminstead of the 25µm which was simulated.
CHAPTER3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 28
Figure 3.14: The top and a bottom view of the Ruwel multilayer balun. The sizeof the board is 13.4mm x 11.8mm.
CHAPTER3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 29
Version line length [mm] line width [µm] note
A1 46.62 300A1m 46.62 300 with test padsB1 46.62 350
B1m 46.62 350 with test padsC1 46.62 400
C1m 46.62 400 with test padsD1 46.62 460 result of simulation
D1m 46.62 460 with test padsE1 46.62 500
E1m 46.62 500 with test padsF1 46.62 550
F1m 46.62 550 with test padsG1 46.62 600
G1m 46.62 600 with test pads
A2 44.3 300A2m 44.3 300 with test padsB2 44.3 350
B2m 44.3 350 with test padsC2 44.3 400
C2m 44.3 400 with test padsD2 44.3 460
D2m 44.3 460 with test padsE2 44.3 500
E2m 44.3 500 with test padsF2 44.3 550
F2m 44.3 550 with test padsG2 44.3 600
G2m 44.3 600 with test pads
Table 3.3: Different versions of the Ruwel balun
CHAPTER3. BALUN IN MULTILAYER-LAMINATE TECHNOLOGY 30
0500 um
0100 um
Figure 3.15: The profile of the Ruwel multilayer balun - version B1. The heightof the board is 1.6 mm and the line width is 350 µm. A small lateral off-set of thelayers is observed. The spacing between the line is only about 18 µm instead of25µm which was simulated.
Chapter 4
Experimental results
4.1 S-parameter characterization of the balun
For S-parameter measurements specific multilayer baluns with pads for measure-ments are produced. Fig. 4.1 shows the details. This results in a 3 port singleended measurement, which can be converted into mixed mode S-parameter withthe equations 3.1 to 3.9.
To illustrate the simulation and measurement results in a smith chart, a transfor-mation of the 3-port S-parameter to a 2-port single ended S-parameter character-ization is necessary. Fig. 4.2 shows the schematic diagram for this transformation,which is conformed with the equations 3.1 to 3.9.
In Fig. 4.3 the simulation and the measurement results of Ruwel multilayer balunversion D1 is shown in a smith chart. All ports are normalized to 50Ω. It showsthat the fundamental wave of S22 is close to the desired 6Ω. For these dimensionsthe balun should transform the 6Ω balanced input into a 50Ω unbalanced output.For a good PAE of the power amplifier/balun system it is necessary that thesecond order harmonic is close to the short circuit point and the third orderharmonic is close to the open circuit point. The simulation shows that with thisdesign, the requirements for higher order harmonics can not be achieved. For this,additional arrangements are necessary.
Fig. 4.4 compares the simulation and measurement results of all produced versionsof the Ruwel multilayer balun. In the smith chart only the fundamental wave isillustrated. It shows that version D1 and D2 are close to the simulation result.Also a phase offset appears. We determined two reasons for this divergence.
The first reason is that the thickness of the high quality layer is about 18 µm afterpressing, whereas the simulation used a thickness of 25 µm. This results in a shiftof the characteristic impedance and modifies the transformation properties of theλ/4 - coupler. The consequence of this is a mismatch of impedance. Secondlyεeff , which is calculated from the simulation program, is too small. The reason
31
CHAPTER4. EXPERIMENTAL RESULTS 32
GND
GND
Signal
GND
GND
GN
D
GN
D
Signal
Sig
na
l
Figure 4.1: For S-parameter measurements specific multilayer baluns with padsfor measurements are produced. The picture shows the position of the three mea-surement pins (each with GND-Signal-GND, 200 µm pitch) for the 3-port singleended S-parameter characterization.
Balun1
2
3
50 Ohm
50 Ohm
T= 1/ 2 : 1
T= -1/ 2 : 1
Figure 4.2: Schematic diagram to transform the 3-port S-parameter to a 2-port single ended S-parameter for illustrating in a smith chart. T = turns ratio(T1/T2).
CHAPTER4. EXPERIMENTAL RESULTS 33
0.2
0.5
1.0
2.0
5.0
+j0.5
-j0.5
+j2.0
-j2.0
0
0
Ruwel D1Simulation and Measurement
S22 Simulation fo
S22 Simulation 2 fo
S22 Simulation 3 fo
S22 Measurement fo
S22 Measurement 2 fo
S22 Measurement 3 fo
Figure 4.3: Comparison of simulation and measurement results of the Ruwel mul-tilayer balun version D1.
for this is that the details of the real buildup is difficult to transfer in the usedsimulation program. Both upper reasons add to the detected divergences.
Now we consider the mixed mode S-parameter. In Fig. 4.5 simulation and mea-surement results of the differential mode to single ended mode transmission Sds21
are illustrated in case of the Ruwel D1 version and for operating conditions (50 Ωsingle ended port, 2x 6Ω balanced port). In comparison to the simulation theinsertion loss of the measurement result is greater. But the important factor isthe frequency shift of the transmission maximum, which is now about 700MHz.
Fig. 4.6 confirms this fact. In this figure simulation and measurement results ofthe differential mode reflection Sdd22 are compared at operating conditions. Thereflection minimum is also frequency shifted to about 700MHz. These frequency
CHAPTER4. EXPERIMENTAL RESULTS 34
0.2
0.5
1.0
+j0.2
-j0.2
+j0.5
0.0
Ruwel D1 simulationRuwel A1 measurementRuwel B1 measurement
Ruwel C1 measurementRuwel D1 measurementRuwel E1 measurementRuwel F1 measurement
Ruwel G1 measurementRuwel A2 measurementRuwel B2 measurementRuwel C2 measurement
Ruwel D2 measurementRuwel E2 measurementRuwel F2 measurement
Ruwel G2 measurement
Figure 4.4: Comparison of the simulation and the measurement results of allproduced Ruwel versions. The results are shown from 800MHz to 1000MHz.
shifts are also a result of the two reasons manifested before.
CHAPTER4. EXPERIMENTAL RESULTS 35
0.6 0.7 0.8 0.9 1.0 1.1 1.2-4.0
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
db(Sds21) - Simulationdb(Sds21) - Measurement
dB
(Sds2
1)
Frequency [GHz]
Figure 4.5: Ruwel D1 - simulation and measurement of the differential mode tosingle ended mode transmission Sds21.
4.2 Power amplifier module
Next, the complete power amplifier module (power amplifier and balun) is con-sidered. To characterize the balun the well known power amplifier PA2SA [seechapter 2] is used. It is mounted and bonded on the top side of the multilayer.The multilayer is soldered on a testboard. The assembled testboard carrying thePA-Module is shown in Fig. 4.7 and in Fig. 4.8. For blocking, small capacitors aresoldered directly on the multilayer and large tantal capacitors are soldered on thetestboard.
The setup for the following measurements is illustrated in [Bakalski 01]. The firstmeasurement is output power versus frequency, which is illustrated in Fig. 4.9.The supply voltage for the driver stage and the power stage is 3.5V. As well as inprevious measurements it also shows a frequency shift of output power maximumto 700MHz. In the specifications for GSM a maximum output power of 35 dBmand 50 % PAE at least is required. In this case the maximum output power of
CHAPTER4. EXPERIMENTAL RESULTS 36
0.6 0.7 0.8 0.9 1.0 1.1 1.2-35
-30
-25
-20
-15
-10
-5
0dB(Sdd22) - SimulationdB(Sdd22) - Measurement
dB
(Sdd22
)
Frequency [GHz]
Figure 4.6: Ruwel D1 - simulation and measurement of the differential modereflection Sdd22.
34 dBm is achieved by the Ruwel D2 module at 720MHz. In comparison to theD2 version, the maximum output power of version D1 is about 0.5 dB greaterand about 30MHz closer to the desired 900MHz. The line length of version D2 isabout 5% less than in version D1. In comparison to the reference balun of chapter2 (Fig. 2.8), in which an output power of 35 dBm is achieved at 3.5V, the Pout ofthe multilayer balun is 1 dB less.
Fig. 4.10 and Fig. 4.11 show the power transfer characteristic and the PAE versusinput power at 700 MHz. The supply voltage is 3.5V; respectively 4V. The figuresshow that the different versions have similar performances and confirm previousmeasurement results. The D2 version achieves 35 dBm and 43% PAE at 4 V.
The reason for the frequency shift is the same as in the section before. A furtherreason for the bad performance of the overall module is that the power amplifieris optimized for 900MHz.
A comparison with the semi-rigid line balun of chapter 2 shows Tab. 4.1, which
CHAPTER4. EXPERIMENTAL RESULTS 37
VCC
output stage
VCC
Driver Stage
VCC
Driver Stage
Power
downDB NC
RUWEL - FR4
h = 0.46 mm
er = 4.5
RF
in19.0
8.0
4R
Fout
PBC0=C1=1-2nF
C2-C4=4.7uF Tantal
C2 C3
C4
C0 C1
Figure 4.7: The multilayer balun is soldered on the testboard. The size of thetestboard is 30 mm x 30 mm.
characterizes that the output power of the multilayer balun is 1 dB less than theoutput power of the other balun. The power added efficiency is about 44% in caseof the multilayer balun, whereas with the semi-rigid line balun a PAE of 57% isachieved.
CHAPTER4. EXPERIMENTAL RESULTS 38
Figure 4.8: Picture of the assembled test buildup. Size: 30mm x 30mm
Semi-rigid line balun Multilayer balun D2at 900 MHz at 700MHz
supply voltage PAE Pout PAE Pout
3.5 V 57% 35 dBm 44% 34dBm4V 57% 36 dBm 43% 35dBm
Table 4.1: Comparison of the multilayer balun (Fig. 4.8) and the semi-rigid linebalun (Fig. 2.6) [Heinz 99]. Both measurements work with Pin = 10 dBm.
CHAPTER4. EXPERIMENTAL RESULTS 39
0.6 0.7 0.8 0.9 1.0
27
28
29
30
31
32
33
34
Ruwel D1
Ruwel C1
Ruwel D2
Outp
utP
ow
er
[dB
m]
Frequency [GHz]
Figure 4.9: The maximum output power of the modul with the power amplifierPA2SA is achieved at 700MHz. The supply voltage is 3.5V for the driver and thepower stage. Pin = 10 dBm
CHAPTER4. EXPERIMENTAL RESULTS 40
-40 -30 -20 -10 0 100
5
10
15
20
25
30
35
40
45
Outp
utP
ow
er[d
Bm
]/P
AE
[%]
Input Power [dBm]
Pout Ruwel D1PAE Ruwel D1Pout Ruwel C1PAE Ruwel C1Pout Ruwel D2PAE Ruwel D2
Figure 4.10: Power transfer characteristic of the PA-module at 700MHz. Thesupply voltage is 3.5 V.
-40 -30 -20 -10 0 100
5
10
15
20
25
30
35
40
45
Outp
utP
ower
[dB
m]/P
AE
[%]
Input Power [dBm]
Pout Ruwel D1PAE Ruwel D1Pout Ruwel C1PAE Ruwel C1Pout Ruwel D2PAE Ruwel D2
Figure 4.11: Power transfer characteristic of the PA-module at 700MHz. Thesupply voltage is 4 V.
Conclusion
In this thesis a new multilayer balun for 900 MHz has been developed and eval-uated. It consists of two λ/4 - couplers, which are implemented as broadsidecoupled striplines. For the important layer between the striplines, the new thinhigh quality substrate LCP by Rogers is used.
S-parameter measurements for the fundamental wave show that the balun trans-forms the 6Ω balanced input into a 50Ω unbalanced output. For a good PAE ofthe power amplifier/balun system, it would be necessary that the second orderharmonic is close to the short circuit point and the third order harmonic is closeto the open circuit point, which could not be achieved with this design. The mea-surement result of the transmission coefficient Sds21 shows that the frequency ofthe transmission maximum is shifted to about 700MHz.
For the PAE and output power measurements, the well known power amplifierPA2SA, which is optimized for 900MHz, was used. With this amplifier/balunmodule an output power of 34 dBm and a PAE of 44% was achieved at 700MHz.In comparison, the reference balun of chapter 2 achieves an output power of35 dBm and a PAE of 57% at 900MHz.
We determined two reasons for this divergence. The first reason is that the thick-ness of the high quality layer is about 18 µm after pressing, whereas the simulationused a thickness of 25µm. These results in a shift of the characteristic impedanceand modifies the transformation properties of the λ/4 - coupler. The consequenceof this is a mismatch of impedance. Secondly εeff , which is calculated from thesimulation program, is too small. The reason for this is that the details of thereal buildup is difficult to transfer in the used simulation program. Both upperreasons add to the detected divergences.
If a redesign is done, the simulation model should be adapted to reality better.Then, the thickness of the high quality layer should be 18 µm, the buildup shouldbe better modeled so that the calculated εeff is correct and the copper lines shouldbe none-ideal. The appendix shows that the ohmic losses are not negligible. Itshould be considered if the program ADS/Momentum is the right tool for thisjob. Also the influence of process tolerances should be analyzed.
One further goal is to minimize the whole design. This is possible by folding thelines in a better way. The size is proportional to the spacing between the lines(smaller spacing⇒ smaller line width⇒ smaller overall size). In conflict with this
41
CHAPTER4. EXPERIMENTAL RESULTS 42
goal are the ohmic losses, which are growing if the copper area will be smaller.Therefore a compromise between minimizing the module and ohmic losses has tomade.
Appendix A
Losses of the multilayer balun
The different forms of losses which appear in the multilayer balun will be consid-ered her. The losses are divided into:
• the dielectric loss
• the ohmic losses
– DC loss
– Rf loss
A.1 The dielectric loss
The simulation in chapter 3.3 with ideal (lossless) lines shows the dielectric lossesof the multilayer balun. In Fig. 3.10 these results are illustrated.
A.2 The ohmic losses
The ohmic losses divide into Rf and DC losses. Under the assumption of PAE =50 %, Pin = 10 dBm (10 mW ), Pout = 35 dBm (3.16 W ) and the line length ofthe balun of l = 46.62 mm we determine the ohmic losses as follows:
A.2.1 DC loss
The assuming DC current is IDC = 2 A, which divides symmetrical to 1 A perbrace. The area of current is ADC = 8.28 · 10−3 mm2. So the impedance resultsin
43
CHAPTERA. LOSSES OF THE MULTILAYER BALUN 44
RDC =%Cu · lADC
= 0.097 Ω, (A.1)
and the power loss per brace results in
UDC = IDC ·RDC = 0.097 V. (A.2)
A.2.2 Rf loss
R = 61
WRFin+ RFin-
RFout
R = 61
W
R = 502
W
VCCR =rf
0.324 W R =rf
0.324 W
R = 0.324Rf
W R =rf
0.324 W
Figure A.1: Schematic diagram for calculate the Rf loss.
Fig. A.1 shows the schematic diagram to calculate the Rf loss. The assuming Rfcurrent is IRf = 2 A · √PAE = 1.41 A, which divides symmetrical to 0.707 Aper brace. At 900 MHz the skin depth is about 2.6 µm and the area of current isARf = 2.5 · 10−3 mm2, which is illustrated in Fig. A.2. So, the impedance resultsin
RRf =%Cu · lARf
= 0.324 Ω, (A.3)
and the power loss per brace results in
URf = IRf ·RRf = 0.229 V. (A.4)
CHAPTERA. LOSSES OF THE MULTILAYER BALUN 45
Conductor
18
mm
460 mm
2.6 mm
Skin depth
for 900 Mhz:
Area of skin depth: A ~ 2,5 10 mmRf
-3 2
Figure A.2: The skin depth of the conductor at 900MHz is 2.6 µm. The line lengthis 0.046m.
Appendix B
Alternative Implementations
Simultaneous to the development of the Ruwel balun (FR4 + Rogers LCP sub-strate), other implementations have been realized. The following comments willgive a short overview about these developments.
The implementations use the same circuit like the Ruwel balun. However, forthe substrate layers between the striplines here Speedboard C by Gore, and theRogers 4350 is used for the other substrate layers. Produced independently bythree different enterprises (Aspocomp, Optiprint and R&D) an identical layoutwas realized. In Fig. B.1 the buildup, which was used in the process, is shown. Incontrast to the Ruwel design the stack is unsymmetrical.
In Fig. B.2, Fig. B.3 and Fig. B.4 the S-parameter measurements are presented.They show that the fundamental wave of the multilayer balun by R&D is closeto the desired 6Ω.
Fig. B.5 and Fig. B.6 illustrate the mixed mode S-parameter measurement resultsof all three implementations. They show that the transmission maximum of Sds21
is close to 900 MHz. In comparison to the Ruwel balun, here the insertion loss isgreater. The modules produced by Aspocomp and R&D have better performancesthan the one which was produced by Optiprint.
46
APPENDIX B. ALTERNATIVE IMPLEMENTATIONS 47
2.2
mils
Sp
ee
db
oa
rdC
(not
critica
l,ca
nb
eo
ther
typ
ea
sw
ell)
2.2
mils
Sp
ee
db
oa
rdC
(not
critica
l,ca
nb
eo
ther
typ
ea
sw
ell)
2.2
mils
Sp
ee
db
oa
rdC
(not
critica
l,ca
nb
eo
ther
typ
ea
sw
ell)
2.2
mils
Sp
ee
db
oa
rdC
Er=
2.6
,ta
nd
=0
.00
36
2.2
mils
Sp
ee
db
oa
rdC
Me
tal2
(GN
DP
lan
e)
Me
tal3
(Co
up
led
Lin
es)
M6
(Co
up
led
Lin
es)
eta
l
Me
tal1
0(E
mp
tyC
atc
hP
ad
s)
M1
0(E
mp
tyC
atc
hP
ad
s)
eta
l
M2
()
eta
lG
ND
Pla
ne
(can
be
om
ite
dif
no
em
pty
ca
tch
pa
ds
are
req
uire
d)
(can
be
om
ite
dif
no
em
pty
ca
tch
pa
ds
are
req
uire
d)
(ca
nb
eo
mite
dif
no
em
pty
ca
tch
pa
ds
are
req
uire
d)
Me
tal4
(Co
up
led
Lin
es)
M7
(Co
up
led
Lin
es)
eta
l
Me
tal2
(GN
DP
lan
e)
M1
0(
)e
tal
Em
pty
Ca
tch
Pa
ds
Me
tal1
(Sig
na
l)5
5u
m
M9
(Sig
na
l)5
5u
me
tal
Pro
ject:
GS
MP
A-
Asp
oco
mp,
R&
Da
nd
Op
tip
rin
tP
roce
ss:
Me
taliz
atio
n:
½o
z.
Co
pp
er
Fo
ilF
inis
h:
Me
tal1
-G
old
pla
tin
g
Bo
nd
Wire
Ep
oxy
Glu
e
0.2
1m
m(b
efo
repla
ting)
Desig
nru
les
used
inth
ela
yout:
min
150um
meta
lto
meta
ldis
tance
for
Meta
l1,
min
200um
for
the
oth
er
layers
,m
in150um
annualring
for
the
catc
hpads
2.2
10.2
SiIC
Via
1
+-
Er=
3.4
8,
tan
=0
.00
5
10
mils
Ro
43
50
Er=
3.4
8,
tan
=0
.00
5
10
mils
Ro
43
50
Er=
3.4
8,
tan
=0
.00
5
10
mils
Ro
43
50
Er=
3.4
8,
tan
=0
.00
5
10
mils
Ro
43
50
Er=
3.4
8,
tan
=0
.00
5
10
mils
Ro
43
50
Er=
3.4
8,
tan
=0
.00
5
10
mils
Ro
43
50
Er=
2.6
,ta
nd
=0
.00
36
2.2
mils
Sp
ee
db
oa
rdC
Figure B.1: Alternative multilayer buildups with Gores Speedboard C from As-pocomp, R&D and Optiprint.
APPENDIX B. ALTERNATIVE IMPLEMENTATIONS 48
0.2
0.5
1.0
2.0
5.0
+j0.2
-j0.2
+j0.5
-j0.5
+j1.0
-j1.0
+j2.0
-j2.0
+j5.0
-j5.0
0.0
S22 Measurement fo
S22 Measurement 2*foS22 Measurement 3*fo
Aspocomp D1Measurement
Figure B.2: Smith Chart from Aspocomp version C1.
APPENDIX B. ALTERNATIVE IMPLEMENTATIONS 49
0.2
0.5
1.0
2.0
5.0
+j0.2
-j0.2
+j0.5
-j0.5
+j1.0
-j1.0
+j2.0
-j2.0
+j5.0
-j5.0
0.0
.
S22 Measurement fo
S22 Measurement 2 fo
S22 Measurement 3 fo.
Optiprint D1Measurement
Figure B.3: Smith Chart from Optiprint version D1.
APPENDIX B. ALTERNATIVE IMPLEMENTATIONS 50
0.2
0.5
1.0
2.0
5.0
+j0.2
-j0.2
+j0.5
-j0.5
+j1.0
-j1.0
+j2.0
-j2.0
+j5.0
-j5.0
0.0
S22 Measurement fo
S22 Measurement 2 fo
S22 Measurement 3 fo
.
.
R&D D1Measurement
Figure B.4: Smith Chart from R&D version D1.
APPENDIX B. ALTERNATIVE IMPLEMENTATIONS 51
0.6 0.7 0.8 0.9 1.0 1.1 1.2
-4.0
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
db(Sds21) Aspocomp C1
db(Sds21) Optiprint D1
db(Sds21) R&D D1
dB
(Sds21)
Frequency [GHz]
Figure B.5: Differential mode to single ended mode transmission Sds21 versusfrequency of the different implementations.
0.6 0.7 0.8 0.9 1.0 1.1 1.2
-18
-16
-14
-12
-10
-8
-6
-4
dB(Sdd22) Aspocomp C1
dB(Sdd22) Optiprint D1
dB(Sdd22) R&D D1
dB
(Sdd22)
Frequency [GHz]
Figure B.6: Differential mode reflection Sdd22 versus frequency of the differentimplementations.
Acknowledgements
The work presented was supported by INFINEON Technologies AG, CorporateResearch, Department for High Frequency Circuits (CPR HF), Munich.
My gratitude goes to my colleague Dr. Werner Simburger for the initial ideasleading to this paper. I would also like to thank Dr. Winfried Bakalski and DINikolay Ilkov for their assistance during the whole development of this thesis.Special thanks go to Prof. Arpad L. Scholtz who supported me in the final stagesof my studies.
I would like to take this opportunity to thank my parents who helped me in anysituation during my studies.
53
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