the morphing bus: a new paradigm in peripheral interconnect bus

IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 4, NO. 2, FEBRUARY 2014 341

Morphing Bus: A New Paradigm in PeripheralInterconnect Bus

Yanzhe Cui, Student Member, IEEE, Richard M. Voyles, Senior Member, IEEE,Robert A. Nawrocki, Student Member, IEEE, and Guangying Jiang, Student Member, IEEE

Abstract— Modern digital peripheral interconnect buses aretypically described as one of the two types, serial or parallel,based on whether or not the physical data channel(s) is (are)shared across the bits of a coherent data word. Conventionalserial and parallel buses operate in a time-multiplexed mode,allowing access to only one peripheral device at a time. PCIex-press expanded this simple bifurcation by combining serial datachannels with simultaneous access to multiple peripheral devices(or multiple regions of the same peripheral). Moving to thatnontime-multiplexed mode opened a new dimension by which busarchitectures could be classified. Under this taxonomy of serialversus parallel and time-multiplexed versus nontime multiplexed,our Morphing Bus presents a new paradigm that fills theparallel, nontime multiplexed interconnect niche. Furthermore,the Morphing Bus eliminates the notion of an intermediate dataformat and thereby obviates the need for bus interface circuitry.Instead of a common data format to which all the sensorsand actuators are translated, the Morphing Bus transforms—or morphs—its signal lines to meet the needs of the connectedsensors or actuators. For digital sensors and actuators, thismorphing is achieved through a field-programmable gate arrayon the processor side of the bus. As programmable devices beginto incorporate analog signal paths, the Morphing Bus pavesthe way for integrating analog and digital signals into a singlebus paradigm. The efficacy of the Morphing Bus is verified viaimplementation on a miniature robot and the bandwidth of thebus implementation is experimentally characterized. Its uniquephysical I/O stack in the form of a helical structure providesefficient cooling and power distribution for compact embeddedsystems in addition to the novel interconnect paradigm.

Index Terms— Bus interface circuitry, bus specification, field-programmable gate array (FPGA), peripheral interconnect.

I. INTRODUCTION

ABUS is the mechanism by which the CPU communicateswith internal components, such as memory and video,

and external peripherals, such as sensors and actuators. Busesevolved to provide a compact and deterministic communica-tion mechanism that simplifies and modularizes design throughstandardization. Therefore, because the use of bus increases

Manuscript received October 30, 2012; revised April 27, 2013; acceptedJune 27, 2013. Date of publication September 10, 2013; date of current versionJanuary 30, 2014. This work was supported in part by the National ScienceFoundation under Grant MRI-0923518, Grant CNS-1042710 and Grant IIS-0938196, and the NSF Safety, Security and Rescue Research Center andI/UCRC. Recommended for publication by Associate Editor P. Franzon uponevaluation of reviewers’ comments.

Y. Cui, R. A. Nawrocki, and G. Jiang are with the Department of Electricaland Computer Engineering, University of Denver, Denver, CO 80208 USA(e-mail: [email protected]; [email protected]; [email protected]).

R. Voyles is with the College of Technology, Purdue University, WestLafayette, IN 47907 USA (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCPMT.2013.2273663

system versatility by allowing devices to be added or removedeasily, systems are typically designed to use the bus to connectall kinds of devices or modules.

As CPU performance increased, bus performance became abottleneck. This, in turn, drove designers to optimize buses forspecialized functions, resulting in a proliferation of bus spec-ifications. Even though the wide variety of bus types and busspecifications available to the designer allows impressive gainsin system performance, it actually increases system complexityas the majority of modern systems incorporate a multitude ofbus types for different purposes. Today’s computer systemsoften use multiple buses optimized for different functions,such as memory access, multiprocessor communication, andperipheral interconnect. It is not uncommon to even employ afew different bus types for each category.

Despite this diversity, all buses have historically operatedunder the same basic paradigm: the implementation of auniversal shared conduit for information based on a standard-ized data format that is optimized with respect to some ratecriterion. Sharing is almost universally achieved through time-division multiplexing (TDM), which allows only one deviceto use the bus at any given time. The standardization of thecontrol, timing, and arbitration of the shared data conduitenable the development of very efficient, yet very specializedbus architectures.

An unfortunate side effect of a standardized data formatis that it necessitates bus interface circuitry on both sides ofthe bus. In other words, desired signals have to be encodedinto and decoded out of the bus protocol. These two issues,namely buses becoming more specialized and the need forspecific circuitry on both the host and the client side, led usto take a fresh look at the bus paradigm. Motivated by our lab’sfocus on miniature real-time and embedded systems, we beganinvestigating alternatives to current peripheral interconnectbuses with smaller footprints. Specifically, as we have afrequent need to connect sensors and actuators that interfaceour computer systems with the physical world (cyber-physicalsystems), we conceived the idea of sensors and actuatorsthat could plug directly into a bus with no interface circuitrywhatsoever. In this approach, the bus signals would have tomorph for accommodating the requirements of the connectedsensor or actuator.

At the beginning of this paper, our goal was to develop abus mechanism that avoided TDM and gave every sensor andactuator a direct conduit to the CPU. In fact, we wanted thebus to optimize itself for the specific sensor or actuator thatwas plugged in, hence the name, Morphing Bus. The signal

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342 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 4, NO. 2, FEBRUARY 2014

lines of our bus morph to the needs of a particular devicethat is connected directly to it—neither interface circuitrynor an arbitrator is necessary. The Morphing Bus provides adedicated conduit between the sensor and the sensor-specificdata converter required to present data in a binary formatamenable to consumption by the CPU.

To the best of our knowledge, this is the first paper todevelop a bus that: 1) avoids the use of an intermediatedata format through the bus-signal morphing process, whichpermits sensors and actuators to connect directly to the bus;2) eliminates bus interface circuitry and moves the converter tothe CPU side, simplifying design on the peripheral side of thebus, which eases the burden on compact embedded systems;and 3) obviates arbitration by employing nontime-multiplexedpoint-to-point connections.

We initially proposed the idea of the Morphing Bus anddemonstrated a prototype in [1]. With this preliminary work,in this paper, we claim the following new contributions.

1) Exploration of a bus taxonomy for peripheral intercon-nect from the perspectives of time and space multi-plexing and revealing the potential new bus paradigmwithin it.

2) Provision of the Morphing Bus specification with respectto printed circuit board (PCB) layout dimensions, con-nector choice, and electrical signal characteristics.

3) Consideration and exploration of details of plug-and-play (PnP) functionality on the Morphing Bus.

4) Implementation of a miniature robot that employs theMorphing Bus.

5) Investigation of electrical signal characteristics and limi-tations of the wedge-based form factor of Morphing Busspecification.

The rest of this paper is organized as follows. Section IIintroduces the details of fixed bus signals for conventionalbuses and adaptive bus signals for the Morphing Bus.Section III presents the proposed expanded bus taxonomythat reveals this as a new bus paradigm. Sections IV and Vdescribe the implementation details of the Morphing Buswith its specifications. Section VI presents a tool, namedMorphAhead, that allows quick and easy configuration of thesystem before deployment by supporting static reconfigurationof the Morphing Bus. Section VII demonstrates the validity ofthe Morphing Bus and MorphAhead through experiments toconstruct a unique helical structure miniature robotic systemwith the Morphing Bus. Moreover, the signal frequency andthe number of wedges on the Morphing Bus are analyzed.Section VIII concludes this paper.

II. BUS-SPECIFIC SIGNALS

For sensors and actuators, which can be generically referredto transducers, the native signal format is not recognizable bythe CPU directly. Thus, some types of converter are requiredto convert the data format of the transducer to that which isreadable or writable by the CPU. For example, a dc motoramplifier transduces a current command from the CPU to atorque at the motor shaft. The input to the motor amplifier,however, must be converted from the n-bit number computed

Sensor/Actuator

ConverterBusInterface

I/O Side of the Bus

CPUBusInterface

CPU Side of the Bus

Conventional BusTransducer-Specific

SignalsCPU-Recognizable

Signals

Fig. 1. Conventional peripheral buses gather information through interfacecircuitry.

by the CPU to a pulsewidth-modulated (PWM) signal from0% to 100%. Likewise, a quadrature shaft encoder transduceschanges in angular position into a pair of pulse streams, whichmust be converted by an encoder counter into an n-bit numberfor the CPU.

All peripheral buses with which the authors are familiar putthe converter on the peripheral side of the bus and define abus-specific data protocol—an intermediate data format—totransfer the converted signal over the bus to the CPU. Fig. 1shows this process. In the case of a shaft encoder, the sensorproduces a native output of quadrature pulse streams on the I/Oside of the bus (Fig. 1), which is converted to an n-bit numberrepresenting net rotation by the converter. The bus interfacecircuitry then packages the converted value into a time-,data-, and arbitration-sensitive protocol for transfer across thebus to the CPU side. This bus-specific protocol requires a businterface circuitry on both sides of the bus for both encodingand decoding of the data.

As illustrated in the above-mentioned case, we know thatto adapt the standardized bus-specific signals, the converterand bus interface circuitry on the peripheral side of the busare essential. This increases the board design complexity andlimits peripheral connection flexibility. Moreover, it enlargesthe PCB; such a solution is not suited for compact embeddedsystems. To make up for the drawbacks of conventional busesbrought about by bus-specific signals, the sensor/actuator-specific signals should be used directly.

The Morphing Bus proposed in this paper uses thetransducer-specific signals directly. Instead of fixed bus-specific signals, to which all the sensors and actuators mustconform, a bus that adapts—or morphs—its signal lines tomeet the needs of the connected sensors or actuators couldprovide demonstrable benefits. Fig. 2 shows a block diagram ofthis process. As shown in the case of a shaft encoder, the nativeoutput of quadrature pulse streams can be transferred throughthe bus directly without using the bus interface circuitry topackage the converted signals and arbitration information.Without the need for an intermediate data format, the convertercan be moved to the processor side of the bus from the periph-eral side, further simplifying the traditional I/O card design.This allows the converter to be dynamically implemented inthe programmable hardware [field-programmable gate array

CUI et al.: NEW PARADIGM IN PERIPHERAL INTERCONNECT BUS 343

Sensor/Actuator

I/O Side of the Bus

Converter CPU

CPU Side of the Bus

Morphing Bus

Fig. 2. Morphing Bus forces the bus signals to conform to the device,eliminating the bus interface circuitry.

PCIISAVMEbus

CANUSBEthernet

Parallel Serial

Fig. 3. Taxonomy of conventional serial and parallel buses.

(FPGA) in the current implementation] on the CPU side ofthe bus, so an n-bit number representing net rotation fromthe converter can be generated. This easily paves the way formixing analog and digital signals on the bus as programmableanalog hardware begins to complement the programmable dig-ital hardware already available (see the Xilinx Virtex-7 seriesof mixed-signal FPGAs, as an example of the future of mixed-signal programmable hardware [2]). In addition, peripheralscan be plugged into the bus directly without any bus interfacecircuitry. Such prudent design increases the flexibility of thebus as well as decreases the amount of space used.

III. BUS TAXONOMY

Engineers commonly consider only two broad classes ofbuses: 1) serial and 2) parallel, as shown in Fig. 3. In case ofserial buses, such as controller area network (CAN) bus [3],universal serial bus (USB) [4], and Ethernet [5], transmissionis typified by all the bits of a coherent data word being sentsequentially on the same channel (wire), as shown in Fig. 4(a).In parallel bus cases, such as industry standard architecture(ISA) bus [6], VME bus [7], and peripheral componentinterconnect (PCI) bus [8], transmission is typified by multiplebits (usually multiples of eight bits) sent simultaneously ondifferent channels (wires), as shown in Fig. 4(b). Parallelbuses have a wider data path than serial buses and cantherefore transfer data in words of one or more bytes at atime. Conceptually, because all the bits arrive simultaneously,there is generally a speedup in the parallel transmission bitrate over the serial transmission bit rate. In practice, thesimplicity of the serial channel allows for greater optimization,which can lead to increased overall data transmission rate.

All of the mentioned serial and parallel buses rely onTDM to share the data channel. Time multiplexed effectively

Serial Bus Interface

Processor

Bus InterfaceDev1

Bus Interface

Dev2

Dev1 Data[1]

Dev1 Data[n]

Dev2 Data[0]

Dev2 Data[1]

Dev2 Data[n]

Dev1 Data[0]

……

(a)

Parallel Bus Interface

Processor

Bus Interface

Bus InterfaceDev2

Dev1

Dev1Data[0]

Dev2 Data[0]

Dev1Data[1]

Dev2 Data[1]

Dev1Data[n]

Dev2 Data[n]

…

(b)

Fig. 4. Two data transmission modes of buses. (a) Serial bus. (b) Parallelbus.

Mul�-Serial Bus Interface

Processor

Bus InterfaceDev2

Dev2 Data[0]

Dev2 Data[1]

Dev2 Data[n]

Bus InterfaceDev1

Dev1 Data[0]

Dev1 Data[1]

Dev1 Data[n]

… …

Fig. 5. Multiserial data transmission.

means that different time slots are used to convey differ-ent data streams [9]. The emergence of PCIexpress (PCIe)[10], [11], however, expanded the concept of conventionalserial or parallel buses by effectively eliminating TDM. PCIe isa monolithic type of bus that dynamically allocates a plethoraof point-to-point serial buses between different subsystemsso that each one can maintain its unbroken data streamsimultaneously. This is shown in Fig. 5. These serial datastreams are not broken up in time, allocating a time slot to eachdevice; hence, they are nontime-multiplexed. This representsan important departure for bus architectures and expands theabove-listed taxonomy, as shown in Fig. 6.

For the purposes of symmetry, we relabeled the parallel andserial columns of the taxonomy in Fig. 6 as space-multiplexedand nonspace-multiplexed, respectively. The channels of serialand parallel buses that transfer data represent the spatiallayout of the bus. Analogous to time multiplexing, a space-multiplexed bus is one in which different space slots are usedto transmit different data channels. Hence, parallel buses arespace multiplexed and serial buses are nonspace multiplexed.As previously noted, PCIe is neither time multiplexed norspace multiplexed.

The taxonomy in Fig. 6 highlights an important point:no bus architecture occupies the lower left quadrant. PCIe,in fact, is a multiserial bus. Thus, the empty quadrant


ISAPCIVMEbus

PCIe

Space Mul�plexing

Tim

e M

ul�

plex

ing

Mul�plexed Not Mul�plexed

Mul

�ple

xed

Not

Mul

�ple

xed

USBCANEthernet

Parallel Serial

Fig. 6. Expanded taxonomy, including PCIe, with symmetric nomenclaturefor multiplexing.

Morphing Bus - Converter

Processor

Dev1

Dev1 Data[0]

Dev1 Data[1]

Dev1 Data[n]

Dev2

Dev2 Data[0]

Dev2 Data[1]

Dev2 Data[n]… …

Fig. 7. Multiparallel bus: Morphing Bus.

of the bus taxonomy should represent a multiparallel bus,meaning space multiplexed and nontime multiplexed. TheMorphing Bus, described here, is such a bus. Each bit ofthe data word of each sensor or actuator is assigned to aseparate wire that is dedicated to a device. Meanwhile, theprocessor can access different devices simultaneously. Overall,the Morphing Bus has multiple simultaneous channels thatdeliver coherent data words instantaneously across the (physi-cal) media. Fig. 7 shows how the Morphing Bus transmits dataamong the peripherals. Fig. 8 shows the expanded bus taxon-omy that includes this new bus paradigm—the Morphing Bus.

IV. MORPHING BUS IMPLEMENTATION

The Morphing Bus is nontime multiplexed; each peripheralis given a dedicated, point-to-point connection from the CPUto the transducer. To maintain a uniform interface, the periph-eral cards, which are referred to wedges, are daisy chainedtogether for uniform signal routing. Each wedge has electricalconnectors at both ends. All the wedges provide the samephysical interface to the preceding and the succeeding stagesby routing unused bus signal lines through the wedge. Giventhe type and number of sensors/actuators serviced by eachwedge, unused signal lines are consumed by the wedge andare morphed into the transducer-specific signals as required.Each wedge uses as many signal bits of the bus as requiredto support the sensors or actuators on that board. The signalsthat are not used on the individual board are passed throughto the board of the next stage. Through the promotion of the

Parallel Buses:ISAPCIVMEbus

Mul�-Serial:PCIexpress

Mul�-Parallel:

Space Mul�plexing

Tim

e M

ul�

plex

ing

Mul�plexed Not Mul�plexed

Mul

�ple

xed

Not

Mul

�ple

xed

Morphing Bus

Serial Buses:USBCANEthernet

Fig. 8. Expanded taxonomy with Morphing Bus fitting in.

first unused signal line of the wedge input connector to thefirst pin of the output connector, the signals are passed in away such that the next board will use the first signals on theMorphing Bus as if they were connected to the first pins onthe base board connection. By passing the unused signals inthis way, each board does not need to know which pins theother boards are connected to.

When a new peripheral is added to the current system,the CPU only needs to know that the signals associatedwith the sensor or actuator can be configured into the FPGApinout. Similarly, if the peripherals currently in the system areswapped, the CPU needs to know which peripheral was takenout and what it was replaced with, then it can reconfigure theFPGA pinout for the newly added wedge. This configurationprocess is the static reconfiguration. A configuration tool tosupport this process is presented in Section V.

Fig. 9(a) shows an example of how the Morphing Bus con-nects each peripheral together. The input lines to a peripheralboard are used as follows: six lines are dedicated to powerand ground. Those are common to all boards and as a result,are taken in all of the wedges. A camera plugged into theCPU uses a required number of lines and the rest of the linesare transferred to the start of an output connector (green). Themotor driver board (blue) and the ZigBee board (red) use twoof these lines, respectively, and pass the remaining lines in asimilar fashion. Thus, the CPU pins are assigned sequentiallyin the same order that the devices are being plugged in. If thepositions of these three boards in the chain are swapped, theI/O pins of the CPU connected to each peripheral will differ,but overall the same number of pins or the same I/O will bereused, as shown in Fig. 9(b).

V. MORPHING BUS SPECIFICATION

One of the goals in the design of the Morphing Bus wasto allow it to work for any kind of systems regardless of theCPU and peripheral, and to be able to handle all the differenttypes of I/O that are attached to the system. To achievethis goal and help the user to configure the Morphing Bussuccessfully, we have considered the following specificationsfor the Morphing Bus.


CameraCircuitry

Motor Driver

Circuitry

ZigBeeCircuitry

Peripheral 1

Peripheral 2

Peripheral 3

BaseboardFPGA

Power MotorConverter

CameraConverter

ZigBeeConverter

(a)

BaseboardFPGA

Power MotorConverter

CameraConverter

ZigBeeConverter

CameraCircuitry

Peripheral 2

Motor Driver

Circuitry

Peripheral 3

ZigBeeCircuitry

Peripheral 1

(b)

Fig. 9. Configuration diagram for Morphing Bus. (a) When the peripheralsare plugged into the base board, they use some pins for the componentsupported; the rest are routed through successive boards are plugged intoprevious ones, forming a chain and all having direct connections to the baseboard CPU. (b) Same peripherals used but the order of connection chain ischanged.

A. Morphing Bus Wedge

The hexagonal wedge design dictates the fundamental unitof measure for the Morphing Bus: the 60° single wedge.

Fig. 10 specifies the single wedge shape of the boardand the positioning of the connectors and mounting holes.The preferred reference for locating the connector on a wedge

60 degrees

34.5

15.5

4.924.92

23.5123.51

Fig. 10. Single wedge size and positioning of connectors and mountingholes.

120 degrees

34.5 34.5

23.51 23.51

4.92

10.72

10.72

4.92

31Fig. 11. Double wedge size and positioning of connectors and mountingholes.

Fig. 12. Component clearance heights for both single and double wedges.

is the mounting hole. The distance to pin 1 is also exact forplacement.

The double wedge covers 120°. To maintain consistencybetween the single and double wedges, they have the sameconnector footprint but the double wedge rotates the J2 con-nector another 60°. The only point we need to consider is thatthe double wedge has one more mounting hole than the singlewedge. Fig. 11 specifies the double wedge shape of the boardand the positioning of the connectors and mounting holes.To allow for a double-helix arrangement of two intertwinedMorphing Bus stacks, the component heights are shown inFig. 12.

For each wedge layout, there is no new PCB technol-ogy required, standard FR4 four-layer stackup is chosen.The copper trace is with 1.2-mil thickness (1/2-oz copper


Fig. 13. Morphing bus wedges: a single wedge is used to connect a ZigBeeand a double wedge is used to connect two channel motors.

Fig. 14. Spiral structure with wrapping around and the side view of spiralstructure.

plated) and 8-mil width for the Morphing Bus signals arethe default standard routing rules. The largest trace length ofthe Morphing Bus is 1540 mil. Therefore, by combining themaximum contact resistance 0.05 � of each DF12 connector,based on the equation in [12], we set the Morphing Bus signaltrace resistance target for each wedge is 0.25 �.

Fig. 13 shows the actual wedges of the Morphing Bus,called cheese wedges. Fig. 14 shows a spiraling staircasewhen the wedges are stacked up. In this assembling style,air flows from the base upward and follows the path alongthe spiral, cooling the integrated chips on every wedge. Thewhole structure can be enclosed in a wrap to maintain rigidityand increase airflow. If excessive cooling is required, thewrap can be made from a thermally conductive materialand the various boards can be heat sinked to the wrap forproviding additional conductive cooling. This is advantageousfor packaging peripherals into a compact embedded systemand makes the system more robust to overheating.

Fig. 15. Morphing Bus DF12 connector.

B. Morphing Bus Connector

Considering the character of compact embedded systems,the DF12 series connector was selected because of its smallerfootprint and the available stacking heights, as shown inFig. 15 [13]. This connector daisy chains the Morphing Busand allows additional wedges to be stacked in a spiral.

The DF12 series connector provides stacking heightsbetween 3.0 and 5.0 mm. Having multiple stacking heightsallows for different wedge sizes (single wedge and doublewedge) because the stacking height can be increased toaccount for the extra width the multislice wedge takes up.The connector width is also important because of the heightconstraints. The components on the wedges can only be of acertain height or the wedge pieces will not fit together properlywhen connected together in the spiral design. The DF12 seriesconnectors have a 0.5-mm terminal pitch. This size is smallenough to ensure a large number of pins can be used, butstill large enough to allow for routing of all the signals on afour-layer board.

For the current design of the Morphing Bus, we chose a50-pin connector as it satisfies most of miniature robot con-straints. We, however, acknowledge that for more complexsystems that require more components, this could present awedge number limitation. This constraint could be overcomeby changing a larger connector with more pins, but the stackelectrical constraints and signal property constraints should bereferred in Sections V-C and VII-C.

C. Electrical Specifications

The DF12 has a 0.3 A per pin current rating [13]. Thisis another important factor that needs to be considered whencreating the individual peripheral wedge based on the Mor-phing Bus. Wedge needs to be designed such that the currentdraw does not exceed the limited current of the connectors.For typical wedges, this current limit should not be an issue,as the current draw for each wedge should not exceed about6.5 mA. Assuming each wedge takes about two or four signals,there would be enough room to add 15 to 20 wedges onto theMorphing Bus. If more current is needed for an individualwedge, the wedge will need to have its own power supply,such as the motor wedge needs to be driven by an externalpower source because of the current requirements.

D. Utility and Signal Lines

At this stage, the utility lines of the Morphing Businclude 3.3 V, 5 V, and ground power lines. These lines are


Fig. 16. Using two extra lines to achieve PnP function.

the same on each wedge, located on the first six contacts of thebus. Unlike conventional buses, in which signal lines includeaddress, control, and data for the bus, the signal lines of theMorphing Bus only include data lines. Because the MorphingBus is a multiparallel bus, and because of its point-to-pointconnection character as mentioned earlier, each wedge doesnot need the address assigned by the CPU dynamically, so theMorphing Bus does not need the address lines. This is theadvantage of the Morphing Bus over other busses currentlyused for embedded systems. The control lines are mainly forthe arbitration of a bus, but the Morphing Bus does not requirearbitration, because it is nontime multiplexed.

E. PnP Functionality

The Morphing Bus, as we have implemented it, does notprovide PnP functionality. We chose not to implement PnPbecause it requires bus interface circuitry, the removal of whichwas a key aspect of our development effort. However, this wasjust an engineering choice to create a very streamlined andelegant bus. The new multiparallel bus paradigm, describedin Section III, is not dependent on this detail. Therefore, it ispossible to implement PnP functionality in the Morphing Bus.

There are many ways to implement PnP in the MorphingBus, and we sketch out a simple example here. Perhaps themost straightforward method is to daisy chain identification(ID) signal lines through the wedges. Daisy chaining allowseach wedge to intercept a query packet from the base boardand either reply to the base board or forward the query to thenext wedge. Two additional unidirectional signal lines, onefor ID transmit and one for ID receive, can be added to theutility bus that passes straight through the entire wedge stack,similar to the power and ground lines. The PnP needs thespecific query circuitry on the peripheral side of the bus and

End PnP query

Commanderreceive ACK from

1st peripheral?

Send queryrequest from PnP

commander ofbaseboard

Send markinformation to the

1st periperal

Y

N

1st peripheral markitself and transferquery request to

the next peripheral

Commanderreceive ACK from2nd peripheral?


2nd peripheral

Y

N


Nth peripheral

Repeat the same transfer,receive, mark processesas 1st and 2nd peripherals

till Nth peripheral

Fig. 17. Whole PnP process for peripherals on the Morphing Bus.

arbitration part on the CPU side of the bus. One line of thePnP is used to transmit the command from the PnP commanderin the base board; another line is used to receive the responsefrom the different peripherals. Fig. 16 shows a conceptual wayin which the problem can be satisfactorily addressed.

Fig. 17 shows the specific recognition and arbitrationprocesses. Assume there are N peripherals on the bus. First, thePnP commander sends the query request to the first peripheral.If the commander does not receive the acknowledgement(ACK) from their first peripheral, it will resend the queryrequest to it until it receives the ACK. After the commanderreceives the ACK from the first peripheral, it will send themark information to this peripheral, meaning this peripheralis the first. Second, after the first peripheral receives the mark,it will transfer the query request from the commander to thenext peripheral. The ACK and mark process are the same asthe first peripheral, so the second peripheral will receive themark information from commander as well. Third, the transferprocess between successive peripherals will be repeated until


Start

Write ImplementationSpecific Data

(VHDL & Device Dependent)

Read Module from List

Add Modules According toConfiguration Requirement

Read and ParseVHDL Specification of

Different Modules

Morphing Bus Pin Mappingfrom Database

(Device Dependent)

Generate .ucf file withabove Information

Stop

Fig. 18. Software configuration flow chart.

the Nth peripheral receives the mark information from thecommander. This shows that the whole PnP query process hascompleted.

VI. MORPHING BUS CONFIGURATION

To simplify system configuration and provide the staticreconfiguration for the Morphing Bus, we have designed anautomating configuration tool called MorphAhead.

MorphAhead contains a database containing a library ofmodules coded in hardware description language (HDL) for-mat that have been individually compiled and tested. Thedevices are connected to the bus before deployment, andthe order in which they are connected can be selected. Thisinformation is used to generate a top-level system designfile and a user constraint file. MorphAhead automates thiscumbersome task that otherwise would have to be performedmanually. The flowchart in Fig. 18 shows the working of thetool in generating the configuration files.

Fig. 19 shows the graphical user interface of MorphAhead.It consists of two panels. The left panel displays the listof available device types that can be connected. The right

Fig. 19. MorphAhead GUI.

panel lists specific devices that can be connected to the busaccording to the user configuration requirement. Modules canbe selected from the database and added to the current busconfiguration. By clicking the add device button, new modulescan be added to the device database and the modified deviceslist can be saved through the save devices button. The generatebutton can help the user produce the top-level design file .vhdand the pin mapping .ucf file, as well as the port maps thatcan be imported in Xilinx Integrated Software Environmentdevelopment environment.

VII. EXPERIMENT AND VERIFICATION

To verify the functionality and the feasibility of the Mor-phing Bus, we have implemented the Morphing Bus on aminiature robotic system—TerminatorBot [14], [15]. More-over, using MorphAhead, the benefit of the Morphing Busabout reconfiguration efficiency with respect to reduction ofconfiguration time is illustrated.

A. Morphing Bus in TerminatorBot

The Morphing Bus is currently being designed for use inTerminatorBot, shown in Fig. 20, which is a soda-can-sizedrobot designed for search and rescue deployments. The baseboard contains the Virtex-4 FPGA, Platform Flash program-mable read-only memory to store the initial configurationfor system bootup, 32 MB of RAM, universal asynchronousreceiver/transmitter, and connectors to start off the bus [16].

The peripheral boards, such as motor wedge, ZigBee wedge,camera wedge, etc., are stacked up and take the form ofa spiraling staircase. The whole structure is enclosed in aplastic wrap (cover) to maintain rigidity. For this version ofTerminatorBot [17], we used a 50-bit Morphing Bus. Threemotor wedges, one ZigBee wedge, and one camera wedgewere installed on the bus. The motor wedges took PWMoutputs and provided encoder counter inputs. The ZigBeewedge had four serial peripheral interface serial signals andone reset signal. The camera wedge used two I2C signals andeight data lines. After these peripherals were connected, therewere still six pins available on the bus, which could use othersensor wedges such as gyroscope and accelerometer.

Each dc motor employed in TerminatorBot is a combina-tion of a sensor (quadrature shaft encoder) and an actuator(motor shaft). Therefore, to attest the proper operation of


(a) (b)

(c)

Fig. 20. TerminatorBot Morphing Bus spiraling structure. (a) FPAG baseboard. (b) Five wedges are connected to the base board, build up a chainwhere every wedge is connected to the previous. (c) Whole TerminatorBotusing Morphing Bus.

the Morphing Bus, we constructed TeminatorBot with wedge-based Morphing Bus and designed a series of tests centeredon TerminatorBot locomotion. We choose the novel andmechanism-specific gaits of TerminatorBot—swimming gaits.This movement is similar to the breaststroke in swimming butis used on dry land only. Swimming gaits are characterized bystances with the arms splayed out to the sides and a full stridethough much of the range of motion of the shoulder joints. Asshown in Fig. 21 of a new TerminatorBot with the MorphingBus, they are a series of cycles, whose exact trajectory isdetermined by gait-specific parameters. The locomotion stepsand positions are corresponding to our design specification,so the Morphing Bus is feasible to applicable scenario inminiature robotics.

B. Efficient Reconfiguration

We connected the modules in various permutations. Then,using MorphAhead, we generated the user constraint andtop-level files. With these files, we programmed the FPGAand tested that all the peripherals on the bus were workingas expected for the different device orderings. The user isnot required to write any HDL code, as the entirety ofthe program is automatically generated. Therefore, the toolfrees up a significant amount of time and effort (30 s withMorphingAhead versus 10 min without MorphingAhead) thatit would otherwise have taken to configure the Morphing Bus.By simplifying this process, robotic operators on the field cannow rapidly deploy robots with different configurations, evenif they may not know about FPGA reconfiguration.

b a

d c

f e

Fig. 21. TerminatorBot constructed by the Morhing Bus locomoting using aswimming gait. (a) and (f) show a starting point to reference forward motionusing the black line.

C. Signal Frequency and Wedge Limitation

An embedded system places a size limiting constraint onthe implementation. This explicitly translates into maximumnumber of wedges (peripheral components) that can be used.Because of the size limitation as well as the typical maximumnumber of peripherals used, in our testing TerminatorBotenvironment, the number of wedges was chosen to be seven.To obtain the maximum bit rate of the Morphing Bus, wehave conducted a series of experiments aimed at monitor-ing signal fidelity across multiple connected wedges. Theintent for the Morphing Bus is to be used for connectingperipheral components, such as pressure sensors, motors, orlow-resolution cameras, that typically do not operate at highbit rates (<100 kbps or 50 kHz), though encoder countersoften allow signals up to 4 MHz. As such we have analyzedthe performance of the Morphing Bus for bandwidths of100 Hz–20 MHz. For measurement purposes, the input signalwas sinusoidal with a magnitude of 5 V peak to peak (majorityof peripheral components use 5 V signals).

The values of wedge resistance and capacitance limit theperformance of the Morphing Bus, such as the magnitude andthe phase shift of the signal. The resistance and capacitanceof seven wedges of the Morphing Bus, measured at 5 V,were 1.5 � and 4.9 nF, respectively. These results are closelymatched by the values obtained from analysis of the Bode plotshown in Fig. 22.


Fig. 22. Bode plot of the Morphing Bus constructed for sinusoidal signal inthe amplitude of 5 V.

Further analysis of the Bode plot reveals that for frequenciesof up to 50 kHz (the equivalent of 100 kbps), there is nonoticeable change in the amplitude nor the phase angle. Forfrequencies up to 500 kHz (1 Mbps), the output amplitudedecreases up to 2% with phase of less than 5°. Increasing thesignal frequency to 3 MHz (6 Mbps) results in output signalattenuating approximately 3.5% with corresponding phase of10°. At a frequency of 10 MHz (20 Mbps), the output signalsuffers a loss of 6% with a phase change of just under20°. Considering the maximum stack size of the MorphingBus is 21 wedges (at only two pins per wedge), a veryconservative bit rate of 6 Mbps would still be compatible withthe performance of presently used busses such as I2C [18],which is one of the most commonly used busses for sensorsin the embedded systems area. 20–40 Mbps is well within the45° 3-dB margins in most rules of thumb for most practicalMorphing Bus stacks.

VIII. CONCLUSION

This paper describes the Morphing Bus, a new bus spec-ification based on a novel multiparallel bus paradigm. TheMorphing Bus permits multiple simultaneous data channelsto different peripheral devices; as such, it is a nontime-multiplexed standard. Moreover, because it permits data bitsthat can be sent through multiple wires in one channel simul-taneously, it is a space-multiplexed standard. Furthermore, theMorphing Bus is designed in such a fashion that it does notrequire a separate bus interface circuitry on the peripheralside. Instead, the conversion logic is incorporated into the bus

interface only on the processor side, which ensures that theperipherals can be directly connected to the bus. This prudentdesign paves the way for integrating analog and digital signalsinto a single bus paradigm.

A configuration management tool, MorphAhead, wasdesigned to simplify the task of setting up the system. Theconfiguration setup ensures that each device is correctly iden-tified and the appropriate signal processing can be performedinside the FPGA. This obviates the need for interface logic atthe sensor end.

To verify the functionality and the feasibility of the Morph-ing Bus, we have implemented the Morphing Bus on Termina-torBot. Moreover, we verified the simplicity of the use for theMorphing Bus by showing that the operations such as adding,removing, or swapping peripherals can be performed withoutprior programming experience. Finally, we have determinedthat the bit rate of our Morphing Bus implementation, fit withseven wedges, is at least 20 Mbps.

ACKNOWLEDGMENT

The authors would like to thank C. D’Souza, J. Huff,G. Edelstein, Prof. R. Whitman, and I. Smith from theUniversity of Denver. The authors would also like to thankXilinx for the donation of license and boards.

REFERENCES

[1] C. D’Souza, B. H. Kim, and R. Voyles, “Morphing bus: A rapiddeployment computing architecture for high performance, resource-constrained robots,” in Proc. IEEE Int. Conf. Robot. Autom., Apr. 2007,pp. 311–316.

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[9] C. M. White, Data Communications and Computer Networks: A Busi-ness User’s Approach, 7th ed. Boston, MA, USA: Course Technol.,2013.

[10] D. A. R. Budruk and T. Shanley, PCI Express System Architecture.Reading, MA, USA: Addison-Wesley, 2004.

[11] M. Ravindran, “Extending cabled PCI express to connect devices withindependent PCI domains,” in Proc. 2nd Annu. IEEE Syst. Conf., Apr.2008, pp. 1–7.

[12] (2013, Apr. 19). PCB Trace Resistance Calculator [Online]. Avail-able: http://circuitcalculator.com/wordpress/2006/01/24/trace-resistance-calculator/

[13] 0.5 mm Pitch SMT Board to Board Connector. Hirose, Torrance, CA,USA, 2012.

[14] R. Voyles, “TerminatorBot: A robot with dual-use arms for manip-ulation and locomotion,” in Proc. IEEE ICRA, vol. 1. Apr. 2000,pp. 61–66.

[15] R. Voyles and A. Larson, “TerminatorBot: A novel robot with dual-use mechanism for locomotion and manipulation,” IEEE/ASME Trans.Mechatron., vol. 10, no. 1, pp. 17–25, Feb. 2005.

[16] UG210(V 1.5.1) ML405 Evaluation Platform, User Guide, Xilinx, SanJose, CA, USA, 2008.


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[18] The I2C-BUS Specification and User Manul(v5), NXP, Eindhoven, TheNetherlands, Oct. 2012.

Yanzhe Cui (S’10) received the B.E. in electri-cal engineering and the M.E. degree in electricalinformation system engineering from the ChongqingUniversity of Technology, Chongqing, China, in2007 and 2010, respectively, where he is currentlypursuing the Ph.D. degree.

He is a Research Assistant with the Collab-orative Mechatronics Laboratory, University ofDenver, Denver, CO, USA. He is interested inthe partial dynamic reconfiguration, wireless sen-sor/acutator/control networks, and cyber physical

systems. His current research interests include heterogeneous team of urbansearch and rescue robots, which needs an infrastructure of dynamic self-adaptation under the volatile environment.

Richard M. Voyles (S’92–M’97–SM’00) receivedthe B.S. degree in electrical engineering from PurdueUniversity, West Lafayette, IN, USA, in 1983, theM.S. degree in manufacturing systems engineeringfrom the Department of Mechanical Engineering,Stanford University, Stanford, CA, USA, in 1989,and the Ph.D. degree in robotics from the Schoolof Computer Science, Carnegie Mellon University,Pittsburgh, PA, USA, in 1997.

He is currently an Associate Professor with theDepartment of Computer Engineering, University

of Denver, Denver, CO, USA. He was with the University of Minnesota,Minneapolis, MN, USA, from 1997 to 2006, and is a Founding Site Director ofthe NSF Safety, Security, and Rescue Research Center, an NSF I/UCRC. Hiscurrent research interests include robotics, mechatronics, artificial intelligence,and autonomic (reconfigurable) computing. He is interested in the coordinationof teams of robotic agents for common goals where resource constraints playan important role. One of the primary application domains is the field ofurban search and rescue, for which he has developed the novel TerminatorBot.Resource constraints of these small robots demand self-adaptation, whichrequires an infrastructure of reconfigurable computing. He has expertisein sensors and sensor calibration, particularly haptic and force sensors.He is interested in mobile manipulation, programming robots by humandemonstration, agent-to-agent skill transfer, MEMS and microassembly. Hiscurrent research interests also include computer vision, including extracting3-D models of objects from a moving camera.

Robert A. Nawrocki (S’98) received the Under-graduate degree in computer engineering from theNew Jersey Institute of Technology, Newark, NJ,USA, in 2004. He is currently pursuing the Ph.D.degree with the University of Denver, Denver, CO,USA. His current studies in polymer neuromorphicengineering focus on the development of solution-processable, distributed processing system basedon polymer components, and biologically inspiredarchitecture.

He completed his internship at ETHZ, Zurich,Switzerland, where he worked on submillimeter scale electromagnetic induc-tion geared toward powering onboard electronics for microscale robotics. Thiswork embraces the study of artificial neural networks (artificial intelligence),as well as polymers and polymer electronics. He is involved in an inter-disciplinary project with the Department of Biological Sciences, Universityof Denver, Denver, CO, USA, aimed at monitoring performance degradationof biological networks subjected to neural damage and mutation throughoutprogression of neurodegenerative diseases.

Guangying Jiang (S’12) received the B.E. degreein electrical engineering from the Nanjing Universityof Aeronautics and Astronautics, Nanjing, China, in2010, where he is currently pursuing the Graduatedegree.

He is a Research Assistant with the CML, Uni-versity of Denver, Denver, CO, USA. His currentresearch interests include unmanned aerial vehicles,and urban search and rescue robotics.

the morphing bus: a new paradigm in peripheral interconnect bus

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