scr operation mode of diode strings for esd protection

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Microelectronics Reliability 47 (2007) 1044–1053

SCR operation mode of diode strings for ESD protection

Ulrich Glaser a,*, Kai Esmark b, Martin Streibl c, Christian Russ b, Krzysztof Domanski b,Mauro Ciappa d, Wolfgang Fichtner d

a AIM AP D TD M1, Infineon Technologies, D-85579 Neubiberg, Germanyb COM BTS LIB ESD, Infineon Technologies, D-85579 Neubiberg, Germany

c QAG PD DS RB, Qimonda, D-85579 Neubiberg, Germanyd Integrated Systems Laboratory, ETH Zurich, CH-8092 Zurich, Switzerland

Received 23 November 2005; received in revised form 9 March 2006Available online 10 January 2007

Abstract

Diodes and diode strings in 90 nm and beyond technologies are investigated by measurement and device simulation. After a thoroughcalibration, the device simulator is utilised to achieve a better understanding and an enhanced device performance of diode strings understatic and transient ESD conditions. Thereto, parasitic transistors and a so far neglected parasitic thyristor (SCR) in the diode string areregarded, exploited and optimised.� 2006 Elsevier Ltd. All rights reserved.

1. Introduction

In ESD protection circuits, diodes are used in powersupply clamps, trigger elements of complex protectionelements (e.g., SCR), cross coupling diodes and simple pro-tection elements. They occur in various configurations likeindividual, cladded and cantilever diodes as well as(snubber clamped, boosted) diode strings. In previouswork [1–5], these configurations have been investigatedby measurement and basic theoretical estimations whileconsidering not all of the inherent parasitic devices.

In this work (earlier version published in [6]), individualdiodes and diode strings are investigated by measurementand device simulation which allows to consider all inherentparasitic devices. The individual diodes are used for devicesimulator calibration and for the discrimination andweighting of pure diode string mode and parasitic deviceeffects. The purpose of this work is a better understandingand an enhanced device performance of diode strings underESD conditions, i.e. a lower high current resistance in for-

0026-2714/$ - see front matter � 2006 Elsevier Ltd. All rights reserved.

doi:10.1016/j.microrel.2006.11.013

* Corresponding author. Tel.: +49 89 234 22047; fax: +49 89 234 9556781.

E-mail address: [email protected] (U. Glaser).

ward bias and correspondingly a lower voltage drop acrossthe device in the ESD operation regime. This can beachieved by introducing and enhancing a snapback charac-teristic of the diode string. Thereto, a so far neglected par-asitic SCR in the diode string is exploited and the operationof the parasitic devices is optimised. On the other hand, thesame parasitic devices are able to endanger the supposedbehaviour of a diode string. The discussed physical mecha-nisms are therefore also important to prevent malfunctionin circuits containing diode strings. Of course, fast tran-sient pulses occur usually during ESD events. The responseto such pulses and its dependencies are examined addition-ally, and methods for an improved response are proposed.

2. Investigated devices and simulator calibration

Two ESD diode devices in a 90 nm p-substrate CMOStechnology are selected for device simulator calibrationand verification. A part of the schematic cross section ofthe single STI (shallow trench isolation) bounded p+/n-welldiode is displayed in Fig. 1. The anode consists of eightgeometrically equivalent p+ diffusion fingers which are sep-arated by silicon dioxide (STI) and n+ contacts to theunderlying retrograde n-well. This n-well also represents

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STI

( )( )

p–substrate

n–well

cathode anode

n+ p+ n+ p+ n+p+

x

y

Fig. 1. A part of the schematic cross section of the investigated p+/n-welldiode.

Fig. 3. Logarithmical plot of the I(V)-characteristics of the p+/n-welldiode for different temperatures.

U. Glaser et al. / Microelectronics Reliability 47 (2007) 1044–1053 1045

the cathode. It is surrounded by a p-well (p-substrate)which is contacted by a p+ guardring. The device topologyis associated with a well-known parasitic vertical pnp-tran-sistor, which is indicated in Fig. 1. The total width of thedevice, i.e. the sum of the width of all fingers in the z-direc-tion amounts to w = 8 Æ 12.5 lm = 100 lm. The seconddevice type is a string of three diodes. The layout of everyindividual diode is analogous to Fig. 1 but with only twop+ fingers with a width of 50 lm each, summing to a totaldiode width of again 100 lm.

For simplicity and clarity, a sketch of a string of twodiodes is shown in Fig. 2. The equivalent circuit of thisdevice is usually drawn as a Darlington series of pnp-tran-sistors. It is sketched by the circuit containing the transis-tors T1 and T2 in Fig. 2. The npn-transistors like T3which are formed by two n-wells and the p-substrate areusually neglected, but T1 forms a parasitic SCR togetherwith T3. This parasitic device will be a central part of thepresent work because it conducts a significant amount ofthe current in the high current regime and allows anenhanced clamping behaviour of diode strings. Of course,even more parasitic devices have to be taken into accountin larger diode strings.

A thorough calibration of the device simulator is man-datory prior to any investigation of design variations. Sev-eral physical model parameters have been adjustedcarefully by comparing measured and simulated I(V)-char-acteristics of the single diode and the static common-emit-

STI STI

Lb

p–substrate

n–w

ell

n–w

ell

1 2 3

T3

)( ( )

T1 T2

anode cathode

p+ p+ n+ p+ p+ n+ p+

x

y

Fig. 2. Sketch of a string of two diodes. The improved equivalent circuitincludes a parasitic npn-transistor T3 which forms a parasitic SCRtogether with T1. The base width Lb is also defined here.

ter current gain b of the inherent parasitic pnp-transistor.Some final results of the calibrated simulator are exemplarycompared with measurements in Figs. 3 and 4. Calibratedsimulations are in excellent agreement with measurementsin the whole temperature range. The parameters from thesingle diode calibration are used in diode string simulationsas well. A comparison of measured and simulated I(V)-characteristics is displayed in Figs. 4 and 5 for a diodestring consisting of three diodes. The good agreement forall temperatures verifies the calibration. The small devia-tion up to approximately 10% in the considered high cur-rent regime of the diode string is attributed to theproperties of the parasitic npn-transistors. In measure-ments, they are not accessible in available devices and theircalibration cannot be achieved completely. It should benoted that the impact of the parasitic npn-transistors isunderestimated in the present calibration. Therefore, theirimpact in the following simulation results (e.g., the amountof the snapback in Section 4) is expected to be even morepronounced in measurements. The I(V)-characteristics inthe high current regime in Fig. 4 originate from the tran-sient response of the device to a current pulse with a rise

Fig. 4. Linear plot of the I(V)-characteristics of the p+/n-well diode andthe string of three p+/n-well diodes at 25 �C.

Fig. 5. Logarithmical plot of the I(V)-characteristics of the string of threep+/n-well diodes for different temperatures.

1046 U. Glaser et al. / Microelectronics Reliability 47 (2007) 1044–1053

time of approximately 7 ns and a duration of 100 ns. Theaverage voltage drop across and the average currentthrough the device in the time range from 60 ns to 90 nsresult in one data point. The mean values and correspond-ing error bars of four such data points from measurementsunder the same stress conditions are shown in the figure.The transient response itself has also been compared withsimulations. The agreement in the time range of severalten nanoseconds is of the same excellent quality like inFig. 4. A comparison of the first nanoseconds is very chal-lenging due to the complex measurement setup and henceparasitic distortions. These distortions complicate theextraction of the intrinsic transient device behaviour frommeasurements. However, a good qualitative agreementbetween measurement and simulation has been obtained.

Emission microscopy (EMMI) has been used to verifythe applicability of two dimensional device simulations.Fig. 6 displays the light emission of a forward biased diodeand a forward biased string of three diodes, respectively.The emission indicates the recombination rate whichdepends on the carrier density. The eight fingers of thediode as well as the three times two fingers of the stringof three diodes are aligned along the z-direction. All fin-gers, respectively, the underlying n-wells exhibit a homoge-neous signal along the device width. EMMI shows

Fig. 6. Forward biased (a) diode and (b) string of three diodes EMMIpictures showing homogeneous device operation. Based on the measure-ment result of the diode string, it is possible to extract the static common-emitter current gain of the inherent parasitic pnp-transistors as outlined inthe main text.

therefore that the devices operate homogeneously and 2Ddevice simulation is applicable.

The static common-emitter current gain b of the inher-ent parasitic pnp-transistors can be extracted approxi-mately from EMMI measurements. Let R1, R2 resp. R3

be the sums of the measured EMMI signals inside the com-mensurate rectangles 1, 2 resp. 3 around the individualdiodes as indicated in Fig. 6. Furthermore, Rd is the sumof the background signal inside another rectangle of thesame size but beside the diode string (not shown inFig. 6). Assuming a linear dependence of the EMMI signalon the recombination rate, it follows for the total recombi-nation Rx in rectangle x, that

Rx � Rx � Rd

for every x 2 {1,2,3}. For an ideal diode [7, p. 84], it can beshown by integrating the current densities over the consid-ered area, integrating the relation between recombinationrate and excess carrier densities under low injection condi-tions over the considered volume, and relating the obtainedequations that

Ix � Rx;

where Ix denotes the current, which is forced into diode x,i.e. the emitter current of the corresponding parasitic pnp-transistor. Due to the Darlington configuration, the emittercurrent of the second (third) parasitic pnp-transistor in thediode string equals the base current of the first (second)parasitic pnp-transistor. Therefore, b is approximately gi-ven by

R1 � ðbþ 1ÞR2 and R2 � ðbþ 1ÞR3:

In the present example, EMMI data verified the electricallymeasured b � 1 at a current I = 1 mA.

3. Diode string configurations

In the following sections, three distinct configurations ofthe diode string are utilised to study the influence of theparasitic devices on the I(V)-characteristics. Configuration

A consists of a full diode string like in Fig. 7 which containsthree adjacent diodes in one connected substrate. This

Fig. 7. Simulated diode string of three p+/n-well diodes and its externalcircuit including definitions for some current variables.


configuration includes all possible parasitic devices. Config-

uration B comprises a diode string which consists of threesingle diodes, i.e. the diodes do not share a common sub-strate as if they are infinite far away from each other.Thereby, parasitic npn-transistors and also the parasiticSCRs are deactivated. Configuration C comprises a diodestring consisting of three single diodes, whose substratesare additionally not connected at all. Now, also the para-sitic pnp-transistors are inactive.

4. Static device operation and optimisation

The I(V)-characteristics of the diode string in the threeconfigurations described in Section 3 are displayed inFig. 8 in logarithmical and linear plots. Configuration Cconducts the lowest current in the low current regimebecause it lacks the well known amplification by the Dar-lington configuration of the parasitic pnp-transistors. Con-figuration B includes this effect leading to a higher currentin the low current regime. But this effect fades above 10 mAdue to the reduction of the current gain at high currents,i.e. the Webster effect [8]. In the high current regime, thevoltage drop across the diode string is even larger in config-

Fig. 8. Logarithmical and linear plots of the I(V)-characteristics at 25 �C.The three diode string configurations are further described in Section 3.The characteristic of configuration A is also shown with halved base widthLb (defined in Fig. 2).

uration B than in configuration C due to the larger deple-tion region at the n-well/p-substrate junction caused by thegrounded p-substrate. ESD devices are supposed to show alow leakage current at normal operating conditions, i.e. atlow voltages, and a high conduction state under ESD injec-tion conditions. Thus, the Darlington amplification wors-ens the device for ESD purposes. Finally, configurationA exhibits in comparison to configuration B a clearincrease of the current in the high current regime due tocurrent conduction by the parasitic SCRs as elaboratedshortly. This effect is highly welcome because it does notincrease the leakage current but improves the clampingcapabilities of the diode string under ESD injection condi-tions. Configuration A is also shown with halved basewidth Lb (defined in Fig. 2). The reduced base resistanceleads to an even further improved conduction in the highcurrent regime. The metal resistance, which is very sensitiveto technology scaling, becomes eventually the main contri-bution to the total on-resistance of the diode and limitstherefore the utilisation of the base width reduction in thiscontext.

The I(V)-characteristics of the string of three diodes inFigs. 5 and 8 do not exhibit any snapback behaviour.For ESD protection applications, snapback devices areused to get a more distinctive off- and on-state current aswell as a lower voltage drop, i.e. an improved clampingbehaviour of the protection devices. A closer look intothe device reveals that the parasitic operation modes (tran-sistor and SCR currents) nevertheless play an importantpart in the different regions of the I(V)-characteristic. Forthe diode string of three p+/n-well diodes (illustration inFig. 7), the current I1, which is forced into the anode ofthe first diode, the current I12 (I23) from the first (second)to the second (third) diode via the metal connections, thecurrent I3, which flows out of the cathode of the thirddiode, the current Is through all substrate contacts andjI3j � jI23j, which is an approximation for the current thatthe cathode of the third diode collects from the substrate,are displayed in Fig. 9 normalised to I1. In a small voltagerange around 0.8 V, Is is small in comparison to I12, I23 andI3, i.e. the current flows mainly through the diodes and theparasitic pnp-transistor does not show a significant influ-ence. Apart from that region, the substrate contacts con-duct the main current up to 2.7 V. Thus, the diode stringbehaviour is dominated by the parasitic pnp-transistorsand the amplification by the Darlington configuration inthe low current regime. A transition occurs around 2.7 V:I3 as well as jI3j � jI23j become greater than I12, I23 and Is

indicating that most of I1 flows via the substrate to thecathode of the third diode, i.e. through the parasiticSCR. From 3.5 V on, I12 and I23 exceed Is. This indicatesthat the current path through the diodes is reinforcedand the parasitic pnp-transistors and the Darlington ampli-fication become insignificant due to the Webster effect.Above 3.8 V, I12 and I23 become even greater than jI3j �jI23j. Therefore the main current flows now through thediodes. The current through the parasitic SCR remains

Fig. 10. Logarithmical and linear plots of the I(V)-characteristics of thestrings of three p+/n-well diodes with different substrate contacting at25 �C. The numbers in the legend indicate the p-substrate contacts whichare connected to ground (cf. Fig. 7). The points (a), (b), (c) indicate thepositions at which the total current density in the diode string is displayedin Fig. 11.

0.0

0.2

0.4

0.6

0.8

1.0

0 1 2 3 4 5

curr

ent /

I1

V [V]

I1I12

I23I3

Is|I3|-|I23|

Fig. 9. For the diode string of three p+/n-well diodes, linear plot ofnormalised currents as a function of the applied voltage. The current I1 isforced into the anode of the first diode, the current I12 (I23) flows from thefirst (second) to the second (third) diode via the metal connections, thecurrent I3 flows out of the cathode of the third diode, the current Is isconducted through all substrate contacts, and jI3j � jI23j is an approxi-mation for the current which the cathode of the third diode collects fromthe substrate. Some displayed variables are illustrated in Fig. 7.


nevertheless significant. Both, pnp-transistors as well asSCRs can show a snapback characteristic. In the following,layout measures, which tune the parasitic device behaviourand thereby improve the clamping capability by enhancinga snapback mode of operation, are examined.

Substrate contacts (cf. Fig. 7) exist close to the outsideof every p+/n-well diode and all of them are connected toone grounded pad in the original device. Devices with dif-ferent substrate contacting have been investigated bydevice simulation. Fig. 10 displays the basic types of resultsat 25 �C. Depending on the substrate contacting, the I(V)-characteristics exhibit no, one or two snapbacks with differ-ent trigger and holding voltages and currents. A look intothe devices identifies the turn on of parasitic SCRs to causethe snapbacks. For the device with only substrate contacts1 and 4 grounded, the total current density is displayed inFig. 11 at positions (a), (b) and (c) as indicated in Fig. 10.At (a), the current level is below any snapback and onlydiode and pnp-transistor currents are present. At (b), thecurrent level lies between first and second snapback. A par-asitic SCR formed by the middle and right diode in thestring has turned on. At (c), the second snapback has takenplace. The parasitic SCR formed by the left and right diodeconducts the main current directly from the anode to thecathode of the diode string. It should be noted that the trig-ger current of the parasitic SCR can be below 1 mA. Withregard to the width comparable SCR ESD protectionstructures trigger at currents that are typically at leastone order of magnitude larger. In addition, the trigger volt-age is quite low because no forward breakover happens dueto the forward biased diode string. Both properties can leadto unexpected device behaviour. In conclusion, the perfor-

mance of the diode string under ESD conditions can bechanged by an optimised substrate contacting. For exam-ple in the case of I = 50 mA, the clamping voltage can bereduced from V � 2.8 V to V � 2.2 V. Of course, also theholding voltage of the snapback, which should be wellabove the normal operating voltage, must be consideredand optimised if necessary to avoid the risk of latch-upwhich is normally not anticipated in diode strings. AnESD event with a 2 kV voltage pulse according to HBM(Human Body Model [9]) leads to a current I � 1.3 Athrough the selected diode string. The linear plot inFig. 10 shows the I(V)-characteristics for such currents. Itreveals that the clamping voltage is also reduced fromV � 5 V to V � 4.5 V just by optimising the substratecontacting.

Assuming a simple model for an SCR [5,7], the triggercondition of the SCR is approximately reached if the staticcommon-emitter current gains bpnp and bnpn of the pnp-and npn-transistors in the model fulfil the inequalitybpnp Æ bnpn P 1. In the case of the studied parasitic SCR,the current gains of the inherent parasitic pnp- and

Fig. 11. Total current density in a string of three p+/n-well diodes withonly substrate contacts 1 and 4 grounded. The pictures are taken atpositions indicated in Fig. 10.

Fig. 12. The static common-emitter current gains bpnp and bnpn of theinherent parasitic pnp- and npn-transistors. The numbers in the legendindicate the p-substrate contacts which are connected to ground.Furthermore, ‘short’ resp. ‘long’ denote parasitic npn-transistors consist-ing of the adjacent n-wells of the second and third diode resp. the furtherspaced n-wells of the first and third diode.


npn-transistors cannot be used in this inequality becausethe parasitic transistors share base and collector regions.Nevertheless, it is instructive to look at the simulated gainsbpnp and bnpn of the inherent parasitic transistors. They aredisplayed in Fig. 12 for different p-substrate contacting andn-well distances. The absolute values of the emittercurrents should not be compared quantitatively to triggercurrents in Fig. 10 because the emitter currents indicatethe carrier injection at the contact whereas the triggeringof parasitic devices in the diode string depends on the distri-bution of injected carriers at internal junctions. Neverthe-less, the curves show the following qualitative features: theemitter efficiency causes the maximum of bnpn to be greaterthan the maximum of bpnp despite the larger base width ofthe npn-transistor because the ratio of emitter and base dop-ing of the npn-transistor is about two orders of magnitudeslarger than this ratio of the pnp-transistor. Furthermore, thegain of the parasitic pnp-transistor is reduced by the band-gap narrowing effect and the Auger effect in the highly dopedemitter region [7]. Regarding bpnp, the substrate contactingaffects only its decrease due to the Webster effect. On theother hand, a smaller base width increases bnpn. Clearly,

the size of both current gains enables the parasitic SCR toturn on. Unfortunately, it is not possible to explain the turnon of the parasitic SCRs in Fig. 10 by the current gains com-pletely. This is another indication that the inequality, whichhas been derived from a simple model, is not sufficient toexplain the presented situation.

5. Dynamic device operation and optimisation

Due to the transient nature of an ESD event, it is essen-tial to study the dynamic behaviour of the ESD device. Ifthe ESD device is not capable to turn on fast enough thena fast transient ESD pulse leads to a large voltage over-shoot and damage may occur. The examination of thedynamic device behaviour is an ideal task for device simu-lation because it does not suffer from limited time resolu-tion issues and parasitic distortions in the experimentalsetup. In the following, the transient response of differentdiode string configurations is analysed for a piecewiselinear ramp of the current with rise time tr. The maximumcurrent level corresponds to a 2 kV HBM voltage pulse andis maintained until the end of the simulation.


Fig. 13 shows the transient response of the three config-urations defined in Section 3 for the pulse rise timestr = 10 ns, 1 ns and 100 ps. At the beginning of the pulse,the voltage drop increases generally until a maximumwhich is determined by the device’s forward recovery prop-erties and the pulse properties, i.e. its slope and duration.The forward recovery is also responsible for the increaseof the maximum voltage drop with decreasing rise time.For t > tr, the devices move towards their equilibrium state.

Especially for shorter tr, the three configurations exhibita diverging behaviour during the rise time. For tr = 100 ps,the behaviour of the diode string including all parasiticdevices is analysed in detail at positions indicated inFig. 13 with the help of the total current density shownin Fig. 14. The voltage decreases from (a) to (b). A compar-ison of the total current density shows that the collectorcurrent of the parasitic pnp-transistor, i.e. the p-substratecurrent increases on the left side. The current ‘through’the n-well/p-substrate boundary on the left side consistsmainly of electrons and holes which are generated byimpact ionisation at that boundary and traverse n-welland p-substrate, respectively. Thus, at (b), the voltagedecrease is caused by the turn on of the left parasiticpnp-transistor and the induced increase in carrier genera-tion by impact ionisation. This is confirmed by the otherdiode string configurations. The single diodes exhibit onlya snapback in the clamping voltage in this region if the sub-strate, i.e. the collector of the parasitic pnp-transistor isconnected. The turn on of the parasitic SCR happens muchlater between (c) and (d) due to the large transit time of theparasitic npn-transistor. The SCR leads to the improvedclamping voltage of the diode string in configuration A incomparison to configuration B. This appears in the V(t)-characteristics for t ’ 10 ns.

The influence of the substrate contact variation on thedynamic behaviour of the diode string is studied in the fol-

Fig. 13. Transient response of three diode string configurations for apiecewise linear ramp of the current with rise times tr = 10 ns, 1 ns and100 ps. The three diode string configurations are further described inSection 3. The points (a)–(d) indicate the positions at which the totalcurrent density in the diode string is displayed in Fig. 14.

Fig. 14. Total current density in a string of three p+/n-well diodes duringa fast transient pulse. The pictures are taken at positions indicated inFig. 13.

lowing. Thereto, the V(t)-characteristics of the diode stringwith different substrate contacting are displayed in Fig. 15for the rise time tr = 100 ps. It turns out that the maximumvoltage drop increases if substrate contacts are removed.Also the small voltage decrease during the current rampbecomes smaller. This indicates clearly that the dynamicbehaviour is worsened by the removal of substrate contactsdue to the reduced impact of the parasitic pnp-transistors.In conclusion, the optimisation of the parasitic pnp-transis-tor poses a tradeoff problem: the device engineer longs forless substrate contacts to enhance the clamping capabilityon a long time scale (t ’ 10 ns). On the other hand, thesubstrate must be well connected to achieve a lower voltage

Fig. 15. Transient response of diode strings in configuration A withdifferent substrate contacting for a piecewise linear ramp of the currentwith rise time tr = 100 ps. The numbers in the legend indicate thep-substrate contacts which are connected to ground.


overshoot during forward recovery. One possible solutionto this tradeoff is the optimisation of the substrate contactsfor, e.g., the long time scale behaviour and the utilisation ofanother parameter for the optimisation of the forwardrecovery response. To accomplish this, a decrease of thebase width Lb (defined in Fig. 2) is an effective possibility.The V(t)-characteristics of three diode string configurationswith halved Lb are compared to the diode string configura-tion A with original base width in Fig. 16. The dynamicbehaviour of the diode string without substrate contacts(configuration C) but halved base width is now even betterthan the behaviour of the diode string with full substratecontacting and original base width.

For a rise time of 100 ps, the transient voltage overshootrises in all simulations to a level which is very high com-pared to the static breakdown voltage of the thin gate oxidein the investigated CMOS technology. The gate oxide with-stands such a voltage only for a short time. A reduction ofthe voltage overshoot improves the reliability and the life-

Fig. 16. Comparison of the transient response of the diode string inconfiguration A with original base width and three diode string config-urations with halved base width Lb (defined in Fig. 2) for different risetimes.

time of the integrated circuit. Due to the calibration, agood qualitative agreement exists between measurementand simulation regarding the transient response to a cur-rent pulse in the first nanoseconds. Hence, the device sim-ulation results in this section indicate first possiblemeasures to reduce the voltage overshoot. Furthermore,all known measures which optimise the dynamic behaviourof an SCR for ESD purposes can be utilised to tune theimpact of the parasitic SCR in the diode string.

6. Experimental evidence

Diode strings with intended alterations have been imple-mented and measured on a 65 nm p-substrate CMOS tech-nology wafer. These measurement results are presented inthis section. They prove the physical findings from devicesimulation which have triggered the experimental researchand have evoked attention to the parasitic SCR operationmode of diode strings. In the following, the comparison ofmeasurement and simulation is limited to a qualitative onedue to the different technologies.

Compared to the 90 nm technology, the diode strings inthe 65 nm technology possess a similar stripe layout. Themost important difference concerns the substrate contact-ing: no p+ guardring surrounds the n-wells. In a variation,a substrate contact is placed 5 lm apart from the diodestring. In addition, every diode consists of only one p+ dif-fusion finger separated by various distances Lb from thesingle n-well contact stripe. The measurements have beenperformed using a four-terminal (Kelvin probe) pulsersetup which generates pulses with a rise time of approxi-mately 7 ns and a pulse duration of 100 ns. For every pulse,the voltage across and the current through the device undertest are averaged over the time range from 60 ns to 90 nsgiving one point in the I(V)-characteristic.

The I(V)-characteristics of the diode strings consisting ofN = 1, . . ., 6 p+/n-well diodes without any substrate con-tacts are displayed in Fig. 17. Clearly, the diode stringswith N P 2 diodes exhibit a snapback behaviour. The trig-ger voltage and the holding voltage of the snapbackincrease with increasing N. At the same time, the snapbackbecomes more pronounced. These properties can be attrib-uted to the parasitic SCR. It necessitates a higher voltageto trigger an SCR if anode and cathode are more distantdue to the decrease of the static common-emitter currentgain bnpn. On the other hand, the bypass of the diode stringbecomes more worthwhile with increasing N. Of course,this effect is reduced by an increase in resistance due tothe increased SCR spacings. Fig. 18 shows the impact ofsubstrate contacts for diode strings with N = 2,3,4 diodes.As expected from device simulation findings, the triggerand holding voltages are higher in the case of groundedsubstrate contacts. In addition, the snapback becomes lesspronounced. A close by substrate contacting might easilyprevent any snapback characteristic as shown by the origi-nal diode string in the 90 nm technology. The I(V)-charac-teristics of a diode string with three p+/n-well diodes and

Fig. 18. Comparison of the I(V)-characteristics of the diode stringsconsisting of N = 2,3,4 p+/n-well diodes with and without substratecontacts at 25 �C.

Fig. 19. Linear plot of the I(V)-characteristics of the diode stringconsisting of three p+/n-well diodes with substrate contacts at 25 �C.The base width Lb (defined in Fig. 2) has been varied starting fromL0 = 0.24 lm.

Fig. 17. Linear plot of the I(V)-characteristics of the diode stringsconsisting of N = 1, . . ., 6 p+/n-well diodes without any substrate contactsat 25 �C.


substrate contacts are depicted in Fig. 19 as a function ofthe base width Lb. The measurement results show a signif-icant dependence on the base width only for larger widths.There the measurement verifies that the clamping capabil-ity of the diode string decreases with increasing Lb. Forsmaller widths, the impact of Lb variations is importantonly for tr ~ 1 ns and t < 10 ns as shown by device simula-tions in Section 5, and is therefore beyond the scope of themeasurement setup.

7. Conclusion

Starting from a thorough simulator calibration, the dif-ferent device operation modes of a diode string and theimpact of inherent parasitic devices on its I(V)- andV(t)-characteristics have been studied by device simula-tion. It turns out that the Darlington configuration isnot advantageous for diode string ESD protection ele-ments in deep submicron technologies because it increasesthe leakage current but does not improve the clampingvoltage in the relevant current regime. On the other hand,a reduction of the substrate contacting efficiently decreasesthe clamping voltage in the relevant current regime of thestatic and transient (t ’ 10 ns) characteristics because itenhances the impact of inherent parasitic SCR devices.The only limit is given by the holding voltage of the snap-back which should be well above the normal operatingvoltage to avoid latch-up. The increase in the voltage over-shoot for very short pulses can be easily compensated byreducing the base width Lb. Despite the beneficial poten-tial of the inherent parasitic SCR devices in diode strings,they also may cause unexpected device or circuit behav-iour if their impact is not considered during device and cir-cuit design.

The studied configurations B and C turn parasiticdevices (transistors and SCRs) completely off. Also thesubstrate contact variation is studied in a digital way, i.e.the individual available contacts are either completely con-nected or completely disconnected. Intermediate configura-tions and substrate contacting may be desirable. They arepossible by changing the distance between the n-wells con-taining the diodes or the distance from an n-well to theclosest p-substrate contacts. Furthermore, an adjustmentof the STI depth [10] also tunes the electrical separationbetween n-wells, or between n-wells and p-substrate con-tacts but with less area consumption than distancevariations.

Exemplary practical applications of the found cogni-tions are the following for improving diode string ESDprotection elements. The parasitic SCR offers new possibil-ities to tune the clamping voltage of the diode string. Incontrast to a change in the numbers of diodes in the string,the clamping voltage can be adjusted continuously andwithout a significant impact on the low current behaviour,e.g., the leakage current. Hence, such measures do notevoke power consumption concerns but help to matchthe stringent requirements of a further shrinking ESD


design window with advancing technologies. An additionalreduction in the transient voltage overshoot enables theprotection and therefore the usage of capacitors and tran-sistors with thinner gate oxides.

This work demonstrates the beneficial usage of devicesimulation to explore the device operation and separatethe impact of parasitic devices. Furthermore, the responseof the devices on fast transient pulses becomes accessibleand possible design optimisations can be verified. The excel-lent qualitative agreement between measurements andsimulations in different deep submicron technologies affirmsall physical findings.

Acknowledgements

The authors thank Jens Schneider for the developmentof the process simulation environment, Michael Ettlingerfor his support with regard to the high resolution measure-ment equipment, and Stephan Schomann for his EMMImeasurements. This work was partially funded by the Fed-eral Ministry of Education and Research (Bundesministe-rium fur Bildung und Forschung, BMBF) under ContractNo. 01M3159C.

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