performance of low density parity check coded continuous phase frequency shift keying (ldpcc-cpfsk)...

INTERNATIONAL JOURNAL OF COMMUNICATION SYSTEMSInt. J. Commun. Syst. 2007; 20:397–410Published online 30 June 2006 in Wiley InterScience (www.interscience.wiley.com). DOI: 10.1002/dac.824

Performance of low density parity check coded continuousphase frequency shift keying (LDPCC-CPFSK) over

fading channels

Yesim Hekim*,y, Niyazi Odabasiogluz and Osman N. Ucan}

Department of Electrical and Electronics Engineering, Istanbul University, 34320 Avcilar, Istanbul, Turkey

SUMMARY

In this paper, in order to improve bit error performance, bandwidth efficiency and reduction of complexitycompared to related schemes such as turbo codes, we combine low density parity check (LDPC) codes andcontinuous phase frequency shift keying (CPFSK) modulation and introduce a new scheme, called ‘lowdensity parity check coded-continuous phase frequency shift keying (LDPCC-CPFSK)’. Since LDPC codeshave very large Euclidean distance and use iterative decoding algorithms, they have high error correctingcapacity and have very close performances to Shannon limit. In all communication systems, phasediscontinuities of modulated signals result extra bandwidth requirements. Continuous phase modulation(CPM) is a powerful solution for this problem. Beside CPM provides good bandwidth efficiency; it alsoimproves bit error performance with its memory unit. In our proposed scheme, LDPC and CPFSK, whichis a special type of CPM, are considered together to improve both error performance and bandwidthefficiencies. We also obtain error performance curves of LDPCC-CPFSK via computer simulations forboth regular and irregular LDPC code. Simulation results are drawn for 4-ary CPFSK, 8-ary CPFSK and16-ary CPFSK over AWGN, Rician and Rayleigh fading channels for maximum 100 iterations, while theframe size is chosen as 504. Copyright # 2006 John Wiley & Sons, Ltd.

Received 1 August 2005; Revised 1 March 2006; Accepted 1 May 2006

KEY WORDS: low density parity check codes; continuous phase frequency shift keying

1. INTRODUCTION

In 1963, Gallager [1] invented low density parity check (LDPC) codes, which provide lowencoder and decoder complexity. Until 1996, Reed-Solomon (RS) and convolutional codes were

*Correspondence to: Yesim Hekim, Department of Electrical and Electronics Engineering, Istanbul University, 34320Avcilar, Istanbul, Turkey.yE-mail: [email protected]: [email protected]}E-mail: [email protected]

Contract/grant sponsor: Research Fund of The University of Istanbul, Turkey; contract/grant number: 354/03062005

Copyright # 2006 John Wiley & Sons, Ltd.

considered perfectly suitable for error control coding and there were only a few studies onLDPC, which are References [2–4]. Then MacKay and Neal [5], Wiberg [6] rediscovered LDPCcodes and there is much research on this subject from then on, since decoding of LDPC codesare faster and has lower complexity than the decoding of turbo codes. LDPC with constrainedrandom code ensembles and iterative decoding algorithms can be considered seriouscompetitors to turbo codes in terms of complexity and performance. Encoder complexity ofLDPC codes is proportional with the square of code length (n2), therefore, encoding processtime is longer than turbo encoding. In construction of LDPC codes, choosing appropriate uppertriangle parity check matrix, provides significant encoding complexity reduction as inReferences [7,8]. These kind of matrix transformations may converse the sparsity of theoriginal matrix, but do not affect code performance. As originally suggested by Tanner [4],LDPC codes are well represented by bipartite graphs having two sets of nodes. These are; bitand check nodes, which correspond to elements of the codeword and parity-check constraints,respectively. Regular LDPC codes are those for which all nodes of the same type have the samedegree. For example, Figure 1(a) represents (3, 4) regular LDPC code in which all bit nodes hasdegree 3 and all check nodes have degree 4. Irregular LDPC codes [9] have variable bit andcheck node degrees. As an example, in Figure 1(b), an irregular LDPC code structure is given,where the degree of the first half of the bit nodes is ‘2’ and the other half is ‘3’.

In this paper, to improve error performance and bandwidth efficiency of LDPC coded signals,they are considered together with continuous phase modulation (CPM) approaches. In band-limited channels, CPM has explicit advantages with its low spectral occupancy property. CPM iscomposed of continuous phase encoder (CPE) and memoryless mapper (MM) [10]. CPE is aconvolutional encoder producing codeword sequences that are mapped onto waveforms byMM, creating a continuous phase signal. CPE also provides power efficiency beside phase

Bit Node

Check Node

Bit Node

Check Node

(a) (b)

Figure 1. Bipartite graph representation of: (a) regular ð3; 4Þ LDPC; and (b) irregular LDPC code.

Y. HEKIM, N. ODABASIOGLU AND O. N. UCAN398

Copyright # 2006 John Wiley & Sons, Ltd. Int. J. Commun. Syst. 2007; 20:397–410

DOI: 10.1002/dac

continuity. The power efficiency of CPM can be further improved by coding. Some classicalcoding techniques such as convolutional and trellis codes have been designed for CPM. In therecent years, several parallel and serial concatenated coding schemes have been proposed for usewith CPM [11,12]. Here, we combine low density parity check codes and continuous phasemodulation and thus, we introduce low density parity check coded-continuous phase frequencyshift keying (LDPCC-CPFSK). In LPDCC-CPFSK scheme, message bits are first encoded byLDPC encoder. Then the coded bits are turned into serial to parallel according to the type ofmodulation. The least significant bits (LSB) of these bit streams are encoded again by CPE toprovide phase continuity. Then the coded bits are mapped into M-ary CPFSK signals by a MMand these signals are sent to channel. At the receiver side, LDPCC-CPFSK receiver demodulatesand decodes noisy signals respectively. Finally, input bits are estimated from decoded bits.

This paper is organized as follows; LDPC codes are described in Section 2 and in Section 3CPFSK is described. In Section 4, LDPCC-CPFSK systems are investigated and errorperformances of the proposed systems are discussed.

2. LOW DENSITY PARITY CHECK CODES

LDPC codes are linear block codes, which are specified by a very sparse parity check matrix,and can be represented easily by a bipartite graph, while parity check matrix H has P columnsand J rows. The bipartite graph of this code has P bit nodes, J check nodes and a certainnumber of edges. The code rate R is 1� ðJ=PÞ: Each bit node represents a bit symbol in thecodewords and each check node represents a parity equation of code. There is a line drawn inbipartite graph between a bit node and a check node if and only if that bit is involved in thatequation. The number of ‘1’ bit in rows can characterize LDPC codes and columns of the paritycheck matrix. LDPC codes are categorized into two groups, regular LDPC codes and irregularLDPC codes.

Regular LDPC codes are those for which all rows and columns of the parity check matrixhave the same degree. A regular LDPC code has a bipartite graph in which all bit nodes havedegree j and all check nodes have degree k. These degrees correspond to the number of ‘1’ bits incolumns and rows of parity check matrix H.

As an example of regular LDPC codes, the partite graph of (3, 4) is chosen (Figure 1(a)) andthe parity check matrix of this code is given in as

H ¼

0 0 1 0 0 1 1 1 0 0 0 0

1 1 0 0 1 0 0 0 0 0 0 1

0 0 0 1 0 0 0 0 1 1 1 0

0 1 0 0 0 1 1 0 0 1 0 0

1 0 1 0 0 0 0 1 0 0 1 0

0 0 0 1 1 0 0 0 1 0 0 1

1 0 0 1 1 0 1 0 0 0 0 0

0 0 0 0 0 1 0 1 0 0 1 1

0 1 1 0 0 0 0 0 1 1 0 0

2666666666666666666664

3777777777777777777775

ð1Þ

PERFORMANCE OF LDPCC-CPFSK OVER FADING CHANNELS 399


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In irregular LDPC codes, degree of nodes in each set is chosen according to some distributionrule. Optimal distribution of the rows and columns of an irregular LDPC code can be computedby density evolution as in Reference [13]. Irregular LDPC codes can be specified by degreedistribution ðl; rÞ pair or generating functions as:

lðxÞ ¼Xdlmax

i¼2

lixi�1

rðxÞ ¼Xdrmax

i¼2

rixi�1

ð2Þ

Here li and ri are the fraction of edges with (left, right) degree i, respectively, and dlmaxis the

maximal left degree of any edges, drmaxis the maximal right degree of any edges. The bipartite

graph of an irregular LDPC code is shown in Figure 1(b) having l2 ¼ 0:4; l3 ¼ 0:6; r3 ¼ 0:6 andr4 ¼ 0:4:

2.1. Encoding of LDPC codes

The parity check matrix (H) of an LDPC is random constructed. Therefore, the code words ofLDPC code, A with length n must be written in systematic form as

v ¼ ð%pj%uÞ ð3Þ

where, %u is the k-tuple message bit and %p is the ðn� kÞ-tuple parity check bits. Let the paritycheck matrix of A be H, can be defined as Equation (4), where A1 and A2 are, respectivelyðn� kÞ � ðn� kÞ and k� ðn� kÞ matrices.

HT ¼A1

A2

" #ð4Þ

Since v:HT ¼ ð%p j %uÞA1

A2

� �; then

%p:A1 þ %u:A2 ¼ 0 ð5Þ

Let be the generator matrix of A is G is the form of ð%%pjIkÞ; where %%p is k� ðn� kÞ matrix. Sincev ¼ %u:G ¼ %u: ½%%p j Ik� we have %p ¼ %u:%%p: Using Equation (5) for any %u we have,

%uð%%pA1 þ A2Þ ¼ 0 ð6Þ

Thus we have %%p ¼ �A2A�11 and a generator matrix in symmetric form is described in

Equation (7).

G ¼ ½%%p j Ik� ¼ ½A2A�11 j Ik� ð7Þ

The codeword can be found by multiplying the message bits with the generator matrix G ð%u:GÞ:

2.2. Decoding of LDPC codes

The decoding of LDPC codes is Tanner graph-based algorithm. Decoding is accomplished bypassing messages along the lines of graph. The messages on the lines that connect to the ith bitnode ci are the estimates of Prðci ¼ 1Þ: The probabilities are combined in each check node inparticular ways. The initial estimation probability of each bit node is the soft output of thechannel. The bit node broadcasts this initial estimate to the parity check nodes on the lines



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connected to that bit node. Each check node makes a new estimate for the bits involved in thatparity equation and sends these new estimates back to the bit nodes.

The probabilities of message to be passed from bit node ci to the check node fj is described asfollows:

qijð0Þ ¼ 1� pi ¼ Prðci ¼ 0 j yiÞ ¼1

1þ e�2yi=s2

qijð1Þ ¼ pi ¼ Prðci ¼ 1 j yiÞ ¼1

1þ e2yi=s2

ð8Þ

where yi is received signal. The probabilities of message to be passed from check node fj to thebit node ci is given in the following equation:

rjið0Þ ¼1

2þ

1

2

Yi02Rj=i

ð1� 2qi0jð1ÞÞ

rjið1Þ ¼ 1� rjið0Þ

ð9Þ

where Rj=i is the set of column locations of ‘1’ bits in the jth row, excluding location i. At thenext step, the probabilities of the message to be passed from bit node to the check node is

qijð0Þ ¼ Kijð1� piÞYj02Ci=j

rj0ið0Þ

qijð1Þ ¼ KijpiYj02Ci=j

rj0ið1Þð10Þ

where Ci=j is the set of row locations of ‘1’ bits in the ith column, excluding location j.Kij constants are chosen to ensure qijð0Þ þ qijð1Þ ¼ 1: The probabilities, which are used to decidethe received signal is whether ‘0’ or ‘1’, are given in the following equation:

Qið0Þ ¼ Kið1� piÞYj2Ci

rijð0Þ

Qið1Þ ¼ KipiYj2Ci

rijð1Þð11Þ

Here the constants Ki are selected to ensure Qið0Þ þQið1Þ ¼ 1: After computing theseprobabilities, finally hard decision is made as

#ci ¼1; Qið1Þ > 1

2

0 other

(ð12Þ

If #ciHT ¼ 0 or number of iterations exceeds limitations then we finish computing the

estimations. If necessary conditions are not obtained, the probabilities in Equations (9)–(11) arecomputed again.

3. CONTINUOUS PHASE FREQUENCY SHIFT KEYING

Here, we study on M-ary CPFSK, which is an M-dimensional form of CPM. Rimoldi derivedthe tilted-phase representation of CPM in Reference [10], with the information-bearing phase



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given by

fðt;YÞ ¼ 4phX1i¼0

Yiqðt� iTÞ ð13Þ

The modulation index h is equal to J/P, where J and P are relatively prime integers. Y is aninput sequence of M-ary symbols, Yi 2 f0; 1; 2; . . . ;M � 1g: T is the channel symbol period. J isgenerally chosen as 1 and modulation index appears in the form of h ¼ 1=P: P is a number thatcan be calculated as 2 to the power of l, number of memories in CPE. The phase responsefunction q(t), is a continuous and monotonically increasing function subject to the constraints

qðtÞ ¼0; t40

12; t5LT

(ð14Þ

where L is an integer. The phase response is usually defined in terms of the integral of afrequency pulse g(t) of duration LT, i.e. qðtÞ ¼

R t�1 gðtÞ dt: For full response signaling L is equal

to ‘1’, and for partial response systems L is greater than ‘1’. Finally, the transmitted signal s(t) isas

sðt;YÞ ¼

ffiffiffiffiffiffiffiffi2Es

T

rcosð2pf1tþ fðt;YÞ þ f0Þ ð15Þ

where f1 is the asymmetric carrier frequency as f1 ¼ fc � hðM � 1Þ=2T and fc is the carrierfrequency. Es is the energy per channel symbol and f0 is the initial carrier phase. We assumethat f1T is an integer; this condition leads to a simplification when using the equivalentrepresentation of the CPM waveform.

4. SYSTEM MODEL

LDPCC-CPFSK system model is shown in Figure 2. As it can be seen in this figure, message bitsare first encoded by LDPC encoder. Then the encoded bits are turned into serial to log2Mparallel branch according to the type of M-ary CPFSK modulation. CPE encodes the LSB bitagain for phase continuity. The coded bits are mapped into M-ary CPFSK signals si i 2ð1; 2; . . . ; 2MÞ by MM according to partitioning rule.

In the partitioning rule, the MSB bit of serial to parallel (S/P) converter output, x1, dividessignal set into two subsets. If x1 ¼ 0; then the first subset is chosen, if x1 ¼ 1 then the secondsubset is chosen. The x2 bit divides the subsets into two groups as the similar way. Thispartitioning process continues until the last partitioning level occurs.

In order to clarify the operation of the partitioning mechanism for LDPCC-CPFSK system,the set partitioning for 8-ary CPFSK is chosen, as shown in Figure 3. Here, if x1 ¼ 0; then firstsubset fs0; s1; s2; s3; s8; s9; s10; s11g; if x1 ¼ 1; then the second subset fs4; s5; s6; s7; s12; s13; s14; s15g ischosen. At the second partitioning level, we assume that the first subset is chosen in firstpartitioning level, x2 determines whether fs0; s1; s8; s9g or fs2; s3; s10; s11g subsets to be chosen.Similarly, in the first partitioning level, if the second subset is chosen, x2 determines whetherfs4; s5; s12; s13g or fs5; s6; s14; s15g subsets to be chosen. In the last partitioning level, x3x4 bitsspecify which signal will be transmitted to the channel. This procedure can be shown in Table I.



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LDPCEncoder

Seri

al /

Pare

llel

CPE Mem

oryl

ess

Map

per

LDPCC-CPFSK Receiver

Channel

Estimated bit sequence

Information bit sequence

LDPCC-CPFSK Transmitter

x1

x2

xN-1

xN

x si

rk

Figure 2. LDPCC-CPFSK scheme.

{s0 ,s2,s4,s6}θn θn+1

π

0 0

π

{s1 ,s3,s5,s7}

{s8 ,s10,s12,s14}

{s9 ,s11,s13,s15}

s0

s1

s9

s8

3 4x x =00 01 10 11

s0 s1

s2

s3

s11s10

00 01 10 11

x2=0 1

{s0 ,s2}

{s1 ,s3}

{s9 ,s11}

{s8 ,s10}

s9 s11s3s2s8 s10

s4

s5

s13s12

00 01 10 11

s4 s5

s6

s7

s15s14

00 01 10 11

x2=0 1

{s4 ,s6}

{s5 ,s7}

{s13 ,s15}

{s12 ,s14}

s13 s15s7s6s12 s14

x1=0 1

Figure 3. Set partitioning of 8-ary CPFSK.



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In LDPCC 8-ary CPFSK system, if modulation index (h) is chosen as 12; initial and ending

phase of transmitted signal will take two different values ð0;pÞ as shown in Figure 3. In Table I,input–output data and signal constellations are given for this system. Here, x1 and x2 aresystematic bits, x3 and x4 are the bits encoded by CPE. Here, x3 helps to show us at which phasethe signal will start at the next coding interval. If the initial phase ðynÞ is ‘0’ and ‘x3’ is 0, theending phase of the instant signal and the starting angle of the next signal phase ðynþ1Þ is ‘0’. Ifyn ¼ 0 and x3 ¼ 1; ynþ1 ¼ p: If yn ¼ 1 and x3 ¼ 0; ynþ1 ¼ p: If yn ¼ 1 and x3 ¼ 1; ynþ1 is 0. If theinitial phase is ‘0’, the signal is positive and, if the initial phase is ‘1’, the signal is negative. Onlyif these conditions are met is continuity granted. According to Figure 3 and Table II, thetransmitted signals at the phase transitions are as follows: from 0 phase to 0, s0; s2; s4; s6; from 0phase to p phase, s1; s3; s5; s7; from p phase to 0 phase, s9; s11; s13; s15 and from p phase to pphase, s8; s10; s12; s14:

At the receiver side, since message passing algorithm, which is used as decoding procedure inLDPC decoder, uses one and zero probabilities of received signal, for every decoding interval,

Table I. Input–output and signal constellation for 8-ary CPFSK.

yn bn x1 x2 x3 x4 ynþ1 8-ary CPFSK

0 0 0 0 0 0 0 s00 1 0 0 1 0 p s10 2 0 1 0 0 0 s20 3 0 1 1 0 p s30 4 1 0 0 0 0 s40 5 1 0 1 0 p s50 6 1 1 0 0 0 s60 7 1 1 1 0 p s7p 0 0 0 0 1 p s8 ¼ �s0p 1 0 0 1 1 0 s9 ¼ �s1p 2 0 1 0 1 p s10 ¼ �s2p 3 0 1 1 1 0 s11 ¼ �s3p 4 1 0 0 1 p s12 ¼ �s4p 5 1 0 1 1 0 s13 ¼ �s5p 6 1 1 0 1 p s14 ¼ �s6p 7 1 1 1 1 0 s15 ¼ �s7

Table II. Degree distribution of irregular LDPC code.

x; y lx ly

2 0.47718 }3 0.28075 }5 0.097222 }7 0.0089286 }8 } 114 0.00099206 }15 0.1002 }



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one and zero probabilities are firstly evaluated for all parallel input branch sequences accordingto partitioning rule. These probabilities are calculated as

PL0 ¼

1

M

XM�1i¼0

1

ðrk � s2iÞ2

" #ð16Þ

PL1 ¼

1

M

XM�1i¼0

1

rk � s2iþ1ð Þ2

" #ð17Þ

where rk is received signal, L is partitioning level and si is the transmitted M-ary CPFSK signal.After computing the one and zero probabilities as in (16) and (17), the received signal is

mapped onto a one-dimensional BPSK signal as below

gL ¼ 1�2 � PL

0

PL0 þ PL

1

ð18Þ

These probability computations and mapping are executed in every partitioning level accordingto the signal set, which is shown in Figure 3. For partitioning level 1–3 these probabilities arecalculated as in Equations (19)–(24) wherePL

i ; i denotes ‘0’ or ‘1’ probability and L denotespartitioning level, rk is the received noisy CPFSK signal:

P10 ¼

1

8

X7i¼0

1

ðrk � s2iÞ2

" #ð19Þ

P11 ¼

1

8

X7i¼0

1

ðrk � s2iþ1Þ2

" #ð20Þ

P20 ¼

1

8

X1i¼0

1

ðrk � siÞ2þ

1

ðrk � siþ4Þ2þ

1

ðrk � siþ8Þ2þ

1

ðrk � siþ12Þ2

� �" #ð21Þ

P21 ¼

1

8

X1i¼0

1

ðrk � siþ2Þ2þ

1

ðrk � siþ6Þ2þ

1

ðrk � siþ10Þ2þ

1

ðrk � siþ14Þ2

� �" #ð22Þ

P30 ¼

1

8

X3i¼0

1

ðrk � siÞ2þ

1

ðrk � siþ8Þ2

� �" #ð23Þ

P31 ¼

1

8

X3i¼0

1

ðrk � siþ4Þ2þ

1

ðrk � siþ12Þ2

� �" #ð24Þ

For every partitioning level, these one and zero probabilities are evaluated and then #ci’sestimated from formulae (8)–(12).



DOI: 10.1002/dac

5. SIMULATIONS RESULTS

In our study, we combine LDPC codes and CPM structure together. For simulation purpose,we use (3,6) regular and irregular, which has a degree distribution shown in Table II,LDPC codes. Block length is chosen 504 bits and the number of maximum iteration is 100. Inboth regular and irregular codes, we design three LDPC coded CPFSK scheme for4-ary CPFSK, 8-ary CPFSK and 16-ary CPFSK. The bit error ratio (BER) versus signal tonoise ratio (SNR) curves of the proposed systems (LDPCC 4-ary CPFSK, LDPCC8-ary CPFSK, LDPCC 16-ary CPFSK) are obtained for AWGN, Rician (for Ricianchannel parameter K ¼ 10 dB) and Rayleigh channels using Monte-Carlo simulationtechnique. To compare performance of our schemes, we also simulate BPSK system, which isencoded by the same LDPC codes. The results are shown in Figures 4–9. Although LDPCC8-ary CPFSK, LDPCC 16-ary CPFSK systems have higher bit/symbol rate than LDPC codedBPSK scheme, our proposed systems have better error performance in all channels and SNRvalues.

For regular LDPC code, our proposed LDPCC-CPFSK systems provide coding gains 1.48 dBup to 3.88 dB on various channels. Consequently irregular LDPCC-CPFSK systems have gainsbetween 1.3 and 4 dB as seen in Table III. As an example, LDPCC 8-ary CPFSK, LDPCC16-ary CPFSK have 1.78 and 2.57 dB coding gains, respectively, on AWGN channel for a biterror rate of 10�4 compared to LDPCC-BPSK system. As it can be seen in simulation resultsLDPCC-BPSK has better error performance than LDPCC 4-ary CPFSK, since BPSK hasdouble bit/symbol rate (1

2bit/symbol) compared to LDPCC 4-ary CPFSK system (1 bit/symbol).

Even though, LDPCC 8-ary CPFSK and 16-ary CPFSK systems also have higher bit/symbolrate (1.5 and 2 bit/symbol) than LDPCC-BPSK system, they have significant coding gains

Figure 4. Error performance of regular LDPCC-CPFSK system on AWGN channel.



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because channel signals have 8 and 16 dimensions for 8-ary CPFSK and 16-ary CPFSK,respectively. Thus, as the modulated signal dimension (M) of M-ary CPFSK modulationincreases, better error performances are obtained.

Figure 5. Error performance of regular LDPCC-CPFSK system on Rayleigh channel.

Figure 6. Error performance of regular LDPCC-CPFSK system on Rician ðK ¼ 10 dBÞ channel.



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6. CONCLUSION

In this paper, we evaluate error performance of LDPC coded CPFSK. For this purpose, wedesign several systems. The performances of these systems are compared to LDPC coded BPSK(LDPCC-BPSK) system. It is shown that our proposed systems provide significant amount of

Figure 7. Error performance of irregular LDPCC-CPFSK system on AWGN channel.

Figure 8. Error performance of regular LDPCC-CPFSK system on Rayleigh channel.



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coding gains over LDPCC-BPSK system. Furthermore, since CPFSK is selected as modulator,our system has also bandwidth efficiency. Thus, our system has important power and bandwidthadvantages and is very suitable for low power and band limited applications such as satellite andmobile radio communications.

ACKNOWLEDGEMENTS

This work was supported by the Research Fund of The University of Istanbul. Project number: 354/03062005.

REFERENCES

1. Gallager RG. Low-Density Parity-Check Codes. MIT Press: Cambridge, MA, 1963.2. Zyablov V, Pinkster M. Estimation of the error-correction complexity of Gallager low-density codes. Problemy

Peredachi Informatsii 1975; 11:23–26.3. Margulis GA. Explicit construction of graphs without short cycles and low density codes. Combinatorica 1982;

2(1):71–78.4. Tanner R. A recursive approach to low complexity codes. IEEE Transactions on Information Theory 1982;

IT-27:533–547.

Figure 9. Error performance of regular LDPCC-CPFSK system on Rician ðK ¼ 10Þ channel.

Table III. Proposed systems’ coding gains (in dB) over LDPCC-BSPK system for Pb ¼ 10�4:

System AWGN channel Rician channel ðK ¼ 10 dBÞ Rayleigh channel

Coding gains for LDPCC-CPFSK over LDPCC-BPSK for regular LDPC code8-ary CPFSK 1.78 1.62 1.4816-ary CPFSK 2.57 2.71 3.88

Coding gains for LDPCC-CPFSK over LDPCC-BPSK for irregular LDPC code8-ary CPFSK 1.59 1.5 1.316-ary CPFSK 2.24 2.5 4



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5. MacKay DJC, Neal RM. Near Shannon limit performance of low density parity check codes. Electronic Letters1996; 32:1645–1646.

6. Wiberg N. Codes and decoding on general graphs. Dissertation on. 440, Department of Electronics, LinkopingUniversity, Linkoping, Sweden, 1996.

7. MacKay DJ, Wilson ST, Davey MC. Comparison of construction of irregular Gallager codes. IEEE Transactions onCommunications 1999; 47:1449–1454.

8. Richardson TJ, Urbanke RL. Efficient encoding of low density parity-check codes. IEEE Transactions onInformation Theory 2001; 47:638–656.

9 Luby MG, Mitzenmacher M, Shrokrollahi MA, Spielman D, Stemann V. Practical loss-resilient codes. InProceedings of the 29th Annual ACM Symposium on Theory of Computing, Texas, U.S.A., 1997; 150–159.

10. Rimoldi BE. A decomposition approach to CPM. IEEE Transactions on Information Theory 1988; 34:260–270.11 Shane MR, Wesel RD. Parallel concatenated turbo codes for continuous phase modulation. In Proceedings of

WCNC, vol. 1, Chicago, U.S.A., 2000; 147–152.12. Szego V, Pasupathy P. Iterative decoding of serially concatenated convolutional codes and MSK. IEEE

Communication Letters 1999; 3(9):272–274.13 Richardson TJ, Urbanke RL. The capacity of low-density parity-check codes under message-passing decoding. IEEE

Transactions on Information Theory 2001; 47:599–618.

AUTHORS’ BIOGRAPHIES

Yesim Hekim was born in Ordu, Turkey in 1981. She received the BSc, MSc degree

from the University of Istanbul, Department of Electrical and Electronics

Engineering in 2003 and 2005, respectively. Since 2004 she has been working as a

research assistant at Istanbul University Engineering Faculty, Department of

Electrical and Electronics Engineering. At present, she is pursuing the PhD degree in

Electrical and Electronics Engineering in the Department of Electrical and

Electronics Engineering at the University of Istanbul. Her research interests include

source coding, channel coding, modulation techniques and image transmission.

Niyazi Odabasioglu was born in Konya, Turkey in 1978. He received the BSc, MSc

and PhD degree from the University of Istanbul, Department of Electrical and

Electronics Engineering in 1999, 2002 and 2006, respectively. Since 1999 he has been

working as a research assistant at Istanbul University Engineering Faculty,

Department of Electrical and Electronics Engineering. His current research interests

are digital and wireless communication systems, especially channel coding and

modulation techniques.

Osman Nuri Ucan was born in Kars, Turkey on January, 1960. He received the

BSEE, MSEE and PhD degrees in Electronics and Communication Engineering

Department from the Istanbul Technical University in 1985, 1988 and 1995,

respectively. During 1986–1997 he worked as a research assistant in the same

university. He is now Professor and Vice Dean of Istanbul University Engineering

Faculty. His current research areas include: information theory, jitter analysis of

modulated signals, channel modeling, cellular neural network systems, turbo coding

and Markov Random Field applications on real geophysics data, satellite based 2-D

data image processing.



DOI: 10.1002/dac

performance of low density parity check coded continuous phase frequency shift keying (ldpcc-cpfsk)...

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