inside: your hipeac jobs poster

Inside:

your HiPEAC

Jobs poster

51APPEARS QUARTERLY | JULY 2017INFO

Team Europe: A workforce for the digital age

Martin Kersten’s forgetful databases

Made in Croatia: the world’s fastest electric car

Digital skills for a competitive Europe

Team Europe. Getting the brains to power the digital revolution

‘Data will rot away like everything in nature’

4 1512

contents

3 WelcomeKoen De Bosschere

4 Policy corner Digital skills for a competitive Europe

Heidi Cigan

12 HiPEAC voices ‘Data will rot away like everything in nature’

Martin Kersten

14 HiPEAC Jobs Trends in computing systems jobs

Xavier Salazar and Anna Molinet

15 Recruitment special Team Europe: Getting the brains to power the digital

revolutionSabri Pllana, Marisa Gil, Dionisios Pnevmatikatos, Alexey Cheptsov, Marc Gonzalez Vidal, Bev Bachmayer, Graham Mudd, Angela Bradfield, Meenakshi Ravindran and Karon Davis

22 Inside the box Well hello, AXIOM board!

Maurizio Caporali, Davide Catani and Xavier Martorell

24 Innovation Europe UpScale framework for real-time HPC applications

Luis Miguel Pinho

25 Innovation Europe InnoHPC brings HPC to the Danube region

Karina Pešatová

26 Innovation Europe The Heterogeneous Hardware and Software Alliance

Karim Djemame and Oliver Barreto

28 Peac performance Parallelizing Python codes using the superscalar

paradigmRosa Badia

30 Technology opinion Neuromorphic Computing: low-power systems,

the brainy wayKemal Delic and Dave Penkler

31 Technology entrepreneurship Keep the revolution going

Colin Adams

33 Industry focus Cache-aware Roofline Model in Intel® Advisor

Leonel Sousa, Aleksandar Ilić and Frederico Pratas

35 SME snapshot Rimac Automobili: The drive to succeed

Aco Momčilović, Matija Gracin and Marta Longin

36 HiPEAC futures Career talk: Michael Hübner, Ruhr-Universität Bochum HiPEAC collaboration grants: When Manchester met

‘Silicon Island’, Crete HiPEAC internships: Transport safety as standard Three-minute thesis: Memory access control which is

right on time

HiPEACINFO 512

The drive to succeedKeep the revolution goingParallelizing Python

353128

This issue is about digital skills. As the director of the computer engineering degree of

Ghent University for more than 10 years, this subject is close to my heart. Two large ICT

companies in Belgium have more open positions every year for computer engineers

than the total number of graduates in one year in Ghent. That is painful for them, but

they can still recruit internationally. Startup companies that do not find local talent face

more serious issues. Every month I receive emails from desperate startup founders who

have the money to hire computer engineers, but simply cannot find them. Hence, the

lack of qualitied ICT workers is slowing down innovation.

In 2016, Google published a report titled ‘Digitizing Belgium’, concluding that digiti

zation could lead to more than 300,000 jobs by 2020, or 100,000 per year from now on.

Yet we know how many computing experts will graduate in 2020 from the numbers

currently at university: at master’s level, there will be less than 1,000 for Belgium as a

whole. At best, taking into account all businessrelated ICT degrees and STEM degrees

that include decent software development skills, we might end up with 10 times more,

not 100 times more.

All wellintended digitization plans (the internet of things, Industrie 4.0, Smart Anything

Everywhere, etc.) will fail to deliver their full potential if we do not fix the workforce

issue first. Structurally increasing the number of graduates will take up to 10 years

because we have to start by sparking interest for computing at highschool level.

Retraining people could help in the short term, but a sixmonth training course will

never be a substitute for a four to fiveyear university degree. This is particularly

important given the complexity of modern information processing systems. Producing

inefficient and incorrect software leads to the accumulation of technical debt, to failing

systems, to security, safety and privacy issues.

Many of you will be reading this issue at the HiPEAC summer school, ACACES, which

is our contribution to training the crème de la crème of computing experts in Europe.

You will find a HiPEAC Jobs poster inside: by posting this at your organization, you will

also help ensure the best candidates find their ideal jobs.

We wish you a relaxing summer, and we hope to see you again after the summer

holiday in good health, and full of plans for the year to come.

Koen De Bosschere, HiPEAC coordinator

welcome

HiPEAC is the European network on high performance and embedded architecture and compilation.

hipeac.net

@hipeac hipeac.net/linkedin

HiPEAC has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement no. 687698.

Design: www.magelaan.be

Editor: Madeleine Gray

Email: [email protected]

HiPEACINFO 51 3

Digital technologies are advancing and

leading to the development of everything

from digital medical diagnosis and auto

nomous vehicles to drones and smart

fridges. Where digital was once a sector, it

is increasingly spreading to the whole

economy as society undergoes a digital

transformation.

This digital transformation of the economy

and society is also accelerating. The pace

of technological adoption is speeding up.

New technologies enter the market and

are being taken up more quickly than ever

before. For example, while it took decades

for the telephone to reach 50 % of house

holds, it took mobile phones less than five

years to reach the same penetration rate.

Today in Europe, there are 137 mobile

phone subscriptions for every 100 people.

Smart phones reached 40 % penetration

in just 10 years. New technologies such as

cloud services and social networks are

also being rapidly taken up. Indeed, in

2016, 62 % of internet users and 45 % of

enterprises in the European Union used

social networks.

To use these new technologies and ensure

individuals, companies, regions and coun

tries get the benefit from them, people

need to be able to use and work with

them. However, while technological

develop ment and adoption is speeding up,

people’s skills and the education and

training systems that are there to develop

them are slower to adapt.

Schools still lag behind in terms of digital

education. Equipment is still lacking in

many places and teachers, though often

willing, lack the skills and confidence to

make the most out of digital tools for

learning and teaching the next generation

how to use them. Digital tools are under

used in the classroom and most students

are still not taught the basics of computer

science and how to code – skills and com

petences that are increasingly becoming

essential for an understanding of the

world we live in. In higher education,

graduations in computer science have

fallen substantially over the past 10 years

and those students who do graduate are

often not considered work ready by

employers.

It is hardly surprising, then, that we do

not have enough of the skilled technology

experts – big data experts, cloud deve

lopers and cybersecurity experts – we

need for the new jobs emerging in the

economy. In fact, Europe already has a

large and growing deficit of digital experts.

From 373,000 in 2015, this gap could

grow to around half a million by 2020.

Digitally skilled workers are lacking at all

levels and in all sectors. For industry, and

the economy more broadly, to digitize,

workers in all sectors need to develop new

skills to work in the digitized workplace

and to remain employable. However, 37 %

of the labour force in the EU lacks basic

skills for the use of digital technologies.

Furthermore, while most companies are

aware that lacking digital skills in their

Digital skills for a competitive EuropeIn a special guest piece for HiPEACinfo, Heidi Cigan of the Directorate-General for Communications Networks, Content and Technology at the European Commission gives us the latest on the digital transformation, the need for new skills and the Digital Skills and Jobs Coalition.

Policy corner

HiPEACINFO 514

workforces negatively affect business per

formance, most do not provide oppor

tunities for their employees to reskill.

To support the development of digital

skills in Europe, on 1 December 2016 the

European Commission launched the

Digital Skills and Jobs Coalition. The

Coalition brings together stakeholders

from, for example, industry, education,

government and social partners to share

best practices and make ‘pledges’ to

provide training and carry out other

activities, such as awarenessraising activi

ties, to increase the digital skills of

European citizens.

Member States have been asked to develop

comprehensive digital skills strategies and

to set up national digital skills coalitions

involving a broad range of stakeholders in

order to support the implementation of

these strategies. The Commission has set

up a Coalition secretariat to support the

setup of national coalitions – for which a

small amount of ‘seed funding’ has been

provided – and other activities.

The Commission is also working with

Member States, through an expert group,

to support the development of national

digital skills strategies. The group has put

together a joint strategy document which

collects the main challenges faced and

solutions found by Member States in the

area of digital skills. A selection of best

practices has been linked to it and

published online as a tool to be used for

the development of digital skills strategies

and replication of solutions that work.

Since its launch, the Coalition has attrac ted

over 200 member organisations and around

70 pledges. Sixteen National Coalitions are

in operation or being developed.

The aim of the Coalition is to train over a

million people over the next two years, to

ensure Europe has a pool of digital experts,

and that workers and citizens more broadly

have the skills they need to succeed in the

digital transformation.

As a concrete contribution to this goal, on

23 March 2017, as part of the Digital Day

in Rome, the Commission announced the

launch of a new multimillion euro ‘Digital

Opportunity’ pilot scheme to provide

intern ships for current and recent

graduates of all disciplines in digital

domains. It is envisaged that these intern

ships should focus on ‘deep tech’ skills

such as such as cybersecurity, big data,

quantum or artificial intelligence, as well

as on more horizontal activities such as

web design, digital marketing, software

development, coding or graphic design.

The pilot scheme will initially run for two

years from 20182020 and will support up

to 6,000 paid internships.

To achieve our goals, we need to get all

stakeholders on board, and the HiPEAC

community can play an important role. You

are a large group of skilled professionals

with a wealth of knowledge in all areas of

digital technology, and you can potentially

make a huge contribution to the dissemi

nation of digital skills across Europe. For

many of you teaching is a primary activity,

so you know the challen ges ahead. We

invite you to join the Coalition and make

your own contribution to securing our

digital future.

MORE INFORMATION:

https://ec.europa.eu/digital-single-market/en/

digital-skills-jobs-coalition


european-digital-progress-report

http://bit.ly/EC_Digital_Skills_Report


digital-scoreboard

Digital skills for a competitive EuropePolicy corner

HiPEACINFO 51 5

HiPEAC news

HiPEAC on the road

Over the last few months, HiPEAC has been at

a number of key events in the computing

calen dar, spreading the word about HiPEAC

services and research by the HiPEAC community.

At Embedded World in March, HiPEAC hosted

a session on high-performance and embedded

architectures, and at DATE 2017 (Design,

Automation and Test in Europe) HiPEAC

organized a special session focusing on Euro-

pean research. Meanwhile, HiPEAC’s exhibition

booths at DATE and ISC High Performance

2017 featured presentations by European

projects and the HiPEAC mobile careers unit,

displaying computing systems vacancies from

across Europe.

HiPEAC also hosted a booth at the Digital

Innovation Forum in May, providing the oppor-

tunity to speak to business leaders about how

HiPEAC’s members can help digitize European

industry.

The HiPEAC Jobs mobile careers unit at DATE

2017

A warm Croatian welcome awaited Com-

puting Systems Week in Zagreb on 27 and

28 April, which brought together over 130

participants from academia and industry.

The event featured keynote talks on how

Rimac Automobili went from a hobby

project to building the world’s fastest

electric car and from Martin Kersten on

database management systems.

In his policy briefing, the European

Commission’s Panagiotis Tsarchopoulos set

out the direction of public HPC research

over the next few years. Advances in HPC

spurred by the European projects MANGO,

ExaNeSt, EcoScale and ExaNoDe were

presented, while EuroLab-4-HPC presented

HPC road mapping work and chaired a panel

session on open-source software for data

centres and HPC.

The event also featured a session focusing

on digital health – a key topic for the

HiPEAC community, given that health is the

second biggest market for embedded

systems in Europe. Representatives from

Ericsson Nikola Tesla, Xsensio and Bluebee

identified challenges and highlighted the

latest innovations in this field.

This Computing Systems Week also sought

to help early career computer scientists

develop their skills and explore career oppor-

tunities. With career advice and com pany

pitches, the ‘Inspiring futures! Researchers’

careers’ session offered students the chance

to find out more about different aspects of

their future in computing.

Meanwhile, the second edition of the

Student Heterogeneous Programming

Challenge gave students free reign to find

the best solutions for k-means clustering, a

popular approach for big data analytics and

machine learning. Marcos Canales, of the

'Heterogeniuses' team, commen ted that the

challenge provided 'a unique opportunity to

work with different people from the super-

computing area’, resulting in an experience

which was ‘truly enriching and represents

the spark of what may become future colla-

boration'. He added: 'The HiPEAC Student

Heterogeneous Programming Challenge is a

must for any student starting a career in

supercomputing.'

With the aim of helping researchers get

their message across, HiPEAC also organized

a media skills workshop at the event.

Learning from good (and bad) examples,

participants learned the basics of working

with the media, drafted press releases, and

gave mock interviews for radio and

television.

Thanks to local host Mario Kovac and his

team at the University of Zagreb for their

hospitality in the stunning Croatian capital.

See our interview with Martin Kersten on

p.12. For more on Rimac Automobili, see

p.25.

Hvala Zagreb!Digital health, the future of HPC and preparing new generations of computer scientists

Phot

o: E

nek

o Il

larr

amen

di

HiPEACINFO 516

HiPEAC news

European cooperation on connected mobility and digital industryDigital Day, which formed part of the 60th anniversary celebrations

of the Treaties of Rome, also saw 29 European countries sign a Letter

of Intent to intensify cooperation on testing of automated road

transport in cross-border test sites. The initiative aims to drive for-

ward plans in the European Data Economy strategy.

National elected representatives and industry leaders also pledged

to collaborate in the European platform on digitizing industry. The

platform will trigger collaboration and joint investments, provide a

forum to explore common approaches to regulatory problems and

help industries and countries exchange the means for workforce

re-skilling.

The event also saw the launch of the European Interoperability

Framework (EIF), which gives specific guidance on setting up inter-

operable digital public services.

Digital Day website: http://bit.ly/DigitalDay_EU

EU states to work together for world-class HPCOn 23 March, during Digital Day in Rome, ministers from seven

European countries (France, Germany, Italy, Luxembourg, the Nether-

lands, Portugal and Spain) signed a declaration to support the next

generation of computing and data infrastructures. The states will

work towards the establishment of a multi-government cooperation

framework for acquiring and deploying an integrated supercomputing

infrastructure for the exascale computing generation. Named

EuroHPC, the European Commission says that this project will be the

size of Airbus in the 1990s and of Galileo in the 2000s. It will provide

a major role for leading supercomputing centres and scientists in

Europe. In June, Belgium also joined the agreement.

HiPEAC co-founder and coordinator of HiPEAC 1, Mateo Valero, who

is the director of Barcelona Supercomputing Center, represented the

view from the supercomputing sector in a panel discussion on ‘How

Europe can regain leadership in HPC’. In his talk, Valero stressed the

importance of investing in hardware design in Europe to complement

existing strengths in software, mentioning how HiPEAC performs a

key role in promoting collaboration across the computing systems

spectrum. ‘If we don’t produce our own hardware, we won’t have

security […] and we also need to protect our companies,’ he

commented. For several years, Valero has been calling for the

establishment of an ‘Airbus-type consortium’ for HPC and big data,

in order to develop a full domestic exascale stack in Europe.

With a view to creating the chips of the future here in Europe, the

Commission included a challenge to develop a working prototype of

a low-power processor design in the ICT-05-2017 call for project

proposals (as reported in HiPEACinfo no.48). Successful projects will

be announced in the autumn.

Further information and a video of the panel discussion are

available on the European Commission website:

http://bit.ly/Digital-Day_HPC. See http://bit.ly/EuroHPC

for more details about EuroHPC.

Imec launches self-learning chip The Belgian innovation hub imec has demonstrated a self-learning neu-

romorphic chip. The chip, which imec says is a world first, is based on

OxRAM technology and has been shown to be able to compose music.

By co-optimizing the hardware and software, the chip concentrates

machine-learning characteristics in a small area, while consuming very

little power.

Ultimately, imec aims to achieve low-power, high-performance, intelli-

gent chips for a range of applications.

Visit the imec website for further information: http://bit.ly/imec_chip

HiPEACINFO 51 7

HiPEAC news

Rainer Leupers, RWTH Aachen University,

TETRAMAX project coordinator

Many HiPEACinfo readers will have heard

about, or even participated in, the TETRACOM

FP7 Coordination Action (www.tetracom.eu)

during 2013-2016. Its focus was on small to

medium scale academia-to-industry technology transfer projects (TTPs),

each one revolving around industrial uptake of specific software or

hardware intellectual property (IP) generated in research projects.

TETRACOM coordinated and sponsored 50 TTPs in total and had a

tangible impact on the European ICT landscape, as indicated by the

numbers given below.

We are excited to announce that this success story will be continued at

a much larger scale and with even higher ambitions during 2017-2021

thanks to the TETRAMAX project (www.tetramax.eu). Enabled by a total

budget of €7 million and 22 partners from all over Europe, this new

Horizon2020 Innovation Action will provide an implementation of the

European Smart Anything Everywhere (SAE) initiative in the domain of

customized and low-energy computing for cyber-physical systems and

the internet of things.

The project builds on three major activity lines:

1. Stimulating, organizing, co-funding, and evaluating different types of

cross-border technology transfer experiments, providing ‘EU added

value’ via innovative technologies to first-time users and broad

markets in European ICT-related industries.

2. Building and leveraging a new European competence centre network,

offering technology brokerage, one-stop shop assistance and training

in customized/low-power computing to small and medium-sized

enterprises (SMEs) and mid-caps. This will have a clear evolution

path towards new regional digital innovation hubs where needed.

3. Paving the way towards self-sustainability based on pragmatic and

customized long-term business plans.

The project impact will be measured based on well-defined, goal-

oriented performance indicators. The immediate aim is to support 50+

industry clients and third parties across the entire European Union with

innovative technologies. This will lead to an estimated revenue increase

of € 25 million based on 50+ new or improved customized, low-power

com puting products, the creation of at least 10 entirely new businesses/

SMEs, over 30 new permanent jobs and significant cost and energy

savings in product manufacturing. Moreover, in the long term,

TETRAMAX will be the trailblazer towards a reinforced, profitable, and

sustainable ecosystem infrastructure, providing competence, services

and a continuous innovation stream in customized/low-power com-

puting at European scale, yet with strong regional presence, as preferred

by SMEs.

Just like TETRACOM, TETRAMAX will work closely with HiPEAC via joint

event organization and dissemination. We also expect that the HiPEAC

community will be particularly interested in participating in our open

calls for co-funded technology transfer experiments.

Stay tuned for further announcements and pass this news on to your

European technology transfer partners, so as to be ready for the first

open calls to be published soon after the project kickoff in September.

www.tetramax.eu

TETRACOM evolves into TETRAMAX

TETRACOM’s vital statistics in tech transfer

HiPEACINFO 518

HiPEAC news

Turbo-charge your code with POP’s webinar series

Want to maximize your code’s performance?

POP, the EU-funded Centre of Excellence in

Performance Optimisation and Productivity, is

offering a series of webinars focusing on how

to optimize parallel codes for research and

industry. The webinars provide expert guid-

ance on code optimization, with practical

demonstrations and implementations on real

applications.

Coordinated by Barcelona Supercomputing

Center, POP brings together expertise from

across Europe. It offers services to provide

greater awareness of issues affecting comput-

ing performance, help manage the complexity

of modern computing and maximize the effi-

ciency of compute-intensive applications.

For further information, visit the POP website:

https://pop-coe.eu

New TaPaSCo tool composes accelerators into bitstreams for FPGAsJens Korinth, Technische Universität Darmstadt

The Embedded Systems and Applications Group (ESA) at TU Darmstadt is pleased to announce

the public release of TaPaSCo (Task Parallel System Composer), the successor to ThreadPool-

Composer, an open-source toolchain for creating task-parallel system-on-chip architectures

for hardware accelerators on FPGAs. TaPaSCo composes accelerators formulated in Verilog/

VHDL, or by high-level synthesis (HLS) in C/C++, into ready-to-use bitstreams for a range of

Xilinx FPGAs.

The tool can automatically scale the number of accelerator instances, aiming for the ideal

trade-off between area utilization and operating frequency. On the software side, the accel-

erators in the bitstreams generated by TaPaSCo are accessible using a universal easy-to-use

C/C++ API across multiple FPGA platforms. TaPaSCo currently supports PyNQ and ZedBoard,

Xilinx ZC706 Zynq and VC709 FPGA platforms, thus spanning the embedded, desktop, and

high-performance computing domains.

The tool is open source and has been designed with easy extensibility and modifiability in

mind. It is the result of three years of development in the EU FP7 project REPARA and is cur-

rently being used by a number of academic and industrial partners outside of TU Darmstadt.

The tool has proven especially useful in conjunction with HLS, since it easily closes the gap

between the hardware of individual accelerators and their integration into a hardware/soft-

ware system.

With the 2017.1 release of TaPaSCo, we cordially invite the research community to make use

of and participate in this project. Both the tool as well as introductory materials are available

from a dedicated GitLab site. We highly appreciate feedback, questions and contributions -

anyone is invited to contribute to the toolchain, be it extensions, modifications, bugfixes,

benchmarks, or other results. A bugtracker is available to request new features, or report

bugs; also, do not hesitate to contact us when you run into problems. Judging from the feed-

back of our existing users, TaPaSCo has significantly reduced their engineering efforts

required to make reconfigurable computing actually usable and avoided the need to reinvent

the wheel for the different computing platforms.

REPARA project: http://repara-project.eu

TaPaSCo GitLab site: http://bit.ly/TaPaSCo_GitLab

“POP webinars provide expert guidance on code optimization”

HiPEACINFO 51 9

Congratulations to Silexica, the RWTH Aachen

University spin-off specializing in multicore

software design automation, on being named

one of three finalists for the German Entrepre-

neur Award 2017 in the StartUp category. At

the time of going to press the winners had

not been announced.

In April, the company released the latest ver-

sion (2017.4) of its SLX Tool Suite. This

release provides many new features to

improve the efficiency of multicore program-

ming and code distribution. These include:

• The SLX Parallelizer now has a powerful

reconfigurable cache analyser that simu-

lates cache behaviour and estimates usage

statistics.

• The SLX Mapper has a new set of visuali-

zation capabilities providing deeper

insights into application runtime behav-

iour of computed/simulated mappings.

• The SLX Generator now features added

support for additional processor cores

such as 32-bit ARMv7 and 64-bit ARMv8,

as well as Linux-based Power-PC 32-bit

and 64-bit processors.

• The SLX Automotive Development pack-

age is now available with the rest of the

SLX tools.

silexica.com

Find out who was named German Entrepre-

neur 2017 on the awards website:

www.deutscher-gruenderpreis.de/en

HiPEAC news

What the F-OMP is going on in OpenMP?F-OMP: A Feedback monitoring infrastruc-

ture for OpenMP on embedded systems

Giacomo Valente, University of L'Aquila

Embedded systems normally execute appli-

cations with both functional and non-func-

tional constraints, and the underlying hard-

ware and software can be very complex and

heterogeneous. Different techniques are

used to manage the complexity of develop-

ing a system which meets the necessary

constraints. Among them is the use of

OpenMP, which supports designers in paral-

lelizing applications written in C/C++ and

Fortran code.

As OpenMP allows implicit parallelism, it is

harder to control all the factors involved in

the performance, such as memory accesses,

cache behaviour and thread mutual exclu-

sions. To solve this, F-OMP proposes a moni-

toring infrastructure which provides feed-

back about the use of OpenMP in an

embedded platform, developed on FPGA.

Specifically, it uses metrics to organize data

collected at runtime into useful information

(estimated speed-up, load balancing and

false sharing), providing feedback to the

designer without inserting software overhead.

We have implemented F-OMP on a Zynq7000

SoC, with a dual-core ARM processor as the

master processing element and four-core

Leon3 SMP as an isle of computational ele-

ments. This isle executes a Linux operating

system, which provides support for OpenMP

applications, and it executes two OpenMP

benchmarks with data provided by the

master processing element. The F-OMP

system was inserted in the platform, provid-

ing the metrics listed above.

Silexica’s Maximilian Odendahl and Johannes Emigholz

Silexica reach German Entrepreneur Award finals

HiPEACINFO 5110

HiPEAC news

Roger Needham Award presented to Alastair Donaldson

Congratulations to HiPEAC member

Alastair Donaldson, who has been pre-

sented the BCS Academy of Computing

Roger Needham Award 2017. The award,

which is sponsored by Microsoft Research

Cambridge, was given to Donaldson ‘in rec-

ognition of his outstanding work in the area

of many-core programming’.

According to BCS, Dr Donaldson, from the

Department of Computing at Imperial Col-

lege London, has ‘made a distinguished

contribution through his design and appli-

cation of rigorous program analysis meth-

ods to the emerging field of many-core

programming. His techniques and case

studies have also made a major contribu-

tion to fundamental Computer Science

research’. Dr Donaldson’s work centres

around formal verification, systematic test-

ing, programming language design and

compiler technology.

On receiving the award, Dr Donaldson said:

‘I'm incredibly honoured to be receiving

the 2017 Roger Needham Award. It's really

exciting to have my work recognized via

the award, and more generally the award

emphasizes the importance and potential

of research in programming languages and

analysis and verification.’

Further information can be found on the

BCS website: http://bit.ly/

RogerNeedham_AlastairDonaldson

Amir Ashouri wins Italian IEEE Computer Society PhD Thesis Award

HiPEAC student Amir Ashouri’s PhD thesis has been

selected as the winner of the 2016 IEEE Computer

Society Italy Section Chapter PhD Thesis Award. His

winning thesis, titled 'Compiler Autotuning Using

Machine Learning Techniques', was written under

the supervision of professors Cristina Silvano and

Gianluca Palermo at the Politecnico di Milano, as

well as John Cavazos of the University of Delaware.

Congratulations to Amir on winning this award!

Further information can be found on the IEEE Computer Society website:

http://bit.ly/IEEE_CS_Italy_PhD

Mateo Valero wins IEEE-CS Charles Babbage AwardMateo Valero, professor in the Computer Archi-

tecture Department at the Universitat Poli-

tècnica de Catalunya – Barcelona Tech and

director of Barcelona Supercomputing Center,

has been awarded the 2017 IEEE Computer

Society Charles Babbage Award. According to

the IEEE, this award recognizes Valero’s ‘contri-

butions to parallel computation through brilliant

technical work, mentoring PhD students, and

building an incredibly productive European

research environment’. The award was presented

at the annual IEEE-CS Inter na tional Parallel and

Distributed Processing Symposium (IPDPS

2017), where Valero presen ted a keynote

speech on runtime-aware architectures.

Valero, who co-founded HiPEAC and coordi-

nated the first phase of the project, has won

numerous awards over his career. These

include the 2007 IEEE/ACM Eckert-Mauchly

Award, the 2015 IEEE-CS Seymour Cray Award,

the 2009 IEEE Harry Goode Award, the 2012

ACM Distinguished Service Award and the

2015 Euro-Par Achievement Award, in addition

to multiple awards in his home country of

Spain. He has been given honorary doctorates

by nine universities and was admitted to the

European Union’s ICT (Innovate, Connect,

Transform) Hall of Fame in 2008 as one of the

25 most influential information technology

researchers in Europe. He is a member of five

academies and the school in his hometown,

Alfamén, has been named after him.

Congratulations from the HiPEAC community

on this award!

HiPEACINFO 51 11


HiPEAC news

What does Monet DB offer that other

database technologies don’t?

Monet DB was developed over a period of

twenty years, and its origin was the

decision to change the storage format

from a recordoriented mechanism to a

column structure. When we started the

project in the 90s, this was a nogo area

proven by science. It took us seven years

to prove that it was in fact possible. An

enormous field opened up called data

analytics, where this was the perfect

solution. Since around 2010, all major

database founders have incorporated

columnoriented technology, which we

pioneered, into their product lines.

What is your favourite application of

MonetDB?

Actually, it’s the product itself. I’m really

proud that we were able to build Monet

DB: we worked for it for about 20 years

and I’m really pleased that for all those

years I had a team of very strong hackers

dedicated to making it a viable product.

What’s the most challenging database

project you’ve ever had to work on?

A milestone was in 2005, when we

thought we had a finished product which

we could ship to the outside world. We

found an example in a big catalogue of

astronomical data that was developed by

Jim Gray and Alex Szalay. It was a pivotal

example because it showed that astro

Is it time to rethink our approach to data storage? In this interview, Martin Kersten (Centrum Wiskunde & Informatica) gives us the lowdown on Monet DB, how to deliver the memory for exascale computing and why we should think about whether we really need to keep data forever.

The astronomy field generates huge amounts of dataPhoto: ESA/ATG medialab; background: ESO/S. Brunier

HiPEACINFO 5112


HiPEAC news

nomers could actually do their research on

a database. As a database was available in

public, we thought, ‘if Microsoft SQL

server can do it, so can we’. So we

reimplemented the existing application

using our technology.

In the end, we were the only ones who

successfully mimicked that approach, and

there were some major hurdles along the

way; but the outcome was that all the

technology was available in Monet DB,

open source, even if you did have to pay

Microsoft for the SQL server licences.

Over the last five years, Monet DB has

opened up the whole software ecosystem.

The database system is not a black box,

where you have to use poor APIs to store

and retrieve data. Instead, we have

achieved the blending of your favourite

programming languages, your favourite

libraries, inside the kernel. This signi fi

cantly improves the effectiveness and the

performance of your application/database

combination.

Why is column-store important?

Going from a roworiented representation

to a columnoriented representation, you

get leaner files of data, which gives you

many more opportunities to compress

your data. Compression in a column store

is often better than you would see in

traditional compression structures. This is

relevant because if you can make things

small they require less storage and less

communication to get the data from the

disk into the memory for processing.

The second aspect of the system is that the

execution method used in Monet DB is

completely different from other database

systems. It is much more attainable for

parallel processing. For the details, see the

literature.

How is ExaNeSt (European Exascale

System Interconnect and Storage)

paving the way to exascale computers?

Exascale storage is already there; in fact,

my own lab alone probably has a couple of

petabytes of storage. In ExaNeSt, our

vision is that we can have hundreds of

thousands of processors with limited

memory. This allows us to give people a

small slice of that machinery to do

database processing without any concern

about others trying to use the same

machinery, meaning that you don’t have

competition for resources.

The underlying technology for that is

elasticity of the system, so that it is easy to

repartition your data, your storage plat

form and your compute platform for

particular uses. This is not something you

do every week, or every night – you may

have to do it every minute while your sys

tem is running. So ExaNeSt is about pro

viding extreme elasticity, with a focus on

providing the user the amount of resources

they need to do their job – quickly.

What’s the biggest challenge in the data-

base world over the next 10 years?

There are many; we’ve published a couple

of vision papers on the topic. The latest one

I put on the table for the database commu

nity itself is to stop keeping data around

forever and ever. Rather, we should start

out from the other end of the spectrum and

say, ‘data will actually lose its value, it will

rot away like everything in nature will rot

away’. So we should design a system using

a fundamentally different mechanism.

What this will lead to is that we ask our

users to be more concerned about how

long the data should be maintained, or to

distil it into summarized information. A

good example is to go back to the

astronomers: in the astronomy world,

they collect years of the light intensity of

stars. You can store that – but every star

can actually be approximated with a

Gaussian distribution. This can be stored

in just a few bytes.

Now, wouldn’t it be nice if we took that

enormous catalogue of observations and

turned it into a collection of Gaussian

models? This actually requires less than

one per cent of the storage, but an

astronomer could no longer distinguish

whether they were looking at the actual

data or at models of the data. That would

be my dream for the future: can we

somehow compress the data into much

smaller, manageable and more valuable

pieces of information. In fact, as

individuals we don’t want our personal

data to be retained forever, so having a

database system which starts forgetting by

itself would be a bright future.

www.monetdb.org

www.exanest.eu

HiPEACINFO 51 13

02005

100

200

300

400

500

600

700

800

2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017

9 4 14 17 15 2365

134176

198

351

525

600

PhD Student

OtherMaster

SoftwareEngineer

Engineer

CompanyResearcher

ResearchAssociate Assistant

ResearcherSenior

Researcher

LecturerAssistantProfessor

AssociateProfessor

Professor

PostDoc

C++ Python

SYCL

Javascript

Verilog

Caffe

OmpSs

MPIVHDLOpenCL

JAVA

CUDA

Hadoop

OpenGL

OpenMPLLVM

Tensorflow

Number of vacancies

Levels of experience

Vacancy locations

IoT (77)CPS (33)

Bioinformatics (31)

Fintech (1)

Machine Learning (114)Deep Learning (28)

Artificial Intelligence (16)

Energy (378)

Smart Cities (6)

Computer Vision (50)

Healthcare (46)

Big Data (93)Data Analytics (46)

Automotive (75)

Climate (52)

Timing Analysis (14)

Avionics (16)

Space (144)

Cloud (229)

Technical skills Technological Expertise

Application areas

HiPEAC jobs

Trends in computing systems jobsWith 10, 000 visitors every month, a number that continues to grow,

the HiPEAC Jobs portal is an indispensable resource for anyone looking

for a new opportunity or seeking high-quality staff for specialist com-

puting roles. Over the years it's become a key tool to take European

research forward: in total, 411 jobs related to European projects have

been published on the portal. The vacancies are published on the web-

site for an average of 65 days, which indicates that the technical skills

in demand may be in short supply and provides an indication of the

time needed to find the right candidate. To help spread the word about

the portal, we invite you to display the HiPEAC Jobs poster in this issue

on information boards at universities and schools.

Numbers provided indicate total number of vacancies posted on

the portal

hipeac.net/jobs

450

1

HiPEACINFO 5114

Recruitment special

As Heidi Cigan indicates in her article (pp.45), the digital skills

gap is approaching crisis levels in Europe. In A New Skills Agenda for Europe (2016), the European Commission estimates that

unfilled vacancies for ICT professionals could almost double to

756,000 by 2020. Yet, as the HiPEAC Vision 2017 notes, from

20072013 the number of European graduates in computing only

grew by about 0.5% per year, and even declined in several major

European states.

Europe boasts 42 of the world’s top 100 universities. Although

the quality of education provision varies across the region and

education providers struggle to keep up with the rapid pace of

technological change, many have access to a highquality

Team EuropeGetting the brains to power the digital revolution

education here. However, many skilled graduates leave for

opportunities outside of Europe, perhaps due to the lack of a

digital ecosystem, with major ICT companies being located

outside of Europe. An absence of highprofile industry

spokespeople may also contribute to computer science being less

attractive as a career choice in Europe.

In this article, HiPEAC experts give their opinion on everything

from getting children interested in computer science, to university

curricula, to the unique advantages of working at a smaller

company or a global brand. We also explore European initiatives

promoting excellence in human resources and discuss how to get

more women on board.

A CHALLENGE FOR THE FUTURE

Sabri Pllana, Associate Professor, Department of Computer

Science, Linnaeus University

Europe is already doing well in terms of

computer science education, but we lack

prominent role models. We need to do

more to promote entrepreneurs who have

studied computer science in Europe and

achieved global success in ICT through

the mainstream media.

To attract children’s interest in computer science, it is important

to establish a link between theoretical knowledge and its

application in solving realworld problems early in the learning

experience. We believe that appropriate pedagogical methods

can increase children’s motivation. For instance, competitions

can promote computer science and discover talent among young

people.

SciChallenge aims to boost children’s interest in education and

careers in science, technology, engineering and mathematics

SciChallenge is inspiring young learners in STEM subjects Photo on top © Kinderbüro Universität Wien (Barbara Mair)

HiPEACINFO 51 15

Recruitment special

(STEM) through a panEuropean contest. Contestants were

asked to submit a poster, presentation or video on any STEM

related topic, although SciChallenge suggested 50 topics as

inspiration. Many of these are related to computer science,

including the internet, robotics, cryptography, 3D printing, or

ehealth.

The contest is designed with gender equality in mind and,

interestingly, more than 50% of the contestants are female. One

presentation created by a group of girls for SciChallenge has

attracted over a million views (http://bit.ly/SciChallenge_

ImmortalGirls). The success of female contestants in SciChallenge

will inspire other girls in future.

The results have been inspirational, and there also some potential

future HiPEAC members among the candidates, such as:

• the creators of a device to transport industrial components

using sensors, vacuum grippers and a programmable logic

controller: http://bit.ly/SciChallenge_SLO_SRB

• a group which used machine learning and data analytics to

predict a musician’s future popularity: http://bit.ly/

SciChallenge_Huemer_Jetzinger

• a contestant who developed an Arduinobased motorized

gimbal for camera stabilization: http://bit.ly/

SciChallenge_TadejStrah

TRAINING THE NEXT GENERATION

Marisa Gil, Associate Professor,

Department of Computer Archi tecture,

Universitat Politècnica de Catalunya

– Barcelona Tech

We need a welltrained workforce in

highperformance computing (HPC) and

embedded systems here in Europe because the problems we face

and the continent’s particular characteristics are different to

those of the United States or Asia, for example. Having

homegrown technology professionals helps ensure that the

objectives, challenges and solutions are appropriate and are

those which will really lead Europe to advance.

As a network of computer scientists, within HiPEAC we have a

responsibility to train and nurture future generations, leaving

successors who will continue the work in this area. Educators

need to be capable of training students to be open minded and

able to identify the main issues and objectives. We should

Tadej Strah built a motorized gimbal to stabilize cameras

The full list of finalists is available on the SciChallenge website:

www.scichallenge.eu

SciChallenge is funded by the European Commission’s Horizon 2020 research and innovation programme under grant agreement no 665868.

encourage students to be aware that people and their needs

come before solving technical problems which won’t make the

world simpler and better for everyone. They should be agile and

unafraid of the effort required to effect real change and create

new ways of thinking.

To push their career forwards, students should first undertake a

thorough and personal examination of how they can make the

most of their studies and the opportunities available to them.

Next, they should share their experiences with students and

senior staff. Finally, they shouldn’t be afraid of being a bit short

of money or not knowing exactly what they will do in the future;

they will certainly achieve great things.

Marisa Gil organizes the Student Programming Challenge at Computing Systems Week with Chris Fensch of Heriot-Watt University and Georgios Goumas of the National Technical University of Athens (see p.6).

HiPEACINFO 5116

Recruitment special

CURRICULUM MATTERS: EUROLAB-4-HPC

Dionisios Pnevmatikatos, Affiliated Researcher, Foundation

for Research and Technology – Hellas (FORTH) and Alexey

Cheptsov, Research Scientist, High Performance Computing

Center Stuttgart (HLRS)

Since the introduction of cloud technology, highperformance

computing (HPC) is no longer limited to a small set of experts

but is visible to and affects even everyday users of desktop PCs

and mobile devices. In recent years, HPC has gone beyond

traditional application areas such as climate analysis, weather

prediction, astrophysics, etc., to new applications in social media,

big data, biomedicine and many more. Many of these new

applications are being pioneered by small and medium

enterprises, facilitated by European Commission initiatives such

as the FORTISSIMO project (www.fortissimoproject.eu).

Research, science and education are the main pillars to ensure

that leadingedge services are delivered in all areas of HPC

provisioning. While HPC is well positioned in terms of research

and science, the educational HPC horizon remains limited.

Unfortunately, there is currently no common view among leading

European educational institutions on the process of expanding

curricula to include HPCspecific topics. Standardi zation in HPC

curricula in Europe should start at the basic level, so that the

foundational set of ideas, terminology, skills, and tools are taught

to all students.

Most current higher education curricula do not stress parallel

thinking from the beginning and more advanced topics are

usually only included in specialized programmes. We need to

increase understanding of parallel programming and algorithms

in the general student population. A good starting point would

be to present parallel computing using students’ mobile phones,

which are usually built with manycore technologies, then

gradually moving out to the scale of modern supercomputers.

‘Think parallel’ should be the main message communicated to

students of computer science and related subjects.

To help address this issue, EuroLab4HPC has been working on

a model HPC curriculum. We have been collecting material from

existing educational programmes around Europe and beyond.

We have also used a questionnaire to find out the opinion of

experts and educators in the field, with their feedback being used

to better focus the direction of the proposed curriculum. In

addition, we collected information about existing courses at

institutions around Europe.

The major educational targets we have set for the curriculum

are:

• to promote parallel thinking

• to develop the ability to program parallel systems

• to promote understanding of performance (in processors,

compilers, code, communication, etc.)

• to evaluate and debug performance

• to promote knowledge of parallel algorithms

• to promote programming and use of heterogeneous systems

Our aim is for the proposed curriculum to act as a reference point

both for educators and institutions that would like to extend

their course inventory into HPC. We also hope it will allow

students to select courses, either within their institutions or via

distance learning, to build their knowledge and skills in parallel

and HPC programming.

HPC experts! Want to help shape the HPC curriculum? Complete the online survey here: http://bit.ly/2n5Pvy7

EuroLab-4-HPC is funded by the European Commission’s Horizon 2020 research and innovation programme under grant agreement no 671610.

HiPEACINFO 51 17

Recruitment special

Being a senior researcher at an institution like BSC offers the

opportunity to work on international projects in a unique

environment with toplevel facilities and interdisciplinary teams.

To progress to research management level, candidates need a

range of skills and experience.

In terms of research, an international reputation based on

research excellence in their field is fundamental, as is critical

judgement in the identification and execution of activities.

Researchers need to have made a substantial contribution

(breakthrough) in their field or across multiple areas. They will

have published and presented influential papers and books,

served on workshop and conference organizing committees and

delivered invited talks. They should recognize the broader

implications and applications of their research and develop a

strategic vision on the future of their research field.

However, the skills to progress go beyond the research itself.

Senior researchers are increasingly required to secure funding

and to manage and lead research projects. As team leaders, they

will need skills in managing and developing others. In addition

to team building, they will need to focus on longterm team

planning, such as career positions for researchers and securing

funding for team positions. Creative and innovative, they will

need to be excellent communicators and networkers in the

research community and beyond, and to act as professional role

models.

At BSC we use a tool to help identify each individual’s develop

ment needs and use the information gained via this tool to

shape our development programme. Researchers, with the

support of their managers, can choose from an extensive

programme of training and development actions including

project management, leadership, scientific writing and time

management, among others.

DEVELOPING THE SKILLS FOR SUCCESS

Marc Gonzalez Vidal, Head of Human Resources, Barcelona Supercomputing Center (BSC)

HiPEACINFO 5118

Recruitment special

POWERING A GLOBAL ELECTRONICS LEADER

SERIOUS FUN AT CODEPLAY

Graham Mudd, Senior Technology Manager, and Angela Bradfield,

Head of Human Resources, Samsung Research UK (SRUK)

The more niche and specific a skillset is for a particular role, the

more challenging it can be to find candidates who meet the

particular requirements. Meeting talented engineers is therefore

one of our highest priorities and greatest challenges: we know

the right people are out there and we cast our net far and wide to

find them. Another challenge we face is communicating exter

nally the fact that, while we benefit from the strength of the

global Samsung brand, our UK R&D site is just over 200 strong,

so we have the advantage of a boutique, familyfeel environment.

It’s a bit of a cliché, but we really look for talented people who

love solving problems and having their solutions show up in

actual products. We often hear employees describe the pride they

felt when purchasing a Samsung device from our staff shop for a

family member or friend and being able to brag that ‘I helped

build that’. Our core domains are embedded graphics, computer

vision, augmented reality, machine learning, digital TV and the

internet of things. At SRUK, you could be working on projects

such as machine learning for power management, stabilizing

virtual reality video or creating a lowlevel graphics API, for

example. We’re a hugely diverse bunch, with over 30 nationalities

represented in the SRUK office, so specific experience, personality

and professional formation are of less importance.

To get the best employees, the three watchwords are edu cation,

environment and enterprise, with commercial organizations,

policy makers and private individuals and associations all having

their part to play. Our strength lies mainly in the area of

enterprise, but we also need access to highquality technology

education for all and for there to be healthy, sustainable and

welcoming local environments in which to live and work.

Keeping people happy and engaged is one of the keys to

Samsung’s global success. Some of the ways we try to achieve

this at SRUK include good compensation, a great working

environment, continuous learning and development opportunities

– whether you decide to focus on the technical or management

route – and the ability to work on gamechanging projects that

will most likely show up in a multimillion unit device.

More detailed information about roles at Samsung can be found on the Samsung Careers page http://bit.ly/SamsungUK_Careers

Meenakshi Ravindran, Staff Software Engineer, Compilers,

and Karon Davis, VP Operations, Codeplay

We work on cuttingedge tech

nologies revolving around

hetero geneous com puting,

parallel computing, providing

a highperfor mance platform

for machine learning, artificial

intelli gence, computer vision

and other computationally intensive graphics applications. These

require technical skills including a strong core knowledge of

modern C++ (11/14), coupled with understanding of closeto

themetal software design, for example how hardware is

programmed at low level for optimized performance. That could

include areas such as compiler debuggers, programming

language design, memory management, graphics programming,

or parallel software design.

Operating in such a highly specialized field, it is quite challenging

to find candidates with the required skills. These skills are in

short supply so we have a global reach: we are very proud of the

international diversity of our team and encourage applications

from all over the world. We also have very good relationships

with universities and organizations like HiPEAC; our internship

programme is well respected, with internships available at both

undergraduate and postgraduate level.

Specific policy measures could boost the number of candidates.

These could include fast tracking visa applications for the people

we need to build our company, encouraging students to study

science and technology at school and supporting girls to succeed

in these areas. It might be worth introducing financial incentives

for students to study relevant subjects.

The single biggest advantage of working at a smaller company

like Codeplay is that, as an individual, your voice and opinion are

always considered and taken into account. You therefore have

the ability to contribute and truly feel part of the company rather

than getting lost in a corporate conglomerate. There are oppor

tunities to take on interesting projects and advance your career

by continuously increasing your knowledge and expertise.

To help settle new colleagues, Codeplay offers a threemonth

mentoring programme to all interns and new starters, whatever

their experience level. We have a robust knowledgesharing

HiPEACINFO 51 19

Recruitment special

The HR Strategy for Researchers at BSCBSC is the leading supercomputing

center in Spain, hosting MareNostrum,

one of the most powerful super

computers in Europe. With over 500

members of staff from 45 countries,

BSC combines HPC service provision

and research and develop ment (R&D)

activities under one roof.

BSC is committed to the principles of the EURAXESS European

Charter for Researchers and the Code of Conduct for the

Recruitment of Researchers. Via the HR Strategy for Researchers,

BSC aims to maintain the best environment for research

excellence, continuously improving through the adoption of

international best practices and highquality standards.

The HR Strategy for Researchers supports organizations to

implement the Charter and Code in their policies and practices.

Concretely implementing the Charter and Code makes research

institutions more attractive to candidates looking for a new

employer or a host for their research project. Funding organi

zations which implement the Charter and Code principles

contribute to the attractiveness of their national research

systems and of the European Research Area more generally. As

a result, the HR Excellence in Research logo identifies

organizations which either provide or support a stimulating

and favourable working environment.

The HR team at BSC

In April 2015, BSC was awarded the HR Excellence in Research

logo, recognizing BSC’s commitment to the principles of the

Charter and Code. This commits the centre to an action plan,

developed inhouse and approved by the European Commission,

to improve its capabilities and performance across a wide range

of training, recruitment and gender issues. The plan has since

been revised by the HRS4R steering group based on an analysis

of the results from 20152016, and a new plan for 20172020

has been created and approved.

Highlights of this ambitious project include:

• the creation of advisory committees

• boosting equal opportunities and gender policies

• strengthening activities in outreach and public engagement

• improving the BSC career development system

• incorporating the EURAXESS Open, Transparent and Merit

based Recruitment of Researchers (OTMR) practices

European Charter for Researchers https://euraxess.ec.europa.eu/jobs/charter

programme and strongly encourage all staff to participate in

local and international communities and events. We also organize

regular social events, from games over lunch and weekly movie

nights to annual company gatherings. We’re very proud of our

record in welcoming staff from over 18 different countries and

helping them to settle in quickly to their new country and role.

For the latest career opportunities, visit the Codeplay websitehttp://bit.ly/Codeplay_Careers.

Find Codeplay, SRUK and many more vacancies on the HiPEAC Jobs Portal: hipeac.net/jobs

HiPEACINFO 5120

Recruitment special

Finding Nema: breaching the ICT gender gapWe caught up with Bev Bachmayer, Vice Chair of ACM-Women Europe (ACM-W), to find out how we can help get more women in ICT.

What are some of the reasons behind

the lack of gender balance?

There are hundreds of studies attempting to explain this

phenomenon. People point out factors such as the difficulty in

achieving work/life balance, problems arising from the male

dominated work environment or blatant bias where companies

do not enforce gender equality regulations. However, it’s not

just the front of the pipeline but the leaky pipeline which finds

us in this predicament.

To combat the problem, we need to focus on the barriers. One

is unconscious bias, which is the perception that women are not

engineers or scientists. A second barrier is the lack of role

models: young impressionable women need to see people like

them doing the job, so that they can identify that they could do

that too. Lastly, a major problem is when qualified women end

up leaving the field because of a multitude of problems.

Why is it important to provide support specifically aimed at

women?

Networking helps women attain higher levels of achievement.

Women often feel isolated when they are the only female in a

group. Bringing technical women together gives them

opportunities to see that they are not alone. Additionally, seeing

successful women talk about issues that are part of many

women’s daily life inspires young women to continue in the

field. Feedback from womENcourage events shows that 89% of

the attendees are more committed to their careers after they

attend womENcourage.

Why should men support initiatives to increase the number

of women in computing systems jobs?

We need to change the culture and men are needed to help

make that change. Many people are unaware of some bias they

may hold, thereby making it difficult for another colleague to

excel. By joining the discussion and supporting such initiatives

people will see that the unconscious bias exists.

Is there a danger that such initiatives unfairly promote

women?

As soon as 50% of working ICT experts are women, conferences

have 50% women technical experts on the programme and

50% of computer science/engineering degrees are earned by

women, then we can worry about whether we are unfairly

promoting women.

What practical action can organizations take?

To recruit:

1. Participate in Celebrations of Women in Computing and

careers fairs (see below).

2. Bring your engineers to these events to network with the

participants.

3. Offer internships.

4. Provide mentors for students.

To retain:

1. Promote work/life balance, flexible working hours, working

from home.

2. Improve maternity leave.

3. Provide child daycare.

4. Proactively build the team with social activities that are

inclusive for all at work.

ACMW organizes regular Celebrations of Women in Computing.

In addition to keynote speeches, panel discussions, workshops

and hackathons, these events feature a careers fair where

supporters can recruit students and professionals. Supporters

this year include HP, Google, Bloomberg, Oracle, Accenture,

Intel, Amazon, Informatics Europe, Inria and Microsoft.

womENcourage 2017, 6-8 September, Barcelona, Spain https://womencourage.acm.org/

HiPEACINFO 51 21

After almost two years, we’re delighted to

present the AXIOM Board, Serial Number:

000000000001. It is the initial result of

thorough research funded by the European

Commission and involving seven different

entities across Europe: three research

groups/universities – the University of

Siena, Barcelona Supercomputing Center

and the Foundation for Research and

Techno logyHellas (FORTH) – and four

enter prises – SECO, Vimar, Evidence and

Herta Security.

This is the first version of the AXIOM

Board, but we truly think we’re on to

something. AXIOM is the first board that

combines three worlds in one: Arduino,

ARM computing and FPGA. It runs a

version of BSC’s flagship programming

model, OmpSs, allowing straightforward

FPGA programming. It’s designed to be

the perfect combination of high

performance computing, embedded

computing and cyberphysical systems. As

such, it aims to provide the ideal platform

for realtime data analysis of a huge

amount of data in a short time frame,

machine learning, neural networks, server

farms, bitcoin miners – you name it.

Take a look at the image on the opposite

page to see what marks the AXIOM board

out from the competition.

AXIOM is funded by the European Commission under the H2020 Framework Programme for Research and Innovation under grant agreement no. 645496.

Inside the box

Well hello, AXIOM board!

Last year (issue 47) we caught up with Maurizio Caporali (Università di Siena) and Xavier Martorell (Universitat Politècnica de Catalunya – Barcelona Tech) to find out about the AXIOM project’s plan to build a European single-board computer. We were very excited when the board finally arrived this year. Along with Davide Catani (SECO), Maurizio and Xavi offer us a peek under the hood to show why this board is so special.

The AXIOM board was debuted at Embedded World 2017

HiPEACINFO 5122

Inside the box

HiPEACINFO 51 23

Innovation Europe

In this issue we find out about a design framework for applications with strict timing and high-performance requirements, a project to bring HPC to the Danube region and the Heterogeneous Hardware and Software Alliance.

NEW UPSCALE FRAMEWORK ALLOWS DEVELOPMENT OF REAL-TIME HPC APPLICATIONS

PSOCRATES, a project cofunded by the European Commission,

has created the UpScale Software Development Kit (UpScale

SDK) for the development of applications with strict timing and

highperformance requirements. The project members designed

and implemented an entirely new design framework, from

conceptual design of the system functionality to its physical

implementation, to facilitate the deployment of standardized

parallel applications in all kinds of realtime systems.

The UpScale SDK targets systems that demand more and more

computational performance to process large amounts of data

from multiple data sources, while requiring guarantees on

processing response times. Such systems may be used in

applications ranging from avionics to traffic management to the

stock exchange. Manycore processor architectures allow these

performance requirements to be achieved by integrating up to

hundreds of cores, interconnected with complex networks on

chip, paving the way for parallel computing.

Unfortunately, parallelization brings many challenges, by

drastically affecting the system’s timing behaviour. Providing

guarantees becomes harder, because the behaviour of the system

running on a multicore processor depends on interactions that

are not usually known by the system designer. This causes system

analysts to struggle to provide timing guarantees for such

platforms.

UpScale tackles this challenge by combining technologies from

different computing segments. These allow developers to

successfully exploit both the performance opportunities brought

by parallel programming models used in the highperformance

domain and timing analysis from the embedded realtime

domain, for the newest manycore embedded processors available.

HiPEACINFO 5124

Innovation Europe

The UpScale SDK includes the following components:

• Sourceto source compiler – enabling the analysis of source

code OpenMP parallelism annotations, extracting the required

information to allow for efficient and predictable mapping and

scheduling of parallel computations.

• Lightweight OpenMP tasking runtime – a smallfootprint, low

overhead implementation of the tasking model of the latest

OpenMP specification, which uses the information extracted by

the compiler to map OpenMP tasks to operating systems

threads.

• Embedded manycore operating system – a small kernel imple

mentation which efficiently handles parallel threads in many

core platforms, supporting both static assignment of threads to

cores as well as global scheduling approaches.

• Analysis tools – an integrated toolset for the timing and

schedulability analysis of realtime parallel applications.

The SDK framework is flexible and applicable to different use

cases, as demonstrated by the project results. Initially released

for the Kalray MPPA processor, it is possible to port to different

hardware architectures as also demonstrated by the project.

After a first showcase at the project’s Industrial Workshop which

took place in Porto in November 2016, the final results of the

project and the UpScale SDK were presented at Embedded World,

the international gathering for the embedded system technology

sector, which took place in Nuremberg in March 2017.

UpScale is openly available and released under commercially

friendly open source licences. It is available to download from

www.upscalesdk.com.

Contacts

Dr Luis Miguel Pinho, Project Coordinador ([email protected])

Dr Sandra Almeida, Project Manager ([email protected])

PROJECT: P-SOCRATES (Parallel Software Framework for Time-Critical

Many-core Systems)

START/END DATE: 01/10/2013-31/12/2016 (completed project)

KEY THEMES: high-performance, embedded, real-time, predictability

COORDINATOR: Instituto Superior de Engenharia do Porto (Portugal)

PARTNERS: Spain: Barcelona Supercomputing Centre, ATOS; Italy:

University of Modena and Reggio Emilia, Evidence SRL, Active

Technologies SRL; Switzerland: Swiss Federal Institute of Technology

Zurich (ETH Zurich)

BUDGET: €3.62M

WEBSITE: www.p-socrates.eu

P-SOCRATES received funding as part of the European Union's Seventh

Framework Programme (FP7/2007-2013) under grant agreement

no. 611016.

INNOHPC BRINGS HPC TO SMES IN THE DANUBE REGION

Launched on 1 January 2017, InnoHPC will enable enterprises as

well as academic and research institutions to cooperate more

closely in the field of supercomputing across national borders. In

the first stage, project partners will evaluate the current level of

exploitation of the regional highperformance computing (HPC)

infrastructures by small and medium enterprises. In the second

stage, they will design and establish a transnational InnoHPC

laboratory whose main purpose is to provide SMEs with remote

access to the HPC infrastructures. The third stage will involve a

pilot in which a number of SMEs from the electrotechnical and

automotive industry use the InnoHPC laboratory and web

platform.

The project runs until June 2019 and is supported by the Interreg

Danube Transnational Programme, whose priority is to promote

innovations and social responsibility in the Danube region. The

lead project partner is the Faculty of Information Studies in Novo

mesto (Slovenia). The focus is mainly on the eastern part of the

Danube region represented by the other partners in the project.

NAME: InnoHPC - High-Performance Computing for Effective

Innovation in the Danube Region

START/END DATE: 01/01/2017-30/06/2019

KEY THEMES: high-performance computing, industrial optimization

COORDINATOR: Faculty of Information Studies Novo Mesto (Slovenia)

PARTNERS: Czech Republic: IT4Innovations National Supercomputing

Center; Austria: RISC Software GmbH; Croatia: University of Rijeka;

Slovakia: Technical University of Košice; Romania: West University of

Timisoara, Executive Agency for Higher Education, Research,

Development and Innovation Funding; Slovenia: University of

Ljubljana, Electronic and Electrical Engineering Association – Chamber

of Commerce and Industry; Bulgaria: Research Centre for Regional

and Global Development; Hungary: Budapest Chamber of Commerce

and Industry

BUDGET: €2.05M

WEBSITE: http://bit.ly/Interreg_InnoHPC

Project co-funded by the European Union.

HiPEACINFO 51 25

Innovation Europe

INTRODUCING THE HETEROGENEOUS HARDWARE AND SOFTWARE ALLIANCE

Karim Djemame, University of Leeds and Oliver Barreto, Atos

In recent years we’ve seen the emergence of cyberphysical

systems (CPS) and the internet of things (IoT), promoted by

initiatives such as the European Commission’s Smart Anything

Everywhere, which have the potential to transform the way we

live and work. For example, the transformational impact of the

IoT in the long term is expected to increase significantly with

mass adoption and tens of billions of things being connected,

generating multitrillions of dollars in economic value. It will act

as a key driver behind new development platforms, analytics

applied to things and distributed/parallel architectures, as

Gartner highlighted in a 2015 report.

As the range of applications grows within CPS, the IoT, high

performance computing (HPC), mobile computing, wearable

computing, etc., there is an urgent need to design more flexible

software abstractions and improved system architectures to fully

exploit the benefits of the heterogeneous platforms on which

they operate. Heterogeneous parallel architectures have received

considerable attention for their ability to improve absolute

performance, minimize power consumption and/or lower costs

by combining different processor types in one system.

New platforms incorporating multicore CPUs, manycore GPUs

and a range of additional devices into a single solution are

increasingly being introduced. These platforms are emerging in a

wide range of environments, from supercomputers to personal

smartphones. One of the challenges for future application

performance lies not only with efficient nodelevel execution but

also with power consumption, a key focal point.

Complex engineering simulations often come to mind when

identifying families of applications that benefit most from

heterogeneous parallel architectures. However, in the upcoming

era of the IoT and big data there is significant interest in exploiting

the capabilities offered by customized heterogeneous hardware,

all of which have various memory hierarchies, size and access

performance properties.

Examples of customized heterogeneous hardware

FPGA – field-programmable gate array

ASIP –application-specific instruction set processor

MPSoC – multiprocessor system-on-chip

Heterogenous CPU (central processing unit) and GPU (graphics

processing unit) chips

Heterogeneous multi-processor clusters

In fact, online big data with nearly instantaneous results demand

massive parallelism and welldevised divideandconquer

approaches in order to exploit heterogeneous hardware, both

clientside and serverside, to its fullest extent. Heterogeneous

systems can handle workloads with fewer and/or smaller servers,

thereby saving costs. They can also slash the energy used to run

certain applications, which provides clear benefits in addressing

the growing interest in ‘green’ solutions and the pressure to

reduce the environmental impact of data centres, for example. As

the HiPEAC Vision notes, a common theme across all scenarios is

the need for lowpower computing systems that are fully

interconnected, selfaware, contextaware and selfoptimizing

within application boundaries.

Because the impact of hardware heterogeneity is rapidly

increasing, innovative architectures, algorithms and specialized

programming environments and tools are needed to efficiently

use these new and mixed/diversified architectures. For example,

the transitions to multicore processors, GPU computing and

hardwareasaservice (HaaS) cloud computing should be viewed

as a single trend. As the market for heterogeneous architectures/

multicore processors in embedded applications begins to move

into the product deployment stage, the need for software and the

underlying programming methodologies is also increasing in

parallel.

However, to put it bluntly, programming directly with this kind of

heterogeneity is a nightmare. We need to take action so that we

can rapidly develop solutions that help companies exploit

heterogeneous architectures to create richer experiences and

innovative business models. Those of us who are software

engineers need a mediator to help us deal with the heterogeneity

and take advantage of highlevel abstractions, as happened in

the past with traditional computing. We need to develop

innovative architectures, algorithms and even specialized

HiPEACINFO 5126

Innovation Europe

programming environments and tools to efficiently deal with

very different architectures in order to be more productive, obtain

rapid learning curves and to build solutions that are more general

purpose.

The TANGO project is creating a toolbox to provide the tools to

deal with this reality. However, we recognize that there are others

in the market and research arena who are also working towards

this direction. Our vision is to avoid creating yet more

heterogeneity in the tools and approaches that will lead this

market in the upcoming years. Therefore, instead of simply

pushing our own tools, TANGO aims to encourage collaboration.

We want to create something that will also create a link between

research and the market and exploit potential synergies.

To drive this forward, we have initiated the Heterogeneous

Hardware & Software Alliance (HHW&SW Alliance). The

initiative aims to unite the efforts of organizations interested in

the development of future technologies and tools to advance and

exploit computing and applications using heterogeneous

hardware. The alliance will focus on all phases of heterogeneous

hardware and software, from design time to enhanced execution,

parallel programming and optimized runtime. It will consider a

number of factors such as energy, performance, realtime, data

locality and security. This will enable a new way of developing

and executing nextgeneration applications.

The main aim of the alliance is to establish an organization in

which anyone interested in related technological areas can

collaborate. Participants will work towards a common objective:

founding a common, opensource and extendable set of

technologies and tools around the development for heterogeneous

hardware. These should be viable for mass adoption utilizing

technologies created by the alliance members, as well as being

attractive, easy to use and broader in scope and value. The

alliance is currently working on the establishment of a reference

architecture and is creating an online catalogue of tools and

technologies.

Interested in finding out more? Contact us: www.heterogeneityalliance.eu/contact

TANGO is funded by the European Commission under the H2020

Framework Programme for Research and Innovation under grant

agreement no 68758.

Further reading

TANGO: Transparent heterogeneous hardware Architecture

deployment for eNergy Gain in Operation

www.tango-project.eu

Smart Anything Everywhere

http://bit.ly/smart-anything-everywhere

Survey Analysis: The Internet of Things Is a Revolution Waiting

to Happen. Gartner report, January 2015

http://bit.ly/Gartner_Report15

HiPEAC Vision

www.hipeac.net/publications/vision

HiPEACINFO 51 27

Peac performance

Rosa M Badia, Barcelona Supercomputing Center (BSC)

Superscalar architectures became

popular in the early 1990s and are

still in use in most processors. A

superscalar processor implements

instructionlevel parallelism and can

execute several instructions in a

clock cycle by trying to feed all the

execution units on the processor.

Traditionally, computer architecture instructions are programmed

sequentially, and a program is an ordered list of instructions.

However, designs such as the superscalar processor allow parallel

execution, with several instructions being executed at the same

time. What is more, the data dependencies between instructions

are dynamically detected by the CPU. This means that outof

order execution and even speculative execution – where some

instructions are executed that may not actually be needed – are

possible. All these techniques help make the most of the

instruction cycle and hence minimize delays in processing.

In the superscalar programming model we follow the same

strategy, but implemented at software level. PyCOMPSs is a task

based programming model that offers an interface based on

Python sequential code, but that enables execution in parallel by

building a datadependency graph of the application tasks at

execution time. A task in PyCOMPSs is a method or a function,

annotated with a Python decorator which also describes the

directionality of the task parameters.

The directionality of a parameter can be ‘in’ when a parameter is

read, ‘out’ when a parameter is written, and ‘inout’ when a parameter

is both read and written by the task.

Tasks in PyCOMPSs are equivalent to the instructions in super

scalar processors, and the objects or files exchanged by the tasks

are equivalent to the registers in the processor. The directionality

of the parameters is used to derive data dependencies between

instances of tasks at execution time. Another idea borrowed from

the computer architecture world is register renaming, which we

apply to the objects/files exchanged by the tasks.

The syntax of PyCOMPSs is minimal, using decorators to annotate

tasks and a small API for synchronization. PyCOMPSs relies on a

runtime that is able to exploit the inherent parallelism at task

level and to execute the application on a distributed parallel

platform (clusters and clouds) while the code remains agnostic

of the existing hardware. The runtime is responsible for scheduling

the tasks on the available computation resources, performing the

necessary data transfers between distributed memory spaces,

synchronizing all activities and interoperating with heterogeneous

computing resources including cloud middlewares, etc.

Parallelizing Python codes using the superscalar paradigm

Rosa Badia of Barcelona Supercomputing Center explains how PyCOMPSs takes inspiration from computer architecture to enable

execution in parallel at the software level.

HiPEACINFO 5128

Peac performance

Parallelizing Python codes using the superscalar paradigmPython was chosen rather than other programming languages

due to its popularity in several scientific communities. The high

level of adoption is not only due to the language features, but

also because of the large number of thirdparty libraries available

for the community. Examples of very popular libraries are NumPy

or SciPy, which offer data structures and numerical routines.

NumPy automatically maps operations on vectors and matrices

to the functions of BLAS and LAPACK numerical libraries, which

are highly optimized and in many cases parallelized at

threadlevel.

With this approach, in PyCOMPSs we can exploit two levels of

parallelism: tasklevel, between nodes of a distributed computing

platform, and threadlevel, inside the nodes. Results with

numerical kernels such as matrix multiplication, Cholesky or QR

factorizations show that we can get performances of up to 60% of

the peak in one node and very good scalabilities up to thousands

of cores. In all cases, it is important to take into account that the

user application is a sequential annotated Python code that is

executed in parallel by the PyCOMPSs runtime.

With the objective of giving support to new storage technologies

such as NVRAMs or SSDs, PyCOMPSs has been enabled to

support persistent storage. The programmer is able to define

which objects of their program will remain persistent after the

execution of the code, although access to these objects by the

program remains unchanged. Similarly, programs can access

objects that were made persistent before. This enables very easy

support of producerconsumer sets of applications, or insitu

processing, visualization, etc. This support has been made

possible by the definition of a Storage API with a set of methods,

some accessed by the PyCOMPSs runtime and others offered

directly to the programmer. The interface for the programmer is

minimal, with a method to make the objects persistent and with

constructors to access data that is already persistent.

Example of how objects can be persisted with the storage API. The object X is created and made persistent. Later, it is accessed normally in the loop

Two backend solutions to store the persistent storage are currently

supported: Hecuba and dataClay. Hecuba is a set of tools and

interfaces that aims to provide programmers with an efficient

and easy interaction with nonrelational databases. More

specifically, Hecuba implements an interface to access data stored

in Cassandra databases, such as regular Python memory objects.

The objectoriented approach is focused by dataClay, a data store

that offers novel techniques for sharing structured data in a

multiprovider ecosystem.

While the PyCOMPSs runtime operates well with clusters and

clouds, up until now it has not been enabled for GPUs, FPGAs or

other types of accelerator. To support these types of architecture,

a hybrid programming model that combines PyCOMPSs, to deal

with coarsegrain tasks, and the BSC programming model

OmpSs, to deal with finer granularity, is under research. This and

other challenges of taskbased programming models will be

described and discussed in my lectures at the ACACES summer

school this year.

COMPSs is open source. Code, compiled packages and documentation are available at compss.bsc.es

Rosa Badia is delivering the course ‘Application programming on parallel/distributed computing platforms’ at ACACES17. Further information: http://bit.ly/ACACES17_Rosa_Badia

“Tasks in PyCOMPSs are equivalent to the instructions in superscalar processors, and the objects or files are equivalent to the registers”

HiPEACINFO 51 29

Tech opinion

Neuromorphic computing explores largely

uncharted territory in several sciences of

living and artificial systems. The idea of

different kind of computing was driven by

the extraordinary capabilities of human

brain to perform on very low levels of

energy consumption. As physical limita

tions began to reach barriers which cannot

be exceeded without drastically changing

the underlying architecture, some 30 years

ago scientists and engineers started thinking

about how to emulate human brain

performances with neuro morphic chips.

Looking at the big picture of computation

vs. communication types of signals (see

figure 1), one should think about neuro

morphic computing as digital communi

cation and analogue compu tation – very

much as the human brain works. Analogue

computing preceded digital computing,

which is dominant today and reaching its

limits. The objective is to achieve the

energy efficiency of the human brain,

which consumes only 20 watts as com

pared with contemporary HPC systems

which consume megawatts of electricity.

Figure 1: Computation vs communication signals

Traditional digital computer technology is

slated to deliver an exascale machine

(1018 FLOPs with 1018 bytes of memory),

but delivering an order of magnitude more

performance will require a radical change

of computing paradigm. This change will

have an impact on the entire chip

hardwaresoftware stack (figure 2) and

imply not only novel neuromorphic

devices but also different types of software

running new types of algorithm. In short,

an entirely new technology landscape and

architecture.

Figure 2: Exascale calls for the reinvention of the full stack

An interesting consequence of this will be

that the different types of problem can be

addressed in a different way and exhibit

superior performances (figure 3). For

example, the use of quantum computing

and highperformance computing to

design effective neuromorphic computer

architectures is being investigated. It is

not beyond the realms of imagination that

an entire new age of computing might

open up.

Figure 3: Different problems may require different approaches

In conclusion, as we witness huge invest

ment in human brain research in the Euro

pean Union and the United States,

amoun ting to the investment of one billion

dollars/euros over the next decade, one

should not make the mistake of thinking

that the human brain will be replaced with

artificial systems. The big challenges will be:

1. To construct systems which consume

watts instead of megawatts of electricity.

2. To reinvent fault tolerance so that it

resembles that of the human brain,

which is constantly improving while

losing neurons daily.

3. To construct systems that can learn from

massive interactions instead of being

programmed.

New computing paradigm(s) will open up

splendid opportunities for the next gene

ration of scientists and engineers con

structing entirely new systems and

deploying novel devices across the entire

architecture stack.

Neuromorphic Computing: low-power systems, the brainy way

Attempts to recreate the human brain in silico have sparked fears that artificial systems will replace the human brain. This is a misconception,

argue Kemal Delic and Dave Penkler of Hewlett Packard Enterprise. Instead, the human brain – the original computer – is the inspiration

for next-generation computing systems.

Figures in this article are adapted from the following sources:Rebooting Computing: The Road Ahead by T.M. Conte et alhttps://www.computer.org/csdl/mags/cs/2017/02/mcs2017020014.htmlA Neuromorph’s Prospectus by K. Boahenhttps://www.computer.org/csdl/mags/co/2017/01/mco2017010020.html

HiPEACINFO 5130

Tech Entrepreneur

Technological innovation has a history of

changing the world in major ways and

making a real impact on society. Just think

of the British Agricultural Revolution of

1700 and the Industrial Revolution of

1780 – they were all about changing the

basic way in which people worked and

produced things by innovatively applying

and scaling the technology breakthroughs

of the time. We have been in a compu

tationdriven revolution for some decades;

it drives much of the modern economy

and compe titiveness for the countries in

which we live. How do we keep the

revolution going?

For those currently doing interesting

scientific research, it is a good idea to take

some time to look at how their findings

might be used by companies and indivi

dual consumers: seeing someone using

the results of your labours and insights is

just as satisfying as getting a best paper

award. It can be a lot of fun, evange lizing

the technology area you enjoy and having

a wider group of people understand and

appreciate it more. It can also be financially

rewarding.

A vision in silicon

Tech entrepreneur Peter Denyer invented

the silicon optical sensor, now used in

most digital cameras. He founded VLSI

Vision and sold it to ST Microelectronics,

before founding a number of other

companies.

Europe has a very good record of making

scientific breakthroughs and though we

have made great strides in turning these

into products people and companies find

useful, it is an area in which we ought,

and need, to do better. We have tended to

lag behind the USA in this dimension. A

number of reasons have been put forward

as to why this has been the case:

We do not have as large a single market

as the USA

That ought not to be true if we take the

European Union (EU) single market into

account. In the digital domain a global

market is accessible instantly through the

internet. As we look at the geographic

addressable market we do need to

consider the wider global market – not

just our individual country.

The USA has easier access to venture

capital and investment

This is no longer the case with a number

venture funds and angel investment

groups now active throughout Europe. As

of the end of 2016 we have 47 unicorns

(startup companies with a valuation

>$ 1 billion) in Europe, with an average

investment of some $ 260 million each. So

there is investment capital available to be

won.

The USA has more technical talent and

knowhow

Europe has a huge talent pool both in the

technical and entre preneurial domain.

Keep the revolution going

Thinking about converting your research results into market-ready products and services? As Director of Commercialisation at the University of Edinburgh from 2006 to 2016, Colin Adams presided over the creation of 70 spin-outs and start-ups which collectively raised over e 250 million in equity investment. Here he explains why and how you should be a technology entrepreneur.

HiPEACINFO 51 31

The strength of our research and univers

ities is key. There is also a growing band of

seasoned technical entrepreneurs who

already have at least one success under

their belt and are available to mentor and

help new comers.

So there is no reason why we should not

make even more headway in turning the

worldleading research that this

community has been carrying out into

innovative products.

Improbable sums

The founders of the UK virtual reality

start-up Improbable Worlds, Herman

Narula, Rob Whitehead and Peter Lipka,

recently raised $520 million from Softbank.

The company is now reported to be valued

at over $1 billion. Between them, the three

founders hold more than 50% of the equity.

If you do have some technology you think

you would like to commercialize, first

work up a very simple working prototype

of what you think people would use. Find

a couple of potential customers (preferably

not coresearchers) and try it on them so

you get some feedback. Listen to their

input and modify your approach based on

that. The prototype can also be used to

show potential investors what you have in

mind, and to people you may want to

recruit onto your team.

The other area to think through is how

you protect the intellectual property in

your invention, e.g. by patenting some

element of it, so others don’t capitalize on

your efforts without you gaining anything

from it.

If you are looking at seriously pursuing

this route, I would advise seeking out

some business mentors who have solid

business experience and contacts, so you

have people to provide feedback on your

ideas for a business plan and how to

develop the commercial side.

An interesting thought in the space we

address in the HIPEAC community is what

happens next to keep Moore’s law – and

with that the technology revolution –

moving forward. I had an interesting

conversation with Steve Jurvetson recently.

He is one of Silicon Valley’s most successful

investors and he came up with the 120

year view of Moore’s Law shown below.

Now, does your research give guidance to

how that curve continues? If so, you could

have something very valuable – so start

thinking about how to commercialize it.

Colin Adams is delivering the Technology Innovation and Entrepreneurship course at the HiPEAC summer school ACACES17.http://bit.ly/ACACES17_ColinAdams

Tech Entrepreneur

HiPEACINFO 5132

As computing systems evolve towards

complex multicore designs with deep and

diverse memory hierarchies, improving

the performance and optimizing the exe

cution of realworld applications become

of fundamental importance. In high

performance computing environ ments, it

is crucial, but not trivial, to determine

which hardware resources represent the

main execution bottlenecks that limit the

application performance, especially when

deciding on the most adequate software

optimization technique to be applied.

To support this decision process, Aleksandar

Ilic, Frederico Pratas and Leonel Sousa,

researchers from INESCID, Instituto

Superior Técnico, University of Lisbon, and

members of HiPEAC, proposed a set of

fundamental Cacheaware Roofl ine

models, which provide a simple and

intuitive way of visually representing the

limits of parallel processing on contem

porary multicore processors.

These models evaluate how key micro

archi tectural aspects, such as accessing

diffe rent functional units or different

memory hierarchy levels, affect realistically

achie vable upperbounds for performance,

power consumption and energyefficiency

on a given multicore architecture. They

have been used to characterize the

behaviour and improve the efficiency of

several realworld applications, e.g. in the

areas of scientific computations and

bioinfor matics.

In 2017, a team of Intel software deve

lopers (leaded by Zakhar Matveev, Roman

Belenov and Philippe Thierry) successfully

integrated the performance Cacheaware

Roofline model as an official feature of

Intel® Advisor, which is part of the Parallel

Studio XE suite (Intel’s main application

development frame work). Within Intel®

Advisor, the process of building the roof

line plots and indepth application charac

te rization are fully automatized with

res pect to the hardware platform where

the applications are executed. The support

for a wide range of Intel devices is also

provided, which covers all contempo rary

Intel CPU microarchi tectures (from

Nehalem to Skylake) up to massively

parallel devices (e.g., Intel Xeon Phi

Knights Landing).

A brief overview of the Cache-aware Roofline in Intel® AdvisorThe performance Cacheaware Roofline is

plotted with the X axis as Arithmetic

Industry focus

Cache-aware Roofline Model in Intel® AdvisorA bird’s eye view for parallel processing

Leonel Sousa, Aleksandar Ilic’ and Frederico Pratas of the University of Lisbon describe how they developed a simple way to visualize the limits

of parallel processing, which has been integrated into Intel® Advisor.

“The models evaluate how key micro-

architectural aspects affect upper-bounds for

performance”

HiPEACINFO 51 33

Intensity (measured in FLOPs/Byte) and

the Y axis as the performance in GFLOPs/

Second, both in logarithmic scale. Before

collecting data of a specific application,

Intel® Advisor automatically runs a set of

quick benchmarks to measure the hard

ware limitations of the used processor,

which it then plots as lines on the chart,

called roofs (see Figure 1). The horizontal

lines represent the number of floating

point computations (of a given type) that

the underlying hardware can perform in a

given span of time. The diagonal lines are

representative of how many bytes of data

a given memory hierarchy level can

deliver per second.

Each dot represents a loop or function in

the program, and its position in the

Roofline plot indicates performance and

Arithmetic Intensity. The size and colour

of the dots in Intel® Advisor’s Roofline

chart indicate how much of the total

program time a loop or function takes.

Small, green dots take up relatively little

time, so are likely not worth optimizing;

large, red dots take up the most time, so

they are the best candidates for optimi

zation, especially the ones with a large

gap to the topmost attainable roofs. In

general, the farther a dot is from the

topmost roofs, the more room for improve

ment there is. For example, the Scalar Add

Peak represents the maximum possible

performance without taking advantage of

vectorization, as indicated by the next

roof up being the Vector Add Peak.

Where can I get Intel® Advisor with Cache-aware Roofline?As stated in the Intel early access pro

gramme, ‘the Intel Advisor offers a great

step forward in memory performance opti

mi zation with a new vivid Advisor

“Roofline” bounds and bottlenecks ana

lysis’. Cacheaware Roofline is currently a

feature of Intel® Advisor beginning

officially with version 2017 Update 2,

which is part of the Parallel Studio XE suite

(Cluster Edition and Professional Edition).

Cache-aware Roofline in Intel® Advisor

‘The Intel Advisor offers a great step forward in

memory performance optimization with

a new vivid Advisor “Roofline” bounds and

bottlenecks analysis’

Further reading

A. Ilic, F. Pratas, and L. Sousa. ‘Cache-aware Roofline model: Upgrading the loft.’

IEEE Computer Architecture Letters, vol. 13, n. 1, pp. 21-24, 2014.

‘Beyond the Roofline: Cache-aware Power and Energy-Efficiency Modeling for Multi-cores.’

IEEE Transactions on Computers, vol. 66, n. 1, pp. 52-58, 2017.

Intel. (2017) Intel® Advisor Roofline

http://bit.ly/Intel_Advisor_Roofline

Intel. (2017) Intel Parallel Studio XE

http://bit.ly/Intel_Parallel_Studio_XE

Industry focus

HiPEACINFO 5134

COMPANY: Rimac Automobili

MAIN BUSINESS: Creating next generation

electric hypercars; providing full solutions

to global original equipment manufacturers,

from high-performance electric vehicle

components to turnkey solutions

LOCATION: Sveta Nedelja, Croatia

WEBSITE: www.rimac-automobili.com

The seeds for the company were first planted back in 2007, when

Mate Rimac started tinkering with his BMW E30 as a hobby, after

the car’s engine blew up during a race. When he managed to give

it an electric powertrain – the engine and transmission – the

project soon attracted press interest. In total, Mate broke five

Fédération Internationale de l’Automobile and Guinness World

Records for the fastest accelerating electric car with this

prototype, affectionately known as the ‘Green Monster’. Wanting

to develop a more powerful version, Rimac brought together a

team of experts to develop their own components, in order to

deliver genuinely highperformance electric propulsion. Thanks

to selling patents and gaining financing from angel investments,

Rimac Automobili was founded in 2009.

The ‘Green Monster’ was the original Rimac prototype

Lovingly crafting each car in house – including everything from

the battery to the transmission to the infotainment system – the

team built on their knowledge from developing the BMW E30

prototype to create first the Concept_One and then the Concept_S.

Accelerating from 0100km/h in just 2.5 seconds, the cars have

beaten even top supercars in test races.

Check out the Concept_One beating LaFerrari in this video:

http://bit.ly/Rimac_ConceptOneLaFerrari.

The Rimac Concept One has beaten LaFerrari

Rimac is fortunate to benefit from a great team and we’ve been

working with the education system in Croatia to help prepare

engineers with the requisite skills. As a smaller company, at

Rimac you have the satisfaction of working on the whole lifecycle

of the product, from design, to production, to testing. This is

contrast to working at a large multinational where you would

likely be working on one small part of the development. Rimac is

currently looking for topquality staff, with roles encompassing

everything from battery engineering to embedded engineering.

We are seeking software engineers for embedded systems

development, from the initial idea to the final product. Candidates

should have C/C++ programming skills, familiarity with basic

electronic circuits and basic knowledge of communication

protocols. Experience with realtime operating systems and

embedded systems projects experience are more than a plus. We

are also recruiting an embedded hardware engineer, who should

have knowledge of electronic components and systems, the

programming language C and communication protocols (UART,

SPI, I2C, CAN...).

Interested in working at Rimac Automobili? Check out the vacancies on

the HiPEAC Jobs Portal: hipeac.net/jobs

SME snapshot

The drive to succeed

From hobby project to building the world’s fastest electric car, Rimac Automobili is a high-octane success story. Here, Chief Human Resources

Officer Aco Momcilovic’, Director of Components Matija Gracin and Marketing Assistant Marta Longin show how this company punches

above its weight and give an insight into why it is a great place to work.

HiPEACINFO 51 35

HiPEAC futures

What first got you interested in computer

science?

My interest began a long time ago. I think my

career started with the first computer my father

bought me. It was a very small Texas Instru

ments (TI) processorbased system which was

programmed with hexadecimal code. Later I

had a TI 99/4A and then of course a Commodore

C64. I was born at a time when computer

systems developed very quickly in a very short

period of time, a phenomenon which has

continued up to the present day. A fascination

with novel systems, processor system trends

and energy optimization has kept my interest

all this time.

What makes embedded computing an exciting

field to work in?

I think embedded systems is the most important

domain, both for industry and academia. We

are seeing trends where embedded technology

is even entering the realm of highperformance

computing due to the effectiveness of perfor

mance per watt. Trends like cyberphysical

systems (CPS) and the internet of things (IoT)

enable better processor systems in terms of

ultralow power and normally high realtime

capability. This is leading to changes in many

fields. Embedded systems form the ‘motor’

which drives megatrends in machine learning,

CPS and IoT.

The TI 99/4A was one of Michael’s first computers Photo credit: Manolis Klaglas, Flickr

creativecommons.org/licenses/by-nc-sa/2.0

Can you describe some highlights of your

career so far?

One highlight in my career was my decision to

study. I was doing a job in the electronics field

and came to a point where I needed to choose

to study or stay on the path I was on. It was not

easy for me because I gave up a permanent

position in order to embark on the ‘adventure’

of studying. What made it even more daunting

was that, at the time, there were no guarantees

that it would become a job. Later, after finishing

my diploma, it was thanks to my former PhD

advisor believing in me that all other steps

were possible. Now, I have the best job I could

wish for as a professor at RuhrUniversität

Bochum .

What makes Europe a great place to work?

I think Europe is an excellent place to work, as

there is a network of excellent researchers and

exchange of knowledge and experience is easily

achieved. In my group at Bochum I always

have researchers from Europe, but also from all

over the world. We like to discuss issues with

other researchers and Europe is an excellent

platform to do so. Funding oppor tunities,

mostly the European Commission ICT calls, are

often an especially good way to collaborate.

What advice would you have for researchers

embarking on their careers now?

I think the most important thing is to stay

curious and open minded, and never be

restrictive with sharing knowledge. Teamwork

is important, as is supporting activities like

EUROPRACTICE (www.europracticeic.com)

which offers microelectronic and micro system

design, prototyping, production and test

services. EUROPRACTICE is an extremely

important source of support for researchers in

Europe and I hope it continues for a long time.

Michael Hübner is delivering a course titled ‘Reconfigurable Hardware, Tools and Applica-tions’ at ACACES 2017http://bit.ly/ACACES17_MichaelHuebner

Career talk: Michael Hübner, Ruhr-Universität Bochum

HiPEACINFO 5136

HiPEAC futures

Creating the future through international exchange: HiPEAC collaboration grants

Collaboration grants allow PhD students and junior post-doctoral researchers within the HiPEAC network to work jointly with a new research group to work

on key challenges for computing systems. For further information about how to apply, visit www.hipeac.net/mobility/collaborations.

NAME: Joshua Lant

RESEARCH CENTRE: University of Manchester

HOST INSTITUTION: Foundation for Research

and Technology Hellas

DATES OF COLLABORATION:

26/07/2016 - 28/10/2016

Epic memories: When Manchester met ‘Silicon Island’, Crete

The Horizon2020 ExaNeSt project is developing and prototyping

network, storage and cooling solutions to make exascale com

puters – those capable of a billion billion calculations per second

– feasible. To help achieve this, ExaNeSt uses UNIMEM: a form of

global address space that allows multiple boards to share memory

regions between them and to communicate at low overhead and

low energy consumption. UNIMEM was developed during the

EUfunded EUROSERVER project, which ended earlier this year.

I spent three months at FORTH to learn about the technical

details of the UNIMEM memory model, its limitations and its

implementation on the Xilinx Ultrascale+ architecture. During

this time I also investigated the requirements of the interconnect

to properly allow the use of UNIMEM. In addition, I worked to

advance the design on FPGA of a custom AXIbased interconnect

for use in the ExaNeSt project at the daughtercard level, and

implementation and testing of this design on Ultrascale+

hardware at FORTH.

This collaboration resulted in documentation on the details of

UNIMEM, with particular focus on the ways in which the memory

model affects the programmability of the hardware and the

differences between the ideal UNIMEM model and the current

implementation. Using the Vivado toolchain, we also created

hardware designs which measure the performance of the custom

AXI interconnect with traffic generators. This has been

implemented and run successfully on the Ultrascale+ hardware.

Real performance metrics can now be gathered and the design

improved to meet higher performance constraints, with more

interesting features of the interconnect design being added and

tested. The aim is to publish the results of the implementation

and performance characteristics of these more advanced features.

The scope for future collaboration is very wide, considering that

ExaNeSt works closely together with the ExaNoDe and EcoScale

projects, which will all run until late 2018, and then the new

EuroEXA project will continue along the same lines until early

2021. Developing networks with the people at FORTH has been

highly beneficial. Now that I’ve spent time with specific members

of the team with specific skills at FORTH, it will be much simpler

to find avenues where FORTH and Manchester may assist one

another on specific parts of the project as work progresses.

Manolis Katevenis of FORTH commented: ‘Joshua’s visit was an

important step in furthering our collaboration with the University

of Manchester, especially on Interprocessor Communication

protocols – a key component for the Modularity of Silicon that

future technologies demand.’

He added: ‘This collaboration builds on FORTH’s strong tradition

of working with colleagues across Europe in R&D projects, which

has already yielded great results. Last year, for example, FORTH

attracted to Crete a Development Lab of the startup KALEAO,

cofounded by University of Manchester professor John Goodacre.

We look forward to continue this strong relationship to help

deliver the exascale machines that Europe desperately needs.’

Dubbed ‘Silicon Island’, Crete offers great opportunities for young computer scientists

HiPEACINFO 51 37

HiPEAC futures

HiPEAC internships: your career starts here

Every year, HiPEAC company members propose topics for internships, which are then funded or part funded by the project. This year, there

was a record number of internships and applicants. For further information, visit the HiPEAC website: hipeac.net/mobility/internships.

In his internship, Hamzeh Ahangari helped Embedded Computing Specialists lay the groundwork for a safety-qualified embedded system

in the transport domain.

NAME: Hamzeh Ahangari

RESEARCH CENTRE: Bilkent

University

HOST COMPANY: Embedded

Computing Specialists

DATES OF INTERNSHIP:

06/11/2016 - 03/02/2017

Transport safety as standard

Safetycritical computers are used exten

sively in many civil domains, such as the

automotive sector, rail transport and

avionics. While general, safe micro con

trollers with limited processing capabi

lities are available on the market, safe

processors with intensive processing capa

bilities should be designed and tailored to

the specific application requirements.

Such designs are always based on com

ponentlevel or systemlevel redundancies.

During this internship, we did a prelimi

nary study of the required standards for

implementing safetycritical electronic

systems. There are several such standards,

including IEC61508, DO178, etc, each of

which addresses a particular domain. From

these documents, the main para meters

addressed were identified and investigated.

These include component failure rates,

common cause failure rate, diagnostic

coverage factor, repair rate and so on.

The second step was to focus on choosing

the platform. Unlike existing systems,

which are usually implemented in

commer cialofftheshelf processors, like

those from Texas Instruments or NXP, we

wanted to check the feasibility of imple

menting such systems on highperfor

wwmance FPGAs like Xilinx Zynq. We

undertook a thorough investigation of the

facilities that FPGA manufacturers provide

for reaching the standards’ safety levels.

We also implemented a draft version of a

compact printed circuit board for Xilinx

Zynq FPGA.

The main aim was to assess the feasibility

of designing and manufacturing a safety

qualified embedded system for the

transportation industry. With the prelimi

nary study phase and part of the FPGA

system implementation complete, I hope

that we will be able to continue working

together on such systems in future.

Embedded Computing Specialists cofoun

der Philippe Manet commented: ‘This

HIPEAC internship allowed us to quickly

understand key aspects of certification in

our business, thanks to the expertise and

previous experience of Hamzeh. It allowed

us find the right strategy to handle this

complex issue.’

“The main aim was to assess the feasibility of

designing and manufacturing a safety-qualified

embedded system for the transportation

industry”

HiPEACINFO 5138

HiPEAC futures

Three-minute thesis

Continuing our series highlighting the work of HiPEAC’s 800-strong network of PhD students, in this issue we focus on memory controller

architecture for real-time applications.

NAME: Yonghui Li

RESEARCH CENTRE: Eindhoven University of

Technology

ADVISERS: Professor Kees Goossens and

Dr Benny Akesson

THESIS TITLE: Design and Formal Analysis of

Real-time Memory Controllers

Featured research: Memory access control which is right on time

Heterogeneous multicore computing platforms are becoming

increasingly popular to achieve the necessary computational

power without using too much energy. These platforms

simultaneously execute multiple applications that interact with

the physical world. The applications typically have realtime

requirements, such as a time deadline or a throughput constraint,

which must be satisfied to ensure the safety or performance of

the applications.

However, it is very challenging to satisfy the realtime

requirements of each application because of the complex

interference caused by resource sharing in the platform. In

particular, synchronous dynamic randomaccess memory

(SDRAM) stores the data and instructions in the platform and is

accessed by other resources issuing read or write memory

requests. It is one of the most shared resources and hence has

great impact on the timing behavior of applications.

This dissertation addresses two critical issues: 1) how to

efficiently serve memory requests with variable sizes, which are

generated by heterogeneous resources in the platform, and 2)

how to guarantee the worstcase response time and bandwidth

when accessing SDRAM, such that application requirements can

be satisfied. A new memory controller architecture is proposed to

serve the variablesized requests by dynamically scheduling the

proper number of memory commands to SDRAM at runtime

(RunDMC). Thanks to the dynamic scheduling scheme, the

memory commands for successive requests are pipelined,

resulting in higher efficiency than static command schedules for

requests. To guarantee the worstcase response time and

bandwidth, three analysis approaches are presented, including a

mathematical formalization, a dataflow model, and a timed

automata model, respectively. These models have different

properties that support the simulation, validation and verification

of the memory controller.

This dissertation is the first to explore and compare different

analysis approaches to obtain the worstcase response time and

bandwidth of realtime memory controllers. The experimental

results demonstrate that the proposed dynamicallyscheduled

memory controller is more efficient than existing (semi)static

controllers for requests with variable sizes, and the derived

worstcase results are tightly bounded.

Models Worst-Case Analyses Tools

Timed Automata model (TA)

Mode-controlled dataflow model

(MCDF)

Mathematical model

Analytical approach (ALAP & Collision)

Scheduled approach (ALAP)

MCDF Analysis

(Collision)

TA analysis

RTMemCtrl: Open source RTMemCtrl: Open source

Ericsson Heracles Ericsson Heracles

SystemC Simulator SystemC Simulator

Cycle-accurate model

Validation Accuracy equal

low high Worst-case

witness Correspondence

HiPEACINFO 51 39

25 July 2017

HPCA 2018 (Vienna) abstract submissions

HiPEAC Paper Award conference

hpca2018.ece.ucsb.edu

2017 JULY

2017 AUGUST

2017 SEPTEMBER

Dates for your diary

4 August 2017

ASPLOS 2018 (Williamsburg, VA, USA)

abstract submissions

HiPEAC Paper Award conference

asplos2018.org/calls

11 - 13 September 2017

2017 ARM Research Summit

Cambridge, UK

developer.arm.com/research/summit

15 September 2017

PDP 2018 (Cambridge, UK)

paper submissions

bioinfo.itb.cnr.it/pdp2018/call.html


FPL 2017

Ghent, Belgium

fpl2017.org

28 August - 1 September 2017

Euro-Par 2017

Santiago de Compostela, Spain

europar2017.usc.es

Phot

o: J

L C

ernad

as, F

lick

rcr

eati

veco

mm

ons.

org/l

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ParCo 2017

Bologna, Italy

parco.org

Phot

o: Y

uri V

irov

ets

crea

tive

com

mon

s.or

g/l

icen

ses/

by/2

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ACM Europe Conference 2017 ft. HiPEAC

Barcelona, Spain

acmeurope-conference.acm.org

Phot

o: Z

apri

ttsk

y, F

lick

rcr

eati

veco

mm

ons.

org/l

icen

ses/

by/2

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inside: your hipeac jobs poster

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