a scalable physical model for nano-electro-mechanical relays

2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

A Scalable Physical Model for N ano-Electro-Mechanical Relays

Haider Alrudainy, Andrey Mokhov, and Alex Yakovlev

School of Electrical and Electronic Engineering,

Newcastle University, Newcastle upon Tyne, NEl 7RU, England, UK

Emails:(h.m.a.alrudainy.andrey.mokhov.alex.yakovlev)@Newcastle.ac.uk

Abstract-Nano-Electro-Mechanical (NEM) relay is a promising device overcoming the energy-efficiency limitations of CMOS transistors operating at or near the sub-threshold voltage. Many exploratory research projects are currently under way investigating the mechanical, electrical and logical characteristics of NEM relays. One particular issue that this paper addresses is the need for a scalable and accurate physical model of the NEM switch that can be plugged into the standard EDA software.

The existing models are accurate and detailed but they suffer from the convergence problem. This problem requires finding ad-hoc workarounds and significantly impacts the designer's productivity. In this paper we propose a new simplified VerilogA model. To test scalability of the proposed model we crosschecked it against our analysis of a range of benchmark circuits. Results show that, compared to standard model, the proposed model is sufficiently accurate with an average of 6% error and can handle larger designs without divergence. In particular the largest circuit we could handle with the standard model in our experiments contained only 22 NEM relays, while the proposed approach could handle circuits comprised of 192 NEM relays.

I. INTRODUCTION

During the last 4 decades, the scaling of complementary metal-oxide-semiconductor (CMOS) has provided significant improvements in terms of performance and energy efficiency of integrated circuits. This scaling has now arrived to a point at which any further reduction in threshold voltage of integrated circuits comes at the expense of power consumption. As a consequence, designers have moved towards parallel computing methodology [1]. In this method each processor is designed to run at a lower throughput, energy per operation, and supply voltage. For example, a dual core microprocessor can improve the overall system performance by employing two parallel processing units as shown in Fig. 1. However, multi-core methodology will eventually become impractical [2]. This is attributed to the fact that CMOS approaches its minimum energy per operation constraint as the number of processor cores increases. Consequently, this would not result to any lower in energy consumption as shown in Fig. 1.

To overcome the energy-performance constraint, another MOSFET alternative devices have been emerged such as: Tunnelling Field Effect transistor (TFET) [4], Tri-Gate transistor , Nano-electromechanical field effect transistor (NEMFET), ferroelectric FETs, impact ionization MOS. Unfortunately, many of these CMOS like transistors achieve a steep subthreshold swing (S < 60mVjdec.) over only a specific range of supply voltage. This leads to a significant shortcoming

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Operating at a lower energy point

... co. ...

� �� oli �cn .. E",

Run in ----.;:==00:( � parallel to recoup performance

o 4 5 6 3 4 5 6 1/ Throughput 1/ Throughput

Fig. 1: Plots of normalized energy per operation vs. lIthrough-put, illustrating the advantages of parallelism and its restricted effectiveness due to CMOS minimum-energy constraint [3].

including: either a poor (I onl 10 f f) current ratio or a very low Ion current at a low supply voltage.

A feasible way to overcome the limitation of energyefficiency in CMOS circuits can be deduced from Fig. 2. If the slope of sub-threshold regime of CMOS can be made steeper, CMOS circuits would experience immeasurable low leakage current at the same supply voltage, making it possible for further improvements in energy-efficiency. This will require, then, an alternative device that overcomes the essential CMOS energy-efficiency limit.

To that end, a micro-electro-mechanical (MEM) relay (shown in Fig. 3) has recently emerged for ultra-low-power digital circuit applications [2] [5] [6]. This is because the relay exhibits perfect abrupt on-off switching behaviour, since it has nearly an ideal switch characteristic. Furthermore, the MEM relay has immeasurable off-state leakage current and steeper sub threshold slope. Therefore, its operating voltage can be scaled down to approach zero, in principle. Thus, the MEM relay can potentially overcome the fundamental energy efficiency limit of the CMOS technology.

Having a scalable model for NEM relay is crucial for design

I aD : � :

CMOS

c � Ideal switch � I � : U I c: I 'j! : c �� __ �I ________ �

Fig. 2: Sub-threshold transistor.

Gate Voltage Vg, regime of MEM relay and CMOS


rl,," .. :,:� .. m' ..

Gate: P+poly - S;0.4 GeO.6

(a) (b) Fig. 3: (a) Schematic 3-D view of 4-terminal suspended gate MEM relay based on [2], (b) Schematic 2-D cross section view in the off state.

systems consist of mixed NEMS and CMOS electronics. To evaluate the mechanical, electrical and logical characteristics of a MEM relay at the 90 nm technology node for a range of VLSI circuits, efforts by Matt Spencer have led to build a Verilog-A switch model based on experimental results in [2]. This model is accurate and detailed, however, it suffers from the long simulation time and convergence problem. To overcome the limitations of the model in [2], this paper proposes an approximate model which is more scalable, fast, simple, and more stable (especially near contact discontinuities). The major contributions of this paper are:

1) Implementing and evaluating the standard NEMS model. The model is analysed and pros and cons are evaluated and discussed. The model is found to be accurate. However, it suffers from the convergence problem for large designs due to the model's complexity.

2) Building a more scalable NEM relay model which can be applicable for VLSI circuits without any divergence issue.

3) Verifying the proposed model against a range of benchmarks with an average error rate 6%. Moreover, for the same benchmarks our model didn't suffer from diversity problems, while the standard one did diverge as the model becomes big and complex in size.

II. BACKGROUND

Relays can be classified based on the method of actuation into electrostatic [7], electrothermal [8], magneto static [9], and piezoelectric [10]. However, they could be also classified either according to the axis of deflection (lateral, vertical) or to the contact interface (ohm ic or capacitive).

Based on the method of actuation, each relay has different characteristics including: bias voltage, bias current, on resistance, delay time, current handling, and endurance as illustrated in Table I.

Among these relays, MEMS has recently received a remarkable attention in digital logic applications due to: low active power consumption, being scalable, and easy to manufacture using conventional planar processing techniques [6]. To mini-

TABLE I: MEM Relay Characteristics Actuated Switching Current Bias

MEMS Voltage Time handling current [V ] [/-is] [rnA] [rnA]

Electrostatic 1-100 0.1- 0.2 0.1-10 0 Thermal 0.5-5 100-5000 10-2000 0.5-10

Magnetostatic \-5 100-5000 10-2000 20-150 Piezoelectric 5-50 10-500 1-1000 0

mize the parasitic capacitor effects and improve the reliability, drastic improvements in relay design have led to design and fabricate three generations of MEMS as reported in [11]. As a consequence, numerous implementations of MEM and NEM relay have been proposed recently that indicate an order of magnitude more power saving than CMOS in low frequency applications :s; 100 MHz [5] [12] [13] [14] [15]. In general, MEM relays can be classified into two types:

1) Three-Terminal MEMS: a 3-Terminal (gate, drain, source) laterally actuated relay has been designed and fabricated in [16] to achieve Ins pull-in delay and 0.1 fJ switching energy at 1.5Y. However, connecting many 3-T switches in series causes the gate to source voltage change undesirably, and hence this may affect the state of switch [17].

2) Four-Terminal MEMS: a vertical actuated relay as shown in Fig. 3 and 4 has emerged to overcome the shortcomings of the 3-T relay. The state of switch can be determined based on gate-body terminal voltage (Vgb), which is independent of the source-drain voltage. Furthermore, adding the fourth terminal makes the relay turn on either by applying positive

Vgb (mimicking NMOSFET operation) or by applying negative

Vgb (mimicking operation of PMOSFET). The 4-Terminal relay can then be categorized into two types:

(A) Cantilever Beam Relay: This relay consists of gate electrode that carry a metal channel separated by a gate oxide [18], in addition to body, drain, and source electrode which is located below the gate as shown in Fig. 4. When the gatebody voltage increases above "pull-in voltage" (lVgbl 2: Vpi), a contact dimple touches the source and drain terminal, causing the current flow. While, the electrical contact is broken when the gate-body voltage decreases below the "pull-out voltage" (lVgb I :s; Vpo), as shown in Fig.4 (b) and (c).


Channel

s Substrate Insulator A-A' cross-section: ON state (I VSb 1 > Vpi)

(a) (c) Fig. 4: Cantilever beam relay as reported in [ IS] (a) plan view (b) cross-section view in the off-state (c) cross-section view

in the on-state.

(B) Suspended Gate Relay: To alleviate the impacts of any residual stress that may cause bending the beam out of plane, a suspended gate relay, as shown in Fig. 3, has emerged to address this problem. The position of gate electrode depends on the balance between the electrostatic force and the spring force. As a result, when the electrostatic force is sufficient enough to overcome the spring force, the channel touches drain/source electrode, thereby allowing current to flow. Otherwise, an air gap separates channel from drain/source electrode when the electrostatic force is less than the spring force. It was reported in [2] that the MEM relay operates at S-10V with a 90nm gap thickness (gd) between drain/source electrode and dimple. Like CMOS, scaling the MEM relay can improve the performance and minimize the energy of operation [5]. In this context, [2] has implied that MEM relay in the 90nm technology node with 5nm gap thickness (gd) can operate at less than 0.5V

III. MODELLING OF SUSPENDED GATE NEM RELAY

A. Terminology and definition of NEM relay parameters

Operating in a pull-in mode (i.e, � ;::: 0.3) results in most energy-efficient relay which is more preferable for digital logic applications [5]. However, pull-in mode of operating causes the electrical characteristics of MEM relay exhibit some hysteresis behaviour [19]. Pull in voltage (Vpi) refers to the voltage which is able to overcome the resistance of the springmass-damper system and causes the relay to turn on. While, release voltage (Vrl) refers to the voltage required to pull-out the device. The mechanical turn-off delay time is less than mechanical turn-on time (T mon > T moff). This is attributed to the fact that the electrical contact is broken rapidly as the gate electrode moves 1 nm away from the body electrode [2]. While, the gate electrode needs to travel the entire gap between gate and body to turn the device on. Noticeably, the mechanical delay time is an order of magnitude more than the electrical delay time. For example, the mechanical delay time of the adopted NEM relay in this work is about 15ns which is approximately 100 times more than the electrical delay time.

B. Mechanical Modelling

The movement of gate electrode under the applied voltage is governed by a Nonlinear time-variant second order differential equation [20]. The spring-mass-damper system as shown in Fig. 3(b) has been used to model the mass of the gate and flexures. 2 � .. {t kmejj .

mejjZ + Q

Z + kZ = Fele(Z) + Fvdw(Z) (1)

where, Z is the displacement of the gate, mej j is the effective mass, Q is the quality factor between [0-1] for digital logic applications [5], K is the spring constant, and Fvdw is the Van der Waals' force. The electrostatic force Fele (which is always attractive, i.e.,

ambipolar) is equal to the derivative of electrostatic energy stored in the Cgb capacitor with respect to the gap thickness.

EoAov Vg2b Fele = 2(go _ Z) 2 (2)

where, EO is the permittivity of free space, Vgb is the voltage between gate-body electrode, go is the area gap thickness when Z=O, Aov is the overlap area between gate and body electrode.

In a nano scale relay, undesirable attraction forces such as Van der Waals' force and Casimir force can significantly affect the pull-in stability of NEM relay. It was noted in [21] that, Van der Waals force is dominant over the dispersion force when the air gap thickness is several tens of nano-meters. Whereas, Casimir attraction force is the effective one as the air gap thickness increases above several nano-meters. Therefore, in this work only Van der Waals will be considered in the simulation as the gap thickness of the adopted NEM relay is lOnm. The Van der Waals force (Fvdw) of the suspended gate NEM relay can be expressed in a more intuitive formula based on [21] as: AwL

Fvdw = 67r(go _ Z)3

(3)

where, A is the Hamaker constant, L and w is the length and width of the suspended gate respectively. The voltage required to switch-on the device "Vp/' can be derived as follow [19]:

8kgJ 27EoAov

(4)

The mechanical delay time "T mech." of NEM relay is inversely proportional to the gate over drive (�), resonant frequency

P' #' and actuation-gap to contact-gap thickness ratio. This is

presented as:

1m ( Vpi ) (9d

) Tmech. ex: V k ' 1V9bl . go

(5)

C. Electrical Modeling

Unlike CMOS, a NEM relay based digital circuit should be designed in a large complex logic gate such that only one mechanical delay incurs at each stage. However, this significantly increases the total on-state resistance, and hence this in turn leads to an increase in electrical delay time. Calculating the amount of time required to charge or discharge


the load capacitance demands precise modeling of both the [Zz···] [ -mOk -VQ;mm ef f 1 [�21] + [-m�] (Fele. + Fvdw) on-state resistance and the device capacitances.

The on state resistance of NEM relay, as shown in Fig. 5, consists of Rtraee (resistance of wire leading to/and from the tungsten electrode), Reh (the resistance of channel), Reon (the resistance of the channel-drain/source contact), and Rpox(the resistance of passive oxide which is used to improve the endurance).

(7)

The load capacitance of a NEM relay is represented by several parasitic capacitances such as gate-body ( Cgb), gate-source ( Cgs), gate-drain ( Cgd), gate-channel ( Cge), and channel-body ( Ceb) capacitance. In the off-state, the gate to channel Cge capacitance will not be contributed in the overall

capacitance as the channel terminal is floating. The electrical delay required to charge and discharge the NEM relay parasitic capacitance can be written in an approximate formula as:

Rch/2

Rtrace d_ ..............

a b j

(6)

Rtrace

Fig. 5: On-state electrical characterictics of NEM relay [2].

D. Simulation of Suspended Gate NEM relay

A digital NEM relay can be modeled by incorporating all the mechanical and the electrical effects shown in Fig. 3. An accurate conservative Verilog-A model has been adopted in this work to simulate the behavior of NEM relay based on fabricated parameters published in [2], and shown in Table II.

The Verilog-A has been utilized in this work as it has a multiphysics framework, which deals with different disciplines such as kinematic, electrical, thermal, and fluidic. This Veri log-A model is co-simulated with the Cadence solver to simulate the mass-spring-damper system defined in Eq.1 and the electrical model shown in Fig. 5. Noteworthy, this model can handle the self-actuation effects of the NEM relay but does not cover the thermal impacts on the electrical parameters. In order to avoid hidden states in Verilog-A, the state-space form has been used to rewrite the inhomogeneous nonlinear differential equation (Eq. I). This equation describes the motion of the gate electrode according to Newton's second law. According to the state-space definition [22], a first order differential equations can be used to describe the input, state, and output variables. This can be presented as:

TABLE II: NEMS parameters based on [2] 90 10nm

9d 5 nm

Aov 0.77 [J.im"l

A 12 [J.im�l Cad(Z = 0), and Cgs(Z - 0) 0.6 [IF]

Cab(Z = 0) 1.46 [fF] R( eh/2+eon+pox) 800 S1

The procedure of simulating the NEM relay in this work can be summarized according to the algorithm shown below:

Algorithm 1 NEMS model.

Define: Source:=s, Drain:=d, Gate:=g, Base:-b, Displacement:-Z. Define: Discipline: Electrical +-- (s, d, g, b).

Discipline: Kinematic +-- (Z, velocity). Input: (Vg, Vs, Vb). Output: (V d). Define: Constant (Gge, Geb, Rtrace, Rch/2' Rpox). Define: Dimple gap (gd), Spring constant (k), mass, Damping ratio.

I: Initially (Vg, Z) +-- O. 2: Calculate Fe, Fs, Fvdw at (Z = 0). 3: Calculate Zl by solving:

Z = velocity = Z2 .. 1 - {/km J J ) Z = -( Q e Z2 - kZ1 + Fele. + Fvdw .

4: If Zl < gd Then: m m

(NEM relay is on)

e Aov _ G - eoA(d) R 5: Calculate Ggb = �, Ggd - gs - (90-ztl' con 4pAE,H F F 3Fele(gd)' ele, vdw ·

6: Find: V(d, a) = V(j,s) = Rtraee*I(d,a), I(g,a) = I(g,j) =

Ggs * dVd�,j) , V(a,!) = V(f,j) = R(ch/2+pox+con) * I(f,a),

I(! g) - G '" dV(g,J) , - gc ' dt .

7: Find I(d,s),Tele,Tmeeh, Vpi. 8: Calculate Switching Energy: Es = (Ggb + Ggd + Ggs)Vld. 9: else: I (d, s) = O. (NEM relay is off)

E. Proposed Model

The equivalent electrical circuit of the NEM relay can be simplified to a lower complexity model. This is advantageous to mitigate the non-linearity issue in the standard model (which is one reason of the divergence problem) while sacrificing some degree of accuracy. This assumption is inspired by the transmission line model approximation in [23]. The proposed simplified paradigm of the NEM relay can be explained through the following stages:

I) The trace resistance is very small in comparison with Reon, Rpox, and Reh/ 2 therefore it can be ignored.

Rtraee « Reon, Rtraee « Rpox, Rtraee « Reh/ 2 . Due to a small overlap area between the body and channel electrode, Ceb is insignificant and can be neglected. In the same way, Ceg can be ignored, as shown below:

( Ceg+Ceb) « Cgb, ( Ceg+Ceb) « Cgd, ( Ceg+Ceb) « Cgs.

g

Rch/2

d b s

Fig. 6: Simplified NEMS model (1).


2) The non-linear parasitic capacitor Cgd, and Cgs can be linearised by taking the maximum value ( Cgd = Cgs =

0.61 F at Z = 5 nm) . Then, they have been added together as shown in Fig. 7.

g

Rpox + ReoD d b s

Fig. 7: Simplified NEMS model (2).

3) In the same way, Rcon can be linearised by taking the average value (200 [con�act]). Then, it has been added

to the Rpox and RCh/2 resistance, as shown in Fig. 8.

Rpox + Rcon+Rch/2

g

Rpox + Rcon+Rch/2

d b s Fig. 8: Simplified NEMS model (3).

In terms of computational complexity, the original model needs to solve 8 non-linear equations to approach the solution. While our proposed model can approach the solution by only solving 5 non-linear equations as shown in Algorithm II.

Algorithm 2 Proposed NEMS model.

Define: Source:=s, Drain:=d, Gate:=g, Base:=b, Displacement:=Z. Define: Discipline: Electrical +- (s, d, g, b)

Discipline: Kinematic +- (Z, velocity). Input: (Vg, Vs, Vb). Output: (Vd). Define: Constant (Ggc, Gcb, Rtrace, Rch/2,Ggd,Ggs, Rpox, Rcon). Define: Dimple gap (gd), Spring constant (k), mass, Damping ratio.

1: Initially (Vg, Z) +- O. 2: Calculate Fe, Fs, Fvdw at (Z = 0). 3: Calculate Zl by solving Eq. 7. 4: If Zl < gd Then: (NEM relay is on) 5: Calculate Ggb, Fe1e, Fvdw . 6: Find: V(d, f) = V(j, s) = R(pox+ch/2+con)*J(d, f), J(j,g) =

2G dV(g,f) J( b) - G '" dV(g,b) gd * dt ' g, - gb ' dt . 7: Find J(d, s) , Tele, Tmech, Vpi, and Es. 8: else: J (d, s) = 0 (NEM relay is oft)

IV. MODEL EVALUATION

A. Simulation of the Proposed NEM Relay Model

To verify the validity of this model, the error rate (latency) between the output signal of the standard and proposed model in (3), of cascade AND gates, as shown in Fig. 9(a), has been measured. The results indicate that a 4.6 % error rate can be noted between the output signal of the two models in the case of adopting one AND gate, while it increases to less than 7% after cascading of 40 AND gate in series as shown in Fig.

A40D- �7. 0 ��e F��r

or [%11 � •••.• "

Al ....... 0 ..••• ti=O-2 \.<6. 5 .....

AO �6. 0 ••••••••••

� ...... • �JV' Al Al0 A40 G5. 5 ...

..... .

I I k> ...1.. ...1.. ...1.. <=i 5 . 0 ' ....... .

AO I H

�� ..... �� 4. 5�')V 'I v, Al--t� Al04 � A404� 0 5 10 15 20 25 30 35 40

� � Number of stages

(a) (b) Fig. 9: (a) CMOS-NEM relay mapping of cascade AND gates (b )Latency Error rate.

7000 -Standard Model � 6000 =:��::: ��:: ; 8 5000 -Proposed Model 1 ! Q) 4000 E � 3000 o

� 2000 E i:7.i 1000

8 10 N-BitAdder 12 14 16

Fig. 10: Simulation runtime vs. number of bits in adder.

9(b). Noteworthy, the error rate is linearly proportional with the number of stages, which is advantageous for adopting this model with this acceptable error rate in the VLSI circuits.

The simulation time of the standard and proposed model in 1, 2, and 3 has been measured for a various number of input bits adder, as shown in Fig. IO. It is clearly shown that the running time of the simulation is correlated to the number of input bits (size of the circuit). Results in Fig.10 show that the standard and proposed model in I suffer from convergence problem while increasing the number of bits to 2 and 5 respectively. unlike, the proposed model in 3 shows better simulation speed and convergence than the other models, at the expense of a small error rate due to the simplification in the electrical circu it.

B. Evaluation with Benchmark Circuits

To evaluate the proposed model in terms of latency, scalability, simulation time and stability, it has been checked against a range of benchmark circuits including: combinational (AND, OR, XOR), sequential (D-Iatch, C-Element), and arithmetic (carry save adder, carry ripple adder) as shown in Table III. Results have clearly shown that, the proposed model is 31 % faster than the standard model on average. However, as the size of the circuits increase, the simulation time of the standard model is expected to be increasing drastically, and hence this percentage can be considered only for the used benchmark circuits.

In terms of latency, results indicate a small difference between the output signal of the two models (less than 6% in average). This is attributed to the presence of approximation in the electrical circuit of the proposed model. It has been noted from the results in Table III that the standard model usually diverges when the design becomes complex and big in size, such as in: 3-inputs C-Element and 5-bit carry ripple adder.


TABLE III: NEM Model Benchmark circuits Circuit No. of relays Latency Simulation Time

Standard Proposed (3) Error (%) Standard Proposed (3) Improvement (%) 2-inp. AND 2 15ns

Logic 2-mp. OR 2 15ns 2-inp. XOR 2 15ns

3-mp. MajorIty 12 15ns D-latch 4 15ns

Sequential 2-inp. C-Element 10 15ns 3-inp. C-Element 14 Div.

I-bit 3-inp. CS adder 22 15ns

Arithmetic I-bit CR adder 12 15ns 2-bit CR adder 24 Div. 5-bit CR adder 60 Div

16-bit CR adder 192 Div Average

This is attributed to the fact that the accumulating error due to contact discontinuities will rise significantly as the number of stage increases. Furthermore, numerous number of non-linear parasitic capacitance in the big design is the second reason of causing the model to be diverging.

The proposed model has checked against the standard one for different clock speed and stage levels. Results in Fig. 11 have shown a very slight impact in the simulation time of the proposed model can happen as the clock period changes from lOOns to 500ns. For example, at stage four the simulation time increases only 10% as the clock period changes to 500ns. In contrast, the standard model shows a significant increasing (which is about 26% at stage four) in the simulation time as the clock period shifts from lOOns to 500ns. This is attributed to the fact that the discontinuity period of the switch will be shorter as the switching frequency increases, and this makes the simulator approaches the solution very fast. In contrast, the simulator needs long time to approach the solution at low switching frequency (long discontinuity period).

V. CONCLUSION

Scaling of CMOS has arrived at a point at which any further reduction in threshold voltage of integrated circuits comes at the expense of high power consumption. Furthermore, supply voltage of the smaller node technology is not expected to be scaled less than the limit set by k:. Thus, an alternative device with a less energy-hungry and steeper sub-threshold regime like a NEM relay is necessary to be implemented in integrated

800

""": 700 o aJ ."'.600

� 500 'M J.J 400 <:: .S 300 J.J '" r< 2 00 § � 100

a

.Standard model [lOOns]

.Proposed model [lOOns] DStandard model [500ns] .Proposed model [500ns]

I r 1 2 3

Number of stages

I-

4

Fig. 11: Model execution time versus clock speed and number of stages.

15.7ns 4.6 3m 4s 2m 23s 23 15.6ns 4.0 4m 49s 3m 26s 29 15.5ns 3.3 848 ms 783 ms 7 16.1ns 7 6m 15s 3m 5s 51 15.7ns 4.6 1m 47s 1m 2s 41 16ns 6.0 6m 28s 3m 55s 39 17ns - Div. 9m 19s --17ns 13 13m 23s 9m 37s 28 16ns 6.0 6m 52s 4m 37s 33 18ns - Div. 14m 34s --22ns - Div. 31m 35s --24ns - Div. 1h 26m --

6 31

circuits. NEM models are crucial to EDA design. However, the standard NEM model suffers from convergence problem and long execution time. This paper proposes a new simplified NEM model that can be used for large scale circuit simulation with insignificant error. The proposed model is evaluated with a variety of benchmark circuits and results show it can be adopted for simulating VLSI circuits with less than 6 % error rate. The proposed model can be integrated in the existing EDAs and can be used for simulating and designing of NEMbased VLSI circuits with better scalability and less execution time than the standard model. As we have demonstrated in the experiments, the proposed approach could handle circuits comprised of 192 NEM relays, while the standard model could not converge on circuits containing more than 22 NEM relays.

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a scalable physical model for nano-electro-mechanical relays

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