7nm Logic Optical Lithography with OPC-Lite

Michael C. Smayling*a, Koichiro Tsujitab, Hidetami Yaegashic, Valery Axelradd

Ryo Nakayamab, Kenichi Oyamac, Shohei Yamauchic, Hiroyuki Ishiib, Koji Mikamib

aTela Innovations, Inc., 485 Alberto Way, Suite 115, Los Gatos, CA, USA 95032 bCanon, Inc., 20-2, Kiyohara-Kogyodanchi, Utsunomiya-shi, Tochigi, Japan 321-3292

cTokyo Electron, Ltd., 650 Mitsuzawa, Hosaka-cho, Nirasaki City, Yamanashi, Japan 407-0192dSequoia Design Systems, Inc., 137 Chapman Rd., Woodside, CA USA 94062

ABSTRACT

The CMOS logic 22nm node was the last one done with single patterning. It used a highly regular layout stylewith Gridded Design Rules (GDR). Smaller nodes have required the same regular layout style but withmultiple patterning for critical layers. A “line/cut” approach is being used to achieve good pattern fidelity andprocess margin.[1] As shown in Fig. 1, even with “line” patterns, pitch division will eventually be necessary.

For the “cut” pattern, Design-Source-Mask Optimization (DSMO) has been demonstrated to be effective atthe 20nm node and below.[2,3,4] Single patterning was found to be suitable down to 16nm, while doublepatterning extended optical lithography for cuts to the 10-12nm nodes. Design optimization avoided the needfor triple patterning. Lines can be patterned with 193nm immersion with no complex OPC. The final linedimensions can be achieved by applying pitch division by two or four.[5]

In this study, we extend the scaling using simplified OPC to the 7nm node for critical FEOL and BEOLlayers. The test block is a reasonably complex logic function with ~100k gates of combinatorial logic andflip-flops, scaled from previous experiments.

Simulation results show that for cuts at 7nm logic dimensions, the gate layer can be done with singlepatterning whose minimum pitch is 53nm, possibly some of the 1x metal layers can be done with doublepatterning whose minimum pitch is 53nm, and the contact layer will require triple patterning whose minimumpitch is 68nm. These pitches are less than the resolution limit of ArF NA=1.35 (72nm). However thesepatterns can be separated by a combination of innovative SMO for less than optical resolution limit and aprocess trick of hole-repair technique. An example of triple patterning coloring is shown in Fig 3. Fin andlocal interconnect are created by lines and trims. The number of trim patterns are 3 times (min. pitch=90nm)and twice (min. pitch=120nm), respectively. The small number of masks, large pitches, and simple patterns oftrims come from the simple 1D layout design.

Experimental demonstration of these cut layers using design optimization, OPC-Lite, and conventionalilluminators at the 7nm node dimensions will be presented. Lines were patterned with 193nm immersion withno complex OPC. The final line dimensions (22nm pitch) were achieved with pitch division 4.[5]

Keywords: Low k1, highly regular layout, gridded design rules, pitch division, spacer double patterning, linesand cuts, design source mask optimization (DSMO)

*mike@tela-inc.com; phone +1 408 558-6321; fax +1 408 354-4900

1. INTRODUCTION

Semiconductor optical photolithography stopped scaling in 2007 with the introduction of ArFimmersion scanners. The rapid introduction of immersion lithography extended the roadmap, whichhad been expected to reach its end several years earlier.[13]

In spite  of   resolution  progress  with  each new optical  system,   the  fitting   factor   in   the  Rayleighequation (half­pitch = k1 /NA) had been decreasing slower prior to 2007. With no improvement inresolution since 2007, the k1 value has dropped quickly for recent logic technology nodes in spite ofresolution   enhancement   techniques   (RET)   such   as   optical   proximity   correction   (OPC),   off­axisillumination (OAI), and phase shift masks (PSM) which had been introduced to maintain reasonablepattern fidelity.

At low k1  values, more regular layout has been used to achieve good pattern fidelity.[14­17] Toimprove scalability,   these regular  patterns can be decomposed into “lines” and “cuts” to  permitindependent optimization of each part of the pattern. However, as shown in Figure 1, even for linepatterns, pitch division has become necessary for production at 20nm and below. SAPD (self­alignedpitch division) is the currently preferred approach as it has been demonstrated in production. The cutand hole layers require multiple patterning below 14nm, with the transition occurring at differentnodes for different design layers.[2,6]

Figure 1. Metal-1 pitch for sub-20nm logic technology nodes.

The line layers will continue to be patterned with optical lithography such as KrF, ArF, or ArFi. Pitchdivision will be applied at pitches below 80nm and can be done by multiple exposures, for examplelitho-etch-litho-etch (LELE), or through self-aligned processes such as spacer-double-patterning(SDP), or by directed self-assembly (DSA). LELE has not been widely adopted due to alignmentrequirements and etch CD requirements.

The “cut” and “hole” patterns can be done optically with single exposures down to ~16nm, whilemultiple exposures are needed for smaller nodes. E-beam direct-write is also a candidate forexposing the cut patterns, since the pattern density is relatively low, but today’s single columnsystems do not have sufficient throughput for high volume manufacturing. Multiple-beam systemsappear feasible and could become an alternative to multiple optical exposures at the right cost /throughput point.

2. MODELING AND SIMULATION

The approach taken for the contact layer simulation has been previously described for work done at20nm, 16nm and 11nm for “cut” layers.[2,3,4] Using the Canon extensions to Sequoia Cell Designer(SCD) for OPC-Lite, the design-source-mask-optimization (DSMO) is done globally on arepresentative set of layout cells. This approach produces simple rectangular shapes in the SMOoutput to greatly reduce mask complexity and improve metrics such as MEEF and DOF.[9]

Simulations were carried out on cells from a logic block drawn at the 11nm node and scaled to 7nm.The metal-1 pitches were in a conventional 7:9 ratio with the gate pitches. The contact layout wentthrough multiple iterations at the cell level to achieve printability while maintaining cell function.Layout changes were also made at the block level to permit the use of triple patterning.

A portion of the logic block test case is shown in Figure 2. The logic block contains ~100k CMOStransistors designed from standard cells and built by a conventional place-and-route design flow.This block has been scaled from 90nm and has been used for evaluations in several generations oflayout rules.

Figure 2. Logic block contact layer before splitting; minimum pitch is 30nm.

Since the initial 30nm pitch is far below the resolution capability of ArFi, pattern splitting wasevaluated. The resultant minimum pitches for each degree of splitting are summarized in Table 2.

Table 1. Pattern splitting comparisonNumber of patterns Min pitch, nm k1 for ArFi NA 1.35

1 30 0.102 60 0.213 68 0.24

4 87 0.305 107 0.37

Since the resolution limit of ArFi NA=1.35 is 71.6nm, a conventional lithography process wouldrequire at least four patterns for the contact layer. However, the “edamame” hole repair allowspatterning at an effective k1 of less than 0.25.[18] This reduction in the number of patterning stepsfor the contact layer is expected to continue to the 5nm node.

Figure 3 shows the contact layer layout after the splitting into three patterns. The minimum pitch is63nm for all three colors. Pattern density was balanced between the colors.

Figure 3. Logic block contact layer with three patterns.

For the three patterns, PV bands were simulated for dose 2%, focus 30nm, and mask 0.5%. Theseresults are summarized in Table 2. Bright field illumination was used with negative tone develop,6% att.PSM mask, ArFi with NA=1.35 scanner, and tangential polarization.

Table 2. Simulation results summary1st pattern 2nd pattern 3rd pattern

IlluminatorOuter/Inner

0.98/0.765 0.98/0.789 0.98/0.797Min Pitch, nm 63 63 63Slimming, nm 40 40 40

Aerial imagecontours at best

condition

Although the contact layer is one of the most challenging, other layers were studied as well tounderstand for each one the balance between the number of trim/cut masks and the patterningdifficulty. Even at the 7nm node, the gate layer can be done with one cut mask; two trim masks arerequired for local interconnect, and three cut masks are required for fins and metal-1.

The aerial images for the gate layer cutmask are shown in Figure 4. Theilluminator is annular with sigmaouter/inner of 0.98/0.796. Therelatively low density of the gatepattern allows such single patteringalong with 30nm of shrink (diameter).The cuts have a 110nm pitch to thelong cuts along the top and bottom ofthe cells, while the pitch is 53nm forthe interal gate cuts.

Figure 4. Gate layer cut mask showing single patterning.

The process is more complex for the local interconnect layer, which requires two trim steps asshown in Figure 5. Annular illumination was used, with sigma outer/inner of 0.736/0.597 and0.854/0.684 for trims 1 and 2, respectively. 40nm of shrink (diameter) was used for both trims.

Figure 5. 7nm node local interconnect trim 1 (left) and trim 2 (right).

Results for the metal-1 triple cut exposures were similar to those of the triple pattern contacts eventhough the minimum pitches were larger at 93, 88, and 89nm. 40nm shrink was applied to each.Annular illumination was used with 0.897/0.726, 0.945/0.645, and 0.898/0.657 for cuts 1, 2, and 3,respectively.

3. EXPERIMENTAL RESULTS

SMO and pattern splitting was done at Canon using OPC-Lite to produce the simple patterns for thereticles. Wafers were processed at the TEL research facilities, including patterning, deposition, etch,and metrology. Line patterns were created with 80nm pitch and reduced to 20nm pitch using SQP.The sequence of deposition and etching for SDP is well described in the literature.[9,10]

For reference, detailed results for the contact LELE process at 11nm are shown in Figure 6.[from 2]Pattern one and pattern two had different CD’s in resist, at ~57.3nm and ~52.1nm for the semi-densecontacts. After etch, the sizing was 25.7 and 23.7nm using an early-version shrink process.

Figure 6. 11nm node contacts Litho-1, Etch-1, Litho-2, Etch-2 (left to right).

With a half-pitch of 31.5nm, equivalent to k1=0.22, the resist pattern has merging of some contactsas shown in Figure 7. Also, the contact size in resist is not uniform. Normally, this would result in anunsatisfactory result after etch.

Figure 7. High resolution SEM of contact resist patterns.

In this work, an improved shrink process was used to handle the “peanut” or “edamame” shape ofthe resist for some pairs of contacts, as well as the non-uniform size of individual contacts. Theshrink process has more etch by-product deposition than a normal dielectric etch, which fills thenarrow gaps between contacts and results in contact holes which are separated after etch. Figure 8shows the contact holes after etch, with a typical diameter of 18nm. The exposure conditions wereset based on the simulations previously discussed.

Figure 8. 7nm contact hole pattern after etch.

Although the results look promising, there is work to be done. For example, in Figure 9, the contacthole pattern after etch is overlaid with the design pattern. There are several locations where the holedisappeared during etch, in the upper left of the image, or where the hole pattern did not resolveduring exposure. Further work is planned in exposure tuning and the etch process optimization.

Figure 9. 7nm contact hole pattern after etch with design overlay.

4. CONCLUSIONS

The application of the 1D gridded design style has been extended to the 7nm CMOS logic node. Inthis study we have demonstrated that critical “hole” layers such as contacts can be fabricated usingan LELELE sequence. Design optimization, source-mask optimization, simple proximity correctionusing OPC-Lite, and careful processing in the process fab were required to get the good results.Combined with previous results for “cuts” we have shown a path to scaling of CMOS logic criticallayers such as Gate, Contact, and Metal-1.

We would like to thank the staff at TEL for the lengthy effort needed to fabricate and analyze thewafers; the staff at Canon for mask design, simulations, and analysis; Sequoia Design Systems forthe use of Sequoia Cell Designer with enhancements, and Tela Innovations for their help in creatingthe design space and design optimization. We appreciate the continued support of our executivemanagement.

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