2242 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 9, SEPTEMBER 2010

Letters

Digital Time-Optimal Phase Shedding in Multiphase Buck Converters

A. Costabeber, P. Mattavelli, and S. Saggini

Abstract—This letter proposes a time-optimal digital controllerfor the phase shedding (PS) in multiphase buck converters. PSis an established technique to improve the efficiency of multiphaseconverters at light load by changing the active number of phases de-pending on the load-current level. In order to minimize the output-voltage deviation and the transient time during PS, a minimumtime algorithm is investigated. The proposed technique is insensi-tive to the power stage parameters, as its operation relies only on afeedforward action, depending on the steady-state duty cycle andthe number of phases to be turned on or turned off. The proposedapproach is validated through experimental tests on a synchronousbuck converter.

Index Terms—DC–DC converters, digital control, field-programmable gate array (FPGA), multiphase converters, phaseshedding (PS).

I. INTRODUCTION

E FFICIENCY improvement in energy-conversion processis becoming more and more important at any power level.

This has led to the investigation of several techniques to main-tain high efficiency at different load, input voltage, and outputvoltage conditions. This is also valid for power managementapplications, where, the cost/complexity increase of “more in-telligent” controller is nowadays more and more justified, ifefficiency is improved.

In power management applications, the multiphase converterwith pulsewidth modulation (PWM) signals interleaved amongthe phases is widely used, since it provides several advantagesin terms of input and output current ripple reduction, and fastertransient response [1]–[5]. When the load current is decreased,it is not necessary to continuously modulate all phases, sincethe load current can be shared among a reduced number ofcells. The operation of disconnecting some phases at light loadin order to improve the converter efficiency is usually denotedas “phase shedding” (PS) [1], [2]. The principle has been pro-posed in several papers and also adopted in some commer-

Manuscript received October 2, 2009; revised January 18, 2010; acceptedMarch 20, 2010. Date of current version September 17, 2010. Recommendedfor publication by Associate Editor R. Zane.

A. Costabeber is with the Department of Information Engineering, Universityof Padova, Padova 35131, Italy (e-mail: costabeber@dei.unipd.it).

P. Mattavelli is with the Department of Industrial Management and Engineer-ing, University of Padova, Padova 35131, Italy (e-mail: mattavelli@ieee.org).

S. Saggini is with the Department of Electrical, Mechanical, and Man-agerial Engineering, University of Udine, Udine 33100, Italy (e-mail:stefano.saggini@uniud.it).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2010.2049374

cial high-performance digital IC controller for switched-modepower supplies (SMPS).

More recently, the topic of digital control of SMPS hasbeen receiving increasing attention from the scientific commu-nity [6]–[11]. Programmability, versatility, reduction of exter-nal passive components, and intrinsic ability to execute complexand strongly algorithmic control actions make digital controllersvery attractive. Thus, it appears intriguing to exploit nonlineardigital controls to implement time-optimal techniques so thatthe PS can be implemented with minimum output-voltage devi-ations and minimum transient-response time. The solutions pro-posed in the literature usually rely on the controller to recoverthe nominal operating conditions after PS. In a more recent con-tribution [12], a PS with an adaptive voltage controller, based onthe number of active phases, is proposed. In [12], the number ofactive phases is based on the inductor current measurement andthe voltage loop (or droop controller) handles the transient dueto the PS. Instead, this letter is restricted to the case, where theload autonomously decides the number of active phases using,for example, the power state indicator (PSI) of the micropro-cessor or the power management bus (PMBus) signal, and itproposes a minimum time controller through a specific feedfor-ward action during the PS. Interesting features of this algorithmare the independence of power stage parameters and the simplecalculation required.

II. PS IN MULTIPHASE BUCK CONVERTERS

Fig. 1 shows the basic scheme of a multiphase buck converter,where the number of phases, for the sake of explanation, hasbeen restricted to three (NP = 3). Depending on the number ofactive phases, the PWM signal is phase-shifted in order to reduceinput and output current ripple and to increase the equivalentswitching frequency seen by the load and the supply.

Without going in the details of a loss analysis, the typicalefficiency curve of a multiphase buck converter versus the loadcurrent is reported in Fig. 2, where N is the number of activephases. From Fig. 2, the maximum efficiency is obtained using:1) N = 3 when Io > Ith2 ; 2) N = 2 when Ith1 < Io < Ith2 ;and 3) N = 1 when Io < Ith1 . Thus, the power stage can bedynamically changed as a function of the load in order to keepthe efficiency at the maximum level [1], [2].

In this letter, it is assumed that an external controller is goingto decide the number of phases, either depending on the loadcurrent or on a command given by the microprocessor or bythe PMBus. The letter focuses on how to minimize the transientduring PS, in order to ensure minimum output-voltage deviation

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Fig. 1. Multiphase buck converter (with N = 3).

Fig. 2. Converter efficiency varying the number of phases (with N = 3).

and minimum recovery time, as the enabling process to thewidespread use of the PS techniques to improve efficiency atlight load.

III. MINIMUM TIME CONTROLLER

In point-of-load (PoL) converters and for voltage regulationmodules (VRMs), the output regulation is either performed onthe output voltage or on a combination between output voltageand output current, usually denoted as droop function [4], thelast one being depicted in Fig. 3. Independently, on the specificcontrol configuration of the multiphase converters, the minimumtime controller is obtained here by adding a specific action δFFto the output-voltage regulator. Being the feedforward actionbased on external load information, there is not any interactionbetween the PID controller and the feedforward control. Thecase would be different in the case, where the PS is based onthe inductor current [12], since the control action depends on astate variable and some interactions between the voltage-loopcontrol and the proposed action may arise.

Following Fig. 4 for the turning off of one phase, the minimumtime controller operates as follows. After receiving an externalPS command, the controller generates the feedforward term δ∗FF ;then, when the currents of the phases to be turned off reach the

Fig. 3. Droop control of multiphase buck converter with minimum timecontroller.

Fig. 4. Average current waveform during turning off of one phase.

zero value, the feedforward term is set to zero and the systemoperates in the nominal conditions with the remaining phases.The same procedure is applied during the phase turn-ON.

For the evaluation of δ∗FF , only the average value of the currentis considered here. Some additional considerations due to thecurrent ripple are reported in the Section IV. In order to minimizethe output-voltage deviation due to PS, the total output currentiLT is kept constant during the transient, i.e.,

〈iLT 〉 =No n-a f t e r P S∑

k=1

〈iLk 〉 +N t u r n e d-o f f∑

h=1

〈iLh〉 = IT (1)

where IT is a generic constant load current and Symbol 〈 〉denotes the average value (averaged over a switching period).During a turn-OFF transient, in (1), iLk is the current in theactive phases after the PS, Non-after PS is the number of activephases after PS, iLh is the current of phases to be turned off, andNturned-off is the number of phases to be turned off. In Fig. 4,Non-after PS = 2 and Nturned-off = 1. Thus, during the PS

No n-a f t e r P S∑

k=1

d

dt〈iLk 〉 +

N t u r n e d-o f f∑

h=1

d

dt〈iLh〉 = 0. (2)

2244 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 9, SEPTEMBER 2010

Referring to Fig. 4 for phases turn-off transient, we have

d

dt〈iLk 〉Non-after PS = − d

dt〈iLh〉Nturned-off (3)

and the terms of current variation can be expressed as follows:

∆ILO N =d

dt〈iLk 〉TFF ∆ILO F F =

d

dt〈iLh〉TFF (4)

and TFF is the time interval for the PS operation.In order to minimize the transient time and to keep constrain

(2), the following conditions are imposed:

δh = 0, h = 1, . . . , Nturned-off (5)

δk = δ∗FF + δPID , k = 1, . . . , Non-after PS (6)

where subscript h indicates the phases to be turned off, subscriptk indicates the active phases after PS, and δPID indicates theoutput of the PID control. Assuming that during the PS, theinput voltage, load voltage, and output currents are constant,current slopes are given by

d

dt〈iLh〉 = −Vo

L

d

dt〈iLk 〉 = δ∗FF

Vin

L. (7)

Thus, by substituting (7) in (3), the feedforward contributionfor the on phases during the turn OFF of other phases δ∗FF isgiven by

δ∗FF =Vo

Vin

Nturned-off

Non-after PS= δSS

Nturned-off

Non-after PS(8)

where δSS is the nominal duty cycle under steady-state condi-tions, available within the PID controller using the output of theintegral term. It is worth to point out that (8) is based only onthe steady-state duty cycle, and it is independent of the powerstage parameters and load conditions. Its evaluation is verysimple, since term Nturned-off /Non-after PS can be easily storedin lookup tables.

In case of duty-cycle saturation, i.e., δk = δ∗FF + δSS > 1,then, the duty cycle of the phases to be turned on is set to unityand the duty cycle to be turned off is set by a feedforwardterm that imposes the constraint (2); thus, (5) and (6) change asfollows:

δh = δ∗FFS + δPID , h = 1, . . . , Nturned-off (9)

δk = 1, k = 1, . . . , Non-after PS . (10)

Following the same reasoning, (7) and (8) are modified in(11) and (12), respectively

d

dt〈iLh〉 = δ∗FFS

Vin

L

d

dt〈iLk 〉 = (1 − δSS)

Vin

L(11)

δ∗FFS = (δSS − 1)Non-after PS

Nturned-off. (12)

The case of duty-cycle saturation is, however, not very com-mon for PoL converters with high voltage-conversion ratio,since δSS � 1 (for example, with Vin = 12 V and Vo =1.1 V).

Fig. 5. Average current waveform during turning on of one phase.

A similar reasoning is done during phase turn-on transient.During the turn-ON transient, (1) is expressed as follows:

〈iLT 〉 =No n-b e fo r e P S∑

k=1

〈iLk 〉 +N t u r n e d-o n∑

h=1

〈iLh〉 = IT (13)

where iLk is now the current in the active phases before the PS,Non-before PS is the number of active phases before PS, iLh is thecurrent of phases to be turned on, and Nturned-on is the numberof phases to be turned on. In Fig. 5, Non-before PS = 2 andNturned-on = 1. Following Fig. 5 and the procedure describedearlier, the feedforward contribution δ∗FF is now given by

δ∗FF = δSSNon-before PS

Nturned-on(14)

δki= 0, ki = 1, . . . , Non-before PS (15)

δkj= δ∗FF , kj = 1, . . . , Nturned-on (16)

where subscript ki indicates the Non-before PS phases active be-fore the transient, subscript kj indicates the Nturned-on phasesto be turned on. Once again, the control algorithm (14)–(16)is simple and independent of the power converter parametersand operating conditions. The case of duty-cycle saturation(δkj

= δ∗FF > 1) can be easily derived following the reasoningused for (9)–(12).

Finally, the proposed analysis is based under the assumptionof steady-state operations. Under these conditions, the proposedalgorithm ensures minimum output-voltage deviation and min-imum transient time. In the case the PS is operated under themore-practical transient conditions, the proposed algorithm en-sures similar properties (i.e., minimum output-voltage deviationand minimum transient time for the PS) with respect to the out-put voltage trajectory imposed by the output-voltage controller.Other issues within the closed-loop control, for example, theadaptation of the controller parameters based on the number ofactive phases, are presented in [12] and not here discussed.

IV. RIPPLE EFFECTS ON PS INSTANT

The previous analysis refers to compensation of the averagevalues of inductor currents, thus neglecting the presence of cur-rent ripple. This section briefly discusses the determination ofthe best instant for the start up of the PS and the strategy for

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Fig. 6. Start-up instant and PWM resynchronization (with N = 2). (a) TurnOFF of phase 2. (b) and (c) Turn ON of phase 2 with PS ending when inductorcurrent reaches half of the total current iLT (case b) or ending after an integernumber of half-switching period (case c).

PWM resynchronization after the nonlinear control action, soas to minimize the effect of the current ripple.

A. PS Start-Up Instant

First, consider the case, where there are two phases (N = 2).The signals are thus shifted of 180◦ to obtain the interleavedmodulation. In order to minimize the ripple effect, the PS isstarted when the total current value is equal to its average valuethat is in the middle of TON or TOFF interval, where the twoinductor currents are equal to half the total load current. Inorder to verify the effect of this provision, simulation analysisusing the parameters of the experimental prototype has beendeveloped. For example, Fig. 6(a) reports the turn OFF of onephase, and using this approach, the total current iLT presents anegligible variation on its average value, being the increase ofthe current ripple the only evident variation of iLT in Fig. 6(a),and thus, the minimum variation on the output voltage. Theoutput-voltage deviation, not present in Fig. 6, can be inferredfrom the variation of the inductor current with respect to itsaverage value.

In the case of the turn ON of one phase, the starting point is stillat the middle of TON or TOFF interval, i.e., when the total currentiLT has its average value. Since the same carrier is chosenduring the PS, the middle of TON interval is chosen to suddenlyswitch on the phase to be activated (phase 2 in Fig. 6(b), whichis thus subject to a duty cycle double with respect to steady-stateconditions).

The transition ends when the current of the activated phaseexceeds half of the total current iLT . The synchronization carriersignal is performed at the end of the transition to restore theinterleaved operation.

B. PWM Resynchronization After PS

Through simulations, two techniques have been comparedwith regard to PWM synchronization after PS. The first case[see Fig. 6(b)] ends suddenly when the phase current is greaterthan iLT /2, while the second [see Fig. 6(c)] waits for a numberof multiple of half-switching period to determine the duration offeedforward. As shown in Fig. 6(b) and (c), the second case pro-vides a better compensation for the current iLT , at the expenseof a less precise current sharing after PS. The first case providesa variation on the average value of iLT , thus a larger output-voltage deviation, but better current sharing after the transient.Moreover, for the second case, the determination of the numberof half-switching period is based on converter parameters andload current level, and thus, these values need to be stored ina lookup table, thus making the whole implementation morecomplex.

V. EXPERIMENTAL RESULTS

The proposed control has been tested on a four-phase syn-chronous buck converter prototype with the following pa-rameters: Vin = 5 − 12 V, Vo ref = 1.1 V, L = 1 µH, C =2.2 mF (OSCON) + 100 µF (ceramic), fsw = 200 kHz, andADC resolution = 2 mV. The digital control algorithm has been

2246 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 9, SEPTEMBER 2010

Fig. 7. Photograph of the experimental prototype (four-phase multiphase buckconverter).

Fig. 8. Measured main waveforms during PS with (a) minimum time controllerand (b) PID controller. Output voltage (vo : 20 mV/div) and inductor currents(iL 1 and iL 2 : 2.5 A/div) turning off one phase, when two are active (time:20 µs/div).

Fig. 9. Measured main waveforms during PS with minimum time controller.Output voltage (vo : 20 mV/div) and inductor currents (iL 1 and iL 2 : 2.5 A/div)turning off one phase, when three are active (time: 20 µs/div).

Fig. 10. Measured main waveforms during PS with minimum time controller.Output voltage (vo : 20 mV/div) and inductor currents (iL 1 and iL 2 : 2.5 A/div)turning on one phase, when two are active (time: 20 µs/div).

implemented in a field-programmable gate array (FPGA). Aphotograph of the experimental prototype is reported in Fig. 7.

Fig. 8(a) shows the turn OFF of one phase when two are activewith the proposed controller. It is worth to point out that thesystem reaches the nominal conditions in minimum time andwithout any appreciable variations on the output voltage. As acomparison, Fig. 8(b) shows the transient due to the PS whenthe proposed action is disabled and the nominal conditions areobtained only with the PID controller. As shown in Fig. 8(b), thetransient time is much longer and the output voltage deviationis more than 40 mV.

Figs. 9 and 10 show the proposed controller during the turningoff of one phase, when three are active and the turning on ofone phase, when two are active. In both cases, the transient isexcellent and close to the theoretical expectations. However,it should be noted that in all reported cases, especially in the

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case of phase turn-ON, there is a small output-voltage deviation,which is mainly due to a set of nonidealities in our prototype,such as the drop of the input voltage during the transient, theresistive losses, driving delays, etc., which were not taken intoaccount in the theoretical analysis. One of the most relevant caseis related to the need of precharge the boost–strap capacitor ofthe high-side driver when a phase needs to be turned on. Infact, as can be seen in Fig. 10, the low-side switch of phase3 is first turned on for a small time interval (inducing a smallnegative current in phase 3), and then, the transient is startedas expected. Even if this delay could be taken into account inour calculation, its effect is limited within other converter andcontrol nonidealities, and the control algorithm was not adjustedto compensate for it.

VI. CONCLUSION

This letter has investigated a digital time-optimal controllerfor the PS in multiphase buck converters. The proposed approachminimizes the transient time for the PS and the output-voltagedeviations. The time-optimal controller is obtained through afeedforward action undertaken as soon as the PS command isreceived. The algorithm is very simple and it does not rely on thepower stage parameters, but only on the steady-state duty cycleand the number of phases to be turned on and off. Experimentaltests on a synchronous buck converter prototype, where thedigital controller is implemented in FPGA, have shown a goodagreement with the theoretical expectations.

ACKNOWLEDGMENT

The authors would like to thank Dr. M. Pelizzer andW. Cerrato for their valuable contribution in the experimentalsetup.

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