tb3155 multiphase interleaved pwm controller with diode...

TB3155Multiphase Interleaved PWM Controller with Diode

Emulation Using 8-Bit PIC® Microcontrollers

INTRODUCTION

This technical brief covers a method of realizing amultiphase PWM controller based on Microchip’s 8-bitPIC® microcontrollers.

This can be achieved by using specific and freelyconfigurable Core Independent Peripherals (CIP)found in 8-bit microcontroller devices. Different SwitchMode Power Supply (SMPS) topologies requiredifferent configurations of the peripherals. The digitalPWM modules (CCP or PWM) and ComplementaryOutput Generators (COG) are used to generate therequired PWM output waveforms for various switchconfigurations. Peripheral blocks like OperationalAmplifiers (OPA), Programmable Ramp Generators(PRG) and Analog High-Speed Comparators (CMP)are used to establish independent, analog feedbackloops supporting Voltage mode, Peak and AverageCurrent mode. There are also additional glue-logicperipheral blocks like the Configurable Logic Cell(CLC) or the Digital Signal Modulator (DSM), whichallows the designer to combine signals for solvingspecific design challenges or dealing with complexFault and operating conditions. Thus, the 8-bit MCUdevices with CIPs are ideally suited to drive and controlsingle and multistage buck/forward, boost and buckboost-type of converters running in fixed and variousvariable frequency modes, as well as single andmultiphase configurations.

This technical brief introduces the required peripheralassembly and configuration to drive and control a fixed-frequency, Peak Current mode controlled, synchronousmultiphase boost converter topology with diodeemulation as best practice example for this and similarmultiphase implementations.

MULTIPHASE INTERLEAVED PWM OPERATION

Multiphase configurations of power converters areoften used to split up currents between multiple,identical, paralleled topologies to achieve system-levelsize, filtering and efficiency optimization. The individualphases share the same input and output and theirindividual switching timing is usually phase-shifted by360°/n (where n = number of phases).

For a two-phase interleaved synchronous boostconverter, the two PWM signals are operated 180° outof phase with each other. The converter operates inPeak Current mode control with one common, outervoltage loop that provides the control reference to twoindependent, inner peak current loops. Proper currentbalancing between the phases, short circuit protectionand low variations during transitions betweenContinuous and Discontinuous Conduction mode areachieved.

For synchronous rectification, additional measures areneeded to prevent currents from flowing back into theinput when the inductor stops discharging duringDiscontinuous Conduction mode. The high-sidesynchronous rectifying switch must be turned off duringthe time the inductor current is zero. This technique ofemulating the function of a diode is called diodeemulation.

TWO-PHASE INTERLEAVED SYNCHRONOUS BOOST CONTROLLER

Figure 1 shows the proposed two-phase interleavedboost converter with synchronous rectification. Theinternal block diagram of the microcontroller showshow the CIPs can be configured and tied together toform the interleaved boost controller.

Author: June Anthony AsistioFranz ThalheimerMicrochip Technology Inc.

2017-2018 Microchip Technology Inc. DS90003155B-page 1

TB3155

FIGURE 1: TWO-PHASE INTERLEAVED SYNCHRONOUS BOOST CONVERTER AND CONTROLLER

MICROCONTROLLER SELECTION

A PIC16F1769 was selected as it contains all of theperipherals required to realize this topology. Figure 2shows the pin assignments for the PIC16F1769functioning as the Interleaved Synchronous BoostController.

FIGURE 2: PIN ASSIGNMENTS FOR THE INTERLEAVED SYNCHRONOUS BOOST CONTROLLER

RECOMMENDED DESIGN TOOLS

The MPLAB® Code Configurator (MCC) plug-in forMPLAB X IDE can be used to set up the peripherals ofthe 8-bit microcontroller to operate as the controller forthe interleaved synchronous boost converter. This canbe done by setting up peripherals one at a time throughMCC and connecting them together as shown in theinternal block diagram in Figure 1.

MPLAB X projects that are used in this technical briefcan be downloaded from www.microchip.com. Thecomplete list can be found in Appendix A: “MPLAB XProject Files”.

PWM5

DAC1

VIN

VOUT

ADC

PIC16F1769

C2IN1‐C1N1‐

C2IN0+C1IN1+ C4IN0‐ OPA1OUT OPA1IN0‐AN8 CLC2OUTCOG2A

14151618109117658

CMP3+

_

CMP1

+

_

CLC1

CLC1OUT C3IN3‐

PRG1FS

OUT IN

OPA1+

_

13

COG1RS

FS B

A

COG2RS

FS B

A

CLC2

CMP2

+

_

CMP4

+

_

PRG2FS

OUT IN

COG1A

PWM6

RC5RC6 RC4 RC1RC7RC3 RB6 RB7 RA1 RC0 RC2 RB4

(slave)(master)

OF5_MATCH OF5_MATCH

PHASE A PHASE B

RA5

RA4

MCLR/RA3

COG1A/RC5

CLC1OUT/RC4

C3IN3-/RC3

AN8/RC6

COG2A/RC7

CLC2OUT/RB7

RA2

RC0/C2IN0+

RC1/C2IN1-/C1IN1-

RC2/OPA1OUT

RB4/OPA1IN0-

RB5

RB6/C1IN1+

PIC16F1769

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

RA1/C4IN0-

RA0

VSSVDD

DS90003155B-page 2 2017-2018 Microchip Technology Inc.

www.microchip.com

www.microchip.com

TB3155

DESIGNING THE TWO-PHASE INTERLEAVED SYNCHRONOUS BOOST CONTROLLER

Establishing the Switching Cell

The two-phase PWM signals can be generated byusing the PWM5 and PWM6 module. Each moduleoperates on the same frequency and a fixed duty cycle;the only difference is that the leading edge of thePWM6 signal is delayed by 180° to the leading edge ofthe PWM5 signal.

For illustration purposes, PWM5 and PWM6 can beconfigured for a switching frequency of 200 kHz, with amaximum duty cycle of 40%. The 180° phase delay ofPWM6 from PWM5 can be implemented by operatingPWM6 on one-shot Slave Run mode, its trigger comingfrom OF5_match. OF5_match is the offset time eventcoming from the master PWM5, set at 2.5us. ThesePWM MCC settings are found in Appendix B: “MCCSettings” of this document.

Figure 3 shows the waveforms of PWM5OUT andPWM6OUT as monitored from RA2 and RB5,respectively.

FIGURE 3: PWM5OUT AND PWM6OUT SIGNALS

Adding Diode Emulation

Diode emulation is achieved by feeding thecomplementary output COGxB of the COG peripheralto a two-input AND logic CLC. The other input of theAND logic is tied to the output of the comparator thatdetects if the high-side synchronous switch has alreadyentered zero current. The inputs of the comparator aretied across the switch. In this way, the zero currentcondition is monitored and the switch is turned offduring zero current.

Simulating the Diode Emulation

To simulate this scenario, the test set-up shown inFigure 4 can be implemented. PWM5 is configured toproduce a square wave with 50% duty and 200 kHzfrequency. An RC integrator is connected to the output,COG1A. This produces a sawtooth waveform thatsimulates the inductor switch current. It is synchronizedwith COG1A and the sawtooth signal is injected to theinput, C1IN1-, of the comparator. The DAC1OUT levelis used to simulate the zero level of the current. TheDAC1OUT is connected to the C1IN+ input. Wheneverthe sawtooth waveform touches the DAC1OUT level,the output of CMP1 is low. CLC1OUT remains lowduring the Discontinuous mode (DCM), this achievesdiode emulation.

FIGURE 4: TEST SET-UP FOR SIMULATING THE DIODE EMULATION

The results for simulating the diode emulation at DCMcan be seen in Figure 5. In an actual application, thesynchronous switch is controlled by CLC1OUT whilethe PWM switch is controlled by COG1A.

FIGURE 5: SIMULATING DIODE EMULATION AND DISCONTINUOUS CONDUCTION MODE

1n

1k

PIC16F1769

RC4

RA0

RC1

RC5

C1IN1‐

CLC1OUT

COG1A

DAC1OUT2V

CLC1

COG1RS

FS B

APWM5 5

6

CMP1+

_

DAC1

15

19


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Be aware that an overlap may happen during the rising time of the COG1A and the falling time of the CLC1OUT1. This must be prevented in an actual application, since this means that both the PWM switch and the synchronous switch are both conducting at this short overlap. The same is true during the falling time of the COG1A and the rising time of the CLC1OUT; this overlap may occur.

A dead time must be added to the rising event andfalling event of the COG1 to ensure that this shortconduction time does not take place. The overlap canbe checked by simulating the Conduction mode (CCM),measuring the overlap gap between the rising ofCOG1A and falling of CLC1OUT. Figure 6 shows theamount of overlap time to be 110 ns.

FIGURE 6: MEASURING THE OVERLAP ON COG1OUT AND CLC1OUT

The effect of adding a 110 ns dead time to the risingevent and falling event of the COG can be observed inFigure 7 and Figure 8.

FIGURE 7: DEAD TIME ADDED ON THE RISING EVENT OF COG1

FIGURE 8: DEAD TIME ADDED ON THE FALLING EVENT OF COG1

Establishing the Feedback Loop

In Figure 1, the feedback loop is created by samplingthe output voltage and feeding it to an error amplifierOPA1. The error amplifier has a reference voltage thatis set by DAC1. The amount of error voltage betweenthe output voltage and the reference voltage iscompensated by using a Type 2 compensator.

Closing the Loop

The error voltage is fed to the current comparators,CMP3 and CMP4. Each comparator compares theerror voltage with the PWM switch currents from eachphase. For stability, slope compensation is added tothe error voltage by using PRG1 and PRG2, before it isfed to the comparators.

OTHER MULTIPHASE PWM CONTROLLER CONFIGURATIONS

Different SMPS topologies require different modifications to the controller design. The configuration of the peripherals for different Multiphase SMPS Topologies is discussed below. For additional information about the SMPS topology theory and design, refer to AN1114, Switch Mode Power Supply (SMPS) Topologies (Part I) (DS01114), and AN1207, Switch Mode Power Supply (SMPS) Topologies (Part II) (DS01207).

Two-Phase Interleaved Boost Controller

If the interleaved boost topology does not includesynchronous rectification, the peripheral configurationis simplified by removing CMP1-CLC1 and CMP2-CLC2 for the diode emulation; there is no longer theneed to generate the COG1B and COG2B outputs.See Figure 9.


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FIGURE 9: TWO-PHASE INTERLEAVED BOOST CONVERTER AND CONTROLLER

PWM5

DAC1

VIN

VOUT

ADC

PIC16F1769

C4IN0‐ OPA1OUT OPA1IN0‐AN8 COG2A

14189758

CMP3+

_

C3IN3‐

PRG1FS

OUT IN

OPA1+

_

13

COG1RS

FS

A

COG2RS

FS

A

CMP4+

_

PRG2FS

OUT IN

COG1A

PWM6

RC5RC6 RC7RC3 RA1 RC2 RB4

(slave)(master)

OF5_MATCH OF5_MATCH


TB3155

Two-Phase Interleaved Synchronous Buck Controller

Figure 10 shows how to configure a PIC16microcontroller as a Two-Phase InterleavedSynchronous Buck Controller.

FIGURE 10: TWO-PHASE INTERLEAVED SYNCHRONOUS BUCK CONVERTER AND CONTROLLER

PWM5

DAC1

VIN

VOUT

ADC

PIC16F1769

C1IN1+ OPA1OUT OPA1IN0‐AN8

1411 7658

CMP3+

_

CMP1

+

_

CLC1

CLC1OUT C3IN3‐

PRG1FS

OUT IN

OPA1+

_

13

COG1RS

FS B

A

COG1A

RC5RC6 RC4 RC3RB6 RC2 RB4

(master)

OF5_MATCH

PWM6

CMP4

+

_

CMP2

+

_

CLC2

PRG2FS

OUT IN

COG2RS

FS B

A

(slave)

OF5_MATCH

COG2A

9

RC7

CLC2OUT

10RB7

C2IN0+

16RC0 RA1

C4IN0‐

18


TB3155

Two-Phase Interleaved Flyback Converter Controller

Figure 11 shows how to configure a PIC16microcontroller as a Two-Phase Interleaved FlybackController. OPA1 is set as unity gain amplifier and it isoptional. The collector can be tied directly to PRG1IN0and PRG2IN1 through RC2.

FIGURE 11: TWO-PHASE INTERLEAVED FLYBACK CONVERTER AND CONTROLLER

PWM5

VIN

VOUT

ADC

PIC16F1769

C4IN0‐AN8 COG2A

189758

CMP3+

_

C3IN3‐

PRG1FS

OUT IN

OPA1+

_COG1RS

FS

A

COG1A

RC5RC6 RC7RC3 RA1

(master)

OF5_MATCH

PWM6

CMP4+

_

`

PRG2FS

OUT IN

COG2RS

FS

A(slave)

OF5_MATCH

OPA1IN0+RB5

12

VDD


TB3155

Two-Phase Interleaved Forward Controller

Figure 12 shows how to configure a PIC16microcontroller as a Two-Phase Interleaved ForwardController. OPA1 is set as unity gain amplifier and it isoptional. The collector can be tied directly to PRG1IN0and PRG2IN1 through RC2.

FIGURE 12: TWO-PHASE INTERLEAVED FORWARD CONVERTER AND CONTROLLER

CONCLUSION

This technical brief discusses the capabilities ofMicrochip’s 8-bit PIC microcontrollers for multiphasePWM operation and how diode emulation can beimplemented on the 8-bit MCU, a feature needed forconverters that use synchronous rectifiers. It alsoshows that the design of a Multiphase InterleavedPWM Controller varies with the complexity of theSMPS topology of choice.

PWM5

VIN

VOUT

ADC

PIC16F1769

C4IN0‐AN8 COG2A

189758

CMP3+

_

C3IN3‐

PRG1FS

OUT IN

OPA1

+

_COG1RS

FS

A

COG1A

RC5RC6 RC7RC3 RA1

(master)

OF5_MATCH

PWM6

CMP4+

_

`

PRG2FS

OUT IN

COG2RS

FS

A

(slave)

OF5_MATCH

OPA1IN0+RB5

12

VDD


TB3155

APPENDIX A: MPLAB X PROJECT FILES

MCC configuration files for this technical brief areavailable for download at Microchip’s website:

(http://www.microchip.com).

DESCRIPTION FILE NAME

1. 2-Phase Interleaved Synchronous Boost Controller Project File (Figure 1 and Figure 2)

2PhIntrlvSyncBoost-PIC16F1769.x

2. Diode Emulation Test Peripheral Project File (Figure 4) DiodeEmuTest-PIC16F1769.x


http://www.microchip.com

TB3155

APPENDIX B: MCC SETTINGS

FIGURE B-1: PWM5 AND PWM6 SETTINGS FOR FREQUENCY, DUTY CYCLE AND PHASE

FIGURE B-2: COG1 SETTINGS


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FIGURE B-3: PRG SETTINGS FOR SLOPE COMPENSATION

FIGURE B-4: OPA1 SETTINGS


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FIGURE B-5: DAC1 SETTINGS FOR VOLTAGE REFERENCE

FIGURE B-6: CMP SETTINGS


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ISBN: 978-1-5224-2930-2

DS90003155B-page 13


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