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July 2013

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Digital Logic Chapter (2):

Intorduction to Logic Circutis

Chapter (3):

Implementation Technology

Chapter (4):

Otimized Implement Mentation of Logic Function

Chapter (5):

Number Representation & Arithmetic Circuit

Chapter (6):

Combinational-Circuit Building Blocks

Chapter (7):

Flip-Flops, Registers, and Counters

،مذكرات شرح وتمارين محلولة

سابقة للعديد من المواد أدناه امتحانات

الموقعين المذكورين أدناه متاحة مجاناً على

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Chapter

2 INTRODUCTION TO LOGIC CIRCUITS

إن لم تثق بنفسك

فمن يمكن أن يثق بك


من المواد أدناه سابقة للعديد امتحانات

الموقعين المذكورين متاحة مجانًا على


من المواد أدناه سابقة للعديد امتحانات

المذكورينالموقعين متاحة مجانًا على


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2.4 Logic Gates and Networks

Gate Symbol Inputs Output Truth Table

Output

AND •

0 0 0

0 1 0

1 0 0

1 1 1

. . .

Any

0 0

All

1 1

OR +

0 0 0

0 1 1

1 0 1

1 1 1

. . .

All

0 0

Any

1 1

NOT −

0 1

1 0


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Example 1:

Given the logic network shown in the figure below, find the following:

I. (the output expression).

II. Truth table for the logic function .

III. Timing diagram for the logic function .

Solution:

I :

1- Name the output of each gate and show its logic symbol:

2- Write the output ( ) in terms of output names, expand it to reach the inputs. (moving

from outputs to inputs)

= C + D

( A · ) + ( B · )

(( ) · ) + (( ) · )

= ( · ) + ( · )

: تتأرجح نفوسنا بين صوتين

(يجب أن تفعل)من خارج أنفسنا يقول أحدهما

(يجب أال تفعل)من داخلنا يقول واآلخر

شعورنا سيئا مهما كان األمر الذي سنفعله ويكون


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II :

1- From part ( I ) above, = ( · ) + ( · ), means = 1 when either C or D is

equal to 1 (review OR gate truth table).

Expanding C and D:

C = 1: when , and

D = 1: when , and

(review AND gate truth table).

The rest of the possible input values give 0’s by default.

2- Fill-in all possible combination inputs in the truth table as follows, and then the outputs

are deduced from the previous step :

(Notice: #Rows = 2#inputs

)

.

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

III :

Copy-paste from the truth table to the timing diagram as follows:

1

0

1

0

1

0

1

0

أن تقول ذلك ينبغيعندما ( ال)تعلم قول


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2.5 Boolean Algebra

Axioms of Boolean

Algebra Single-Variable Theorems

1a. 0 · 0 = 0

1b. 1 + 1 = 1

2a. 1 · 1 = 1

2b. 0 + 0 = 0

3a. 0 · 1 = 1 · 0 = 0

3b. 1 + 0 = 0 + 1 = 1

4a.

4b.

5a.

5b.

6a.

6b.

7a.

7b.

8a.

8b.

9.

Duality (ازدواجية الخصائص)

replace each with + and vice versa

and replace each 0 with 1 and vice versa

To convert Logic Expression Dual Logic Expression

(Notice that any ‘a’ is a dual of ‘b’ below it and vice versa)

Two- or Three-Variables Properties.

10a.

10b.

Commutative تبادلي

11a.

11b.

Associative تجميعي

12a.

12b.

Distributive توزيعي

13a.

13b.

Absorption امتصاص

14a.

14b.

Combining مزج

15a.

15b.

DeMorgan’s

theorem

16a.

16b.

17a. 17b.

Consensus إجماع

تخلص من االعتقاد الفاسد

تك محدودةابأن إمكان


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Example 2 (exercise 2.1 - 2nd

ed):

Use algebraic manipulation to prove that:

).

Note that this is the distributive rule, as stated in identity 12b in section 2.5.

Solution:

Starting with Right Hand Side:

Why choose RHS?

Has more manipulations than LHS.

= Using 12a (left to right) to

distribute the left parentheses over

the right one

= Using 12a (left to right) again for

each small parentheses

= Using 7a (

= Take out as a common factor

from all terms containing

= = 1

(OR gate = 1, when any input = 1)

= Using 6a,

= LHS

توقع السعادة أو التعاسة فستحصل حتما

على القدر الكافي حسب قوة اعتقادك


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Example 3 (example 2.2 - 2nd

ed):

Validate the following expression:

Solution:

In this example, since both sides have approximately equivalent amount of

manipulations, we can try to simplify both sides.

Using 10b to exchange places of

2nd

and 3rd

terms.

= Using 12a (right to left) to take out

as a common factor from 1st &

2nd

terms; and from 3rd

and 4th

.

= Using 8b,

= … ( * ) Using 6a,

= Using 12a (right to left) to take out

as a common factor from 2nd

&

3rd

terms.

= Using 8b and

6a for the 2nd

term.

= … ( * ) Using 16a,

both sides are equivalent after simplifying.

ل اآلن ــن األفضــإن لم تك

فثق أن األمر مسألة وقت


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Example 4 (2.7 - 2nd

ed): Validate the following expressions:

(a)

Solution - Using truth table:

Idea: We may construct a truth table for each side of the expression (LHS & RHS). If the truth tables are

identical, then the expression is valid.

1- Since each side of the expression is an OR function (4-inputs), then it’s easier to find when the output =

1 (OR gate = 1, when any term = 1). The rest of the possible input values give 0’s by default.

+ +

0 0/1 1 OR 1 1 0 OR 0 1 0/1 OR 1 0 0/1

A B C D

For each term, recall AND truth table:

Output = 1 when All inputs = 1

+ +

0/1 0 1 OR 1 0/1 0 OR 0/1 1 0 OR 0 1 1

E F G H

0 0 0 0 0

0 0 1 A 1 E 1

0 1 0 C 1 G 1

0 1 1 A, C 1 H 1

1 0 0 D 1 F 1

1 0 1 D 1 E 1

1 1 0 B 1 F, G 1

1 1 1 0 0

LHS = RHS Valid

Since is missing, then

its value could be 0 or 1.


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ed): Validate the following expressions:

(c)

Solution - Using truth table:

Idea: We need to construct a truth table for each side of the expression (LHS & RHS). If the

truth tables are identical, then the expression is valid.

2- Since each side of the expression is an AND function (3-inputs), then it’s easier to find

when the output = 0 (AND gate = 0, when any term = 0). The rest of the possible input

values gives 1’s by default.

)

0 0/1 0 AND 1 1 1 AND 1 0 0/1

A B C

For each parenthesis, recall OR truth table:

Output = 0 when All inputs = 0

+

0 0 0/1 AND 0/1 0 0 AND 1 0/1 1

D E F

0 0 0 A 0 D, E 0

0 0 1 1 D 0

0 1 0 A 0 1

0 1 1 1 1

1 0 0 C 0 E 0

1 0 1 C 0 F 0

1 1 0 1 1

1 1 1 B 0 F 0

LHS RHS Not Valid

Since is missing, then

it value could be 0 or 1.


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2.6 Functions Synthesis (Using AND, OR, NOT Gates)

Row# Minterm (Force to 1,

then product the inputs)

Maxterm (Force to 0,

then Sum the inputs)

(e.g.)

0 0 0 0 1

1 0 0 1 1

2 0 1 0 0

3 0 1 1 0

4 1 0 0 0

5 1 0 1 1

6 1 1 0 1

7 1 1 1 0

Let n = #inputs,

then #Rows = 2#inputs

Let be a function of variables, then can be represented in the canonical form as Sum-of-

Products (SOP), or as Product-of-Sums (POS) as follows:

=

=

= =

=

=

=

= =

=

إن ثقتك بنفسك وراحة قلبك أكثر أهمية من

نظرة الناس لك ومن كل فروض العالم


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Example 6:

Given the truth table below, write the expression of as the following:

a. Sum-of-products.

b. Product-of-sums.

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

Solution:

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

=

=

=

=

أن تضيء شمعة صغيرة

خير لك من أن تنفق

عمرك تلعن الظالم


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ed):

Use algebraic manipulation to show that for three input variables and

Solution:

Which is Sum-of-Products

=

Writing the minterms from 1 to 7.

=

Comparing both sides of the expression,

we need to gather the terms that have

and take as a common factor from those

terms. Do the same for and . Note: the same term can be used more than

once if you use 7a. ( from right to

left.

=

Using 12a to factor out common terms.

=

Using 8b, to reduce

the small parenthesizes

into 1.

=

Using 6a .

=

Using 8b and 6a again for the

parenthesis.

=

إذا لممم تعمممل شمميئا تيممر اسممتثنائي

فلن تحصل إال على الشيء العادي


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ed):

Use algebraic manipulation to find the minimum product-of-sums

expression for the function :

Solution:

Let’s see the truth table for more insight into the question:

Sum#

0 0 0 0 0 0 1st

1 0 0 0 1 1

2 0 0 1 0 1

3 0 0 1 1 1

4 0 1 0 0 0 1st, 2

nd

5 0 1 0 1 0 2nd

6 0 1 1 0 0 3rd

7 0 1 1 1 1

.

.

.

.

.

.

.

.

.

.

.

.

15 1 1 1 1 1

=

=

In order to minimize the 3rd

sum, we need to add row# 4 as

4 terms into the expression

(row# 4 2nd

sum)

=

Using 14b

= Using 8a and 6b.


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2.7 NAND, NOR Logic Networks

Gate Symbol Inputs Output Truth Table

NAND

=

Output

0 0 1

0 1 1

1 0 1

1 1 0

NOR

=

Output

0 0 1

0 1 0

1 0 0

1 1 0


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ed):

Implement the function in the figure below using only NAND gates:

Solution:

جميل أن يموت اإلنسان

من أجل وطنه، وأجمل

من ذلك أن يعيش ألجله


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ed):

Implement the function in the figure below using only NOR gates:

Solution:

أن تغير طريقك ال بأس أبدًا

درجة متى 082بمقدار

كنت أنت مقتنعا بذلك


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2.8 Design Examples

(Multiplexer Circuit)

Figure 1: Multiplexer Circuit

“0-to-0 multiplexer”

Figure 2: Multiplexer Truth Table

0

0

0

0

0 0 0

0 1 0

1 0 1

1 1 1

1

1

1

1

0 0 0

0 1 1

1 0 0

1 1 1

Figure 3: Multiplexer Graphical symbol

Figure 4: Compact truth-table representation

.

0

1

اآلن، أنممت أيممن يهممم ال

أيممن إلممى المهممم ولكممن

اللحظة هذه في تتجه


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ed): Design the simplest circuit that has four inputs, which

produces an output value of 1 whenever three or more of the input variables

have value 1; otherwise, the output has to be 0.

Solution:

1. Fill-in all possible combination inputs in the truth table. Assign 1 as an output for all

combinations with three or more inputs equal to 1. Otherwise assign 0.

Term#

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 1 1st

1 0 0 0 0 1 0 0 1 0

1 0 1 0 0 1 0 1 1 1 2

nd

1 1 0 0 0 1 1 0 1 1 3

rd

1 1 1 0 1 4th

1 1 1 1 1 5

th

لديك نقاط قوة يمكن أن

تسرع بك للوصول للقمة

تعرف عليها . . .


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2. Use Sum-of-products since the 1’s are less than 0’s.

=

Minimizing:

Let’s try to move from 4 to 3 variables per term. To do so, we need to find each

term’s differ-by-one couple term ( . From the truth table we notice:

- 1st and 5

th differ by , which results: = .

- 2nd

and 5th

differ by , which results: = .

- 3rd

and 5th differ by , which results: = .

- 4th

and 5th differ by , which results: = .

Note: the same 5th term can be used more than once if you use 7a. ( from right to left.

=

+

+

+

=

+

=

=

تمشممممى أن األفضممممل مممممن

أن مممن األمممام إلممى بممب ء

الخلف إلى مسرعًا تمشى


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2.9 Introduction to CAD Tools (Introduction to Verilog Code)

Example A

Verilog

Specification

Str

uct

ura

l

(gat

e le

vel

pri

mit

ives

)

module exampleA (x1, x2, x3, f);

input x1, x2, x3;

output f;

not (a, x1);

and (b, x2, x3);

or (f, a, b);

endmodule

module moduleName (input & output list);

input inputs list;

output outputs list;

not (output, input);

and (output, inputs list);

or (output, inputs list);

endmodule

Con

tin

uou

s A

ssig

nm

ent

(logic

expre

ssio

ns)


input x1, x2, x3;

output f;

assign f = ~x1 | (x2 & x3);

endmodule

~ NOT

assign LHS = RHS:

means continuous assignment

for the signal LHS (i.e f ).

Whenever any signal on RHS

changes its state, the value at

LHS will be re-evaluated.

| OR

& AND

Alw

ays

(pro

cedu

ral

stat

emen

ts)


input x1, x2, x3;

output f;

reg f;

always @ (x1, x2, x3)

f = ~x1 | (x2 & x3);

endmodule

always @ (sensitivity list):

The statements inside an always block are

executed by the simulator only when one or more

of the signals (i.e. x1, x2, x3) in the sensitivity list

changes values.

Any assigned signal (e.g f ) using always must be

declared as a variable using the keyword reg.


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Example B

Verilog

Specification

Str

uct

ura

l

(gat

e le

vel

pri

mit

ives

)

module exampleB (x1, x2, x3, f);

input x1, x2, x3;

output f;

not (notx1, x1);

not (notx2, x2);

not (notx3, x3);

and (a, notx1, notx2, x3);

and (b, notx1, x2, notx3);

and (c, x1, notx2, notx3);

and (d, x1, x2, x3);

or (f, a, b, c, d);

endmodule

Con

tin

uou

s A

ssig

nm

ent

(logic

expre

ssio

ns)


input x1, x2, x3;

output f;

assign f = (~x1 & ~x2 & x3) |

(~x1 & x2 & ~x3) |

(x1 & ~x2 & ~x3) |

(x1 & x2 & x3);

endmodule

Alw

ays

(pro

cedu

ral

stat

emen

ts)


input x1, x2, x3;

output reg f;

always @ (x1, x2, x3)

assign f = (~x1 & ~x2 & x3) |

(~x1 & x2 & ~x3) |

(x1 & ~x2 & ~x3) |

(x1 & x2 & x3);

endmodule

من ضمن فاتورة النجاح بعض

خرالخسائر الطفيفة من حين آل


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Example C: (Using if…else)

Implement the above circuit using if…else procedural statements.

Solution:

Note: if…else can only be used inside always block.

module exampleC(s, x1, x2, f);

input s, x1, x2;

output reg f;

always @ (s, x1, x2)

if (s == 1) f = x2;

else f = x1;

endmodule

Other Solution: (using conditional operator (…. ? … : …) )

module exampleC(s, x1, x2, f);

input s, x1, x2;

output reg f;

always @ (s, x1, x2) f = (s==1? X2 : x1);

endmodule

مهما قدمت لألسد من طعام

فإنه يظل يحن إلى الغابة


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Example 11 (modified 2.50 - 2nd

ed): (a) Write Verilog code to describe the following functions

(b) Use algebraic manipulation to prove that

Solution:

module prob2_50(x1, x2, x3, x4, f1, f2);

input x1, x2, x3, x4;

output f1, f2;

assign f1 = (x1 & ~x3) | (x2 & ~x3) | (~x3 & ~x4) | (x1 & x2) | (x1 & ~x4);

assign f2 = (x1 | ~x3) & (x1 | x2 | ~x4) & (x2 | ~x3 | ~x4);

endmodule

Term# Term#

0 0 0 0 1 3rd

1

0 0 0 1 0 0 2nd

0 0 1 0 0 0 1st

0 0 1 1 0 0 All terms

0 1 0 0 1 2nd

, 3rd

1

0 1 0 1 1 2nd

1

0 1 1 0 0 0 1st

0 1 1 1 0 0 1st

1 0 0 0 1 1st, 3

rd, 5

th 1

1 0 0 1 1 1st 1

1 0 1 0 1 5th 1

1 0 1 1 0 0 3rd

1 1 0 0 1 All terms 1

1 1 0 1 1 1st, 2

nd, 4

th 1

1 1 1 0 1 4th, 5

th 1

1 1 1 1 1 4th 1

From the truth table, .

♣ وما نيل المطالب بالتمني

اــا تالبـدنيــذ الـؤخـولكن ت


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