digital design - combinational logic design chapter 2 - combinational logic design
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Digital Design - Combinational Logic Design
Chapter 2 - Combinational Logic Design
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Digital DesignCombinational Logic Design
Figure 2.1 Motion-in-the-dark-detector system: (a) system block diagram, (b) implementation using a microprocessor, (c)
implementation using a custom digital circuit.
Motionsensor
sensorLight
Detectora
b
F
Lamp
Detectora
b
F
Detectora
b
FI0
I1
P0uProc.
(a) (b) (c)
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Digital DesignCombinational Logic Design
9V battery connected to light bulb
+- 9V
2 ohms
4.5 A
9 V0 V
4.5
A
Ohms Law
V = IRI = V/R
I = 9V/2 Ohms I = 4.5 A
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Digital DesignCombinational Logic Design
The evolution of switches: • Relays (1930s)• Vacuum tubes (1940s)• Discrete transistors (1950s)• Integrated circuit (IC) containing transistors (1960s--present).
IC’s originally held about ten transistors; now they can hold almost one billion.
ICt ra n si st or
t u bere la y
q ua r te r ( to s ee t he re la t i ve si z e )
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Digital DesignCombinational Logic Design
Figure 2.3 (b) Simple View of a Switch
output
“off”
input
control input
source
output
“on”
input
control input
source
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Digital DesignCombinational Logic Design
Figure 2.4 CMOS transistors: (left) transistor on silicon, (right top) nMOS transistor symbol with indication of conducting when gate=1, (right bottom)
pMOS transistor symbol conducts when gate=0
source drain oxide gate
silicon
A positive voltage here...
- - -
... attracts electrons here, turning the channel
between source and drain into a conductor.
IC package IC
gate 1 0
conducts does notconduct
gate 1 0
does notconduct
nMOS
pMOS
conducts
1 1
1
1
1 1
1
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Digital DesignCombinational Logic Design
Figure 2.5 CMOS transistor operation analogy -- Crossing a river may be too difficult, until just enough stepping stones are attracted into one
pathway
drain
gate
source drain
gate
source
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Digital DesignCombinational Logic Design
Figure 2.6 Having the right building blocks can make all the difference when building things.
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Digital DesignCombinational Logic Design
Figure 2.7 Basic logic gates.
x F
1
0
x01
F10
x F
x F
x
y
y0 00 11 01 1
0111
x
F
1
0
y
F
y
x
x Fy0 00 11 01 1
0001
xF
1
y
y
x
NOT OR ANDx
yF
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Digital DesignCombinational Logic Design
NOT
x
F
time
1010x F
x
F
time
10
10
y10
Behavior and Timing
OR
Fx
y
Fx
y
x
F
time
10
10
y10
AND
Logic Gate
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Digital DesignCombinational Logic Design
Figure 2.11 Seatbelt Warning Circuit
BeltWarnk
s
w
k
s
w time
1010
10
Inputs
Outputs
Figure 2.11 Timing diagram for seatbelt warning circuit
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Digital DesignCombinational Logic Design
Figure 2.13 Seatbelt warning circuit with
person sensor.
BeltWarnk
s
wp
Figure 2.14 Extended seatbelt warning circuit.
BeltWarnk
s
wp
t
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Digital DesignCombinational Logic Design
Commutative: a + b = b + a
a * b = b * a
Distributive a*(b + c) = a*b + a*c
a+(b * c) = (a+b) * (a+c)
Associative (a + b) + c = a + (b + c)
(a * b) * c = a * (b * c)
Identity 0 + a = a + 0 = a
1 * a = a * 1 = a
Complement a + a’ = 1
a * a’ = 0
Boolean Algebra – Basic Properties
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Digital DesignCombinational Logic Design
Null elements a + 1 = 1
a * 0 = 0
Idempotent Law a + a = a
a * a = a
Involution Law (a’)’ = a
DeMorgan’s Law (a + b)’ = a’b’
(ab)’ = a’ + b’
Boolean Algebra – Additional Properties
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Digital DesignCombinational Logic Design
Truth Table
Inputs Outputs
a b F
0 0 1
0 1 1
1 0 0
1 1 1
F = ab + a’
a=0 and b=0, F = 0*0 + 1 = 0 + 1 = 1a=0 and b=1, F = 0*1 + 1 = 0 + 1 = 1a=1 and b=0, F = 1*0 + 0 = 0 + 0 = 0a=1 and b=1, F = 1*1 + 0 = 1 + 0 = 1
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Digital DesignCombinational Logic Design
Even Parity for Three-bit Generator
Inputs Outputs
a b c P
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
P = a’b’c + a’bc’ + ab’c’ + abc
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Digital DesignCombinational Logic Design
Figure 2.18 Seven-segment display (left), sample numbers 0, 1 and 2 (center), and connections of inputs to segments (right)
a
b cd
e fg
abcdefg = 1110111 0010010 1011101
abcdefg
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Digital DesignCombinational Logic Design
Table 2.2 4-bit binary number to seven-segment display truth table
w x y z a b c d e f g0 0 0 0 1 1 1 0 1 1 10 0 0 1 0 0 1 0 0 1 00 0 1 0 1 0 1 1 1 0 10 0 1 1 1 0 1 1 0 1 10 1 0 0 0 1 1 1 0 1 00 1 0 1 1 1 0 1 0 1 10 1 1 0 1 1 0 1 1 1 10 1 1 1 1 0 1 0 0 1 01 0 0 0 1 1 1 1 1 1 11 0 0 1 1 1 1 1 0 1 11 0 1 0 0 0 0 0 0 0 01 0 1 1 0 0 0 0 0 0 01 1 0 0 0 0 0 0 0 0 01 1 0 1 0 0 0 0 0 0 01 1 1 0 0 0 0 0 0 0 01 1 1 1 0 0 0 0 0 0 0
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Digital DesignCombinational Logic Design
Combinational Logic Design Process
Description
Ste
p 1 Capture the
function
Create a truth table or equations, whichever is most natural for the given problem, to describe the desired behavior of the combinational logic.
Ste
p 2 Convert to
equations
This step is only necessary if you captured the function using a truth table instead of equations. Create an equation for each output by ORing all the minterms for that output. Simplify the equations if desired.
Ste
p 3
Implement as a gate-based circuit
For each output, create a circuit corresponding to the output’s equation. (Sharing gates among multiple outputs is O.K. optionally)
Step
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Digital DesignCombinational Logic Design
Three 1s pattern detector
Step 1: Capture the function
y = abc + bcd + cde + def + efg + fgh
Step 2: Convert to equations
Skip this as we have the equations.
Step 3: Implement as a gate-based circuit
bc
d
e
f
g
h
abc
bcd
cde
def
efg
fgh
y
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Digital DesignCombinational Logic Design
Step 1: Capture the function
Step 2: Convert to equations
y = a’bc + ab’c + abc’ + abc
z = a’b’c + a’bc’ + ab’c’ + abc
(# of 1s)a b c y z0 0 0 (0) 0 00 0 1 (1) 0 10 1 0 (1) 0 10 1 1 (2) 1 01 0 0 (1) 0 11 0 1 (2) 1 01 1 0 (2) 1 01 1 1 (3) 1 1
OutputsInputs
Number-of-1s counter gate-based circuit
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Digital DesignCombinational Logic Design
Number-of-1s counter gate-based circuit
abc
yabc
ab
abcabcabc
bc
a
z
Step 3: Implement as a gate-based circuit
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Digital DesignCombinational Logic Design
Figure 2.22 Sprinkler valve controller block diagram.
Micro-processor
e
zone 0zone 1
23 4
567
decoder
abc
d0d1d2d3d4d5d6d7
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Digital DesignCombinational Logic Design
Sprinkler valve controller circuit (actually a 3x8 decoder with enable)
Step 1: Capture the functiond0 = a’b’c’ed1 = a’b’ced2 = a’bc’ed3 = a’bced4 = ab’c’ed5 = ab’ced6 = abc’ed7 = abce
Step 2: Convert to equations
Skip this as we have the equations.
Step 3: Implement as a gate-based circuit
d0
d1
d2
d3
d4
d5
d6
d7
abc
e
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Digital DesignCombinational Logic Design
Figure 2.24 NAND, NOR, XOR and XNOR
x F
x
y
y0 00 11 01 1
1000
xF
1
0
y
F
y
x
x Fy0 00 11 01 1
1110
x
F
1
0
y
y
x
NORNAND
Fx
y
x Fy0 00 11 01 1
0110
XOR
x Fy0 00 11 01 1
1001
XNOR
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Digital DesignCombinational Logic Design
Figure 2.25 2x4 decoder: (a) outputs for possible input combinations, (b) internal design
d0
d1
d2
d3
i0
i1
d0
d1
d2
d3
i0
i1
d0
d1
d2
d3
i0
i1
d0
d1
d2
d3
i0
i1
0
0
0
0
0
1
0
1
1
0
0
0
1
0 1
0
0
0
1
1
0
0
0
1
i0i1
d0
d1
d2
d3
(a)
(b)
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Digital DesignCombinational Logic Design
Figure 2.26 sing a 6x64 decoder to interface a microprocessor and a column of lights for a New Year’s
Eve display
i0i1i2i3i4
e
d0d1d2d3
d58d59d60d61d62d63
5958
3
12
HappyNew Year!
Mic
ropr
oces
sor
6x64
i5
0
dcd
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Digital DesignCombinational Logic Design
Figure 2.27 A multiplexer is like a railyard switch, determining which input track connects to the single output track, according to the
switch’s control lever.
i0
i1
i2
i3
d
01 2
3control lever
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Digital DesignCombinational Logic Design
Figure 2.28 2x1 multiplexer block symbol (left), connections for s0=0 and s0=1 (middle), and internal
design (right).
i0
i1
s0
d
2x1i0
i1
s0
d
2x1
0 1
i0
i1
s0
d
2x1
s0
i0
i1
d
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Digital DesignCombinational Logic Design
Figure 2.29 4x1 multiplexer block symbol (left) and internal design (right).
i0
i1
s1
d
4x1i0
i1d
i2
i3
s0
i2
i3
s1 s0
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Digital DesignCombinational Logic Design
Figure 2.30 Mayor’s vote display system implemented using a 4x1 mux.
i0
i1
s1
d
4x1
i2
i3
s0
Pro
posa
l
1
2
3
4 LED
switches
Mayor’s switches
Red
on/off
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Digital DesignCombinational Logic Design
Figure 2.31 Four 2x1 muxes for selecting among 4-bit data items A or B (left), and a simpler way to represent the same component using a 4-bit 2x1 mux
component (right).
i0i1 s0
d2x1
i0i1 s0
d2x1
i0i1 s0
d2x1
i0i1 s0
d2x1
a3
a2
a1
a0
b3
b2
b1
b0
s0
c3
c2
c1
c0
i0
i1
A
B
4-bit2x1
d C
s0
4
44
33
TAIM
x y
D
i0
i1
i2
i3
d
s1s0
To the above-m
irror display
4x18-bit
button
Digital DesignCombinational Logic Design
Figure 2.32 Above-mirror display using an 8-bit 4x1 mux.
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Digital DesignCombinational Logic Design
Figure 2.33 Schematic for 2x4 drawn using a popular commercial schematic capture tool.
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Digital DesignCombinational Logic Design
Figure 2.34 Simulation: (a) begins with us defining the inputs signal over time, (b) automatically generates the output waveforms when
we ask the simulator to simulate the circuit.
i0i1
d3d2d1d0
Inputs
Outputs Simulate
i0i1
d3d2d1d0
Inputs
Outputs Simulate
(a) (b)
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Digital DesignCombinational Logic Design
Figure 2.35 OR gate timing diagram: (a) without gate delay, (b) with gate delay.
x
F
time
10
10
y10
yF
x
F
10
10
y10
time(a) (b)