es 244: digital logic design chapter 4 chapter 4: combinational logic uchechukwu ofoegbu temple...
TRANSCRIPT
ES 244: Digital Logic Design Chapter 4
Chapter 4: Combinational Logic
Uchechukwu Ofoegbu
Temple University
ES 244: Digital Logic Design Chapter 4
One-bit Carry Ripple AdderOne-bit Carry Ripple Adder
– s = sum– cout – carry-out– a, b = added bits– C = carry in
a b c cout s
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
– S = a’b’c+a’bc’+ab’c’+abc– cout = a’bc+ab’c+abc’+abc– = bc+ac+ab– S = c(a’b’+ab)+c’(ab’+a’b)– cout = c(a+b)+ab– S = c(aΦb)’+c’(aΦb) = c Φ(aΦb)– Xor can be replaced with 4 two
input NAND gates– cout = c(a+b)+ab
5 three-input NAND, 3 two-input NAND, 1 four-5 three-input NAND, 3 two-input NAND, 1 four-input NAND, and three not gates if input NAND, and three not gates if
complemented inputs are not availablecomplemented inputs are not available
12 two-input NAND, two not gates or12 two-input NAND, two not gates or 9 two-input NAND gates assuming all input are 9 two-input NAND gates assuming all input are
available both complemented and uncomplementedavailable both complemented and uncomplemented
2 two-input XOR, 3 two-input NANDs, 1 three-2 two-input XOR, 3 two-input NANDs, 1 three-input ORinput OR
ES 244: Digital Logic Design Chapter 4
One-bit Full Binary AdderOne-bit Full Binary Adder
Gate implementation for the One-bit Full Adder
n-bit “ripple-carry” binary adder
Worst case propagation delay – 2n time units; Gate delay=1
ES 244: Digital Logic Design Chapter 4
Copyright © 2008 The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Gate Delay through a 1-bit Adder
ES 244: Digital Logic Design Chapter 4
Gate Delay through an n-bit Adder
1.1. Delay from inputs to cDelay from inputs to cout out ++
2.2. (n-2)*delay from c(n-2)*delay from cin in to cto cout out ++
3.3. Max(delay from cMax(delay from cin in to cto cout out or or
ccin in to s)to s)
For the multilevel adder:For the multilevel adder:
55∆ + 2(n-2) ∆ + 2(n-2) ∆ + 3 ∆∆ + 3 ∆
= (2n+4) ∆= (2n+4) ∆
What is the delay for a 64 What is the delay for a 64 bit adder?bit adder?
Total delay does Total delay does not have to be so not have to be so
long!!long!!
ES 244: Digital Logic Design Chapter 4
• SOP minimization for two-bit adders• Complex equations
• Fan-in limitations
• With a maximum fan-in of 7, adding n-bit would have a total delay of (n+1)∆
• Four-bit adders• 7483, 7483A, 74283 – differ only in pin connections
• Produces the sum with four-level inputs
• Uses combination of NAND, NOR, AND, NOT and XOR gates
• Delay from ccin in to cto cout out = 3= 3∆
• Total delay = of (3/4 n+1)∆
• 4-bit adders are cascaded for larger adders
Gate Delay ImprovementsGate Delay Improvements
ES 244: Digital Logic Design Chapter 4
One-bit Full Binary AdderOne-bit Full Binary Adder
Gate implementation for the One-bit Full Adder
n-bit “ripple-carry” binary adder
Worst case propagation delay – 2n time units; Gate delay=1
aa
bb
cc
ss
CCoutout
ES 244: Digital Logic Design Chapter 4
Copyright © 2008 The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Gate Delay ImprovementsGate Delay Improvements
ES 244: Digital Logic Design Chapter 4
• Carry-Look-Ahead Adder• Carry generate signal (g) is 1 if that stage of the adder has a carryout of 1
whether or not there was a carry-in
• Carry propagate signal (p) is 1 if that stage of the adder has a carryout of 1 if he carry-in is 1
• Both g and p can be generated for all n bits in 1 gate delay.
• The carry out is 1 if the last bit generated a carry, or if it propagated a carry and the stage below it generated one.
• All the carries can be generated in 2 additional delays after g and p are available, independent of n.
• All sums can be generated in 4∆, independent of n.
Gate Delay ImprovementsGate Delay Improvements
ES 244: Digital Logic Design Chapter 4
One-bit Full Binary Subtractor/AdderOne-bit Full Binary Subtractor/Adder
• Subtract y from x , with a borrow-in from the previous bit position, bin
– d: difference
– bout: borrow-out
x y bin bout d
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
inout ybbxyxb
)( yxbd in
ES 244: Digital Logic Design Chapter 4
Organization of a 1-bit comparator
• Compares two numbers to determine if – A is less than B– A is equal to B– A if greater than B
• Can be extended to any bit size
ES 244: Digital Logic Design Chapter 4
Truth Table for Simple 1-bit ComparatorTruth Table for Simple 1-bit ComparatorA2 B2 A1 B1 Y:
A=BY:
A>B
Y
A<B
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1.1. In groups, In groups, come up with a minimum come up with a minimum SOP expression for this SOP expression for this simple comparator. simple comparator. Assume all inputs are Assume all inputs are available in both available in both complimented and complimented and uncomplemented versions, uncomplemented versions, design a logic circuit for your design a logic circuit for your algebraic expressionalgebraic expressionWhat is the minimum delay What is the minimum delay for your designfor your design
ES 244: Digital Logic Design Chapter 4
• Selects one of several outputs when activated• n-bit binary number results in 2n output lines
Binary DecodersBinary Decoders
ES 244: Digital Logic Design Chapter 4
Binary DecodersBinary Decoders
Selected output is highSelected output is high
ES 244: Digital Logic Design Chapter 4
Binary DecodersBinary Decoders
Selected output is lowSelected output is low
ES 244: Digital Logic Design Chapter 4
Binary DecodersBinary Decoders
Selected output is high only when Enable Selected output is high only when Enable bit is high or Enable Prime is lowbit is high or Enable Prime is low
ES 244: Digital Logic Design Chapter 4
Active Low and three enable bitsActive Low and three enable bits
Active when ALL THREE enable bits are Active when ALL THREE enable bits are activeactive
Binary DecodersBinary Decoders
ES 244: Digital Logic Design Chapter 4
Copyright © 2008 The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Binary DecodersBinary Decoders
ES 244: Digital Logic Design Chapter 4
• Exact Opposite of a binary decoder• Used to select a device from several possible devices• If only one of the inputs can be 1, then the truth table for a 4-2
encoder is:
Binary EncodersBinary Encoders
AA00 AA11 AA22 AA33 zz00 zz11
1 0 0 0 0 0
0 1 0 0 0 1
0 0 1 0 1 0
0 0 0 1 1 1
ZZ0 0 ==AA22+A+A33
ZZ1 1 ==AA11+A+A33
What is the difference What is the difference
between Device between Device AA0 0
and when there is no and when there is no device signaling?device signaling?
ES 244: Digital Logic Design Chapter 4
0 1 2 3 4 5 6 7
0 4 5 6 7
1 6 7 2 3 4 5
2 7 5 6 3 4 6 1 2 4 6
( )
NR A A A A A A A A
Z A A A A
Z A A A A A A
Z A A A A A A A A A A
Priority EncodersPriority Encoders
ES 244: Digital Logic Design Chapter 4
MultiplexersMultiplexers
• A switch that is used to pass one input as a function of select inputs
ES 244: Digital Logic Design Chapter 4
MultiplexersMultiplexers
ES 244: Digital Logic Design Chapter 4
HomeworkHomework
• 1• 3• 5• 9• 14• 24• 29• 30• 34