dfx guidelines

DFX GUIDELINES

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O_GD0322_10 DFX GUIDELINES

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Glossary

Abbreviation Description

ADHESIVE (SMT) A substance such as glue or cement used to fasten objects together. In surface mounting, an epoxy adhesive is used to adhere SMD’s to the substrate.

AQUEOUS WASH (SMT and PTH)

De-ionized water wash process used to remove contaminates and flux residue from the PCB. Teradyne uses an aqueous cleaning system.

AUTO PLACE (SMT) The act or operation of assembling discrete components to printed boards by means of electronically controlled equipment.

CABLE ASSEMBLY Manual process to route, solder and tie down coax or other cable assemblies.

COMPONENT INSERTION (PTH)

Component insertion equipment installs the leads of a PTH component

Into the PCB, cuts each lead to the proper length and then clinches some or all of the leads against the Surface of the PCB. Current capability includes axial insertion, DIP insertion, SIP insertion and socket Insertion.

CURE A chemical reaction that changes the physical properties of a substance, e.g., an adhesive.

DPMO Defects per million opportunities is the number of defects divided by the number of opportunities multiplied by one million.

DISPENSING (SMT) Process to dispense adhesive material used to secure large parts on the bottom side of PCB. Solder paste is also dispensed on land pads for BGA rework.

ECO ASSEMBLY Manual process to incorporate jumper wires and other add-on components required by engineering change documentation.

LEAD FORM (PTH) Preconditioning leaded components by forming and/or trimming leads prior to insertion.

MANUAL SOLDER (PTH)

Manual process. Soldering using a solder iron or other hand-held, operator controlled apparatus.

MECHANICAL ASSEMBLY

Manual installation of mechanical components such as Ejectors, Heat sink

Plates, air baffles etc.


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PRESS-FIT Manual process to press-fit an electrical contact into a hole in a printed board with or without Plated thru holes.

PRINTING (SMT) Process to apply a material (solder paste or thermally conductive epoxy) by forcing it thru a stainless steel stencil. Two methods are employed in printing: automated (solder paste printing for PCBs) and manual (thermally conductive epoxy for heat sink applications).

REFLOW SOLDERING (SMT)

The joining of surfaces that have been tinned and have solder between them, placing them together, heating them until solder flows, and allowing the surfaces and the solder to cool in the joined surfaces.

REWORK (PTH and SMT)

The act of reprocessing non-complying articles, thru the use of original or alternate equivalent processing, in a manner that assures compliance of the article with applicable drawings or specifications.

SOCKET ASSEMBLY Manual process to hand load socketed components such as relays into pre-installed sockets.

SOLDER PASTE APPLICATION (SMT)

Solder paste is a homogeneous mixture of metal spheres and flux that promotes wetting. Two automated methods are used to apply solder paste to the PCB surface: printing or dispensing. Printing, which has the fastest cycle time and best process capability, is the preferred process.

SURFACE PREP Manual process where the bonding surfaces are abraded prior to applying epoxy.

WAVE SOLDERING (PTH)

A process wherein an assembled printed board is brought in contact with the surface of a continuously flowing and circulating mass of solder

ALIGNMENT HOLES Unplated holes used to position component alignment fixtures during assembly and soldering.

BREAKOFF BORDERS PCB material used to adapt PCB arrays to conform to PTH, In-Line or Carrier formats.

BREAKOFF EXTENSIONS

PCB material used to extend the dimensions of a PCB image or array to conform to PTH or In-Line formats.

BREAK-OFF TABS Snap-off tabs between images in an array to permit depanelization after assembly.

MULTI-IMAGE ARRAYS PCB images arranged in rows & columns to reduce costs or meet processing format requirements.


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PANELIZATION Method to reduce costs by using break off borders, extensions or by creating multi-image arrays.

CARRIER FORMAT Processing format for Mixed Technology Boards that do not meet requirement of In-Line format.

PCB IMAGE Refers to a single PCB which can be processed individually or as part of an array.

PTH FORMAT Processing format for leaded technology boards that permits use of standard board holding plates.

ROUTER TABS Webs of PCB material between images in an array which are cut or routed after assembly.

SAW SCORING Grooves cut between images in an array to permit depanelization after assembly.

SMT CARRIER FORMAT

Processing format for SMT or Mixed Technology Boards that do not meet requirement of In-Line format.

SMT IN-LINE FORMAT Processing format for Mixed Technology Boards that permits conveyorized board handling.

TOOLING HOLES Un plated holes used for mechanical board alignment during assembly and test.


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Table of Contents

1 Introduction..................................................................................................................................8

2 Tooling Holes, Fiducials..............................................................................................................8

3 Layout considerations (SMT/THT)...............................................................................................9

4 PTH Calculations .......................................................................................................................11

5 Outline Drawing dimension and requirements.........................................................................12

6 Stackup construction ................................................................................................................12

7 Silkscreen guidelines ................................................................................................................13

8 SOLDERMASK REQUIREMENTS ..............................................................................................13

9 Solder Paste Requirements.......................................................................................................14

10 PCB Surface Finishes................................................................................................................14

11 Soldering Types and Layout Requirements .............................................................................16

11.1 Design Guideline for Reflow soldering...........................................................................16

11.2 Design Guideline for Intrusive Reflow............................................................................16

11.3 Design Guideline for Wave Soldering............................................................................17

11.4 Selective Wave Soldering Requirements.......................................................................18

12 Assembly Drawing Requirements:............................................................................................18

13 Panelization and De-Panelization..............................................................................................19

13.1 Panelization: .................................................................................................................19

13.2 Depanelization Methods:...............................................................................................20

14 Vias (Types, Preferred, Via Selection).......................................................................................22

15 Laminate Material Selection ......................................................................................................25

16 Pb-free Laminate Characteristics..............................................................................................26

16.1 Laminate Selection .......................................................................................................27

17 ROHS compliance......................................................................................................................28

17.1 Minimum RoHS Component Requirements ...................................................................28

17.2 All PCB surface finishes must meet the following requirements .....................................29

18 Chip Components......................................................................................................................30

19 Design for Testability Guidelines..............................................................................................52

19.1 ICT (In circuit Test) Mechanical Guidelines ...................................................................52

19.1.1 Probe Spacing .....................................................................................................52

19.1.2 Probe Access.......................................................................................................52

19.1.3 Test Pad Density..................................................................................................53

19.1.4 Test Pad Requirement: ........................................................................................53

19.1.5 Test Pad Diameter: ..............................................................................................54


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19.1.6 Test Pad to Test Pad Spacing: .............................................................................54

19.1.7 Test Pad to a Via Clearance.................................................................................55

19.1.8 Test Pad to Component Pad Clearance ...............................................................55

19.1.9 Test Pad to Edge of Secondary Side Component Clearance ................................56

19.1.10 Test Pad to Secondary Side Trace Clearance ....................................................56

19.1.11 Test Pad to Edge of Board Clearance ................................................................57

19.1.12 Test Pad to Tooling Hole Clearance ...................................................................57

19.1.13 Test Pad to thru-hole device lead clearance .......................................................58

19.1.14 Test Pad to high components.............................................................................58

19.1.15 Table for quick reference....................................................................................59

19.2 Design for Test (DFT) Deliverables: ..............................................................................59

19.3 ICT (In circuit Test) Electrical Guidelines.......................................................................60

19.3.1 Tri-State Devices, Output Enables........................................................................60

19.3.2 Do Not Tie Control Pins Directly to Power or Ground Rails. ..................................60

19.3.3 Common Circuitry Must Have Unique Control.......................................................61

19.3.4 Break Feedback Loops ........................................................................................62

19.3.5 Clocks and Oscillators..........................................................................................62

19.3.6 Tweaks ................................................................................................................63

19.3.7 Three-Pin Polarized Capacitors............................................................................64

19.3.8 Logic Cell Programmable Gate Arrays (LCA)........................................................64

19.3.9 Boundary Scan Implementation............................................................................64

19.3.10 FPGA's and Non-1149.1 ASICS.........................................................................65

19.3.11 Pass-Through Mode...........................................................................................65

19.3.12 Identification and Revision Code ........................................................................65

19.4 Mixed Signal ASICS......................................................................................................66

19.4.1 Digital Testability..................................................................................................66

19.4.2 Analog Testability.................................................................................................66

19.5 PALS and GALS...........................................................................................................66

19.5.1 Tri-State Control Pin.............................................................................................66

19.6 BGA devices with NAND-Chain Test Capability.............................................................67

19.6.1 Tri-State Control Pin/Sequence............................................................................67

19.6.2 Maximum Size Pin Group or NAND Chain Length ................................................67

19.6.3 NAND Chain Test Point Allocation........................................................................67

19.7 Power & Ground Test Pad Requirements......................................................................67

19.7.1 Supply Power Probe Calculations.........................................................................67

19.7.2 Ground Probe Calculations ..................................................................................68


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20 COMPONENT AND ASSEMBLY ISSUES:..................................................................................69

20.1 Considerations for Component Mounting:......................................................................69

20.2 Automatic/Manual placement and Insertion: ..................................................................70

20.3 PCB AND ASSEMBLY PANELIZATION:.......................................................................72

20.4 PRINTED BOARD AND ASSEMBLY VIEWING PRINCIPLES:......................................74

20.5 COMPONENT SELECTION & LAND PATTERN DESIGN.............................................75

20.5.1 SMT component Selection: ..................................................................................75

20.5.2 Component Mix....................................................................................................75

20.5.3 Process Compatibility Requirements ....................................................................75

20.5.4 Non-Preferred Components .................................................................................76

20.5.5 Land Pattern Design: ...........................................................................................76

20.6 COMPONENT PLACEMENT ........................................................................................77

20.6.1 Primary vs. Secondary Side Placement................................................................77

20.6.2 COMPONENT ORIENTATIONS ..........................................................................82

20.7 ASSEMBLY CONSIDERATIONS FOR SURFACE MOUNT ..........................................88

20.7.1 TECHNOLOGY (SMT) .........................................................................................88

20.7.2 SMT Assembly Process Sequence.......................................................................88

20.8 PCB ASSEMBLY DRAWING NOTES ...........................................................................90

20.9 ASSEMBLY PANEL DRAWING....................................................................................90

20.10 HARDWARE ASSEMBLY INSTRUCTIONS..................................................................91

20.11 DESIGN FOR ASSEMBLY (DFA) O/P DATA REQUIREMENT......................................91

20.12 REWORK .....................................................................................................................92

20.13 Heatsink Effects............................................................................................................93

20.14 Dependence on Printed Board Material Type ................................................................93

20.15 Dependence on Copper Land and Conductor Layout ....................................................93

20.16 Design Considerations for Repair and Inspection ..........................................................93


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1 Introduction

Design for Manufacturability, which defines the rules and standards for the best suitability of the PCB manufacturability by most of the vendors. By implementing these rules at design phase (i.e., before proto build) will gives us following advantages,

Production Cost - get reduced as the problems at production will be less

Engineering Change Cost - will be less, as changes at production stage will be less in turn the staffing required for the ECO will be less

Quality – by following the DFM guidelines all the problem which could occur in the field will be identified at the proto development itself. This increases the quality of the product developed

Reduced Time to Market – Design cycle of the DFM implemented products will take more time than the regular designs but the production phase and the deliverable phase will get reduced dramatically. Almost 40% of the product development time will be reduced by following DFM guidelines.

2 Tooling Holes, Fiducials

a) Tooling holes should be of NPTH with drill size of 125 mils to 157 mils

and should be placed 200mils (+/-5 mils) inside from the board edges. Minimum of two tooling holes should be placed and three is preferred and should be placed at diagonal corners of the board. Tooling holes will be used in following places

PTH Technology SMT Technology

Automatic Insertion In-Circuit Test Fixtures

In-Circuit Test Fixtures Custom Carrier Fixtures

Custom Carrier Fixtures Wave Solder Fixtures

Wave Solder Fixtures Press Fit Fixtures

b) Fiducials are used to get the reference on the board, for auto placement of components and other PCB handling equipments to avoid mechanical placement errors. Local, Global and Panel fuducials are the types of fiducial marking.

Following rules should adhere to have a clear use of Fiducials on the board

i) Should be placed minimum of 0.200” and maximum of 1.5” from the board edges

ii) Should have clearance from silk, mask and copper. Mask should be cleared for the size of at least double as pad size.


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iii) Should be visible all the time, even after the board is populated

iv) There should be 3 board fiducials placed each on either side of the board on the corners, 2 of them should be placed in diagonal corners. Bottom side fiducials should be placed in the same location as of the Top side fiducials, as this will give a different image for both the layers while the board is placed in PCB handling equipments.

v) These fiducials should be placed where there is no plane underneath or the plane under the fiducials can be voided to have clarity of the fiducial.

vi) Local fiducials should be placed for the fine pitch components which have less than 0.5mm pitch including BGA and this fiducial can be shared by the fine pitch components placed within 5” circumferences. This will lead to find accurate position of the component and placement.

vii) Preferred fiducial size is 0.040” pad and 0.080” soldermask.

3 Layout considerations (SMT/THT)

a) Technology grouping of components on the board is preferred, SMT components should be grouped in a segregated area and Thru hole parts in a segregated area, this will help us to give enough clearance for manufacturing process and wave soldering fixture cost and complexity reduction.

b) On the Bottom (Solder side) Wave soldering clearance of 0.150” is required between thru hole pad edge to the SMT pad edge, this will be useful to mask the SMT parts while the board is undergoing wave soldering process and to get clear dip of the thru hole parts in the solder wave.

c) Bottom / Solder side placement is to be done with the following rules

i) Chip components, SO16 and smaller components can be placed on bottom side, provided the maximum height of the component should be less than 0.150”.

ii) “J” leaded and BGA components should be avoided.

d) SMT parts and “PRESS FIT” parts placement in 90° rotation is preferred and 1° increment is allowed, but for Though hole parts 90° rotation is only allowed and preferably these parts should be placed in same direction. Auto insertion of thru hole components is not possible other than 90°. Nomenclatures should be placed in 90° rotation for readability.

e) Rework clearance for all the components to be provided for debugging and rework. This will vary per component size and height of the component. Please refer page no 75 & 76 for these values.

f) Thermal relief should be used to connect thru hole pin to get connected to copper area/plane, else the heat will be dissipated and solder alloy will not get the temperature for proper solder flow, results in cold solder joints.


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g) Copper traces connected to 1206 and smaller components should have equal width on both pins, this will help to prevent part movement during re-flow soldering.

h) Copper traces should not be routed between discrete component packages, to avoid soldermask opening (Copper expose) in that areas due to adhesive material usage during solder process. Vias also should be avoided underneath the components like

i) In BGA, fan-out vias can be removed wherever not used, but the fan-out trace should be retained to hold the pads of BGA to the PCB during rework process.

j) Direct routing between the SMD pins not allowed, routing should be done outside the land pattern, which will be used to do rework when there is a need. Direct short will make the board testing person to think that it is unintentionally done.

k) Enough clearance should be maintained between via to via and pad to via.

VIA to VIA Minimum spacing 12 mil Trace width / space 4 / 4

VIA to VIA Minimum spacing 15 mil Trace width / space 5 / 5

Pad to VIA Minimum spacing 12 mil Solder Mask web is 6 mil


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4 PTH Calculations

Axial lead span calculation, Lead protrusion, Hole clearance

a) Axial lead span can be calculated as follows

Lead span X = A + B + 0.200”

Lead span value to be rounded off to the next largest 0.025” increment.

b) Lead Protrusion:

c) Hole Clearance:

d = Pin Size (diameter if lead is round, diagonal size if the pin

is rectangular or square)

D = Hole Clearance

d+0.015” if d < 0.050”

d+0.018” if d = 0.050” to 0.080”

d+0.020” if d = 0.081” to 0.100” and

d+0.022” if d > 0.100”

X A

Dia = B

PCB

Lead Prot = 0.020”

d D Pad


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5 Outline Drawing dimension and requirements

Outline Drawing should provide following details

a) Dimensions of the board outline including all cut-outs and chamfers.

b) All Mechanical details, all mechanical parts positions, Placement and Routing keepout details, Standoff areas, stiffeners, edge guides etc.,

c) Copper area/clearance requirement if there is any card guide is used

d) Mounting holes positions from the board edge (hole edge should have 0.150” from board edge, this value can go down upto 0.100” if the board thickness is above 0.125”)

e) Mechanical parts having large height should have enough clearance area for the nearby smaller components to have rework visibility.

f) Board thickness details should be provided clearly (typical thicknesses are 0.032” to 0.096”).

g) All the height restrictions should be defined wherever applicable on the board.

h) Board dimensions should preferably be in Inches with three decimal precision.

6 Stackup construction

Stackup should be designed such a way that the copper weight is balanced from centerline of the cross section of the board, by symmetrically distributed Plane layers and Signal layers.

Stackup diagram should give all the necessary details like, layer order, thickness of signal, plane and dielectric layers, total thickness of the board with tolerance.

Stackup Rules:

a) Symmetrical dielectric thickness to be used.

b) Layer count cannot be odd, use even number of layers (like 2, 4, 6, 8T)

c) Dielectric layer thickness should be more than 0.004”

d) Offset the plane layer edges around the perimeter to avoid mechanical damages to the dielectric, for minimum of 0.025”.

e) Copper weight should be equal on both sides of each core layer.

f) Copper distribution should be done across each individual layer.


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7 Silkscreen guidelines

Silkscreen is used in a PCB to identify component locations, polarity, component orientation, component reference designators and label locations. Following are the requirements of silkscreen in PCB,

a) Pin one marking should be done on silkscreen layer for both SMT and PTH multi-leaded device.

b) Polarity marking should be done for the polarized components.

c) Reference Designators for the components should have the minimum dimension of 0.031” height by 0.023” wide with 0.006” line width and preferred dimension is 0.031” width and 0.050” height with 0.006” line width.

d) Silkscreen is not allowed on solderable pads, should be cleared from these pads for a minimum distance of 0.016” to 0.020”. On a complex design these values can be 0.005” to 0.010”. Silkscreen to silkscreen overlap should be avoided.

e) Reference designators and polarity marking of a component should be placed outside the symbol to have the visibility of the same during testing and rework.

f) Label location should be defined in Silkscreen, Label type and size will vary depends on the requirement. This will be used to identify the part number and the serialization of the work done.

g) Label area should be away from SMT locations, test pads and nomenclature.

h) Multiple Pin numbers on silkscreen for high pin count component is advisable and if the pin number for BGA is provided on non-component side, debugging will be easier.

8 SOLDERMASK REQUIREMENTS

a) Solder Mask is provided to avoid soldering of unwanted portions of a pad and trace, usually the mask will have a clearance maximum of 3 mils on all sides of the pad.

b) LPI is the material being used usually for the board containing fine pitch components like BGA.

c) SolderMask web of less than 0.005” should be avoided in dense packages like QFP, QFN, and SOP. To achieve this gang mask will be used for the pins on each side of the package. Gang mask is required on the components having pin pitch less than 0.020”.

Regular Solder Mask Gang Mask

d) Soldermask dam should be present between via and the solder pad to avoid copper thieving on via.

Pins

Solder Mask


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e) On Thermal pads inside a component should have adequate opening in soldermask and should have solder paste if required.

f) Vias can be tented wherever the density of via is high to avoid shorts.

g) Via plug-in to be used where vias are tented on one side, and via plug-in should not extend beyond the via pad edge and should have height less than 0.002” from via surface.

h) Solder mask tenting is not preferred with HASL and immersion surface finishes due to solder ball formation or contamination entrapment.

9 Solder Paste Requirements

Solder paste is used to generate stencil sheet to apply solder paste on the solderable pads. Solder paste to be defined with the following rules,

a) Should be defined for all solderable SMT pads with the size as same as SMT copper pad.

b) Solder paste will be defined for selective thru hole pads also, wherever needed, solder paste will be applied and then the thru hole component will be inserted and this setup will undergo reflow soldering to get soldered along with SMT parts on the board. This technology is called Paste-in-Hole or Pin-in-Paste.

c) On thermal pads under components which needs to be soldered also should have solder paste applied, and this should made the size of the solder mask opened on these thermal pads.

10 PCB Surface Finishes

a) Hot Air Solder Leveled (HASL)

Use: Standard for SMT with lead pitc hes >= 25mils, BGA ball pitches >= 50mils and

plated-through hole designs

Plus: Common technology, “Nothing solders like solder”. Press fit compatible. Plated solder

with flat topology is highly desirable for lead free application.

Minus: Horizontal vs. Vertical Domed Surface makes it unsuitable to Fine Pitch QFPs, BGAs and 0402/0201 passives

PCB thickness limits

b) Organic Solderability Preservatives (OSP)

Use: Surface mount, Plated-through hole HASL alternative

Plus: Low cost alternative to HASL. Environmental friendly, planar surface perfect for Fine

Pitch QFPs, BGA and small passives Press fit compatible Capable of being "renewed" prior to use if oxidized Lead free alternative


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Minus: Variability in spread, not visible to the eye Prone to oxidation if poorly handled Shelf-

life less than 6 months

Degrades with exposure to high temperatures and alcohol/water washes

c) Immersion Gold over Electro less Nickel (Also known as Electro less Nickel,

Immersion Gold (ENIG))

Use: Surface mount with ultrafine pitch and co planarity, 3-8 micro inches gold

Plus: Low, stable electrical contact resistance over long period’s excellent solderability, may

be wire bonded

Planar surface perfect for Fine Pitch QFPs, BGA and small passives Press fit compatible, cosmetically appealing and Low oxidation. Lead free alternative

Minus: Tight process window, Phosphorus Enrichment, Skip plating, Black Pad, Brittle

Ni/Sn inter-metallic,

Micro-voiding

d) Electrolytic Gold over Nickel

Use: Full body gold plating, Selective plating for surface mount connectors and internal

switch contacts, typical 20–40 micro inches

Plus: Low and stable electrical contact resistance over long periods cosmetically appealing.

Low oxidation.

Minus: Requires bussing or pre-etch plating distribution and thickness variation across panel. Selective gold requires extra process and adds cost. Bussing leaves stubs and embrittlement.

e) Tab Plated Hard Gold over Nickel

Use: Edge connectors for plug-in boards

Plus: Excellent wear resistance

Minus: Conveyor driven, plating line bussing required, Taping required

f) Immersion Tin

Use: Surface Mount with ultrafine pitch and co-planarity

Plus: Planar surface. Metallic finish applied over copper with Ni barrier. Uses the same

chemistry and set up as HASL.

Shelf life of two years Lead free alternative

Minus: Batch Plating Line. Tin whisker potential

g) Immersion Silver

Use: Surface Mount with ultrafine pitch and co-planarity, typical 30-60 micro inch thickness

Plus: Planar surface perfect for Fine Pitch QFPs, BGA and small passives Press fit

compatible. Cosmetically appealing.

Low oxidation. Lead free alternative for Class I & II Products only


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Minus: Emerging technology. Not available at all suppliers. Limited assembly performance

data. Micro-voiding

11 Soldering Types and Layout Requirements

11.1 Design Guideline for Reflow soldering

a) All the thru hole parts to be placed on the component side as much as possible and small sized and lesser weight components can be placed on the solder side of the PCB. Bulkier SMT component will fall down during the wave soldering process, also will hide the thru hole pins to get contact with solder wave (form a shadow area for the thru hole pins).

b) When components are evenly distributed over the surface of the board, the board temperature remains relatively evenly distributed with no excessive temperature in any one area. This also helps prevent bowing and twisting of the board during soldering.

c) Placing active SMT components on the secondary side of the board may require selective soldering, which will increase the assembly cost.

d) Components should be placed with prescribed clearance to have clean soldering, without formation of Solder Bridge.

11.2 Design Guideline for Intrusive Reflow

Intrusive Reflow (IR) is a process in which solder paste is printed into the plated through holes and on the top or both surface of a PCB, through-hole parts are inserted and reflow soldered. The intrusive reflow process is sometimes called pin-in-paste, through-hole reflow. Intrusive reflow is used where a product design incorporates a few through-hole component types on a design that is otherwise employing surface mount technology.

a) Clearance for overprint on the Primary Side of the PCA is recommended to be 60 mils while 80 mils are desired for 2nd side for over print.

b) HASL the preferred surface finish for IR. However, other solderability preservatives such as ENIG are acceptable.

c) A stand off height of 15 mils is required along with a stand off clearance of 110 mils.

d) Minimum device pitch and lead protrusion recommendations are as detailed below.

Minimum pitch: 31.50 mils

Min. lead (>31.5 pitch) extrude from PCB: 40 mils

Max. lead (>31.5 pitch) extrude from PCB : 70 mils

e) Ensure that all components for IR application are compatible with the required reflow or soldering temperature.


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11.3 Design Guideline for Wave Soldering

a) Active SMT and Fine Pitch components typically should not be wave soldered.

b) Small components should not be placed next to tall components to prevent shadowing.

c) Topside PTH connectors should be oriented with the long axis perpendicular to the wave.

d) A large number of open vias can cause fine pitch SMT components on the component side of the PCB to reflow during wave. Tenting or plugging vias can help reduce thermal heat transfer to the top of the PCB. Dispersing vias away from the fine pitch component will also help.

e) Orient bottom side components in one direction if the assembly is to be waved. Axis of chip components should be parallel to wave and IC’s should have long axis perpendicular to wave. Incorrect component orientation can result in uneven solder joint fillet formation or solder skip as shown in figures below

Fig. 1 Uneven Solder fillet due to incorrect device orientation


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f) Minimum pad-to-pad spacing for a surface mount pads and through-hole PGA and axial component for wave soldering is recommended to be as shown in figures below

11.4 Selective Wave Soldering Requirements

a) A minimum spacing of 0.175” is recommended between a high profile (>.150”) component body and a PTH pad to minimize solder skip during selective wave soldering.

b) A minimum clearance of 0.150” between a PTH pad and adjacent component (with < 0.150” profile) body is required for effective selective wave fixturing.

c) Isolation or local grouping of PTH components enhances selective masking efficiency and minimizes soldering defects.

d) Avoid placing surface mount components on the bottom side of PCA directly underneath a PTH component area such as a PGA or DIP, for better fixturing and soldering yield.

12 Assembly Drawing Requirements:

Following are the elements to be printed on Assembly Drawing,

a) Package outlines

b) Component identifiers (Reference Designators)


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c) Pin numbers at corners if pin count is higher than 24

d) Board outline

e) Board title block

f) Notes, to describe assembly instructions if there is any

g) Cross reference for the mechanical parts against the Assembly BOM

13 Panelization and De-Panelization

13.1 Panelization:

a) Information will be gathered from fabrication vendor, regarding maximum panel size, working borders, and any other space needed for coupons.

b) A common master panel size is 18" x 24" with a 1" border. A typical router channel dimension is 2.4mm (0.094”). This will vary per vendor.

c) Panelization will contain details as shown in figure

1 2 3

4

6

7

5


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1. Non-plated tooling hole at left bottom corner, the drill size allowed is between 0.125” and 0.157” with tolerance of +0.003” / -0.000”.

2. Space to be provided to paste Bad-Board Marker (also called Image Reject Marker (IRM)), is used to identify the partially good image or partially good panel, where the assembly process will not be carried out so that the process cycle time will get reduced by omission of the bad board.

i. There should be space allotted for local IRM and Global IRM as shown in the figure and there are two types of IRM used as shown, one is local and another is global.

ii. One IRM per side should be placed where components to be populated on PCB (Component / Solder side).

iii. Edge of these IRM should be away from the board edge as well as panel edge for 0.197”.

3. Local Bad-Board Markers or IRMs located at a corner of the panel, one per each board image and in the same pattern as the board images placed in the panel.

4. Two sides of the Panel other than conveyor edges should have cleared from all elements for 0.080”.

5. Global fiducials on the panel, minimum of two fiducials must be placed at diagonal corners and three fiducials preferred as shown in the figure.

6. Component keepout area left free between edge of board image and the conveyor area. Minimum of 0.100” is required.

7. Clearance required for the board to travel in conveyor belt during assembly and solder processes

d) If any of the images crosses the panel keepout should follow the panel keepout for components.

e) Solder mask must be removed from the board edge for a minimum of 0.015” and preferred is 0.025”.

f) Copper must be avoided for 0.025” from the board edge to mitigate corrosion issues that affect the reliability of the PCB.

g) Maximum board thickness for panelized edges is 0.150” based on maximum router-bit cutting depth.

h) Asymmetric placement of tooling holes and global fiducials are preferred to prevent incorrect board orientation

13.2 Depanelization Methods:

Depanelization is the process of separating individual boards from the panel, there are different depanelization methods are available and they have their own merits/demerits as follows,

1) Router

Plus: Gives clean and accurate cuts on all FR4 applications.


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Minus: Requires custom fixturing, requires custom programs, Highest manufacturing

costs, Process generates dust, requires solder sample for programming and setup.

Recommended For Small boards, complex outlines, more number of images on subpanels. Boards are less than 0.150” nominal thickness.

Accuracy: ± 0.005” and 0.015” for less expensive routing.

2) Score and break

Plus: Inexpensive depanelization method, Requires no unique fixturing, de-lamination is

less likely since solder mask layer is cut off during scoring.

Minus: Less accurate than routing, rough edge with thick boards, Requires 0.025" solder mask to edge keepout, Requires largest copper pullback and component keepout.

Recommended For: Rectangular boards, ≤0.093" boards, No cosmetic or precise dimensional requirement.

Accuracy: 0.015".

3) Shear:

Plus: Allows for quick separation of thin cards using guillotine.

Minus: Only advised on boards less than 0.032" thick, Imparts a high degree of stress to

the PCA.

Recommended For: Thin boards with simple outline and nominal thickness of 0.029".

Accuracy: 0.020".

4) Breakaway:

Plus: Inexpensive manual method of breaking cards out of panel.

Minus: Leaves rough edges at tab locations.

Recommended For: Boards greater than 0.093", Non-rectangular boards, No cosmetic or precise dimensional requirement (external breaks extend past the outer dimensions of the card).

Accuracy: 0.005" except at break locations.


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14 Vias (Types, Preferred, Via Selection)

1) Via types are thru hole, blind and buried. Depends on the complexity of the routing and component placement, the via selection must be done.

2) Thru hole via is used to connect all the layers on the board from top layer to bottom layer.

3) Solder mask tenting is generally used to cap vias, as shown in figure below, via tenting prevents vacuum leaks during testing and reduces heat transfer at BGA sites.

4) Thru hole vias should not be placed on SMT pads, blind vias can be used on decaps to connect to the immediate plane layer.

5) Vias should not be placed between the pads of passive components. This will reduce solder shorts.


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6) Plug or tent vias within BGA footprint on the device side. On the opposite side of the board bring mask up to knee of barrel but leave via open. This will reduce the risk of out-gassing.

7) Spacing between via-via and via-pad limited to 0.015” and can go down upto 0.010” on a complex board.

8) Preferred thru via sizes are 0.010” drill 0.020” pad for digital signals and 0.020” drill 0.036 drill for power and analog signals, but the calculations will be done by the design engineer to decide what sizes to be used on the board depends on the design requirement.

9) Via drill should be selected as per the aspect ratio requirement as follows,

The aspect ratio of plated-through holes plays an important part in the ability of the ratio guidelines for holes. Exceptions can be made depending on board house capability and plated-through hole life requirements. Aspect ratio is defined as the ratio of the length or depth of a hole relative to its pre-plated (drilled) diameter. The aspect ratio plays an important part in the ability of the manufacturer to provide sufficient plating within the drilled hole.

The producibilty impact of various levels of complexity is shown below (reference IPC-D- 275, paragraph 5.4.8.1)

Level a General Design Complexity Preferred AR 3:1 to 5:1

Level B Moderate Design Complexity Standard AR 6:1 to 8:1

Level C High Design Complexity Reduced AR > 9:1

A PWB with a nominal thickness of .090 and with minimum diameter holes drilled using a .0135 (#80) drill falls into the moderate design complexity range i.e., .090/.0135 = 6.7:1

10) Recommended minimum drill size versus board thickness is given in the table below


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11) Blind via plated-through holes extend from the surface and connect the surface layer with one or more internal layers. If an interconnection is desired between the surface layer and more than one internal layer, sequential etching, laminating, drilling and plating-through of these layers together before final multilayer lamination is required. Blind via holes should be filled or plugged with a polymer or solder resist preventing solder form entering them since solder in the small holes decreases reliability.

Minimum drill sizes for blind vias are given below (as per IPC – 2221),

12) Buried via plated-through holes do not extend to the surface but interconnect only internal layers. Most commonly the interconnection is between two adjacent internal layers. These are produced by drilling the thin laminate material, plating the holes through and then etching the internal layer pattern on the layers prior to multilayer lamination. Buried vias between non-adjacent layers requires sequential etching of


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inside layers, laminating them together, drilling the laminated panel, plating the holes through, etching external sides and laminating this panel into the final multilayer panel.

Minimum drill sizes for buried vias are given below (as per IPC – 2221),

15 Laminate Material Selection

Generally while selecting laminate Basic physical and electrical parameters to consider.

When selecting laminates the following factors should be considered:

• Material Stability (Tg)

• Impedance requirements (Dk and Df)

When selecting laminates for high frequency applications make sure the Dk and Df for a given Tg is appropriate for the application of the product.

Other laminate characteristics have become more critical at Pb-free soldering temperatures. When selecting laminates for use in the Pb-free process the following additional characteristics should be considered:

• Decomposition Temp

• Z-axis expansion

• CAF Resistance

• Moisture Sensitivity

• Time to de-lamination - at T = 288ºC and T = 260ºC

Table below prescribes laminate recommendations based on reliability requirements of the assembly, complexity of technology used in the assembly and the physical PCB characteristics (thickness, layer count and weight of Cu). Although the table includes typical technology descriptions of the PCBs for the respective reliability categories, the primary driver when selecting a laminate should be the reliability requirements.

Note: CAF (Conductive Anodic Filament) - describes the growth of a conductive filament from an anodic (-ve) to a cathodic (+ve) surface along the glass-epoxy interface. This growth can result in shorts between adjacent vias and ground or power planes, if the filament is allowed to bridge completely. De-lamination may also occur in severe cases. CAF resistance is affected by the plating process, size of barrel, laminate material (coupling agents) and quality of drilling process. At elevated temperatures, where there is a higher propensity for laminate cracking, the threat of filament growth increases and CAF resistance becomes a critical parameter. The


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effects of filament growth are only detectable in the field and cannot be caught at ICT. The growth of the CAF does not immediately lead to a reduction in resistance between vias, in fact resistance only drops as the CAF grows the last few percent of the gap.

Dicyandiamide (dicy), is the most common cross-linking agent used in FR-4. The traditional "dicy" resin system that has been used for High Tg FR4 based materials generally will not be able to withstand the higher temperature reflow profiles, and as such, a "non-dicy" resin based material will need be used in most cases.

16 Pb-free Laminate Characteristics


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16.1 Laminate Selection

For low frequency applications (<900 MHz) standard FR4 material will be sufficient if the board thickness and number of layers is kept to a minimum. Applications in the 900MHz – 1.9 GHz a more stable glass based material can be used. If the application is over 1.9 GHz or the temperature is extreme then a PTFE/Ceramic material will be required. If design requires mixed signals such as RF/IF or RF/Digital then a board with mixed materials design should be considered. As in all designs the number of layers (thickness) should be kept to a minimum (2 preferred for RF only designs), but also the diameter of the vias should be kept as small as possible.


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17 ROHS compliance

The Restriction of Hazardous Substances (RoHS) Directive comes into effect on July 1, 2006 and bans the sale of electrical and electronic equipment containing the following chemicals:

• Lead (Pb)

• Cadmium (Cd)

• Mercury (Hg)

• Hexavalent Chromium (Cr6+ or Cr VI)

• Polybrominated Biphenyls (PBB)

• Polybrominated Diphenyl Ethers (PBDE)

The proposed wording of the legislation indicates that "... the maximum permissible amount of each material is 0.1% by weight in the applicable homogeneous material, with the exception of Cadmium. The maximum permissible amount of cadmium is 0.01% by weight in the applicable homogeneous material."

The Waste Electrical and Electronic Equipment (WEEE) Directive introduces mandatory collection, re-use and recycling of electrical and electronic products, and requires producers of electrical and electronic equipment to finance collection arrangements for their products -both new products and goods already on the market - at the end-of-life. Compliance readiness expectations for WEEE begin in 2004.

The biggest challenge to the printed circuit assembly process due to RoHS, is the elimination of Lead (Pb) from the soldering process. The new Pb-free products that primarily affect the following areas.

• Component Selection

• PCB surface finishes

• PCB laminate selection

• Hot Air Rework

• Via technology

• Through hole processes (Pin through Hole (PTH) wave and Paste in Hole PIH))

17.1 Minimum RoHS Component Requirements

All Lead (Pb)-free or RoHS compliant parts must meet or exceed the requirements.

1. Handling, Packing, Shipping and Use (per IPC/JEDEC J-STD-033)

2. Marking and Labelling (per IPC/JEDEC JESD97)

3. All components shall be capable of withstanding one dry rework condition (as defined in IPC/JEDEC J-STD-020) at a process temperature of 260°C +5°C/-0°C. The MSL rating at this temperature shall be determined using the method listed in J-STD-020. This rating shall be clearly indicated on the barcode or MSL Caution Label as defined in J-STD-033.


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4. All components shall meet the Pb-Free process package classification reflow temperatures as defined in J-STD-020.

5. All components should meet the RoHS directive (2002/95/EC) material requirements.

17.2 All PCB surface finishes must meet the following requirements

• Environmental impact: RoHS banned substance must not be part of the finish Chemistry.

• Must be capable of withstanding multiple reflows at elevated temperatures (max 260ºC)

• Must be compatible with the finish on the component leads to limit the impact of intermetallic growth after reflow.

• Must exhibit good wetting, as per J-STD-003 and IPC-A-610 specifications.

• Dendrite formation - should show minimum amounts of electro migration (effect worsens at Pb-free process temps)

• Discolouration - should show minimum amounts of discoloration from soldering operations (effect worsens at Pb-free process temps)

• It is preferred (but not required) that the surface finish can be used with both SnPb and Pb-free soldering operations.

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COMPONENT LIBRARY CREATION

18 Chip Components

CHIP RESISTORS

COMPONENT DIMENSIONS

L W T1

Standard Name min

(mm)

max

(mm)

min

(mm)

max

(mm)

min

(mm)

max

(mm)

H

Max(mm)

EIA 0201, METRIC 0603 0.57 0.63 0.27 0.33 0.10 0.20 0.33

EIA 0402, METRIC 1005 0.92 1.22 0.43 0.69 0.12 0.38 0.84

EIA 0504, METRIC 1310 1.12 1.42 0.89 1.15 0.12 0.38 0.51

EIA 0603, METRIC 1608 1.48 1.78 0.68 0.94 0.12 0.38 0.84

EIA 0805, METRIC 2012 1.80 2.20 1.15 1.35 0.20 0.60 0.70

EIA 1206, METRIC 3216 3.05 3.35 1.47 1.73 0.26 0.64 0.84

EIA 1210, METRIC 3225 3.00 3.40 2.30 2.70 0.30 0.70 0.70

EIA 2010, METRIC 5025 4.80 5.20 2.30 2.70 0.40 0.80 0.70

EIA 2512, METRIC 6332 6.10 6.50 3.00 3.40 0.25 0.65 0.70


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CHIP RESISTORS

LAND PATTERN DIMENSIONS

Standard Name Z

(mm)

G

(mm)

X

(mm)

Y(REF)

(mm)

C(REF)

(mm)

EIA 0201, METRIC 0603

1.15 0.25 0.40 0.45 0.70


1.65 0.35 0.75 0.65 1.00


1.85 0.55 1.20 0.65 1.20


2.50 0.90 1.00 0.80 1.70


2.95 0.85 1.40 1.05 1.90


4.05 1.95 1.75 1.05 3.00


4.15 1.85 2.70 1.15 3.00


5.95 3.45 2.70 1.25 4.70


7.20 5.00 3.45 1.10 6.10


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Standard Name Z

(mm)

G

(mm)

X

(mm)

Y(REF)

(mm)

C(REF)

(mm)

CHIP CAPACITORS


L W T1

Standard Name min

(mm)

max

(mm)

min

(mm)

max

(mm)

min

(mm)

max

(mm)

H

Max(mm)


0.57 0.63 0.27 0.33 0.10 0.20 0.33


0.90 1.10 0.40 0.60 0.10 0.40 0.56


1.45 1.75 0.65 0.95 0.20 0.50 0.95


1.81 2.21 1.05 1.45 0.25 0.75 1.27


3.00 3.40 1.40 1.80 0.25 0.75 1.90


3.00 3.40 2.30 2.70 0.25 0.75 2.79


4.20 4.80 3.00 3.40 0.25 0.97 2.79


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L W T1

Standard Name min

(mm)

max

(mm)

min

(mm)

max

(mm)

min

(mm)

max

(mm)

H

Max(mm)


4.25 4.75 6.15 6.65 0.25 0.76 2.18


5.20 6.00 4.60 5.40 0.25 0.95 1.65


5.40 5.80 6.00 6.80 0.50 1.00 2.00

CHIP CAPACITORS


Standard Name Z

(mm)

G

(mm)

X

(mm)

Y(REF)

(mm)

C(REF)

(mm)


1.15 0.25 0.40 0.45 0.70


1.55 0.25 0.65 0.65 0.90


2.55 0.65 1.0 0.95 1.60


2.95 0.65 1.45 1.15 1.80


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Standard Name Z

(mm)

G

(mm)

X

(mm)

Y(REF)

(mm)

C(REF)

(mm)


4.15 1.85 1.80 1.15 3.00


4.15 1.85 2.70 1.15 3.00


5.50 2.70 3.40 1.40 4.10


5.50 3.10 6.65 1.20 4.30


6.70 3.70 5.40 1.50 5.20


6.50 3.70 6.80 1.40 5.10

INDUCTORS


L W T1 Component Identifier

(mm) min

(mm)

max

(mm)

min

(mm)

max

(mm)

min

(mm)

max

(mm)

H

Max(mm)

1005 Chip 0.90 1.10 0.30 0.70 0.10 0.40 0.60

1608 Chip 1.45 1.75 0.65 0.95 0.20 0.50 0.95


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L W T1 Component Identifier

(mm) min

(mm)

max

(mm)

min

(mm)

max

(mm)

min

(mm)

max

(mm)

H

Max(mm)

2012 Chip 1.80 2.20 1.05 1.45 0.20 0.80 1.30

2520 Chip 2.30 2.70 1.70 2.30 0.20 0.50 2.20

3216 Chip

3225 Chip 3.00 3.40 2.30 2.70 0.25 0.75 1.35

4532 Chip 4.20 4.80 3.00 3.40 0.25 0.95 1.75

5750 Chip 5.50 5.90 4.70 5.30 0.30 0.80 1.80

6350 Chip 6.10 6.50 4.70 5.30 0.30 0.80 2.00

INDUCTORS


Standard Name Z

(mm)

G

(mm)

X

(mm)

Y(REF)

(mm)

C(REF)

(mm)

1005 Chip 1.55 0.25 0.70 0.65 0.90

1608 Chip 2.55 0.65 1.00 0.95 1.60

2012 Chip 2.90 0.50 1.45 1.20 1.70

2520 Chip 3.45 1.55 2.30 0.95 2.50


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Standard Name Z

(mm)

G

(mm)

X

(mm)

Y(REF)

(mm)

C(REF)

(mm)

3225 Chip 4.15 1.85 2.70 1.15 3.00

4532 Chip 5.50 2.70 3.40 1.40 4.10

5750 Chip 6.60 4.20 5.30 1.20 5.40

6350 Chip 7.20 4.80 5.30 1.20 6.00

TANTALUM CAPACITORS



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L W T TW Component Identifier

(mm) min

(mm)

max

(mm)

min

(mm)

max

(mm)

min

(mm

max

(mm)

min

(mm)

max

(mm)

H

3216 3.00 3.40 1.40 1.80 0.50 1.10 1.10 1.30 1.80

3528 3.30 3.70 2.60 3.00 0.50 1.10 2.10 2.30 2.10

6032 5.70 6.30 2.90 3.50 1.00 1.60 2.10 2.30 2.80

7343 7.00 7.60 4.00 4.60 1.00 1.60 2.30 2.50 4.30

TANTALUM CAPACITORS


Component Identifier

(mm)

Z

(mm)

G

(mm)

X

(mm)

Y

(mm)

C

(mm)

3216 4.40 0.80 1.25 1.80 2.6

3528 4.70 1.10 2.25 1.80 2.90

6032 2.55 7.25 2.25 2.35 4.90

7343 8.55 3.85 2.45 2.35 6.20


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METAL ELECTRODE FACE (MELF) COMPONENTS


L W T Component Identifier

(mm) min

(mm)

max

(mm)

min

(mm)

max

(mm)

min

(mm

max

(mm)

Component Type

1911 1.80 2.00 1.10 1.20 0.15 0.25 Micro MELF

3414 3.30 3.60 1.30 1.50 0.35 0.50 LL-34 Diode

3516 3.30 3.70 1.60 1.70 0.41 0.55 Diode

3520 3.30 3.70 2.00 2.10 0.30 0.30 Diode

7028 6.80 7.20 2.65 2.95 1.35 1.65 Resistor


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METAL ELECTRODE FACE (MELF) COMPONENTS


OPTIONAL DETENT PATTERN


(mm)

Z

(mm)

G

(mm)

X

(mm)

Y

(mm)

C

(mm)

1911(Micro MELF) 4.40 0.80 1.25 1.80 2.6

LL34 (Diode) 4.40 2.20 1.65 1.10 3.30

3516 (Diode) 4.50 2.10 1.85 1.25 3.30

3520 (Diode) 4.50 2.50 2.25 1.00 3.50


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(mm)

Z

(mm)

G

(mm)

X

(mm)

Y

(mm)

C

(mm)

7028 (Resistor) 8.05 3.55 3.10 2.25 5.80

SOT23


L W T A B H Pitch Component Identifier

(mm) min

(mm)

max

(mm)

min

(mm)

max

(mm)

min

(mm

max

(mm)

max

(mm)

max

(mm)

max

(mm) (mm)

SOT 23 2.60 3.00 0.41 0.55 0.35 1.30 2.90 0.55 1.35 0.95


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SOT23



Z

(mm)

G

(mm)

X

(mm)

Y

(mm)

C

(mm)

P

(mm)

SOT 23 3.75 1.25 0.65 1.25 2.50 0.95


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SOIC


L W T A B H P K Component Identifier

(mm) min

(mm)

max

(mm)

min

(mm)

max

(mm)

min

(mm

max

(mm)

max

(mm)

max

(mm)

max

(mm)

(mm)

Min

(mm)

SOIC28 10.00 10.65 0.36 0.49 0.40 1.10 7.60 18.10 2.65 1.27 0.10


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Z

(mm)

G

(mm)

X

(mm)

Y

(mm)

C

(mm)

E

(mm)

SOIC28 11.30 7.50 0.60 1.90 9.40 1.27


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SOJ


L W T A B H P Component Identifier

(mm) min

(mm)

max

(mm)

min

(mm)

max

(mm)

min

(mm

max

(mm)

max

(mm)

max

(mm)

max

(mm) (mm)

SOJ28 11.05 11.30 0.38 0.51 1.52 2.04 10.29 18.85 3.75 1.27


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Z

(mm)

G

(mm)

X

(mm)

Y

(mm)

C

(mm)

E

(mm)

SOIC28 12.00 7.20 0.65 2.40 9.60 1.27


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QFN


A B W1 W2 / T2 T1 H P Component Identifier

(mm) min

(mm)

max

(mm)

min

(mm)

min

(mm

max

(mm)

max

(mm)

min

(mm

max

(mm)

max

(mm)

max

(mm)

max

(mm) (mm)

QFN16 2.90 3.10 2.90 3.10 0.20 0.30 0.95 1.25 0.30 0.50 0.80 0.50


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Z1/Z2

(mm)

X1

(mm)

Y1

(mm)

X2/Y2

(mm)

C1/C2

(mm)

E

(mm)

QFN16 3.75 0.30 0.85 1.25 2.90 0.50


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PLCC


L1 L2 A B W1 T1 H P Component Identifier

(mm) min

(mm)

max

(mm)

min

(mm)

min

(mm

max

(mm)

max

(mm)

min

(mm

max

(mm)

max

(mm)

max

(mm)

max

(mm) (mm)

PLCC32 12.32 12.57 14.86 15.11 11.51 14.05 0.33 0.53 1.50 2.00 3.57 1.27


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Z1 Z2 G1 G2 C1 C2 X1 Y1 E Component Identifier

(mm) min

(mm)

max

(mm)

min

(mm)

min

(mm

max

(mm)

max

(mm)

min

(mm

max

(mm) (mm)

PLCC32 13.30 15.90 8.50 11.10 10.90 13.50 0.65 2.40 1.27


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BGA


A B Ball Size

H Row Pitch / Column Pitch


(mm) Ref.

(mm)

Ref.

(mm)

Nom.

(mm

Max

(mm)

Nom.

(mm)

BGA256 27.00 27.00 0.75 2.56 1.27


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C1/C2 X E1 / E2 Component Identifier

(mm) (mm) (mm (mm)

BGA256 24.13 0.60 1.27

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Design for Testability Guidelines

19 Design for Testability Guidelines

This document is basic guidelines for Testability of the circuit in PCB/PCBA and its implementation. It describes flow in implementing Testability of the circuit from Mechanical, schematic, Fabrication, assembly and Test engineer’s point of view. It is quick reference for the Logic and Physical Design engineer’s.

The term test point will be used to refer to any feature that is probed during electrical test, i.e. test via, test pad, through-hole lead. Test points can be utilized by all test process including ICT, Flying Probe Testing, and Boundary Scan.

• A test via is a plated through-hole with an exposed annular ring; the test probe strikes either the solder that fills via holes during processing or the outer edges of the empty via barrel.

• A test pad is a solid area of exposed metallization; there is no through-hole; the test probe strikes the flat surface of the feature.

Building test fixtures for almost anything is possible given enough time and money. However, using the guidelines presented here will help you design boards that are economical and reliable to test. In many cases you may not be able to fully follow the guidelines, but if you deviate as little as possible, you will achieve the best success

19.1 ICT (In circuit Test) Mechanical Guidelines

19.1.1 Probe Spacing

Ideally, boards should be tested with industry-standard 0.100" spring probes. These low-cost and reliable probes are designed to probe circuit points that are 100-mil (.100") or more apart from center to center. If it is not possible to have the luxury of 0.100" spacing, standard probes are designed for .075" access, .050" access, and even closer spacing is available. Note that as the probe size decreases, the cost increases and obtaining high reliability becomes more difficult.

19.1.2 Probe Access

All modern test fixtures are designed to accommodate, as the standard, bottom access to the UUT. Whenever possible, you should provide access at the bottom of the UUT for each network on the board. Fixtures can be designed to also have access to the top side of the UUT. However, due to the added complexity, non-bottom access increases the cost and decreases the reliability of the fixture.


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19.1.3 Test Pad Density

While doing Fan out after placement, plan to use the test pads/vias to start the coverage, see that all the test pads are not in the same area. If all the test pads are placed in one area of the board, the force from the probes will be concentrated on that area. This concentrated force may exceed the pressure pushing on the board, so it will not hold against the probes. The concentrated pressure may also cause board warping that can damage the board, components or solder joints. Therefore maintaining a maximum pad density of 30/inch² for an average PCBA is recommended.

• Provide test pads for component pins that are not connected or are unused. Shorts to unused pins can cause problems that are difficult to detect.

• All surfaces to be probed must be solder coated, or coated with an equivalent conductive, non-oxidizing surface.

• Leaving test points in the same location as the pervious revision or EC is recommended.

• There should not be any obstruction, including solder resist, within 0.003" around a test point.

• Placing all test nodes on one side of the board even by adding test pads where necessary is highly recommended. Dual access fixtures generally increase the test error probability and are very expensive to produce and maintain.

Probe Targets or Preferred Test Points

Assignment of test points should be prioritized in part by the type of test target. Maintain the following priority when assigning test points listed in descending order of preference:

• Test pad, round or square,

• Through-hole with a soldered lead,

• Open through-hole.

• Non-masked via

19.1.4 Test Pad Requirement:

Larger test pad diameter increases probing contact reliability and reduces fixture cost. For reliable probing, the probes need to have good targets. Each probe should contact a target .035" in diameter or larger. The targets should be as large as possible, ideally .050"-.060". When top probing an assembly, targets on the top should be .045" or larger.

For probing on soldered leads, ensure that the lead trim-length is consistent within plus and minus .030". Open through-holes should have a relatively small hole diameter so that the probe can contact the hole edge. For standard probing, the hole should be less than .050". Probing on leads of surface-mount-technology (SMT) devices should be avoided. Because of the variability of the placement and edge geometry, probing can be unreliable on SMT leads. Also, the probe can press the SMT lead to the pad, causing a bad connection to test well.


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19.1.5 Test Pad Diameter:

Test PAD

A = Minimum Test Pad diameter = 0.762mm (0.030")

B = Minimum Solder Mask and Silkscreen -

- Keep Out diameter = A + 0.152mm (0.006")

19.1.6 Test Pad to Test Pad Spacing:

The spacing between test pads dictates which style probe to use. 100 mil test probes provide optimum price, performance, reliability, and contribute to a robust test fixture. Use of 50 mil probes provides the worst price, performance, and reliability and requires regular special maintenance. Spacing less than 0.050" requires 50 mil probes and is discouraged. So, attempts should be made to completely avoid or minimize test pad spacing of less than 0.050".

D

A

B


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19.1.7 Test Pad to a Via Clearance

As shown in below Figure, the minimum spacing, D, between a test pad and via should be 0.010". However a spacing of 0.015" is preferred for proper clearance.

Test PAD VIA

Minimum test pad to via distance

19.1.8 Test Pad to Component Pad Clearance

As shown in below Figure, the minimum clearance, D, required between a test pad and a Component pad is 0.015". However a spacing of 0.020" is preferred for proper clearance.

Test PAD COMPO�E�T.

Minimum test pad to component pad clearance

D

D


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19.1.9 Test Pad to Edge of Secondary Side Component Clearance

As shown in below Figure, the minimum clearance, D, required between a test pad and edge of secondary or bottom side component is 0.030". However a spacing of 0.050" is preferred for proper clearance

Test PAD COMPO�E�T.

Minimum test pad to component body clearance

19.1.10 Test Pad to Secondary Side Trace Clearance

As shown in below Figure, the minimum clearance, D, required between a test pad and

Secondary or bottom side trace is 0.010". However a spacing of 0.015" is preferred for

proper clearance.

nce.

Minimum test pad to trace clearance

D

D


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19.1.11 Test Pad to Edge of Board Clearance

As shown in below Figure, the minimum clearance, D, required between a test pad and edge of board or any big aperture of the board is 0.040". However a spacing of 0.125" is recommended.

Test pad to edge of board clearance

19.1.12 Test Pad to Tooling Hole Clearance

As shown in below Figure, the minimum spacing, D, required between a test pad and a tooling hole is 0.125". However, a space of 0.200" is recommended. Benefit of this is it ensures that the test pad will have a probe assigned to it.

D

Test PAD

Tooling

Hole

D

D

Edge of BUT

Test PAD


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19.1.13 Test Pad to thru-hole device lead clearance

As shown in below Figure, the minimum clearance, D, required between a test pad and

Through-hole device lead is 0.125".

Test PAD Thu-hole Device lead

Minimum test pad to thru-hole device lead clearance

19.1.14 Test Pad to high components

The minimum clearance required between a test pad and a high component (> 0.2") is 0.200".

Edge of a gold finger to PTH test pad

As shown in below Figure, the minimum spacing between edge of gold finger and PTH test pad is 0.040" however a spacing of 0.050" is recommended.

Minimum edge gold finger to PTH test pad clearance

D

Trace

D


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19.1.15 Table for quick reference

PART TYPE BOARD SIDES

MINIMUM CLEARANCE FROM TEST POINT CENTER

NOTES

Short component

(height<=7.62mm (0.300"))

Both 0.762mm (0.030")

Includes IPC component placement acceptability, ICT probe radius, and ICT probing accuracy.

Bottom

(Primary probe side)

1.905mm (0.075") Tall component

(height>

7.62mm (0.300")) Top (Secondary probe side)

19.05mm (0.750")

Special test fixture features may be required. Consult for further details.

Adequate clearance critical for topside probes and fixture hold-downs, which may collide with tail components when the fixture lid is closed.

Bottom (Primary probe side)

1.905mm (0.075")

Overhanging heat sink

Top (Secondary probe side)

19.05mm (0.750")

Assumes heat sink placement tolerance=+/-0.762mm (+/-0.030").

Special test fixture features may be required. Consult for further details.

Adequate clearance critical for topside probes and fixture hold-downs, which may collide with tall components when the fixture lid is closed.

Board Edge Both 0.762mm (0.030")

Tooling Hole Edge Both 5.715mm (0.225")

Non-tooling Hole Edge

Both 0.762mm (0.030")

19.2 Design for Test (DFT) Deliverables:

DFT Software Tool: eM Test Expert V8G2 (Old name FABMASTER)

Required file formats: CAD output in ASCII format

Test Expert needs ASCII format outputs from CAD systems. Some of the CAD systems need to run scripts to generate the Test Expert needed file. Following list gives the list of files needed for the specified CAD tools.


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CAD Tool ASCII Output File

Cadence Allegro

<job name>.cad or

<job name>.val

Needs to run an extraction script (CDS2FAB) to extract the ASCII output.

Mentor 6.1 – 8.x

MENTOR ASCII File

Components file

Nets File

ASCII Parts file

Wires (traces) file

V7 Name

COMP_FILE

NETS_FILE

PARTS_FILE

WIRES_FILE

V8 Name

COM

NET

GEOM (Parts)

WIR (Traces)

Test Expert File

CF.VSS

NF.VSS

PF.VSS

ROUTE.VSS

Zuken-redac <job name>.udf – ASCII layout file

<job name>.bsf – ASCII technology file (layer count, units, etc.)

<job name>.mdf – ASCII representation of the footprints used in the design

(package description file). file (layer count, units, etc.).

<job name>.ccf file is the ASCII netlist.

Pads Power

PCB

<job_name>.asc

In addition to the ASCII CAD output, the following supplementary information required:

1) Schematic 2) BOM 3) NC drills 4) Fabrication drawing 5) Assembly drawing

19.3 ICT (In circuit Test) Electrical Guidelines

19.3.1 Tri-State Devices, Output Enables

Guideline: Wherever possible use devices with tri-state or output enable control instead of non-controllable devices.

Benefit: Tri-state and controllable devices provide a simple means of disabling surrounding components for in-circuit test.

19.3.2 Do Not Tie Control Pins Directly to Power or Ground Rails.


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Guideline: Enable, Set, Reset, Clear, and tri-state control pins must not be tied directly to a power or ground rail. As shown in below figure, this can be achieved by using individual pull-up/pull-down resistors. The value of the resistor depends on the power line the resistor is place and the capability of the system, the value of resistor will be calculated with the following formula

V=RI

Where “V” is the power line tied to the resistor and “I” is the maximum current the in circuit system can handle.

Benefit: Control pins that are not constrained to power or ground allow easy disabling.

Preferred way to wire control lines

19.3.3 Common Circuitry Must Have Unique Control

Guideline: As shown in the below Figure, devices sharing common circuitry must have unique control.

Benefit: Common circuitry that does not provide unique control imposes constraints that make initialization and test pattern generation difficult.

Preferred way to control common circuitry


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19.3.4 Break Feedback Loops

Guideline: Feedback loops must be capable of being broken. As shown in the below figure, this can be accomplished by inserting a tri-statable gate in the feedback path.

Benefit: Feedback loops make it difficult to isolate the DUT and can result in drive conflicts between the tester and the device, producing unstable test results.

Example of preferred feedback path

19.3.5 Clocks and Oscillators

Guideline: Clock circuits and oscillators must have the ability to be disabled. As shown in the below figures, a buffered clock circuit or an oscillator with a built in output control pin is preferred.

Benefit: Free running clocks or oscillators can prohibit in-circuit testing.

Preferred

VCC

CLOCK

CIRCUIT

LOGIC

CIRCUITS


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Preferred way to disable clocks

Preferred

LOGIC

CIRCUITS

ctl

vcc

gnd

OSC

VCC

Preferred way to disable oscillators

19.3.6 Tweaks

Guideline: Hardware tweaks such as those used to interrupt a PC run in order to isolate a clock signal must only be used as a last resort. If tweaks are utilized, avoid those that require a soldering operation. The preferred technique is to utilize a two-pin header that accepts a 2-pin jumper that can be manually inserted. If a soldering operation is required, do not solder directly to the PC board. Specify soldering terminals be used.

Benefit: Hardware tweaks require an extra process step to perform. Additional soldering may compromise the board quality and reliability. Using solder terminals will help maintain the board’s quality during the tweak installation solder operation.


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19.3.7 Three-Pin Polarized Capacitors

Guideline: It is strongly recommended that three-pin polarized capacitors be used instead of the two-pin types.

Benefit: In-circuit test techniques cannot, in every case, determine if a polarized capacitor has been installed backwards. By using three-pin packages, the chance that it will be backwards is reduced dramatically.

19.3.8 Logic Cell Programmable Gate Arrays (LCA)

LCAs are gate arrays that are configured on the circuit card by an external serial prom. In order to efficiently test this type of part, ATE must take control of the serial prom and the LCA.

Guideline: Provide access and a means to override the Serial prom Chip Enable and Clock outputs supplied to the Serial PROM by the LCA. Provide unique access to each of the Mode or control pin locations on the LCA.

Benefit: Configuration vectors and test vectors may be generated that will allow efficient testing of the component.

19.3.9 Boundary Scan Implementation

Guidelines:

¤ Boundary Scan implementation on custom devices should be tested along with the device BSDL file before circuit card assembly begins in order to avoid complex debug at the production stage.

¤ Group components with similar input power requirements and provide buffering between TDO of one group to TDI of the other.

¤ For chained devices, provide test point access so that, devices may be tested as individuals if a problem arises with chain testing.

¤ Install a Pull up resistor on TRST

¤ Ensure that all devices in the same chain are having the same TCK and TMS.

¤ Provide buffering of signals to compensate for fan-out and to provide a versatile interface between different logic families.

¤ It is essential that TCK is quiet and reliable.

¤ Files need to be IEEE JTAG 1149.X compliant.

¤ BSCAN signals must be independent of all other components signals.

Benefit: A correctly implemented Boundary Scan scheme will yield enhanced test coverage for minimal cost.


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19.3.10 FPGA's and Non-1149.1 ASICS

Tri-State Control Pin

Guideline: All device outputs must be tri-stateable by a single dedicated tri-state control pin without using the JTAG port.

Benefit: Place the device in a high impedance state to allow in-circuit testing of neighboring devices.

19.3.11 Pass-Through Mode

Guideline: As shown in the below figure, a pass-through mode should be designed into the device that allows signals to pass directly from input pins to outputs using minimal test vectors.

Benefit: Pass through mode allows pin fault coverage to be obtained easily for device inputs and outputs.

Example of a pass-through mode designed into an FPGA

(This specific architecture uses a 4-to-1 mux scheme to pass input signals to output pins in only a few vectors).

19.3.12 Identification and Revision Code

Guideline: Use an ID and Rev code.

Benefit: The ID and REV code features enable verification of the proper revision and differentiation of similar devices.


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19.4 Mixed Signal ASICS

19.4.1 Digital Testability

OR-Inputs/Muxed-Outputs

Guideline: Use OR-inputs and/or muxed-outputs where practical as shown in the below figure.

Benefit: In-circuit pin fault coverage can be obtained on digital pins using only a couple of vectors.

Example of using OR-inputs and muxed outputs for testability of digital signals

19.4.2 Analog Testability

Interpolator DAC Pin

Guideline: For interpolators bring the DAC output to a pin and provide a test point.

Benefit: Bringing the DAC output to a pin will provide allowances to perform DAC functionality testing at the board level.

19.5 PALS and GALS

19.5.1 Tri-State Control Pin

Guideline: All device outputs must be tri-stateable by a single dedicated tri-state control pin that is pulled up/down to power or ground by a resistor.


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Benefit: Place the device in a high impedance state to allow in-circuit testing of neighboring devices.

19.6 BGA devices with NAND-Chain Test Capability

19.6.1 Tri-State Control Pin/Sequence

Guideline: Tri-state function must be accomplished by using a control or test pin that can be pulled up/down to power or ground through a resistor.

Benefit: Place the device in a high impedance state to allow in-circuit testing of down stream devices.

19.6.2 Maximum Size Pin Group or NAND Chain Length

Guideline: The number of pins in any chain or pin group should not exceed 80 nodes. Multiple pin groups or chains are preferable in this case. Note: This item is usually not under the designer’s control but only to be aware that if a device is chosen that exceeds this requirement then it probably will have limited equipment choices for successful testability.

Benefit: Device chains in excess of 80 nodes place a high demand on in-circuit tester resources because all pins must be driven simultaneously. Following this guideline will enable this type of test to be performed on a wider range of test equipment with limited or reduced node resources.

19.6.3 NAND Chain Test Point Allocation

Guideline: In order for this test strategy to be successful 100% of all pins in each pin group or chain must receive a test point assignment. This must occur even if the device pin is not required for the functionality of the overall board circuit design.

Benefit: If even a single pin is not accessible the entire pin group or chain will be rendered un-testable.

19.7 Power & Ground Test Pad Requirements

19.7.1 Supply Power Probe Calculations

For all power sources there should be an absolute minimum of 2 probes + one extra probe for each amp (rounded up to the next highest integer) of current drawn from the source.

Example:

Vcc 5.0V @ 2.2 amps : Min = 2 probes

2.2 � 3 amps = 3 probes

Total = 5 probes


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19.7.2 Ground Probe Calculations

¤ One probe is required for each amp (rounded up to the next highest integer) of current drawn from all power sources.

¤ One addition probe is needed for each power supply.

¤ Add one ground return for every 32 nodes (rounding up).

Example: Two supplies:

Vcc = 5.0v @ 2.2Amps � 3 Amps

+12v = 12.0v @ 0.8Amps � 1 Amp

Number of Nodes = 1203 / 32 = 37.6 � 38

Number of Ground wires required: 3.0 Amps = + 03

1.0 Amps = + 01

Number of Supplies = + 02

Number of nodes = + 38

Total = 44

We recommend that an additional 10% be added to the above total to help resolve possible fixturing accessibility issues.

Notes:

There are 3 problems that result from not having enough ground probes connected to the board. They are:

¤ Power supplies may drop out of regulation.

¤ Ground bounce may appear between the board and the system.

¤ The quality of high-speed digital signals is affected.

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Design for Assembly Guidelines

20 COMPONENT AND ASSEMBLY ISSUES:

20.1 Considerations for Component Mounting:

Component mounting and attachment are fast becoming the most important element of printed board design. The issues have always been important because of component density and conductor routing considerations. However, an increase in the complexity of the assembly process occurs due to:

• The drive for more functions per assembly.

• Combing surface mount and through-hole components on one printed board.

• Using both sides of the printed board to attach the parts (impacts assembly, solder joint integrity, reliability and testing).

The tradeoffs to be made regarding component mounting must be considered early in design.

Through-hole components are mostly mounted on the side opposite to that which comes into contact with the solder. Automatic insertion techniques are preferred, so rules for these conditions should be taken into account when arranging through-hole parts. These rules include appropriate clearances for the insertion heads of the automatic equipment, and having sufficient clearance between the lead diameter and the components hold used for attachment and electrical connection. The orientation of the components is also important. This includes the direction in which the components are lined up electrically with respect to the polarity of polarized components to one another and usually with respect to the board edges. In addition, uniform component orientation, i.e. all pin #1s located at the lower left, reduces machine cycle time, thus controlling cost during the assembly operation.

The edge of the board becomes the design envelope. Except for connectors, components should not extend over the edge of the board or interfere with board mounting. Design for Assembly (DFA) principles dictate that the designer also know how the assembly will be manufactured. Automated techniques require that standard assembly panels be used to maximize the use and the efficiency of the equipment. Special fixtures can accommodate any shape, however, these fixtures add unnecessary cost to the assembly process. Thus the board perimeter at LMC (least material condition) should be the boundary that no component, at MMC (maximum material condition), extends beyond. Assembly equipment limitations must be recognized early in the design process. Mounting rails for the automatic machines may require additional clearance. All requirements should be documented on the assembly drawing.

There are many other parameters that must be considered for component mounting; component body centering, mounting over conductive areas, clearance between components, and physical support are just a few. When designing mixed assemblies that include standard SMT, fine pitch, BGA and CSP parts along with through-hole parts the designer must have close contact with the assembly manufacturing representative to ensure an assembly doesn’t require work-arounds of the process being used by the manufacturer.


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Another element of through-hole component mounting that must be considered is the lead clinching requirement. Is it allowed? Is it required? Will it interfere with the surface mount parts? Sometimes it is left to the discretion of the assembly manufacturer. If the requirements are restrictive they should be indicated on the assembly drawing. The designer should also be knowledgeable of electrical test requirements. Test point lands must be established before the design starts.

20.2 Automatic/Manual placement and Insertion:

There are many things that must be taken into account when determining the method of through-hole insertion. Manual insertion techniques, although they have greater flexibility for placing components very densely or close together, can be error prone. The need to reduce the possibility of placing a part in the wrong location has necessitated a great variety of manufacturing assembly aids.

These aids or systems help to conveyorize the process so that each operator on an assembly line has only a few functions to manage. Components are kitted into groups which, when kept to a minimum number of different or similar parts, are easy to manage.

Automatic component insertion is the act or operation of assembling discrete components to the printed board by means of electronically controlled equipment. The orientation of the components, the clearance between components, the sequence in which the parts are to be assemble, plus many more factors all become issues that the designer must address. The size of the board is also important since may assembly companies want to treat the boards in a panel format to ease board handling. The relationship between the board fabrication panel and the assembly panel, plus the amount of room needed for tooling, or conveyor guides, are issues that impact the design methodology and approval of the final layout.

The days when printed boards consisted only of through-hole parts are past. Today’s design have intermixed assemblies that mount both through-hole and surface mount parts. The parts that were only on one side of the board are now on both sides, thus the design process establishing parameters for component positioning must take into account the placement, insertion, and attachment processes used to develop the final assembly. Some design facilities pause after initial component placement in the CAD system to send a preliminary arrangement to the assembly company, thus creating a true concurrent engineering environment.

Lead clinching is another important consideration to be taken into account when deciding if a part is to be manually or automatically inserted. Most automatic equipment heads have the feature capability to clinch leads. They are trimmed to size and then clinched, or partially clinched to retain the parts during the solder operation. It becomes an important parameter for the designer to understand the exact methods for part retention in that the land size or electrical clearance of adjacent conductors can be affected. Manual assembly is less precise and requirements of the design should not exceed the physical dexterity of the operator.


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Last, but not least, is the relationship between the hole size and the lead diameter. In general, automated assembly requires a slightly larger hole than manual techniques. The larger hole is intended to account for the differences in machine accuracy versus printed board hole location accuracy. Some companies provide additional targets called Fiducials to compensate for hole to machine location mismatch. Other systems require that the hole is oversize from what is could be with manual insertion. But, it is important that the hole diameter should no exceed the lead diameter too much. If this occurs the solder might not stay in plated-through or unsupported hole. The maximum for automated attachment is usually 0.7mm (0.028”) larger than the lead.

Surface mounting (SMT) is the process of electrically connecting components to the surface of a conductive pattern that does not utilize component holes. The process requires placing the components on the pattern and attaching them using solder. The attachment process can take a variety of forms but fall into two distinct groups; those where solder is added to the joint and those where existing solder (tin and lead) is reflowed. The differences between manual and automatic placement depends a great deal on the method of attachment.

Manual placement has its limitations in speed and accuracy (even though some operators have excellent skills in positioning and hand soldering very small parts or leads to the surface of the printed board). To get started in SMT many companies first experimented with manual techniques. They positioned components into a location and added the solder with a fine tip soldering iron.

As the parts became more exotic or wave soldered, they used a small dot of adhesive to secure the part before soldering. So the process was one of positioning and soldering. If the solder was already on the land in the form of solder paste or a solid solder dot, the manual technique was to use a hot air device which reflowed the solder. This hot air technique is currently used in many assembly operations to remove and replace defective parts.

It is important to know the methods of attachment in order to take full advantage of the placement technology. Adding solder is done manually with solder paste dispensers (solder dot), or solder wire that contains the flux. Solder is also added automatically by:

• Sending the board through a wave solder machine – where a rotating solder wave or dual waves comes into contact with the components and the board.

• Drag soldering – where the parts are brought into contact with a stagnant pool of hot solder.

• Reflow soldering – requires that solder is on the land prior to component placement. Following component placement, the board must be exposed to a heat source in order to get the solder to liquefy or reflow. Techniques include hot air, vapor phase, infra-red, or a combination of these. The reflow may be accomplished in a normal or inert oven environment. A blanket or nitrogen gas has been used for the tin/lead reflow process. The technique varies for the higher temperature lead free alloy, and depends on the paste composition.


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• Pin in Paste is a process where solder paste is deposited on a through-hole land pattern prior to the component being inserted. The volume of paste is critical so that it fills the plated-through hole when the assembly is submitted to reflow.

• Solid Solder Deposition, or solder bumping, is another technique where the solder is added into a mask opening, reflowed and flatted. The solder bump is coated with flux which holds the component in place during the reflow process.

Automatic component placement is performed by machine that pick up parts from reels of tape, trays, or cassettes, hence the name pick-and-place. The placement is very fast and in most instances, very accurate provided that the board or panel is properly registered to the machine origin. The fastest machines are those that place discrete resistors and capacitors. These are called “chip shooters.” They place the parts into solder paste that is already on the board, or glue them on the side intended to go through the wave. Most of these machines use a vacuum pick-up so the heads do not require any special added clearance. However, some components require electrical test before they are placed and the pick-up tool must make contact with the electrodes of the chip in order to test the part.

More complex IC parts that are packaged in a variety of configurations are also placed automatically, though not as fast as the discrete chips. Most require that they are reflowed using solder paste or forms of solid solder already on the land. A few components, for example SOT’s and SOIC’s can tolerate the temperature of wave or drag soldering, and may be reflowed or have the solder added. These components are attached with adhesive to position them.

Very complex parts with may leads and small lead pitch require that the machine reorient itself to the exact placement locations. Typically, machines require 2 Fiducials in opposite corners. They are positioned near the fine-pitch part, and an optical TV camera senses their location and repositions the machine’s memory board and part location.

20.3 PCB AND ASSEMBLY PANELIZATION:

The definition of a panel is a rectangular sheet of base material, of predetermined size, that is used for the processing of one or more printed boards, and when required, one or more test coupons. Panelization is the term commonly associated with the production of bare boards. Palletization or assembly arrays are the terms usually associated with printed board assembly. The development of each panel has a set of rules to follow that make the process of building boards and assemblies more products ionized. Some of the rules deal with the extra material that is required around the border and the room between each of the boards. Techniques for separation must also be taken into account.

Board fabrication companies try to use the largest panel possible to make the most efficient use of the manufacturing process and ease printed board handling. The size is usually based on the common size sheet in the market place. In the United States the common sheet size is 36 X


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48 inches; in Europe and Asia the common sheet size is 1 meter square. The designer should be aware of the board size that the manufacturer of choice uses in production so they will be able to optimize the board to panel yield and cost relationships. There was a time that it was sufficient to simply take the board dimensions, divide them into the fabrication dimensions, and allow sufficient room for borders. The issues are more complex today since many assembly companies do not want to assemble boards in individual format. They also want boards delivered in arrays.

The use of the largest panel in board fabrication provides the most effective labor cost per unit area. The industry processes panels. Being able to get twelve boards on a panel instead of six (3 X 4 versus 2 X 3), immediately increases the yield by 100%. The most common panel in the US is 457 X 610mm [18 X 24 inches]. Some of the processing equipment can accommodate larger panels, however, human factors such as strength, reach and control, preclude the use of much larger panels, Borders and margins are usually required and range between 9.5 to 38 mm [0.38 to 1.5 inches]. Tooling holes, coupons, and other manufacturing entities such as serialization or customer control numbers are also contained in the borders of the panel.

Separating boards or assembly arrays from the fabrication panel varies depending on the next use of the board, material, the shape and size, and volume of production. Higher volume production requirements utilize punching and blanking dies to excise boards, or assembly arrays, from fabrication panels.

Fixturing is relatively expensive and requires careful maintenance to assure good quality board edges.

Freshly sharpened blanking dies will generally provide a relatively smooth board edge. However, as the die is used, the board edges tend to roughen with exposed broken fibers.

Scoring and routing are two of the most common methods used for excising printed boards or assembly panels. The easiest way to separate the board is to score each side with a diamond grinder and break the boards or panels apart. The board must be square or rectangular, in shape, in order to use scoring and care is required to not have conductors too close to the scored area, as the score wheel is chamfered. It is required to score the board on each side to approximately 1/3 of the thickness. If the boards are routed, an amount should be left between the boards to accommodate the router bit. This is usually 4.8, 5.0 or 6.3 mm [0.19, 0.20, or 0.25 inches]. When boards are routed the edges are usually very smooth. Scoring leaves the edges a bit rough where the remaining board thickness has exposed broken fibers.

Assembly arrays also require borders but these are usually related to the conveyor of the assembly machines. The borders also contain tooling holes or Fiducials. Borders are only on opposite sides of the panel where the conveyer grips the panels, however, some material is necessary at the leading and trailing edge where the final board comes close to the panel edge. The relationship of the final board and the two panel concepts must be understood and considered in the design to maximize the manufacturing operations. Some companies find it


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useful to develop a Panelization drawing in order to maintain control of the tooling features of the assembly panel.

20.4 PRINTED BOARD AND ASSEMBLY VIEWING PRINCIPLES:

When only through-hole assembly existed, the viewing principles were fairly straightforward. One viewed the board from the component side and the opposite side was the solder side. With the advent of surface mounting, the definition was no longer as clear. New terms were needed as were new rules for identifying each side. The term primary side replaces component side, and the term secondary side replaces solder side. The primary side is the side of the packaging and interconnecting structure (printed board) that is so defined on the master drawing. It is usually the side that contains the most complex or the largest number of components. In any case, it is the side the designer determined to be the most critical. The secondary side is opposite the primary side, and when viewed from the primary side, will appear mirrored, as will the secondary legend and secondary solder mask.

The design dictates how each layer should be named. The designer develops the assembly drawing so in many cases the reasons for selecting one side over the other is related to the intensity of the assembly operation. It is conceivable that the primary side could be the side opposite the through-hole components even though that side has, for example, only one component, a microprocessor. That is the side the designer wanted to view, as the layout proceeded. Primary and secondary sides should not be confused with primary and secondary datums. The datums are used for dimensioning purposes. The primary datum plane is that side which is opposite the primary side.

The datum features are used to position the printed board in relation to a set of three mutually perpendicular planes. Typically, printed board drawings are oriented with layer one facing up. This orientation establishes the backside of printed board as the first (primary) of the three required datum planes according to ASME Y14.5M. The other two datum planes (secondary and tertiary) are typically established using holes or etched features of the board. There are then the datum features that set up planes from which all dimensions are determined. All of these conditions are used to convey intent to the manufacturer of the Board or the Assembler. They take the information and establish the panels for board fabrication and board assembly. Nevertheless, the master drawing descriptions form the final accept or reject criterion for the final product.

Understanding how layers are viewed and numbered is important to maintain consistency in communication between design and manufacturing. Conductive layers are numbered sequentially staring with the primary side as layer one. If there are no conductors or lands on the primary side, then the next conductive layer becomes layer one. Nonconductive layers are numbered after all the conductive layers have been identified, starting over at the primary side. Nonconductive layers are those for which there is an image or dimensional configuration in the secondary/tertiary datum planes. Legend, Soldermask, cover coat, or any layer that remains with the board is numbered according to these principles.


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Sequential layer conventions only apply to things that stay with the board. Data Layers for temporary masking, solder paste stencils, hole drilling templates can be numbered in any fashion because, as of this date, there is no industry-accepted consensus standard.

20.5 COMPONENT SELECTION & LAND PATTERN DESIGN

20.5.1 SMT component Selection:

1. Avoid using large leadless ceramic devices due to CTE mismatch with standard laminate materials (example FR-4).

2. The use of BGA devices is highly recommended in place of peripheral leaded

Components (QFPs, PLCC, etc.) with lead pitch less 0.020. (0.5mm).

3. Use components with tin/lead lead finishes only. Avoid the following lead finishes:

Palladium, Tin Palladium, and Alloy 42.

4. Labels on SMT components must be centered to present a flat surface for pick and place equipment. The label must be larger than the pick up nozzle of the SMT equipment to avoid vacuum leaks and the subsequent dropping of the part. Consult with manufacturing engineer for specifics of nozzles used.

5. All SMT parts should be supplied in tape and reel format as a first choice. Tape and reel allows the fastest machine cycle time. Second choice is SMT trays. This is slower than tape and reel, but many larger components are only packaged in this manner. Make sure trays are machine capable. Last choice is in tubes. Tubes are prone to jamming and bending leads. Most plants have discarded tube-handling equipment and will attempt to Tape and reel the components causing delays and additional cost. Never supply SMT components in bulk unless equipment to handle the bulk components, such as bulk feeder, is available.

20.5.2 Component Mix

The mix of surface mount and through-hole components on a PCB can dramatically impact assembly costs. Refer to the process hierarchy for the preferred combinations of types of components for each side of the board. The combinations closer to the top of the list tend to be less expensive; however, the level of automation required is also a key factor affecting overall cost.

20.5.3 Process Compatibility Requirements

Components must be able to withstand the manufacturing process and temperature

profiles. It is important to note what soldering temperatures the component will be exposed to during component selection.


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20.5.4 Non-Preferred Components

Follow these guidelines to choose components to help minimize assembly costs on a PCB:

• Avoid the unnecessary use of discrete component sizes below 0603.

• If sockets must be used for leadless components, ensure that they allow a hand-held

diagnostic probe to make connection with the socket leads.

• If using SMT connectors or non-standard parts such as DIP sockets or EMI fences, select parts designed for auto-insertion.

• Avoid SMT components at 16 mil pitch or less.

• Avoid using MELF components due to poor yield. Use alternative SMT packages instead.

• Avoid using sockets. These increase the cost of the board due to added material and

labor.

• Avoid using tall SMT and Paste-in-Hole components as they tend to shift in handling and during transit on the conveyor. This is particularly important for high volume production.

• For fine pitch leaded components, the lead coplanarity is a critical factor in high yield

assembly. Avoid using leaded parts with lead coplanarity > 0.10mm (0.004"), which do not conform to JEDEC Publication 95, Section 4.4.

• Avoid using components that do not have orientation or vendor markings.

• Avoid using components that require special tooling for placement or insertion.

20.5.5 Land Pattern Design:

One of the most critical Design for Assembly considerations is land pattern design. A well-designed Land pattern:

. Consistently produces reliable solder joint

. Accommodates PCB manufacturing tolerances

. Accommodates placement equipment tolerances

. Is robust to component dimensional variation

. Minimizes assembly defects and optimizes inspection

. Facilitates defect reworkability

. Enhances heat transfer to the PCB, etc.


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20.6 COMPONENT PLACEMENT

20.6.1 Primary vs. Secondary Side Placement

PTH Component Placement

Where possible, avoid placing soldered PTH components on both sides of the board. If

Components with through-hole pins are required on both sides of the board; they should not be placed back-to-back with the pins sharing the same holes. This includes combination parts with both SMT and PTH pins, e.g. with PTH grounding pins.

Height Limitations

See Table below for placement limitations due to height restrictions.

Table : Height Restrictions

Overhanging devices and ICT

Place overhanging devices/hardware (such as heatsinks that are larger than their

corresponding components) on the side opposite to the primary ICT probing side. For example, usually ICT probing is done only on the bottom side of the board. In that case, it would be preferable to place components having overhanging heatsinks on the top side of the board.

Wave Soldered SMT Components

The component packages detailed here are those that can pass through a full solder wave during assembly, i.e. those that can be placed on the solder side of the board when wave


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soldering will be used. These components are attached to the board with adhesive during the SMT process.

Table: Wave Solderable SMT Components

SMT Weight Limits for Side 2

When designing a double-sided reflow board, ensure that components on the bottom side of the board will not fall off during the second reflow cycle. The weight of the component in relation to its solderable surface area determines whether there is enough surface tension to hold the component to the board. Place all components that will fall off on the same side of the board to be assembled during the second SMT pass. Refer to Figure 1 for a graph of package weight limits. Calculate the SMT component weight limit for the B-side as follows:

Note: If the actual weight is greater than the allowable weight, the part WILL fall off.

Heat Dissipation

It is preferred to have high-power parts (i.e. parts requiring heatsinks) placed on the top-side of the card for better heat dissipation within an enclosed test fixture during board testing. This is especially important if there is no provision of a low-power or sleep mode to prevent excessive heat generation.

Parts with Large Variations in Position

Parts with > 0.100" variation in body position should be evaluated, as they may interfere with ICT testing. Eliminate/replace these parts, or place on "top" side (Non Probing Side) if possible. Examples of potential problem parts: PTH soldered parts (e.g. parts that float in wave solder), tall parts that may lean over (e.g. standing TO220, PTH capacitors), manually placed or soldered parts, EMI shields, glued heatsinks, and other mechanical hardware. Impact on "probe" side of board is potential interference between part and milled-out fixture, and possible board damage. Impact on "top" side of board is potential interference between part and push


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fingers or other fixturing mechanical parts (including Opens Xpress and TestJet probes), and possible board damage and/or loss of test coverage. Large variations in body position can be more tolerable on the "top" side, if the test fixture is designed for this.

General Component Spacing/Orientation Guidelines

Component spacings are dictated by three factors:

• Component placement accuracy.

• Rework access.

• Inspection (visual and automated).

In order of preference, ensure that:

• All manually assembled polarized components have the same orientation.

• All manually assembled components in the same package have the same orientation.

• All manually assembled components have the same orientation.

• All components that are polarized have the same orientation.

• All components with the same package style have the same orientation.

• All components have the same orientation.

In addition:

• Components may overhang the edge of the PCB, but they may not hang below the plane of the PCB. Components below the plane either restrict card processing and fixturing or make it impossible.

Component Distribution

Follow these guidelines for component distribution:

• Distribute components evenly across the board surface to result in a more even thermal profile across the board and to improve solder joint quality.

• Unpopulated areas of the PCB may be prone to overheat and thermal damage.

• When possible, keep large and heavy PTH components distributed towards the card

edges. This lessens the degree to which the card warps as it travels through the machine.

• When possible, keep PTH components grouped together. This will: create benefits in tool design, improve speed and accuracy during component insertion, and improve quality and cycle time during soldering processes.

Component Spacing Matrix

Note: Distances are always from the part or land (whichever is bigger) to the next part or land (whichever is closer).

Adjacent Tall Components

Because soldering irons are used for most repair operations, orient discrete components, especially ones between two tall TH parts, to allow for soldering iron accessibility.


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Figure. Discrete and Tall Component Orientation

In the instances where the spacing matrix is not followed for small SMT components to tall components, one option to allow repair access is to orient discrete components parallel to the tall components.

Minimum Distance between Components:

For better machine programming, component verification and placement accuracy, rework, cleaning, test, etc. a minimum distance between components must be maintained. The required minimum distance is a function of device profile, shape, orientation, soldering options (reflow, wave, hand soldering), cleaning and overall PCBA configuration. The recommended minimum distance between components for primary or top and secondary or bottom side are provided in Table 1 and Table 2 respectively. Three spacing specifications, namely Preferred, Acceptable, Violation, are provided in both Table 1 & Table 2.

Violation: spacing below this limit is a complete violation and can have detrimental effect in the manufacturability, testability or reliability of the product resulting in significant increase in manufacturing cost.

Acceptable: any spacing above the violation limit that is expected to offer manufacturing benefits. Generally, manufacturability gains are expected to scale up with larger spacing.

Preferred: is the most generous spacing range that generally simplifies manufacturability.

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Table 1. Recommended Minimum Distance between Components on PCB Primary or Top side

NOTES: Distances between components are based on closest features whether it is the component or component land.


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Table 2. Recommended Minimum Distances between secondary side SMT components for wave soldering.

NOTE:

* All dimensions in mils

* The dimensions listed above for SMT chips refer to the minimum distances between devices to prevent component shadowing during wave soldering.

* For double-sided SMT without wave soldering use spacing provided in Table 1.

* Do not mount PGA, axial, DIP or other through hole devices on secondary side

20.6.2 COMPONENT ORIENTATIONS

The zero component orientations expressed in IPC-7351 are defined in terms of the standard component CAD library with respect to a given PCB design. Recognizing

that a single land pattern may be used for the same component part from different suppliers and that each component supplier may have different orientations on their reels or that the components may come in trays, there exists the possibility that the PCB designer loses the ability to reference a single land pattern if the zero rotation of a part is according to the method the component is delivered to the assembly machine. Since the CAD library contains a single land pattern, the zero component rotation is thus defined according to the CAD library.


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Subsequently, component suppliers can identify the orientation of the parts on the reels by associating the placement of the part on the reel to zero orientations defined in IPC-7351. If pin 1 is at the lower left as defined by the pick and place machine tape and reel, for example, then the component on the reel is rotated 90° counterclockwise from the zero rotation given in IPC-7351. Standardizing the orientation of components for the installation and utilization of various packaging methods, such as tubes, trays or tapes and reels, among the

variations of automated assembly equipment existing today is outside the scope of this document.

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Figure 1-1 lists the most commonly used parts and their proper zero component rotation.


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20.7 ASSEMBLY CONSIDERATIONS FOR SURFACE MOUNT

20.7.1 TECHNOLOGY (SMT)

The smaller size of surface mount components and the option of mounting them on one or both sides of the packaging and interconnecting structure reduces board real estate significantly. The type of SMT assembly is basically determined by the type of surface mount components to be used.

20.7.2 SMT Assembly Process Sequence

The SMT assemblies are soldered by reflow (infrared, hot air convection, laser, conduction, vapor phase, and/or wave soldering processes) depending upon the mix of surface mount and through-hole mount components. The process sequence for one-sided SMT is shown in Figure 1. Solder paste is applied, components are placed, the assembly is reflow soldered and cleaned. For two-sided SMT assemblies, the board is turned over and the process sequence just described is repeated. The assembly process for two-sided SMT is simply a sequential combination of SMT processes; however, component weight vs. surface tension should be calculated to determine if heavy components will require additional reinforcement prior to the second reflow soldering process.


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Fig.1 Typical Process Flow for Full Surface Mount Type 1b and 2b Surface Mount

Technology

The process sequence for surface mount with through-hole or pin-in-hole (PIH) component technology is shown in Figure 2. Adhesive is applied and the surface mounted components placed. The adhesive is then cured, and the board is inverted to receive the through-hole component leads automatically or by hand insertion. After lead clinching (if required), and with the through-hole components on top and the surface mount components beneath, the board is typically wave soldered. An alternative sequence is to reverse the initial stages i.e., insert (and clinch) the through-hole components before attaching the surface mounted components and then wave soldering.

Finally the assembly may be cleaned, inspected, repaired if necessary, and tested, though not necessarily in that order.

Figure 2 Assembly Process Flow for Two-Side Surface Mount with PIH


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20.8 PCB ASSEMBLY DRAWING NOTES

Include the following items on fabrication drawings as indicated.

• Reference IPC-A-610 workmanship for acceptability and note any waivers/exceptions (e.g. hole fill on thick boards).

• When possible, use the BOM to control PCA, PCB, and Schematic Drawings. When using the PCA drawing as the control, ensure that the other documents are referenced.

• Ensure that all required labels are identified on the assembly drawing, including programmed parts if their labeling is not controlled separately.

• If the label orientation is critical, show sample text (i.e. ABC123) on the label.

• Identify any plated holes that must not be solder filled. (Avoid this practice, as it can add cost).

• Identify any special paste, soldering, or placement requirements where combination footprints are used (i.e. for memory components with different lead counts on the same land pattern).

• Indicate the datum location.

20.9 ASSEMBLY PANEL DRAWING

If panelization is done then the following guidelines apply:

1. The drawing must be approved by both the PCB supplier and the Assembler.

2. The drawing must specify the following:

• Overall panel dimensions

• Datum within one card image (non-plated primary drilled hole)

• Assembly panel datum

• Chamfered or rounded corner dimensions

3. If required include details on the following:

• Scoring detail, showing total angle, remaining material, and tolerance on both. For reference see the score angle detail in section 5.8.2.

• Break-away details, if not included in the drill file, showing drill and slot size and location from the datum. For reference see the break-away detail in section 5.8.3.

• Routing detail (include pre-route width, and location)

• Fiducial size and location

• Tooling hole size and location

• Chamfered or rounded corner dimensions

• Step and repeat dimensions from the assembly panel datum


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20.10 HARDWARE ASSEMBLY INSTRUCTIONS

The following may or may not be included as part of the PCA drawing:

• Identify any hardware by part number or by BOM item number.

• Where critical, identify the assembly sequence.

• Identify torque requirements for all screws, nuts, and bolts.

• Identify the maximum allowable lift and tilt for all connectors.

• For thread lock and adhesives, where critical, identify the volume or weight to be used.

• Where applicable, identify the temperature and cure time requirements for adhesives.

• Identify the locations for jumpers to be fitted. In the case of connectors, identify the jumper’s keying.

• Identify whether components that use process seals (i.e. switches, speakers, and so on) should be removed prior to shipping, or whether they should be shipped with the card.

• Where necessary, specify any orientation requirements of the finished assemblies in the packaging.

• Ensure that hardware drawings clearly specify all critical dimensions and tolerance information.

• Clearly indicate plating thickness and tolerance on the individual part drawings for all plated mechanical parts.

• Indicate which labels are required and their location.

• Reference any relevant specifications, such as corporate or industry workmanship standards for mechanical assembly, or cosmetics.

20.11 DESIGN FOR ASSEMBLY (DFA) O/P DATA REQUIREMENT

DFM Software Tool: Valor Trilogy 5000 version 6.01B

Required file formats: ODB++ (i.e. _.tgz)

The DFA team uses Trilogy 5000 to perform DFA analysis of circuit assemblies. This tool requires ODB++ formatted files in order to conduct the analysis. While most CAD tools in use in the EMS industry can output in ODB++ format the DFX team can do the conversion if native CAD files are received. In such a scenario please comply with the following table, which lists the ODB++ data set formats required for each CAD design tools:


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Besides the above-mentioned data sets, the system also requires the following additional information regardless of CAD tools used. In order to create ODB++ intelligence and perform DFA analysis, the following lists the additional information needed:

1) Approved Vendor List (AVL) – Manufacturer, Manufacturer part number (mandatory)

2) Bill of Material (BOM) – Customer part number, quantity, ref. designators (mandatory)

20.12 REWORK

The repair/rework of surface mount assemblies requires special care in design and practice. Because of the small land geometries, heat applied to the board should be minimized. There are various tools available for removing components. Resistance heating tweezers are usually used for removing surface mounted components. Various types of hot air/gas and IR systems are also used for removing surface mounted components. One of the main issues when using hot air/gas devices is preventing damage to adjacent components. Refer to IPC-7711/21. There are four basic requirements for a successful rework; good printed board design layout, selection


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of the correct rework equipment or tools, sufficient manual skill, and adequate training. Successful removal of large multi-leaded integrated circuit packages involves the use of hot gas or heated electrode tools. Sufficient clearance around the package to permit the re-work is essential. Clearance should be provided completely around the device as identified in the standards as the ‘‘courtyard manufacturing zone.’’

20.13 Heatsink Effects

Large ground planes or heatsinks will conduct heat away from the component being reworked if present in a printed board substrate. Extra heat, perhaps for longer periods, is then required which, in turn, can lead to damage to components or the board. The fact that the solder joints may not reach reflow temperature is no guarantee that the component or the board has not been overheated. Heatsinking effect is a design problem which must be tackled at the printed board layout stage. Whenever possible, any component termination which may not rework, including leaded-through hole type, should be thermally isolated from any ground plane or integral heatsink by a short length of copper conductor.

20.14 Dependence on Printed Board Material Type

To ensure minimum damage to the printed board during rework, base laminate should be a good quality resin and reinforcement type from a high copper peel strength material. High packing density is required. The use of inferior laminates can easily lead to problems with lands peeling away during rework. This may result in either scrapping of complete assemblies or expensive repair of damaged copper area. For boards having high thermal mass such as middle-core types or those with large area ground planes, To avoid employing a tool with high heat input rate, the use of a hot plate to provide background heating is essential.

20.15 Dependence on Copper Land and Conductor Layout

The space on a board is at a premium or single conductors must be kept very short. Designers will often route a conductor between adjacent device land space at a pitch of the component device being placed. In such cases, conductors should be covered with a soldermask to minimize the risk of lifting conductors during rework operations.

Routing conductors between lands at 1.0 mm pitch and below increases the risk of damage to the conductors during the rework operation.

20.16 Design Considerations for Repair and Inspection

* There are two main methods of removing and replacing a defective component. For simple reworks and small parts a soldering iron or hot air pencil is used to heat the joints locally. It is important that access for these devices is given and no parts that may be damaged by the heat (such as plastics) are in danger of coming into contact with the iron.


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* It is important to allow enough room around components for the rework nozzle for BGA type rework. Further, clearance around components may be required to minimize undesired and adjacent component Reflow.

* For component replacement the site must be prepared. There are various replacement site preparation techniques. The most common method involve screen-printing solder paste with a .micro stencil, placing the new part and reflow. A minimum clearance of 0.300. Around the component location may be required for printing and reflow.

* For visual inspection and repair accessibility, a maximized view angle and spacing of 0.250 to 0.300 is recommended between high profile components such as PLCCs and ICs as shown in Figure 3

Figure 3 When a large part is too close to a small part, joints cannot be inspected or reworked.

* A minimum spacing of 0.050 between chip devices and a minimum clearance of 0.200 between a PTH lead and nearest component body is recommended for repair without damaging adjacent component due to burning or solder splash.

* Design ground planes to minimize thermal heat sinking effects. Component leads should not be connected directly to a large ground plane. Instead, device leads should be thermally isolated by using short conductors to ground as shown in Figure 4. Minimizing the time and temperature necessary to repair a defective site reduces the likelihood of damaging the PCB or adjacent components.

Figure 4: Thermal Isolation of Ground Planes


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Hot Air Rework Station

Hot air rework stations are used to remove & replace large devices such as QFP’s & BGA’s, but can also be used for smaller devices such as CSP’s, connectors, etc. The basic principle of removal & replacement is shown in Figure 5. The board is first pre-heated, to reduce stresses on the board, and a nozzle fitted to the part size is brought down over the component. Hot air or nitrogen is blown through the nozzle to heat the part to the reflow temperature. Once the solder is molten a vacuum nozzle lifts the part from the board completing the cycle. Before a new device is placed, the rework site (where the part was removed from) must be cleaned. This usually involves removal of the excess solder left on the pads followed by application of solder paste prior device placement. The solder paste is usually applied using a “micro-stencil”. This is a small section of stencil, similar to a screen-printing stencil, with the necessary apertures. The stencil fits over the site area and is manually aligned and solder paste is printed onto the pads

Figure 5: Hot Air Reflow Process

It should be noted this method is designed to offer primarily localized heating. However, it is possible that parts close to the part being heated, or on the opposite side of the board, may also reflow and may be displaced or removed by accident

dfx guidelines

Documents

long axis perpendicular

electronically controlled equipment

planar surface perfect

free laminate characteristics

high impedance state

fine pitch qfps

assembling discrete components

precise dimensional requirement