04/27/2023 1

KLE Society’s B.V. Bhoomaraddi College of Engineering and

Technology,Hubli

High speed op amp with different compensation techniques

Under the guidance of Dr. R B Shettar

Mentor:Rakesh Sawant

By, Mr. Abhishek C Math

04/27/2023 2

About Internship Introduction Objective Literature Survey Frequency Compensation Compensation Techniques Design plan Results Layout Conclusion References

Overview

04/27/2023 3

Company : SmartPlay, founded in 2008, currently has design centres at

San Jose, San Diego and Austin in the US, and at Bangalore and Greater Noida in India.

CEO: Pradeep Vajram. SmartPlay Technologies is an established design services

company with expertise in digital, analog, wireless software and system design.

It is ranked as second largest VLSI Design service company in India by Cyber Media Research Ltd.

Number of employees: +1200

About Internship

04/27/2023 4

ServicesSmartPlay offers a comprehensive range of services across multiple industry segments:

04/27/2023 5

At present, they catered to close to 30 clients in the US, India Taiwan, Japan, Korea and China. 

The main Clients : Qualcomm Broadcom Texas Instrument Intel NXP Semiconductor AMD

Clients

04/27/2023 6

Where I was

Mixed Analog Mode Design

Digital Domain

04/27/2023 7

Task

Design of high speed two stage op amp with different types of

compensation circuits .

04/27/2023 8

Op Amps are the most versatile and integral part of many analog and mixed signal system.

They are employed from dc bias application to high speed amplifiers and filters

General purpose op amps can be used as summer, buffer, integrator, differentiator, comparators and many other applications

Introduction

04/27/2023 9

Transient FrequencyThe expression for a short channel MOSFET transitionfrequency (fT) and open-loop gain (gm*ro) are given as

Important!!

Therefore from the above eqn we can see that scaling down of feature size results in higher fT

04/27/2023 10

Must use minimum length devices Larger overdrive results in faster circuits For minimum power use minimum size devices - For nm CMOS minimum (drawn) W is, generally, 10 times

minimum L

Biasing for high speed

04/27/2023 11

Open loop gain trends in future CMOS process

The projection of open-loop voltage gain drops from CMOStransistors.

04/27/2023 12

Transistor transition frequency (fT) trends in future CMOS processes

04/27/2023 13

To design the high speed two stage op amp with different types of compensation circuits like

1. with nulling resistor 2. with voltage follower 3. with current buffer

and the optimized layout design.

Objective

04/27/2023 14

Parameters TargetSupply voltage = 1.8V +/- 10%Vin,cm =1.2V +/-10%DC gain > 50dBUGB > 1GHzPM > 60degSettling time < 3nsCL = 1pFTechnology = 130nm

Specification

04/27/2023 15

Literature surveyStability of an opamp

Closed loop response

“Barkhausen’s Criteria”.

04/27/2023 16

Time-Domain Response of a System Versus Position of Poles

The location of the poles of a closedLoop system is shown

04/27/2023 17

One-Pole System(one-pole feed forward amplifier)

one pole system isUnconditionally Stable.

04/27/2023 18

Two-Pole System

The system is stable since theloop gain is less than 1 at a frequencyFor which the angle(βH(ω))=-180.

When β is reduced,the system becomesmore stable.

Assumption:β does not dependon frequency.

04/27/2023 19

04/27/2023 20

The pole locations of the classical second-order homogeneous system

The locations of the poles are

If β=0, s1,2=ωp1,ωp2

04/27/2023 21

If ζ ≥ 1, corresponding to an overdamped system, the two poles are real and lie in the left-halfplane

For an underdamped system, 0 ≤ ζ < 1, the poles form a complex conjugate pair,

04/27/2023 22

04/27/2023 23

Transient Response Versus PM Peaking is usually correlated with ringing in

the time domain!

PM=60o, usually the optimum value.

04/27/2023 24

Frequency Compensation Reason for frequency compensation:

◦ |βH(ω)| does not drop to unity when <βH(ω) reaches -180o.

◦ Possible Solution:

(Push PX Out) (push GX in)

04/27/2023 25

Miller Theorem

The method that “transforms” a floating capacitor to two grounded capacitors, thereby allowing association of one pole with each node

04/27/2023 26

Two stage OTAWithout Rz

04/27/2023 27

Small signal analysis

The small signal transfer function for the two stage miller compensation

Compensation capacitor (Cc) between the output of the gain stages causes pole-splitting and achieves dominant pole compensation.

The first pole is located at

The second pole is located at

An RHP zero exists at

04/27/2023 28

04/27/2023 29

Pole splitting with CcPole splitting with gm2

04/27/2023 30

What is the origin of the positive zero??

04/27/2023 31

Origin of positive zero

This is the result of the feedforward current which adds extra phase margin -90deg

04/27/2023 32

The different types of compensation circuit to remove zero is With nulling resistor

With current buffer

With voltage buffer

Types of compensation techniques

04/27/2023 33

With the nulling resistor

If Rc=1/gm2 ; Z=infinity

If Rc>1/gm2 ; Z=LHP

This resistor causes some cancellation of the effect of the feedforward by thefeedback.

Z=1/Rc*Cc

04/27/2023 34

Let us assume that Z>=10GBW

Max and Min Rc

04/27/2023 35

Let us assume that Z>=10GBWFor 60deg phase margin we have Cc>0.22CL I5=SR*Cc

Design plan

For M3,M4

For M1,M2

For M5

For M6

For M3,M4

Gain

04/27/2023 36

Another choice of Rc is to make z1 cancelP2:

z1=gm6/CC(1-gm6Rz) ≈ - gm6/(CL+C1)

Rc = gm6CC

CC+CL+C1

04/27/2023 37

WKT

Optimum design for high GBW

AssumeTherefore

04/27/2023 38

Nulling resistor

Devices Values (W/L)um

(W/L)1,2 12/0.4(W/L)3,4 42/0.8(W/L)5 18/1(W/L)6 22/0.16(W/L)7 23/1

04/27/2023 39

With current buffer

The compensation current is indirectly feedback from low impedance nodeThe RHP pole zero can be eliminated as the feedforward current is blocked

by the common gate amplifierNode V1 is now not loaded by the compensation capacitor (as previously)

and thus results in a much faster second stage and increased unity gain frequency

04/27/2023 40

Small Signal AnalysisCc

gm1Vd

R1 C1

V1 VA

gmcVA

roc

1/gmc RA CA gm5V1 R2CL

Vout

TAKING KCL AT EACHNODE

04/27/2023 41

Simplified Transfer Function The transfer function can be

simplified and approximated as:-

The coefficients can be evaluated as

Evaluating the poles and zeros Assuming the pole |p1| >> |p2|, |p3|

The denominator can now be approximated

Complex Poles

04/27/2023 42

The third order transfer function as 3 poles and 1 zeroDominant Pole location

Non-dominant poles are complex conjugate Condition For complex Poles

LHP Zero Location

bserving the Pole/Zero Locations

Remains at the same location

Improves Phase Margin

04/27/2023 43

Analytical Results SummaryPole / Zero Location

Complex Poles Condition

Quick Facts Complex P2,P3 moved to much

higher frequency

Z=UGB

LHP zero improves the phase margin near UGB

Much faster op-amp with lower power and CC

XO

X

X

Complex conjugate Z=UGB

Dominat pole

04/27/2023 44

Design plan

Cc

Id1

(W/L)1,2

gmc=gm1

gm1 P2=2UGB

gm2

Id2

(W/L)6

<-Noise

<- UGB

<-SR=Id1/Cc

<-Assume Z=UGBId1=Idc

<-For 60deg PM

<-gm2=4gm1

<-SR=Id2/CL

04/27/2023 45

Current buffer

Devices Values (W/L)um

(W/L)1,2 72/0.8(W/L)3,4 48/0.8(W/L)5 12/1(W/L)6 84/0.15(W/L)7 36/1(W/L)8 (CG) 12/0.6(W/L)9 12/1

04/27/2023 46

Voltage buffer

Devices Values (W/L)um

(W/L)1,2 16/0.8(W/L)3,4 38/0.8(W/L)5 16/1(W/L)6 34/0.15(W/L)7 26/1(W/L)8 (VB) 14/0.6(W/L)9 6/1

04/27/2023 47

With current buffer

Results

DC GAIN

04/27/2023 48

Settling time

04/27/2023 49

Slew Rate

04/27/2023 50

Current buffer

Parameter Simulated values

UGB 1GHzDC gain 59.8dBPM 61.12degCc 0.4pFSettling time 3.4ns(2%)Slew Rate 707V/usPdiss 2.66mW

04/27/2023 51

With nulling resistor

Parameter Nulling resistor

UGB 235MHzDC gain 61dBPM 60.15degCc 1.2pFPdiss 1.94mW

04/27/2023 52

With voltage follower

Parameter Voltage follower

UGB 478MHzDC gain 54dBPM 60.9degCc 0.7pFPdiss 2.22mW

04/27/2023 53

Parameter Nulling resistor

Voltage follower

Current buffer

UGB 235MHz 478.84MHz 1GHzDC gain 61dB 54.4dB 59.8dBPM 60.15deg 60.9deg 61.12degCc 1.2pF 700fF 400fFPdiss 1.94mW 2.22mW 2.66mW

Comparison

04/27/2023 54

Layout of current buffer

04/27/2023 55

04/27/2023 56

The three compensated OTA is compared with gain, UGB, Power dissipation,PM.

We can observe that Cc of current buffer is reduced to 0.4pF when compared to Cc of nulling resistor of 1.2pF.

Current buffer compensated OTA there is improvement in the gain, UGB, PM and area requirement is also less compared to nulling resistor compensated OTA.

Conclusion

04/27/2023 57

[1] X. H. Fan, C. Mishra, and E. Sanchez-Sinencio, "Single miller capacitor frequency compensation technique for low-power multistage ampliers” IEEE Journal of Solid-State Circuits, vol. 40, no. 3, pp. 584-592, 2005.

[2] P. R. Gray, and R. G. Meyer,, "Analysis and design of analog integrated circuits,"' ,3rd ed., New York: Wiley, 1993.

[3] G. Palmisano, and G. Palumbo, "A compensation strategy for two-stage CMOS opamps based on current buer" IEEE Transactions on Circuits and Systems I-Fundamental Theory and Applications, vol. 44, no. 3, pp. 257-262, Mar, 1997.

[4] B. K. Ahuja, An Improved Frequency Compensation Technique for CMOS Operational-Ampliers" IEEE Journal of Solid-State Circuits, vol. 18, no. 6, pp. 629-633, 1983

[5] K. N. Leung, and P. K. T. Mok,"Analysis of multistage amplier frequency compensation" IEEE Transactions on Circuits and Systems I-Fundamental Theory and Applications, vol. 48, no. 9, pp. 1041-1056, Sep, 2001.

[6] H. Lee, and P. K. T. Mok, Active-feedback frequency-compensation technique for low-power multistage ampliers" IEEE Journal of Solid-State Circuits, vol. 38, no. 3, pp. 511-520, 2003.

[7] D.A.Johns and K.Martin, "Analog Integrated Circuit Design", New York: John Wiley and Sond,Inc.,1997.

[8] A. Pugliese, F. A. Amoroso, G. Cappuccino et al., "Design approach for fastsettling two-stage ampliers employing current-buer Miller compensation" Analog Integrated Circuits and Signal Processing, vol. 59, no. 2, pp. 151-159, 2009.

References

04/27/2023 58

[9] H. Mahattanakul, and J. Chutichatuporn, "Design procedure for two- stage CMOS opamp with exible noise-power balancing scheme" IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 52, no. 8, pp. 1508-1514, 2005.

[10] R. J. Reay, and G. T. A. Kovacs,, "An Unconditionally Stable 2-Stage CMOS Amplier" IEEE Journal of Solid-State Circuits, vol. 30, no. 5, pp. 591-594, 1995.

[11] A. Pugliese, F. A. Amoroso, G. Cappuccino et al., "Design approach for fastsettling two-stage ampliers employing current-buer Miller compensation" Analog Integrated Circuits and Signal Processing, vol. 59, no.2, pp. 151-159, 2009.

[12] A. Pugliese, F. Amoroso, G. Cappuccino et al., "Settling time optimisation for two-stage CMOS ampliers with current-buer Miller compensation" Electronics Letters, vol. 43, no. 23, pp. 1257-1258, 2007.

[13] M. Loikkanen, and J. Kostamovaara, "Improving capacitive drive capability of two-stage op amps with current buer" Proceedings of the 2005 European Conference on Circuit Theory and Design, Vol 1, pp. 99-102,2005.

[14] Mahattanakul, J., "Design Procedure for Two-Stage CMOS Operational Ampliers Employing Current Buer" IEEE Transaction on Circuits and Systems II- Express Briefs, vol. 52, no. 11, Nov 2005.

04/27/2023 59

[15] Saxena, V. and Baker, R. J., "Indirect Compensation Technique for Low Voltage Op-Amps" Proceedings of the 3rd Annual Austin Conference on Integrated Systems and Circuits (ACISC), May 7-9, 2008.[16] Behzad Razavi " Design of analog cmos integrated circuits" McGrawHill, 2001.

17] Phillip E. Allen and Douglas R. Holberg " CMOS analog circuit Design“ McGraw-Hill, 2001.

[18] Baker, R.J., "CMOS: Circuit Design, Layout, and Simulation" 2nd Ed.,Wiley Inter science, 2005.

[19] Dan Clein, "CMOS IC LAYOUT Concepts, Methodologies, and Tool”2nd Ed., Wiley Inter science, 2005.

[20] Alan Hastings, "The Art of Analog Layout (Sencond Edition)" 2007.IEEE Journal of Solid-State Circuits, vol. SC-14, Issue 6, Dec.1979, pp.1111-1114. 1996.

[21] Pelgrom, M. J. M., Duinmaiger, A. C. J., andWelbers, A. P. G, "Matching Properties of MOS Transistors" 2007. IEEE J. Solid-State Circuits,Vol. SC-24, Oct. 1989, pp. 1433-1439.

04/27/2023 60

THANK YOU