DESIGN AND CHARACTERISATION OF

SOI-LDMOS FOR POWER AMPLIFIER IN TCAD

A Project Report

submitted by

AFTAB ALAM KHAN

in partial fulfilment of the requirements

for the award of the degree of

MASTER OF TECHNOLOGY

DEPARTMENT OF ELECTRICAL ENGINEERINGINDIAN INSTITUTE OF TECHNOLOGY MADRAS.

JUNE 2015

THESIS CERTIFICATE

This is to certify that the thesis titled Design and Characterisation of SOI-LDMOS

for Power Amplifier in TCAD, submitted by Aftab Alam Khan, to the Indian Institute

of Technology, Madras, for the award of the degree of Master of Technology, is a bona

fide record of the research work done by him under our supervision. The contents of

this thesis, in full or in parts, have not been submitted to any other Institute or University

for the award of any degree or diploma.

Prof.Anjan ChakravortyResearch GuideAssociate ProfessorDept. of Electrical EngineeringIIT-Madras, 600 036

Prof.Amitava DasguptaResearch GuideProfessorDept. of Electrical EngineeringIIT-Madras, 600 036

Place: Chennai

Date:JUNE 2015

ACKNOWLEDGEMENTS

I am extremely thankful to Almighty ALLAH for giving me this opportunity to do re-

search in such a prestigious institute.

I am thankful to Prof.Anjan Chakravorty for allowing me to work with him and show-

ing confidence in me. I have been immensely benefited by his constant guidance, sup-

port and motivation. He is an excellent teacher to whom I greatly admire. His lectures

on "semiconductor devices" and "compact modelling" were key to my interest in this

research work. I would also like to gratefully acknowledge Prof.Amitava Dasgupta

and Prof.Nandita Dasgupta for their guidance and for providing direction to my work.

I have learned and benefited from their deep knowledge on LDMOS. Prof.Amitava Das-

gupta lectures on "MOS Modelling" has inspired and increased my interest to work in

Micro-electronics.

Thanks to Prof.Deleep Nair and Prof.S.Aniruddhan for their motivating and insight

full lectures on "Advance CMOS" and "RF IC Design" respectively from whom I have

learned a lot. Thanks to our faculty advisor Prof.Nagendra Krishnapura for sorting

out our problems and for always being there for us.

I am greatly thankful to my lab mate Nikhil K S for the discussions, advice’s and guid-

ance he has given by which I am benefited a lot. Thanks to my batch mates and friends

for the laughter we had together.

At the end, thanks to my parents who have always been kind and motivating. Today

whatever I am is due to their hard work and blessings.

i

ABSTRACT

KEYWORDS: LDMOS ; Power Amplifier ; TCAD ; LTE ; CLP.

Ever increasing communication system demands for low price RF devices for extensive

deployment, also emergence of new communication standards needs improved RF de-

vices. Power amplifiers (PAs) forms the most important component of RF system as

it deals with huge amount of power, so improving its performance and making it easy

to integrate should be of prime importance. Due to this Lateral Double-diffused Mos-

fets(LDMOS) has been the best option from long time as they can be easily integrated

with low voltage circuitry to form High Voltage Intergrated Circuits (HVIC). LDMOS

based PAs are being widely used in base-station applications while its usage for low

power mobile handsets are very less.

Due to introduction of new materials and technology it has become a need to car-

ryout device and circuit design in the same platform to test its capability of providing

better performance PA before fabrication and compact modeling of the device is mature.

This will reduce design time and will decrease cost by eliminating iterative fabrication

and testing process. This common platform is provided by TCAD tools.

This thesis deals with device(LDMOS) design and circuit design for a class AB

power amplifier in TCAD. Design is aimed for LTE(2.3-2.4GHz) application for both

low power(28dBm) and high power(50dBm) usage.

The outcome of this work shows that our Low power amplifier (LPA) circuit per-

formance parameters are below than currently available LPAs, which points out the fact

of LDMOS not being used for LPA applications. Whereas our HPA meets all specs as

compared to current commercially available PAs as well as with state-of-art published

results.

ii

TABLE OF CONTENTS

ACKNOWLEDGEMENTS i

ABSTRACT ii

LIST OF TABLES vi

LIST OF FIGURES ix

ABBREVIATIONS x

NOTATION xi

1 INTRODUCTION 1

1.1 History of power devices . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Overview of devices used in communication system . . . . . . . . . 3

1.3 Factors important in transistor design . . . . . . . . . . . . . . . . . 5

1.4 Future trends in RF Power device technology . . . . . . . . . . . . 8

1.5 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.6 Structure of the thesis . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 TECHNOLOGY COMPUTER AIDED DESIGN (TCAD) 11

2.1 Introduction to TCAD . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2 Device simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 Advantage of TCAD over CAD tools . . . . . . . . . . . . . . . . . 12

2.4 Models used in our SOI-LDMOS design . . . . . . . . . . . . . . . 13

2.5 Applications of TCAD . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Power Amplifier (PA) 15

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2 PA Operation classes . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2.1 Linear PAs . . . . . . . . . . . . . . . . . . . . . . . . . . 16

iii

3.2.2 Switching PAs . . . . . . . . . . . . . . . . . . . . . . . . 18

3.3 PA Design Consideration . . . . . . . . . . . . . . . . . . . . . . . 20

3.3.1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.3.2 Power Gain (G) . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3.3 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3.4 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3.5 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.4 Large signal characterization and matching network . . . . . . . . . 24

3.4.1 Load Pull . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4 Silicon Semiconductor on Insulator Laterally Diffused MOSFET (Si SOI-LDMOS) 26

4.1 Device structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1.1 Device structure before this project work . . . . . . . . . . 27

4.1.2 Final Device structure . . . . . . . . . . . . . . . . . . . . 27

5 SOI-LDMOS Design optimization for Power Amplifier and Analysis 30

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.2 Optimizing Length of region 1, 2 and 3 for Low Power Amplifier (LPA) 30

5.2.1 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.3 Optimizing Length of region 1, 2 and 3 for High Power Amplifier (HPA) 39

5.3.1 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.4 Gradient channel or Double diffusion analysis for LPA and HPA . . 46

5.4.1 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5.5 Introducing region 4 and doping analysis of region 2 and 3 . . . . . 54

5.5.1 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.6 Buried oxide optimization and Gate Isolation oxide analysis . . . . 65

5.6.1 Box-Oxide thickness optimization . . . . . . . . . . . . . . 65

5.6.2 Isolation oxide changed from LOCOS to STI (HPA) . . . . 67

6 Power Amplifier Circuit Implementation and Analysis 70

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.2 Active Computational Load Pull Test (CLP) . . . . . . . . . . . . . 70

6.3 Changing from fixed drain Ac source to RLC network . . . . . . . . 73

iv

6.4 Two-tone Intermodulation Analysis . . . . . . . . . . . . . . . . . 78

6.5 Performance over the band 2.3-2.4GHz . . . . . . . . . . . . . . . 79

7 Conclusion and Scope of future work 81

7.1 Findings of the thesis . . . . . . . . . . . . . . . . . . . . . . . . . 81

7.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

A A SAMPLE APPENDIX 83

LIST OF TABLES

1.1 Comparind different physical properties of various semiconductors usedin RF applications. . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.1 Conduction angle mode . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1 Important lengths of final device . . . . . . . . . . . . . . . . . . . 29

5.1 LPA channel doping concentration. . . . . . . . . . . . . . . . . . . 31

5.2 HPA channel doping concentration. . . . . . . . . . . . . . . . . . 40

6.1 Summary of PAE and Gian at 1dB compression point. . . . . . . . . 77

6.2 ACPR at 1dB compression point. . . . . . . . . . . . . . . . . . . . 79

7.1 Circuit Level Parameter comparision with Industry reference PA. . . 81

7.2 Final device parameters of the designed transistor. . . . . . . . . . . 82

7.3 State-of-art Class AB HPA based on LDMOS devices. . . . . . . . 82

vi

LIST OF FIGURES

1.1 Characteristics of LDMOS transistor at (a) Input(gate), (b) Output(drain) 6

1.2 Various components of Ron . . . . . . . . . . . . . . . . . . . . . . 6

2.1 TCAD device simulation flow . . . . . . . . . . . . . . . . . . . . 12

3.1 Quiescent points for different PAs . . . . . . . . . . . . . . . . . . 16

3.2 Drain characteristics for class A . . . . . . . . . . . . . . . . . . . 17

3.3 Drain characteristics for class B . . . . . . . . . . . . . . . . . . . 17

3.4 Drain characteristics for class AB . . . . . . . . . . . . . . . . . . 18

3.5 Power Amplifier setup . . . . . . . . . . . . . . . . . . . . . . . . 20

3.6 1 dB compression point . . . . . . . . . . . . . . . . . . . . . . . . 21

3.7 Two tone power spectrum with dominant harmonics . . . . . . . . . 23

3.8 Two tone test, 3rd order intercepts for IMD behavior . . . . . . . . 23

3.9 Load-Pull test setup . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1 Device structure before start of work . . . . . . . . . . . . . . . . . 28

4.2 Final high power device structure . . . . . . . . . . . . . . . . . . . 28

5.1 Current Waveform for devices with different L_R1 showing constantVth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.2 IDV G for L_R1 = 0.05µm . . . . . . . . . . . . . . . . . . . . . 32

5.3 IDV GwithL_R2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.4 IDV G Comparision with L_R1 and L_R2 . . . . . . . . . . . . . 33

5.5 Breakdown Voltage variation with L_R1 and L_R2 . . . . . . . . . 33

5.6 Anomalous Breakdown behavior of L_R1 = 0.05µm, . . . . . . . . 34

5.7 Anomalous Impact Ionization Rate behavior of L_R1 = 0.05µm . . 34

5.8 Breakdown Voltage behavior for L_R1 = 0.1µm and L_R1 = 0.2µm 35

5.9 Ron variation with L_R2 . . . . . . . . . . . . . . . . . . . . . . . 36

5.10 Capacitance variation with Vgs . . . . . . . . . . . . . . . . . . . . 37

5.11 FT variation with Vgs . . . . . . . . . . . . . . . . . . . . . . . . . 37

vii

5.12 FTmax variation with Vgs . . . . . . . . . . . . . . . . . . . . . . . 38

5.13 Fmax and peak Fmax for varies region lengths . . . . . . . . . . . . 38

5.14 IDV G for L_R1 = 0.1µm . . . . . . . . . . . . . . . . . . . . . . 40

5.15 IDV G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.16 IDV G Comparision . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.17 IDV D for HPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.18 Comaprision for Vgs = 6V . . . . . . . . . . . . . . . . . . . . . . 43

5.19 Comaprision for Vgs = 0V . . . . . . . . . . . . . . . . . . . . . . 43

5.20 IDV D Comparision at Vgs = 0V without R4 . . . . . . . . . . . . 44

5.21 ON-state resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.22 FTmax Comparison for different L_R1 . . . . . . . . . . . . . . . . 45

5.23 Peak Fmax variation . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.24 Cuts for doping analysis . . . . . . . . . . . . . . . . . . . . . . . 47

5.25 Doping profile along the device channel . . . . . . . . . . . . . . . 48

5.26 Doping profile with L_R1 = 0.1µm for low PA . . . . . . . . . . . 48

5.27 Doping profile with L_R1 = 0.1µm for high PA . . . . . . . . . . . 49

5.28 Doping profile with L_R1 = 0.2µm for high PA . . . . . . . . . . . 49

5.29 IDV G of Low PA for L_R1 = 0.05 and 0.1µm . . . . . . . . . . . 50

5.30 IDV G comparison for high PA . . . . . . . . . . . . . . . . . . . 50

5.31 Breakdown Voltage variation for Double diffused Low PA . . . . . 51

5.32 Breakdown Voltage variation for Double diffused High PA . . . . . 51

5.33 ON resistance variation (U-Uniform doping, DD-Double diffusion) . 52

5.34 FTmax variation (U-Uniform doping, DD-Double diffusion) . . . . 52

5.35 Peak Fmax comparison for Uniform channel doping(U) and Double dif-fused doping(DD) . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.36 Drain characteristics for 4 cases for High PA . . . . . . . . . . . . . 55

5.37 Electric field for 4 cases for High PA . . . . . . . . . . . . . . . . . 55

5.38 Electric field distribution for High PA at Vgs = 6 . . . . . . . . . . . 56

5.39 region 4 doping analysis for High PA at Vgs = 6 . . . . . . . . . . . 59

5.40 Electric field profile for High PA at Vgs = 6 . . . . . . . . . . . . . 59

5.41 Improved IDV G . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.42 Drain Characteristics IDV D for Low PA . . . . . . . . . . . . . . 61

5.43 Drain Characteristics IDV D and Breakdown for Low PA . . . . . . 62

viii

5.44 Drain Characteristics IDV D for High PA . . . . . . . . . . . . . . 62

5.45 Breakdown at low and high Vg for High PA . . . . . . . . . . . . . 63

5.46 ON resistance Comparison . . . . . . . . . . . . . . . . . . . . . . 63

5.47 FTmax Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.48 Peak Fmax comparison . . . . . . . . . . . . . . . . . . . . . . . . 64

5.49 breakdown or snapback voltage changes due to oxide thickness (LPA) 66

5.50 breakdown or snapback voltage changes due to oxide thickness (HPA) 66

5.51 large signal characteristics (HPA-LOCOS) . . . . . . . . . . . . . . 67

5.52 Isolation techniques to improve linearity . . . . . . . . . . . . . . . 67

5.53 large signal characteristics (HPA-STI) . . . . . . . . . . . . . . . . 68

5.54 DC characteristics comparison before and after STI (HPA) . . . . . 68

5.55 Comparison of RON , FT and Fmax B-before A-after STI . . . . . . 69

6.1 Active CLP system . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.2 PAE and Gain at Matched Condition using Active CLP . . . . . . . 72

6.3 Power Amplifier setup . . . . . . . . . . . . . . . . . . . . . . . . 74

6.4 Pout variation with Pin for LPA(Legend corresponds to 1dB compres-sion point) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

6.5 Pout variation with Pin for HPA (Legend corresponds to 1dB compres-sion point) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

6.6 PAE and Gain variation with RF Output Power . . . . . . . . . . . 76

6.7 Large Signal Characteristics with Active CLP at 1dB compression point 76

6.8 Large Signal Characteristics with RLC network at 1dB compressionpoint (LPA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.9 Large Signal Characteristics with RLC network at 1dB compressionpoint (HPA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.10 3rd harmonic Inter-modulation Analysis for LPA . . . . . . . . . . 78

6.11 3rd harmonic Inter-modulation Analysis for HPA . . . . . . . . . . 79

6.12 PAE and Gain analysis over the entire LTE band . . . . . . . . . . . 80

ix

ABBREVIATIONS

IITM Indian Institute of Technology, Madras

RTFM Read the Fine Manual

x

NOTATION

r Radius, mα Angle of thesis in degreesβ Flight path in degrees

xi

CHAPTER 1

INTRODUCTION

1.1 History of power devices

Power Amplifiers play a vital role in communication system as it is the most power

hungry component. Its improvement will create a huge impact on the system. Power

Amplifiers functionality is directly correlated with performance of the power device.

The ever improving communication standards will require high performance power de-

vices.

Power semiconductor devices have become integral component of the semiconduc-

tor industry in designing high voltage integrated circuits(HVICs). They have come a

long way since the inception of bipolar junction transistors and thyristors. In 1952 first

significant power device (power diode) fabricated using germanium mesa alloy junc-

tions was demonstrated by Hall (Hall, 1952). In 1957 came thyristors that could with-

stand large reverse breakdown voltages but turning off and on without cut off the power

supply was a problem which led to the introduction of Gate turn off thyristors(GTO) in

1960. Requirement for higher switching speed and lower switching losses led to the de-

velopment of bipolar transistors. The first commercial silicon transistor was introduced

by Texas Instruments in 1954 but it took almost a decade to find practical applications

in high voltage circuits. Introduction of planar process by Fairchild (Hoerni, 1960) and

use of photolithography on wafer processing gave birth to power transistor market in

1960’s.

Further advancement in silicon fabrication technology led to the development of

novel device structures such as power MOSFETs. The motivation behind its develop-

ment was reduction in large base drive current required by bipolar transistors, difficulty

in integration and their limited switching capability. Power MOSFETs were introduced

in late seventies (Adler et al., 1984) and they made way for the development of new

generation of devices. By breaking the the symmetry of conventional MOSFET, the

power MOSFETs were developed. The symmetry was broken to improve the reverse

capability of the device (Declereq and Plummer, 1976). One such power MOSFET that

was developed was the lateral double diffused metal oxide semiconductor (LDMOS)

transistors.

One of the main advantage of LDMOS devices is that they can be easily integrated

with low voltage circuitry. They continue to be industry standard even today for medium

voltage power applications. Their main drawback is the fact that they suffer from low

current rating and breakdown voltage on-resistance(RON ) trade off. To increase the

voltage handling capabilities of this device, we need to increase the length of lightly

doped drain region across which the reverse voltage is dropped. This increases the area

requirement of the device.

To circumvent this problem, vertical double diffused MOS (VDMOS) technology

was developed. VDMOS provides larger current ratings and higher breakdown voltage

compared to LDMOS (Temple and Gray, 1979), but requires complicated process steps

and integration with low voltage circuitry is not easy. Though VDMOS finds appli-

cations in high voltage industries, medium power applications are still dominated by

LDMOS devices.

Nowadays, HVICs and power integrated circuits (PICs) are replacing discrete ele-

ments such as DC-DC convertors, switch mode power supplies and power amplifiers

(Sakamoto et al., 1999; Perugupalli et al., 1998; Tsui et al., 1992). Integration of high

and low voltage circuits on the same chip improves the overall performance and reduces

the chip size. PICs are used as a bridge between power load and low voltage digital logic

Tsui et al. (1995); Baliga (1991). They are also useful in power line communications

(PLCs) where digital information is transmitted over a power line. LDMOS devices

form an integral part of many of these interesting applications.

LDMOS are being used in interesting consumer and automotive applications so it

becomes essential to improve its performance. Recently, fabrication of LDMOS devices

2

on a Silicon-on-Insulator (SOI) substrate has become popular. LDMOS fabricated on

an SOI substrate offers additional advantages such as lower leakage currents, higher

latchup, higher packing density and reduced parasitics paraldmos. Further, the use of

an SOI substrate enables isolation between power devices and low voltage circuitry

which is essential in smart power ICs.

Due to high RON , higher losses at increasing frequency and RON , breakdown volt-

age trade off has led to the development of many new power device technologies such

as HBTs, MESFETs and HEMTs. These new technologies have captured large por-

tion of the power device market with only drawback of integration and manufacturing

cost. Due to these drawbacks LDMOS business is still alive for medium voltage/power

systems.

1.2 Overview of devices used in communication system

Germanium based BJTs were used in communication system for upto 1GHz applica-

tions (Cooke, 1971). Germanium was taken over by silicon based BJTs since former

lack natural passive oxide. Si BJTs enhanced the operation upto 3GHz. At the same

time to increase performance III-V compound semiconductors, AIP, InSb, InP, GaAs,

GaAsP, AlGaAs etc were studied for using it into new RF devices such as BJTs, HBTs,

MESFET etc. The basic working of hetro-junction bipolar transistor was patented by

Shockley in 1951 (Shockely, 1951). GaAs based BJT was was developed in 1970 for

high frequency applications to overcome the limitations of Si-BJTs. But this new BJT

faced two major problems. 1) High Cost and 2) The low mobility holes in the P-type

base of the BJTs gave rise to noise factor. Based on the principle of schottky diode

in 1980 GaAs based metal semiconductor Field Effect Transistor (MESFET) devices

devices were developed. It operated as medium power low noise noise transistor upto

12GHz and also achieved some commercial success but was still very much costly.

These devices today are operating above 50GHz (Aaen et al., 2007).

Wireless communication system before 1980 was mostly comprised of TV, broad-

casting radio and radars communication for both commercial and military applications

3

and not for point to point communication. When cellular communication was intro-

duced in 1990 it brought a new start up of technologies in wireless communication

system with introduction of transferring data along with voice at high operating fre-

quency. It was this tremendous growth of cellular communication system which led to

the research and development of new solid state devices to meet the requirement of low

cost and high performance.

LDMOS in 1996 replaced silicon BJTs (Wood et al., 1996) due to their advanta-

geous properties such as higher gain, low inter-modulation and reduced thermal effect

(Bouny, 1996) for base station application. Substrate in LDMOS provides large area

contact to dissipate heat compared to other devices. LDMOS has a dominant role in

medium power and low frequency applications upto 4GHz. It is used in various sys-

tems for more than a decade e.g. in HF, UHF and VHF, cellular and WiMAX base

stations (Wood, 1997; De Meyer and Beaulaton, 2008; Euro-Global, 2007).

Recent years have introduced wideband gap (WBG) semiconductors with SiC and

GaN as promising candidates for future RF power applications due to their physical

properties such as thermal conductivity, high breakdown electric field etc. (Chu et al.,

2008; Szweda, 2003; Temcamani et al., 2001, 2000). These properties have led to re-

duction in device size which are beneficial for portable military applications, where

along with performance reduced device size also has play a huge role. So though the

power density provided by GaN devices is 10 times higher than Si-LDMOS but the

cost of fabrication is not comparable. Also having high power density will not provide

any benefit unless the package of the device is good enough to manage the thermal

management properly, which leads to additional cost. Recently GaN devices are grown

on Si substrate to reduce the manufacturing cost but it compromises on thermal con-

ductivity. In the table-1.1 (Institute) shows physical property comparision of different

semiconductors. These properties shows that future RF devices can be made using

III-IV semiconductors such as GaAs and GaN but as of now these devices will never

overtake LDMOS devices below 4GHz and medium power application due to their low

fabrication cost.

4

Table 1.1: Comparind different physical properties of various semiconductors used inRF applications.

Physical Properties Si SiGe GaAS GaN InP 4H-SiC

Band Gap 1.1 0.84-1.1 1.42 3.28 1.35 3.26(eV)

Mobility 1400 1400-4315 8500 2000 5400 900(cm2/Vs)

Thermal conducti- 1.5 0.8-1.3 0.5 1.3 0.7 3.7vity (W/cm.K)Critical Electric 0.3 0.3 0.4 5.0 0.5 3.0field (MV/cm)

Electron thermal 2.3 2.4 4.4 2.1 3.9 1.9velocity (107cm/s)Cost of fabrication low high high v.high v.high v.high

Transistor type BJTs BJTs MESFETs MESFETs MESFETs MESFETsHBTs HBTs HEMTs HEMTs HEMTs HEMTs

MOSFET MOSFET HBTs HBTs

1.3 Factors important in transistor design

There are few important factors which can be termed as Figure of merit (FoM) for a

transistor. These FoM provide a direct way to understand the performance of a tran-

sistor. Using these FoM it becomes straight forward to compare different devices from

different fabrication unit having same technology. It can also be used to compare tech-

nologies based on different semiconductors (e.g. Si, SiGe, GaAS, InP, and GaN etc) and

different devices as well (e.g. LDMOS, MOSFET, BJT, HBT, MESFET and HEMTs).

FoM properties are derived from DC, AC and large signal analysis to analyze the tran-

sistor for RF applications.

DC FoM parameters are obtained from current-voltage characteristics of input(gate)

and output(drain) as shown in the Fig. 1.1(a) and Fig. 1.1(b), FoM parameters obtained

from these characteristics are (1)Breakdown voltage (Vb) which shown in Fig. 1.1(a) it

defines maximum drain voltage (Vd) above which Vd cannot be increased as it marks the

point from where there is a drastic increase in current with increase in Vd, higher the Vb

better the device . (2) On-resistance (RON ) it is obtained from Fig. 1.1(a) at near zero

Vd considering linear characteristics. It gives an idea about rate of increase of current

with Vd, faster the increase better is the device hence it is expected to have low value of

5

0 2 4 6 80

1

2

3

4

5

Ids

gm

Vgs [Volts]

I ds[A/m]*1

0-4

0.0

0.3

0.6

0.9

1.2

1.5

gm [

-1/m]*10

-4

(a) (a)

0 20 40 60 80 100 1200

2

4

6

8

10

I ds [A

/m

]*10-4

Vds [Volts]

Breakdown points

(b) (b)

Figure 1.1: Characteristics of LDMOS transistor at (a) Input(gate), (b) Output(drain)

RON . Ron is composed of various components (Fu et al., 2014):

Ron = Rcs +Rch +Racc +Rdrift +Rcd

Figure 1.2: Various components of Ron

Rcs and Rcd are source and drain resistance which can be ignored as they are very

small. Rch channel resistance is given by using standard equation

Rch =Lch

2µiCox(Vgs − Vth)

Cox is the gate capacitance. Mobility µi is of electrons in the inverse layer. Racc is

the accumulation layer resistance, it is defined as the resistance of the drift region over-

lapped with the gate, as Vgs increases mobility µa of L_R2 increases and so resistance

decreases.

Racc =Lacc

4µaCox(Vgs − Vth)

6

The drift region resistance is calculated by

Rdrift =Ldrift

qµnNddeff

where deff is the effective N-well thickness due to unequal distribution of current flow.

The value of Rdrift dominates over Racc and Rch .

(3) Knee voltage (Vk) is obtained from Fig. 1.1(a) it is equal to Vd at which current

saturates. Vd safe operating voltage is defined from Vk to Vb, so it is expected to have a

lower Vk to maximize safe operating area.

(4) Maximum current rating (Idsat) gives idea of current density of the device and

maximum available current. It is shown in Fig. 1.1(b) marking the saturation current

value. (5) Transconductance (gm) is shown in Fig. 1.1(b) it is an important parameter

which gives an idea of gain provided by the transistor. Higher gm implies higher gain

which is important for a transistor.

gm =∂Id∂Vgs

=µnCoxW (Vgs − Vth)

L

where µn is the channel mobility, Cox is the gate capacitance, W is the device width, L

is the channel length and Vth is threshold voltage of the device.

FoM parameters obtained from small signal analysis are related to frequency of op-

eration. Transition frequency FT and Maximum Oscillation frequency Fmax are critical

parameters. As the operating frequency goes closer to these critical frequencies transis-

tor starts to behave non-linearly hence operating frequency has to below these critical

frequencies to get proper characteristics. FT provides information on how rapidly a

transistor can transfer charge in to its channel from gate to drain.

FT =gm

2π(Cgs + Cgd)

where Cgs is gate to source capacitance, Cgd is gate to drain capacitance. The above

MOSFET FT equation is valed for LDMOS as well, which is also shown by (Muller

et al., 2007) .

7

Fmax =

√FT

8 ∗ π ∗ Cgd ∗Rg

where, Rg is the gate resistance. To find Rg AC S-parameter analysis is done for input

gate and output drain nodes and these S-parameters are converted to Y-Parameter in

matlab.

Y11 =ω2 ∗ (Cgs + Cds)

2 ∗Rg + jω ∗ (Cgs + Cds)

1 + ω2 ∗ (Cgs + Cds)2 ∗R2g

Rg =real(Y11)

Imag(Y11)2

where for ω used should have denominator of Y11 close to 1 (Kwon et al.). Fmax is

the critical frequency at which power gain is equal to 1, In principle it gives intrinsic

switching speed.

Large signal analysis provides the most important FoM, which describes the perfor-

mance of the transistor as a power amplifier. Designers mostly concentrate on this large

signal analysis and try to extract its equivalent circuit model. After getting the circuit

Load pull (LP) measurement are done on the power amplifier to extract most important

FoM parameters like Output RF power (Pout), RF power gain (Gain), Power added ef-

ficiency (PAE), drain efficiency (ηd) and distortion parameters showing non-linearity of

the transistor.

1.4 Future trends in RF Power device technology

RF power devices have an important share in wireless communication business. As of

today there are number of wireless communication standards in use. So for this grow-

ing market there is a need for low cost, high power density and high market potential

devices and this demand is increasing day by day and it will be there in coming years

as well. There has been a tremendous increase in power amplifier applications ranging

from very low power e.g less than a Watt to 100’s of Watt.

Due to this increasing cellular communication market PA designers are facing chal-

lenge of designing PA of high power levels, high frequency of operation, excellent

8

linearity and efficiency but everything at a very less cost. So accurately characterizing

both at the circuit and device level is of prime importance in order to enhance system

performance in a reduced time. It would be much better if we can couple both device

and circuit characterization in order to extract the best performance.

Device design is done in Technology computer aided design (TCAD) softwares

prior to fabrication to get the best optimized design (Synopsys, 2005; Silvaco, 2000).

TCAD is a versatile software based on physical models to represent the device in terms

of carrier transport equations along with geometrical limitations. These physical mod-

els take large computational time in order to solve huge number of carrier transport

equations compared to circuit simulators but results provided by them exactly repre-

sents that of real fabricated device structures (Snowden, 1994). Today using TCAD

has become easy because of advancement in processors and high clock frequency also

there are memories to store huge amount of dynamic data, which has reduced the design

time hence decreasing the cost. Nowadays PA designers are making use of TCAD soft-

wares in order to couple circuit and device designs use large signal analysis for more

effective designs, this has reduced iterative fabrication and testing problems as TCAD

represents the real device structure and its importance has already been demonstrated [].

1.5 Objectives

The main objective of this project is as follows.

• To design SOI-LDMOS transistor for power amplifier application. It is designedfor LTE band (2.3-2.4GHz) in India. The transistor is designed for mobile hand-set application (Low Power Amplifier (LPA)) and for base stations (High PowerAmplifier (HPA)). LPA is designed for DC drain source of 3.7V and RF outputpower of around 28dBm. HPA is designed for DC drain source of 28V and RFoutput power of around 50dBm.

• During device design our aim is to increase current density and reduce ON-resistance (Ron) by satisfying condition of breakdown voltage. Also increaseFT and Fmax as much as possible above 2.4GHz.

• To do circuit design of the power amplifier in class AB and to achieve both deviceand circuit design of the power amplifier in TCAD. To carryout Two tone linearitytest of power amplifier in TCAD.

9

1.6 Structure of the thesis

Chapter 2: Technology computer Aided design (TCAD)

In this chapter importance of TCAD is illustrated and comparison with CAD tool is

done. It shows importance of mixed mode simulation and TCAD’s increasing

application. Various medici models used in our simulation is also illustrated.

Chapter 3: Power Amplifier

Various classes of power amplifiers are introduced here and different parameters

important for power amplifier design is also described. Large signal characterization

of PAs are described in detail.

Chapter 4: Silicon Semiconductor on Insulator Laterally Diffused MOSFET (Si

SOI-LDMOS)

Here SOI-LDMOS structure available before this project is explained and also the

modified structure obtained at the end of the project is described.

Chapter 5: LDMOS Design optimization for Power Amplifier and Analysis

Here LDMOS device is designed for PA and various device structure parameters are

optimized in order to get best transistor FoM. Gradual channel is implemented and

region 4 (new region) is introduced which gives excellent results for PA design. Here

importance of STI as compared to Locos technology is also described.

Chapter 6: Power Amplifier Circuit Implementation and Analysis

The designed device is used to make power amplifier circuit and then analyzed for

different PA circuit FoMs. Computational Load Pull (CLP) is introduced for PA

characterization in TCAD. Two tone test for linearity analysis is also done in medici.

Chapter 7: Conclusion

The contribution and perspective offered by this work is presented. Scope for future

work is also presented.

10

CHAPTER 2

TECHNOLOGY COMPUTER AIDED DESIGN

(TCAD)

2.1 Introduction to TCAD

TCAD is a branch of electronic design automation that models semiconductor fabri-

cation and semiconductor device operation. Modeling fabrication process is termed

as process TCAD while modeling device operation is termed as device TCAD. The

concept of TCAD was first introduced in 1970s to study physics related challenges of

bipolar transistor (DeMan and Mertens, 1973). TCAD is now used in the development

of new technologies from micro to nanometer regime. It gives close insight of device

operation which is comparable to actual fabricated device. This makes optimization of

the device much easier and quicker as compared to iterative device fabrication and test-

ing procedure. TCAD is a versatile tool which contains fabrication process steps such

as ion-implantation, diffusion, annealing, etching, metallization and device electrical

properties for semiconductor physics models.

TCAD aims to provide accurate results with respect to scalabilty of the device,

here scalability includes varying device dimensions and doping concentration, and these

results should have exact match with the fabricated device . A Device in TCAD device

simulator is represented as a virtual device whose physical properties are given by grid

or mesh. 2 or 3 dimension simulations are used to study basic device operation by

defining device dimensions and process steps.

2.2 Device simulation

TCAD device simulator is used to understand electrical behavior of the virtual device

through simulations. The virtual device is engineered, applied process and may also

contain circuit elements. TCAD helps to detect problems at engineering, process and

manufacturing levels. The device simulator solves Poisson equations by coupled sys-

tems of partial differential equations of each grid box under applied boundary condi-

tions. The mesh file provides information regarding different device regions, doping

concentration, material, contacts etc. The device simulator performs various types of

analysis such as dc, Ac, transient, noise and large signal analysis with defined models.

The grid or mesh is part of device design, it advisable to have finer grids where current

are large and coarser where current levels are low. The flow of device simulation is

shown in the figure below.

Figure 2.1: TCAD device simulation flow

A mixed mode device and circuit simulation can be done in TCAD. It provides

performance from real circuit perspective. Mixed mode provides an opportunity to do

analyze both device and circuit performance at the same time. Stress provided by the

circuit to the device can be studied and critical changes in the device design or process

can be done if required. So here mixed mode reduces iterative fabrication and testing

time.

2.3 Advantage of TCAD over CAD tools

Unlike CAD tools which uses compact models to simulate circuit level behavior, TCAD

is completely physics based and uses drift-diffusion and Poisson equations to model

semiconductor device behavior. Its graphical user interface (GUI) gives better insight

to device engineers. TCAD tools have a strong hold in industry because of its various

advantages.

• TCAD provides information of wafer topography, junction widths, electric fielddensity, current density, dopant profile etc for best device design which is hiddenin CAD tools.

12

• Availability of testing many process on the device designed reduces iterative fab-rication process and reducing time to market as well. where as compact modelscan only be made once the device design, process and manufacturing is matured.Circuit designers can investigate and make process changes for better perfor-mance of technology.

• Complex device equations used to describe circuit behavior are simply imple-mented in TCAD using analytical form Chin et al. (1991).

• TCAD provides both device-process simulation along with circuit simulation inmixed mode analysis, where as CAD tools provide only circuit simulation soeffect of circuit on device cannot be analyzed in CAD tools. TCAD has spicecircuit models for better reliability from electro-migration, breakdown, electro-static discharge, latch-up and hot carrier effects.

• TCAD’s mixed mode simulation provides opportunity for implementing new ma-terials, structures, process etc and visualize its effects on circuit simulation itselfwithout fabrication, so it opens whole new opportunity of trying new things.

2.4 Models used in our SOI-LDMOS design

In this present work 2D simulator Taurus Medici from Synopsys (guide, 2003) is used.

It is used to model the electrical, thermal and optical characteristics of semiconductor

devices. A variety of devices can be designed including MOSFETs, HBTs, BJTs, power

devices, HEMTs, IGBTs, CCDs and photodetectors etc.

MODELs: Different physics models used in our current work are as follows:

• ANALYTIC : Specifies concentration and temperature dependent mobility calcu-lated from an analytic expression.

• FLDMOB : Specifies a mobility model using the parallel electric field component.

• CONSRH : Specifies Shockley-Read-Hall recombination with concentration de-pendent lifetimes.

• AUGER : Specifies Auger recombination.

• BGN : Specifies band-gap narrowing.

• PRPMOB : Specifies a mobility model using the perpendicular electric field com-ponent.

• IMPACT.I : Specifies carrier generation due to impact ionization is included inthe solution self-consistently

13

It uses Newtons two carrier (electron, hole) solution method. For self heating it

has following parameters: (1) LAT.TEMP : Specifies that the simulation is done for

Poisson, continuity and lattice temperature. (2) COUP.LAT : Specifies that the lattice

temperature equation is fully coupled with the Poisson and continuity equations. Both

parameters are only used with the Lattice Temperature AAM.

2.5 Applications of TCAD

TCAD has a tremendous capability and will remain a dominant tool in the future. As

device dimension are shrinking, understanding of different physical phenomenon hap-

pening in the fabricated device and its modeling is very difficult without the use of

TCAD tools. Now we have reached to 10nm gate node length devices (e.g. Finfet) and

TCAD tools are proving to be a great help in understanding and developing of compact

models. In future, device dimensions will be approaching to atomic level so devices

may be comparable to many biological microstructures and TCAD can help in model-

ing of these structures. So it has a lot of applications in design of biosensors (Hassibi

et al., 2008). In wireless communication system there has been introduction of different

materials such as SiC, GaN, ZnO etc and different devices like HEMTs etc inorder to

provide low cost and better performance RFICs, TCAD has been the best tools to test

the feasibility of these technologies before going to actual fabrication. TCAD uses finite

element method or matrices to solve equations which is time consuming. So in order

to speed up the process of circuit analysis in TCAD we will be using Computational

Load-Pull test (CLP) which is explained in later chapter. CLP in TCAD has been used

to analyze RF LDMOS for broadband power amplifier (Kashif et al., 2013) .

14

CHAPTER 3

Power Amplifier (PA)

3.1 Introduction

Power Amplifiers required for communication system must show high linearity and

high efficiency for narrow or broadband systems. The performance of the PA directly

depends on the transistor used in the design (Raab et al., 2002). In order to have high

performance PA, transistor is designed such that it has high output current, high break-

down voltage, low on-resistance, low harmonic content which implies to have high

transition frequency and high maximum oscillation frequency. PA can be designed

most efficiently if analysis is done from device to circuit level. For almost all applica-

tions equivalent model of the transistor is extracted using small and large signals and

then it is used for circuit design inside circuit simulators. Low noise amplifier (LNA)

used in the receiver end can be designed optimally from small signal S-parameters of

the transistor because here the signal level handled by the LNA is small and very close

to its biasing values. As compared to LNA, power amplifier used in the transmitter han-

dles large signal hence its biasing point itself changes therefore it becomes challenging

to model large signal equivalent circuit, so designing PA based on equivalent circuit

may not lead to optimal design due to imperfect equivalent circuit. The primary goal

of small signal or large signal modeling is same to obtain input and output impedance

though the method used is different, for small signal equivalent circuit I-V characteris-

tics is sufficient on the other hand large signal equivalent circuit requires load pull test

and two port S-parameter analysis (Al-Shahrani, 2001).

3.2 PA Operation classes

Power Amplifier (PA) is categorized into two categories Linear PAs and Switching PAs.

3.2.1 Linear PAs

PAs of class A, AB and B are considered as linear PAs.

Table 3.1: Conduction angle mode

Mode Quiescent Id,dc Conduction angleA 0.5 2π

AB 0-0.5 π − 2πB 0 π

In the table 3.1 Id,dc is normalized to its maximum value. Conduction angle is

defined as Ton Tperiod*2π,Ton is the total time interval for which drain current is above

zero in one time period and Tperiod is the time period.

0.0 0.2 0.4 0.6 0.8 1.0 1.20.0

0.2

0.4

0.6

0.8

1.0

1.2

I ds [N

orm

aliz

ed]

Vgs [Normalized]

class A

class C

class Bclass AB

Figure 3.1: Quiescent points for different PAs

Class A

As seen in Fig. 3.2 current is above zero through out the period hence the conduction

angle is 2π . Voltage and current values are normalized, here Vd,dc = 1 and so theoret-

ically drain voltage swings from 0 to 2*Vd,dc i.e. till 2. Class A PA is biased as shown

in the Fig. 3.1. i.e at midpoint of maximum drain current. Class A PA provides high

linearity at the expense of efficiency. Maximum theoretical drain efficiency (ηD) is 50%

but in practical its less than 40% (Razavi). It is used at an early stage in cascade design

16

0 90 180 270 360 450 540 630 7200.0

0.5

1.0

1.5

2.0

Angle [degree]

Voltage Current

Figure 3.2: Drain characteristics for class A

because early stages component contribute most towards overall non-linearity and also

popularly used in Low power applications beyond 5GHz where high power gain is the

need.

Class B

0 90 180 270 360 450 540 630 7200.0

0.5

1.0

1.5

2.0

Angle [degree]

Voltage Current

Figure 3.3: Drain characteristics for class B

Class B amplifier is biased at the threshold voltage such that it conducts only for half

cycle and is off for the other half cycle hence conduction angle is π. Here efficiency

17

is high but gain and linearity becomes poor compared to class A. Theoretical drain

efficiency for class B is 78.5% . Class B PA is seen in the form of push-pull amplifier

for audio applications.

Class AB

0 90 180 270 360 450 540 630 7200.0

0.5

1.0

1.5

2.0

Angle [degree]

Voltage Current

Figure 3.4: Drain characteristics for class AB

Since PA cannot practically have exactly π conduction angle therefore class AB is

more practical. Its quiescent point lies in between class A and B as shown in the Fig.

3.1. Class AB Power amplifier is a compromise of high efficiency of class B and high

linearity of class A. It is famous and normally used as a linear PA in telecommunication

technology. LDMOS is mainly used in class AB mode.

3.2.2 Switching PAs

The concept of switching power amplifier was proposed by Ewing, G in 1964 (Ewing,

1964). Switching PAs have become attractive due to their high efficiency and focus on

linearity is reduced. Switching PAs consist of class C, D, E, F (Al-Shahrani, 2001).

18

Class C

Conduction angle for class C PA is less than π and biasing point as shown in the Fig.

3.1. Theoretical efficiency of the PA can go upto 100% but that is not feasible because

at that point peak output power and gain approaches to zero (Razavi). High efficiency of

class C is achieved on compromising for linearity. Class C PAs have lowest linearity so

not useful for audio application, they are mostly used in RF Oscillator, boost amplifiers

etc.

Class D

It works similar to push-pull class B with two transistors. An ideal switch passes all

current through it when ON without voltage drop across it. While during OFF state

the entire voltage remains across it with no current will flow through it. So power

is not wasted across the switching element which does the amplification, and this is

the reason for very high efficiency of Class D PAs. It is also called digital amplifier

and favorable with square wave input signals. It has low heat dissipation with reduced

size and weight. Drawback for class D PA is non-zero saturation voltage has static

dissipation in switching behavior, because of the reason it works good at well below

transition frequency (FT )(Lee, 2004) .

Class E

The concept of class E PA was first proposed by N. Sokal (Sokal and Sokal, 1975).

Theoretically it can achieve efficiency of 100% with good output power which is an

advantage compared to class-C PA. Class E deals with finite input and dissipation will

degrade the efficiency, therefore proper harmonic loading is required to force a zero

switching for non-zero interval of time. Therefore there exist a trade off between effi-

ciency and output harmonics. Another drawback of class-E PA is 3.56Vd,dc (Sokal and

Sokal, 1975) is the maximum voltage the switch can sustain in the off state. Power han-

dling capability is very low and has an excellent performance with discrete components

.

19

Class F

In class F mode active device output is properly loaded with appropriate terminations at

fundamental and harmonic frequencies to improve efficiency (similar to class-E). Here

when the drain voltage waveform build the shape of the square wave by adding odd

harmonics, than the drain current waveform adds even harmonics to build the shape

of half sine wave. This leads to no power is generated at the harmonics because there

is either no current or no voltage present for a particular harmonic. Therefore, ideal

efficiency (100%) can be achieved together with desired (high) output power by proper

controls of the harmonic loads. Since, class F has twice power handling capability

compared to class-E PAs. class F power amplifier has been designed using LDMOS in

TCAD by (Kashif et al., 2014) .

There also exist some more class of PAs such as G, H, S etc which uses different

techniques to increase efficiency of the amplifier.

3.3 PA Design Consideration

Figure 3.5: Power Amplifier setup

LDMOS used in this work finds application in GSM, GSM-PCS, WLAN etc. It is

widely used in base stations with 28V DC supply. Parameters required to characterize

PA is discussed below.

3.3.1 Power

There are 3 types of power involved in PA. Input power (Pin) is defined as the amount

that is provided by the input source. DC power (Pdc) is the amount provided by the

20

source at the drain end. RF output power (Pout) is the amount that is consumed by the

load. High Pout is always important as signal have to be sent long distances in com-

munication system and high power will reduce the number of base stations required.

As communication system is very large number of base stations are huge, hence de-

signers are forced to design PAs of low cost and high Pout. LDMOS is seen to provide

320-640W power for GSM base stations (Bengtsson, 2008).

1 dB compression point

1dB compression point as shown in Fig. 3.5 is a point at which power gain drops by

1dB. It is the upper limit for input power range to supplied and upper limit on maximum

output power that can be extracted with PA becomes too non-linear.

Actual response

P out [

dBm

]

Pin [dBm]

Small signal region

Theoretical response

1 dB1-dB compression point

Large signal region

Figure 3.6: 1 dB compression point

3.3.2 Power Gain (G)

Power gain has various definition such as unilateral power gain, transducer power gain

and operating power gain etc. These definitions are used to highlight different properties

of an amplifier. Most commonly used power gain is operating power gain (G).

G =Power delivered to load

power supplied to the amplifier=

PL

Pin

21

In our design ideal circuit components are used hence PL = Pout. For optimal

performance gain is expected to be constant for large input signals.

3.3.3 Efficiency

Efficiency is defined as the ability to convert DC power (Pdc) available from the supply

source to RF output power (Pout). Mainly there are two types of efficiency Power Added

Efficiency (PAE) and drain efficiency (ηd).

Drain efficiency (ηd)

It is defined as the ratio of RF output power to DC power supplied by the power supply

source.

ηd =Pout

Pdc

here Pdc = Vd,dc ∗ Id,dc, Vd,dc is drain dc voltage and Id,dc is drain dc current.

Power added efficiency (PAE)

It is an important definition used for PA design. It is important when supply power is

low or when heat dissipation is of concern.

PAE =Pout − Pin

Pdc

Efficiency depends on quiescent point and it increases with reducing conduction

angle.

3.3.4 Linearity

Designing PAs with good linearity is important in new communication standard. Tran-

sistors used in PA design are inherently non-linear hence making it completely linear is

not possible. PA is linear only upto certain small level of input power and then it goes

22

into the non-linear region. Filter circuits are used to remove harmonic contents from the

output but harmonics close to fundamental frequency are difficult to remove completely

and causes distortion, which is referred to as inter-modulation distortion (IMD).

Non-linear behavior only upto 1dB compression point is entertained and marks the

point of maximum input and output power. To analyze the nonlinear behavior of PAs

two-tone test can be used. In this test PAs input is loaded with two signal sources of

same amplitude and slightly different frequency (same channel frequency). The output

contains many harmonics but IM3 frequencies lie very close to fundamental and are the

main contributors of distortion as seen in the Fig. 3.6.

Figure 3.7: Two tone power spectrum with dominant harmonics

Output power of 3rd inter-modulated harmonic is plotted along with actual response

(fundamental tone) in Fig. 3.7. OIP3 is important figure of merit in non-linearity

analysis and it is expected to be as high as possible for better linearity.

Actual response

Out

put p

ower

[dBm

]

Pin [dBm]

1 dB1-dB compression point

3rd order intercept

IIP3

OIP3

3rd order Intermodulation

IP1dB

Figure 3.8: Two tone test, 3rd order intercepts for IMD behavior

23

3.3.5 Stability

PA can become unstable due to gate to drain coupling and layout of the amplifier. The

condition for stability is defined by stability factor (K).

K =1− |S11|2 − |S22|2 + |∆|2

2|S12.S21|≻ 1

if |∆| ≺ 1 the amplifier will become unconditionally stable, where ∆ = S11S22 −

S12S21

3.4 Large signal characterization and matching network

Large signal impedance matching is important to obtain optimal performance of a PA.

The technique used to obtained this impedance is called Load-Pull. Load pull can be

used for different frequencies for both on wafer and in-fixture setup.

3.4.1 Load Pull

Obtaining proper load impedance is necessary to extract optimum efficiency, output

power and gain. For different optimum parameters of efficiency, output power and

gain (EOG) required output impedance may be different, hence load impedance is cho-

sen such that it gives optimum compromised efficiency, power and gain (EOG). In Load

pull measurements different input and output impedance are loaded on the PA terminals

and for each impedance EOG values are measured and plotted on a contour. These con-

tour are used in the design of power amplifier to extract optimum matching impedance

(Arthaber et al., 2005).

Figure 3.9: Load-Pull test setup

Here load an source impedance are given by the tuners. Load-Pull test is of two

24

types active and passive load pull test. Matching network is not required at the input if

PA is used in integrated circuit though input source should have output impedance of

the previous stage.

Passive load-pull

In this electromechanical and PIN diode based tuners are used for source and load

matching. In this system load-pull analysis has limitation of upto 100-200W with min-

imum 1 impedance and frequency of upto 2GHz. It is not useful for PAs of optimum

impedance less than 1. If it used at higher frequency than power of the PA must be less.

Active load-pull

It is more famous and widely used for large signal characterization. In this instead of

using impedance tuner at the output, attenuator and phase shifter coupled with coupler

are used for impedance matching. Load impedance is synthesized by sampling the

output signal and modifying its phase and amplitude. Active load-pull has a drawback

of stability of amplifier which may cause distortion. Impedance obtained from load-pull

test is used to make input and output matching network.

25

CHAPTER 4

Silicon Semiconductor on Insulator Laterally Diffused

MOSFET (Si SOI-LDMOS)

The High Voltage (HV) lateral MOS transistor device, where extension of the gate elec-

trode works as a field plate, is one of the most interesting structures in the mainstream

HV technologies. LDMOS on silicon on insulator is preferred more compared to bulk

LDMOS because it offers much better dielectric isolation and lesser leakage currents.

The structure of the LDMOS is different from that of conventional MOSFET owing

to the presence of the extended drain region as well as a lateral non-uniformly doped

channel region which makes the behavior of the LDMOS very complex compared to

the simple MOSFET. LDMOS device has been improved with time by optimizing its

structure in various ways. The source region is connected to the substrate with p-type

deep sinker in order to eliminate the source bonding wire (Wood et al., 1996; Kim et al.,

2001), different alloys of polysilicon-silicides are utilized (Yoshida, 1997), gate short-

ening (Shindo et al., 2001), drift region is made as step (two-stage drift techniques)

(Xu et al., 1999), drift region have stacked layers of different doping (Cai et al., 2001),

dual implanted buried layer (n and p-type ) at RESURF (reduced surface field) (Olsson

et al., 2002), applying a trench gate (Cortes et al., 2007a), adding field plate on the

gate (Cortes et al., 2007b) etc. These optimization’s are aimed at providing better RF

performance.

4.1 Device structure

The LDMOS is a asymmetric device with a drift region located between the channel

and the heavily doped drain contact. The channel region is self assigned to the gate and

is created by the diffusion of p-type under the gate. The resulting distribution along

the channel is non-uniform decreasing towards the drain. The source is then formed by

diffusion of n-type. Since the channel and source are formed by successive diffusion

steps, these devices are called as lateral double-diffused transistors. Since LDMOS uses

lateral double diffusion technique, it is possible to have much shorter channels without

the limitations imposed by photolithography. The n-drift region is to withstand high

voltages applied. The gate electrode covers the surface of the channel region as well

as part of the drift region. The n-drift region is lightly doped compared to the channel

region and hence the depletion region extends more into the drift region leading to

a voltage drop between drain contact and the active channel of the device. It is this

voltage which allows higher breakdown voltages to be achieved. The entire transistor

is isolated from the bulk by a buried oxidewhich will provide dielectric isolation of the

device. The drain electrode, source electrode and the gate electrode are located at the

surface of the device and hence it is easy to integrate the LDMOS with low voltage

circuits to form High Voltage Integrated Circuits.

4.1.1 Device structure before this project work

P-well i.e. the channel region (Region 1) is uniformly doped for simplifying the mod-

eling. The abrupt transition from region 1 to n-drift region is indicated by the point

’Di’. The device has a very long drift region to withstand externally applied high volt-

ages. The n-drift region consists of two parts: one under the thin oxide (region 2) and

the other under the field oxide (region 3). The transition from region 2 to region 3 is

represented by ’D’. The entire drift region is lightly doped to withstand high operating

voltages. The length of the drift region varies with increase in the voltage blocking ca-

pability of the device. There is no significant extension of the gate electrode on region

3. Also the field oxide is very thick. Hence the variation of the gate to source voltage

does not directly affect the behavior of this region. The important dimensions of the

LDMOS devices are the length of region-1 (L_R1), the length of region-2 (L_R2) and

the length of region-3 (L_R3).

4.1.2 Final Device structure

In this project work we tried to re-designed the LDMOS for Low Power Amplifier

(LPA) and Higher Power Amplifier (HPA). Structural design for LPA remains same as

shown in the Fig. 4.1 but in HPA structural changes are there as shown in the Fig. 4.2.

Instead of Locos it was found that STI gives better Isolation. In this structure N-drift

27

Figure 4.1: Device structure before start of work

region is divided into 2 regions i.e. region 3 and region 4 as compared to only region

3 in Fig. 4.1. Region 4 has higher doping compared to region 3 which is explained in

chapter 5. Also region 2 and 3 are divide horizontally by a dash line parallel to length

of the device as shown in Fig. 4.2, the upper region has less doping compared to lower

in order to increase breakdown voltage as explained in the next chapter.

Figure 4.2: Final high power device structure

28

Table 4.1: Important lengths of final device

Parameters HPA LPAL_R1 (µm) 0.1 0.05L_R2 (µm) 0.5 0.3L_R3 (µm) 2.775 1.025L_R4 (µm) 1.9 −−L_locos (µm) −− 0.725L_STI (µm) 4.3 −−

Total Length (µm) 7.9 4

29

CHAPTER 5

SOI-LDMOS Design optimization for Power Amplifier

and Analysis

5.1 Introduction

The given SOI-LDMOS device needs to be improved for using it in PAs. Our target

is to use these devices in communication system e.g. Mobile handsets (Low PA) and

base stations (High PA). To improve this device various device design parameters need

to be analyzed. These parameters are discussed and analyzed in detail in the section

below form the perspective of both LPA and HPA. LDMOS in HPA are used widely

in base stations but LDMOS in handsets are rarely used but it has shown by (Asbeck

et al., 2012) that by using different circuit techniques CMOS technology can be used in

handsets so it would be a good decesion to improve LDMOS design as well.

Device FoMs as discussed in introduction are improved to make it suitable for power

amplifier. LPA is designed for drain dc voltage of 3.7V and thershold voltage (Vth) of

around 0.4V . HPA is designed for drain dc voltage of 28V and Vth of around 1.72V .

The PA design is amid for Long-Term Evolution (LTE) system in India which lies

from 2.3GHz to 2.4GHz, hence Ac FoMs has to be such that is works well in this

frequency band.

5.2 Optimizing Length of region 1, 2 and 3 for Low

Power Amplifier (LPA)

The Mobile used (Low power) Amplifier design is considered in this part. Here first

the optimum lengths of region 1,2 and 3 are investigated. In order to start with the

design,as we know it is for a lower power amplifier so we fix the total length of the

device as 4.5µm based on experience. The Analysis is done by varying region 1 length

(L_R1) and region 2 length (L_R2) and in this way length region 3 length (L_R3) also

changes as total length of the device is fixed. L_R1 is varied as 0.05µm, 0.1µm and

0.2µm where as L_R2 is varied from 0.1µm - 0.7µm at a step of 0.1µm. For different

channel lengths the doping of the channel is changed so as to obtain a constant Vth of

approximately 0.4V . At the start of the design process our motive is just to catch the

right values of L_R1 and L_R2 so as to get the correct start in the design process. For

choosing the appropriate values of these lengths we will analyze with respect to parame-

ters as Transition Frequency(FT ), Maximum Oscillation Frequency(Fmax), Breakdown

Voltage(Vb), ON-State Resistance(Ron) and Maximum saturation current (Idsat).

5.2.1 Analysis

Constant Thershold Voltage Vth and IDV G characteristics

Constant Vt is achieved by using different uniform channel doping Nch.

Table 5.1: LPA channel doping concentration.

L_R1 Nch(/cm3)

0.05µm 5e17

0.1µm 2e17

0.2µm 1.16e17

0 2 4 6 8 100.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

R2 = 0.4 mVds= 3.7V

R1=0.2 m R1=0.1 m

I ds (A

/m

)*10

-4

Vgs (Volts)

R1=0.05 m

(a) Linear

0.0 0.5 1.0 1.5 2.0

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

R2 = 0.4 mVds= 3.7V

R1=0.2 m R1=0.1 m

I ds (A

/m

)

Vgs (Volts)

R1=0.05 m

(b) Log

Figure 5.1: Current Waveform for devices with different L_R1 showing constant Vth

The Vth of 0.4V is taken as per the convention of a low PA. From the Fig. 5.1.

we can see that as L_R1 increases the saturation current increases because saturation

occurs at high Vgs and at this condition L_R1 and L_R2 acts as low resistance region

31

and L_R3 acts as high resistance region which decreases with increase in L_R1 as

device total length is fixed.

0 2 4 6 8 100.0

0.5

1.0

1.5

2.0

2.5

Increasing R2

0.1-0.7 m at a step of 0.1 m

I ds (A

/m

)*10

-4

Vgs (Volts)

R1=0.05 mVd=3.7V

Figure 5.2: IDV G for L_R1 = 0.05µm

0 2 4 6 8 100.0

0.5

1.0

1.5

2.0

2.5

Increasing R2

0.1-0.7 m at a step of 0.1 m

I ds (A

/m

)*10

-4

Vgs (Volts)

R1=0.1 mVd=3.7V

(a) L_R1 = 0.1µm

0 2 4 6 8 100.0

0.5

1.0

1.5

2.0

2.5

3.0

Increasing R2

0.1-0.7 m at a step of 0.1 m

I ds (A

/m

)*10

-4

Vgs (Volts)

R1=0.2 mVd=3.7V

(b) L_R1 = 0.2µm

Figure 5.3: IDV GwithL_R2

From the above figure 5.2 and 5.3 we can see that for any L_R1 current increases

with increase in L_R2 this is because conductivity of region R2 is more than region

R3 because it is under the gate which cause accumulation of charge carriers, so as

L_R2 increases L_R3 decreases because total device length is fixed and hence current

increases.

The comparison plot clearly shows advantage of using large channel length as well as

large region 2 length.

32

0 2 4 6 8 100.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

R1=0.2 m R1=0.1 m

R2= 0.1 m

R2= 0.4 m

R2= 0.7 m

I ds (A

/m

)*10

-4

Vgs (Volts)

R1=0.05 m

Figure 5.4: IDV G Comparision with L_R1 and L_R2

Breakdown Voltage Vb

The maximum swing of Vd ideally possible is 2 ∗ 3.7 = 7.4V , so the Snapback voltage

(Vbmax) at highest Vgs of operation should be more than atleast 20% of 7.4V, which also

implies the snapback Voltage at Vgs = 0V also known as breakdown Voltage should be

much more than Vbmax, as snapback voltage decreases on increasing Vgs .

0.1 0.2 0.3 0.4 0.5 0.6 0.7

22

24

26

28

30

32

34

36

38

R1=0.2 m

R1=0.1 m

Brea

kdow

n Vo

ltage

Vb (

Volts

)

R2 length ( m)

R1=0.05 m

(a) Vgs = 0V

0.1 0.2 0.3 0.4 0.5 0.6 0.7

15

16

17

18

19

20

21

22

23

24

R1=0.2 m R1=0.1 m

Brea

kdow

n Vo

ltage

Vb (

Volts

)

R2 length ( m)

R1=0.05 m

(b) Vgs = 3V

Figure 5.5: Breakdown Voltage variation with L_R1 and L_R2

From the above figure 5.5 it can be seen that as L_R2 increases breakdown voltage

decreases because with increase in L_R2 drift region length(L_R3) decreases as the

total device length is fixed. Decrease in L_R3 causes most of the electric field generated

due to drain to decrease in this small region and hence high value of electric field is

reached at lower Vds which causes it to breakdown early. Similarly breakdown voltage

33

decreases with increase in L_R1. In Fig. 5.5(a) some anomalous behavior can be seen

by L_R1 = 0.05µm and L_R1 = 0.1µm. We had made sure that Vth of all the 3 devices

to be equal by changing the channel doping of each device.

0 5 10 15 20 25 30 35

0.0

1.3

2.6

3.9

5.2

6.5

7.8

R1=0.05 mVg=0V

R2=0.7 m R2=0.6 m R2=0.5 m R2=0.4 m R2=0.3 m R2=0.2 m

I ds (A

/m

)*10

-4

Vds (Volts)

R2=0.1 m

(a)

0 5 10 15 201E-10

1E-9

1E-8

1E-7

1E-6

R1=0.05 mVg=0V

R2=0.7 m R2=0.6 m R2=0.5 m

R2=0.4 m R2=0.3 m R2=0.2 m

I ds (A

/m

)

Vds (Volts)

R2=0.1 m

(b)

0.0 0.9 1.8 2.7 3.6 4.5

0

1

2

3

4

5

6

R1=0.05 mVg=0VVd=20V

R2=0.7 m R2=0.6 m R2=0.5 m

R2=0.4 m R2=0.3 m R2=0.2 m

Elec

tric

feild

(V/c

m)*

105

Device length ( m)

R2=0.1 m

(c)

Figure 5.6: Anomalous Breakdown behavior of L_R1 = 0.05µm,

Doping done is of uniform nature but with decreasing channel length due to the in-

fluence(diffusion) of source region the doping profile becomes nonuniform, as well as

effect of diffusion current becomes more prominent with increasing Vds and decreasing

channel length. Fig. 5.6(a) shows same anomalous trend of breakdown trend as seen

in Fig 5.5(a) for L_R1 = 0.05µm, from Fig 5.6(b) it can be seen that leakage current

is very high which is an important factor in deciding breakdown voltage with Impact

Ionization, Fig. 5.6(c) does not show any anomalous behavior and electric field in-

creases with increase in L_R2. So it is not only high electric field which is causing the

breakdown but it is a combination of both current and electric field.

0.0 0.9 1.8 2.7 3.6 4.51E15

1E16

1E17

1E18

1E19

1E20

1E21

1E22

1E23

1E24

1E25

R1=0.05 mVg=0VVd=20V

R2=0.7 m R2=0.6 m R2=0.5 m R2=0.4 m R2=0.3 m R2=0.2 m

Impa

ct Io

niza

tion

Gen

erat

ion

Rat

e (p

airs

/cm

3 /s)

Device length ( m)

R2=0.1 m

(a) Log scale

0.0 0.9 1.8 2.7 3.6 4.50

2

4

6

8

10

12

14

R1=0.05 mVg=0VVd=20V

R2=0.7 m R2=0.6 m R2=0.5 m R2=0.4 m R2=0.3 m R2=0.2 m

Impa

ct Io

niza

tion

Gen

erat

ion

Rat

e (p

airs

/cm

3 /s)*

1024

Device length ( m)

R2=0.1 m

(b) Linear scale

Figure 5.7: Anomalous Impact Ionization Rate behavior of L_R1 = 0.05µm

Which is proved to be true in Fig. 5.7(a) as Impact Ionization(II) rate is highest for

L_R2 = 0.1µm though the electric field for it is minimum. The analysis of II rate is

done at Vds = 20V which is below the breakdown Voltage of any L_R2 hence II pairs

34

generated is dominated by that L_R2 region which has highest leakage current but from

Fig. 5.7(a) it is seen that II rate for higher L_R2 starts to peak as 20V is closer to

their breakdown voltage. Another important thing to notice is highest electric field and

highest II pairs generation does not take place at the same position in the device. It was

found that though highest electric field point is located at interface of region 2 and 3 but

current density is very low at that place which results in decreased II rate.

5 10 15 201E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4 L_R1=0.1 mVds=28VVgs=0V

I ds (A

/m

)

Vds (Volts)

Increasing L_R2 0.1-0.7 mstep: 0.1 m

(a) L_R1 = 0.1µm

0 5 10 15 201E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

R1=0.2 mVg=0VVd=20V

R2=0.7 m R2=0.6 m R2=0.5 m R2=0.4 m R2=0.3 m R2=0.2 m

I ds(A

/m

)

Vds (Volts)

R2=0.1 m

(b) L_R1 = 0.2µm

Figure 5.8: Breakdown Voltage behavior for L_R1 = 0.1µm and L_R1 = 0.2µm

Similar is the case of device with L_R1 = 0.1µm, as seen in Fig. 5.8 the leakage

current is high as compared to device with L_R1 = 0.2µm which shows no anomalous

behavior. In Fig. 5.5(b) we do not see any anomalous behavior as at high Vgs current

in all the 3 devices is high so the deciding factor is high electric field which follows an

usual trend.

ON-state Resistance Ron

Ron variation in Fig. 5.9 follows the same trend as explained by equations mentioned

in the introduction. Ron decreases with L_R1 as well as L_R2 because the effective

L_R3 length decreases so does the ON-state resistance. As the breakdown voltages

are more than required, Ron can be further decreased by increasing the L_R3 doping

concentration.

Transition Frequency FT

Transition frequency is defined as the frequency at which current gain of transistor is

equal to unity. It is an important parameter which defines gain as well as non-linearity

35

0.1 0.2 0.3 0.4 0.5 0.6 0.7

1.0

1.5

2.0

2.5

3.0

3.5

4.0

ON

-Sta

te R

esis

tanc

e R

ON (

-m

)*10

4

L_R2 ( m)

L_R1=0.05 m L_R1=0.1 m L_R1=0.2 m

Vgs=2V

Figure 5.9: Ron variation with L_R2

of the transistor. If the operating frequency is orders of magnitude below FT then tran-

sistor is assumed to have less non-linear effects. Since at this position our operating

point is not fixed then comparing FT with our operating frequency would be mean-

ingless hence here we will try to maximize the overall maximum transition frequency

(FTmax) and once the complete design is done and our operating point is fixed then we

will compare our operating frequency with FT .

FT =gm

2π(Cgs + Cgd)

For extracting FT we use low frequency which insures the above equation is valid,

in our case we use frequency of 5e7Hz to extract gm, Cgs and Cgd.

It can be seen that with increase in L_R2 area of the gate overlapped region in-

crease so does the capacitance. So these increase in capacitance will decrease FT as

gm variation is very small compared to capacitance.

We see here that FTmax is large as compared to our operating frequency of 2.35GHz

(midpoint of 2.3-2.4GHz band) but can further be increased by reducing parasitic ca-

pacitance which will be done once lengths of all the 3 regions are finalized. One way to

decrease parasitic capacitance is to increase LOCOS thickness.

36

-1 0 1 2 30

1

2

3

4

R1=0.2 mVd=3.7V

R2=0.7 m R2=0.6 m R2=0.5 m R2=0.4 m R2=0.3 m R2=0.2 m

Cgd

+ C

gs (F

arad

s/m

)*10

-15

Vgs (Volts)

R2=0.1 m

Figure 5.10: Capacitance variation with Vgs

1E-7 1E-6 1E-5 1E-40

2

4

6

8

10

12

14

16

FTmax

Tran

sitio

n Fr

eque

ncy

FT (G

Hz)

Id (A/ m)

L_R1=0.2 mL_R2=0.4 mVd=3.7V

Figure 5.11: FT variation with Vgs

37

0.1 0.2 0.3 0.4 0.5 0.6 0.710

15

20

25

30

35

40

Max

imum

Tra

nsiti

on F

requ

ency

FT m

ax (G

Hz)

L_R2 ( m)

L_R1=0.05 m L_R1=0.1 m L_R1=0.2 m

Vds=3.7V

Figure 5.12: FTmax variation with Vgs

Maximum Oscillation Frequency Fmax

Fmax is defined when power gain of the transistor becomes equal to unity. If the oper-

ating frequency is above Fmax then sole purpose of the power amplifier is lost. Hence it

is one of the key parameter while designing a power amplifier. In literature authors try

to reduce Rg to further increase Fmax by using different metal gates. Here also since

device operating point is not fixed hence comparing operating frequency with Fmax

would not make sense hence Maximum Fmax plot is compared with variation in L_R1

and L_R2 .

1E-9 1E-8 1E-7 1E-6 1E-5 1E-40

3

6

9

12

15

18

21

24

Peak Fmax

Max

imum

Osc

illat

ion

Freq

uenc

y F m

ax (G

Hz)

Id (A/ m)

L_R1=0.2 mL_R2=0.4 mVd=3.7V

(a) Fmax

0.1 0.2 0.3 0.4 0.5 0.6 0.7

20

30

40

50

60

70

Peak

Max

imum

Osc

illat

ion

Freq

uenc

y F m

ax (G

Hz)

L_R2 ( m)

L_R1=0.05 m L_R1=0.1 m L_R1=0.2 m

Vds=3.7V

(b) peak Fmax

Figure 5.13: Fmax and peak Fmax for varies region lengths

One very important point to note is FT and Fmax are small signal parameters and

for power amplifiers the operating point is never fixed but keeps on changing hence FT

38

and Fmax is taken as the average value over the entire range of operation.

Conclusion

For L_R1 there is a trade off between 0.05µm and 0.1µm former is better in all except

leakage current, Ron and saturation current. Also there is a trade off for L_R2 between

0.3µm, 0.4µm and 0.5µm.

5.3 Optimizing Length of region 1, 2 and 3 for High

Power Amplifier (HPA)

The kind of analysis done above for LPA is done now for HPA. We have started the

device design for High Power Amplifier using some default structure and will go on

optimizing each parameter in the process. Here we have analyzed for L_R1 = 0.1µm,

0.2µm and 0.3µm. We have started with least value of L_R1 = 0.1µm (channel length)

based on previous experience and other authors designs. L_R2 (length of drift region

under the gate) is varied from 0.1 − 0.7µm with a step of 0.1µm and total length of

the device is kept constant at 9.9µm so L_R3 (length of drift region not under the gate)

also changes accordingly as L_R1 and L_R2 are changed. The channel doping of all

the 3 devices are adjusted so as to produce same Threshold Voltage Vt of around 1.72V .

At the start of the design process our motive is just to catch the right values of L_R1

and L_R2 so as to get the correct start in the design process. Inorder to get appropriate

values of these lengths we will analyze it with respect to parameters such as Transi-

tion Frequency(FT ), Maximum Oscillation Frequency(Fmax), Breakdown Voltage(Vb),

ON-State Resistance(Ron)and Saturation current.

5.3.1 Analysis

Constant Thershold Voltage Vt and IDV G characteristics

Constant Vt is achieved by using different channel doping Nch.

Decreasing channel length causes decrease in Vt hence channel doping has to be

39

Table 5.2: HPA channel doping concentration.

L_R1 Nch(/cm3)

0.1µm 4.25e17

0.2µm 2.42e17

0.3µm 1.8e17

increased to maintain it at a particular value. The IDV G for different L_R1 and L_R2

are shown below.

0 2 4 6 8 10 12 140.0

0.5

1.0

1.5

2.0

2.5

3.0

Increasing R2

0.1-0.7 m at a step of 0.1 m

I ds (A

/m

)*10

-4

Vgs (Volts)

R1=0.1 mVd=28V

Figure 5.14: IDV G for L_R1 = 0.1µm

From the Fig. 5.14 and 5.15 it can seen that for any L_R1 current increases with in-

crease in L_R2 this is because conductivity of region R2 is more than region R3 because

it is under the gate which cause accumulation of charge carriers, so as L_R2 increases

L_R3 decreases because total device length is fixed and hence current increases.

Now from Fig. 5.16 we can observe 2 things. First as L_R1 decreases current increases

though it should be opposite because decrease in L_R1 increase length of high resistive

region R3.

Second with decrease in L_R1 Transconductance gm also increases. As this device is

operated at 28V a large part of the voltage drops across the channel which decreases the

effective channel length. Effective decrease in channel length is more for short channel

devices hence in Fig. 5.16 deviation of curve for L_R1 = 0.1µm is more as compared

to other two.

40

0 2 4 6 8 10 12 140.0

0.5

1.0

1.5

2.0

2.5

3.0

Increasing R2

0.1-0.7 m at a step of 0.1 m

I ds (A

/m

)*10

-4

Vgs (Volts)

R1=0.2 mVd=28V

(a) L_R1 = 0.2µm

0 2 4 6 8 10 12 140.0

0.5

1.0

1.5

2.0

2.5

3.0

Increasing R2

0.1-0.7 m at a step of 0.1 m

I ds (A

/m

)*10

-4

Vgs (Volts)

R1=0.3 mVd=28V

(b) L_R1 = 0.3µm

Figure 5.15: IDV G

0 2 4 6 8 10 12 140.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

R1=0.3 m R1=0.2 m

R2= 0.1 m

R2= 0.7 m

I ds (A

/m

)*10

-4

Vgs (Volts)

R1=0.1 m

Figure 5.16: IDV G Comparision

41

Ids =1

2∗ µn ∗ Cox ∗

W

L∗ (Vgs − Vt)

2

=1

2∗ µn ∗ (

ϵ

d) ∗ W

L∗ (Vgs − Vt)

2

=µn ∗W ∗ ϵ ∗ (Vgs − Vt)

2

2 ∗ d∗ 1

L

gm =µn ∗W ∗ ϵ ∗ (Vgs − Vt)

d∗ 1

L

(5.1)

In the above equation d is oxide thickness and L is the effective channel length.

So here increase in resistance of region R3 has less effect as compared to LPA seen in

previous section.

Breakdown Voltage Vb

The device is operated at DC Vds of 28V hence for PA application Vds should swing

from theoretically 0 − 56V . The safe operating region of Vds should contain this large

swing.

(a) Vgs = 0V (b) Vgs = 6V

Figure 5.17: IDV D for HPA

As seen from Fig. 5.17(a) device starts to breakdown at approximately Vds = 53.5V

but snapback occurs at a much higher voltage of around Vds = 145V , our safe operating

condition is just satisfied and improvement is required, also there is no appreciable

variation of breakdown voltage with L_R2 .

Safe operating region condition should be satisfied for Vgs = 0V to approximately

Vgs = 6V (as seen from Fig. 5.16). From Fig. 5.17(b) it can clearly be seen that the

Safe operating region condition is violated. So first we need to find solution for this

42

problem and then proceed further.

0 2 4 6 8

0

1

2

3

4

L_R1=0.1 mL_R2=0.4 mVgs=6VVds=25V

Before region 4 After region 4

Elec

tric

Feild

(V/c

m)*

105

Device Length ( m)

(a) Electric Feild

0 10 20 30 40 50 60 700

1

2

3

4

5

6

7

8

L_R1=0.1 mL_R2=0.4 mVgs=6V

Before region 4 After region 4

I ds (A

/m

)*10

-4

Vds (Volts)

(b) IDV D

Figure 5.18: Comaprision for Vgs = 6V

So by introducing region R4 which is part of region R3 on the drain side as explained

in chapter 4, huge improvements can be seen in Fig 5.18 and Fig 5.19 . Doping of region

R3 is 1e16/cm3 while doping of new region R4 is 4e16/cm3 which causes P-N Junction

depletion region of the channel and R2 not to reach the drain but instead only till the

junction of R3 and R4. If the depletion region reaches the very highly doped drain, the

electric field will be high because it will not be able to deplete the drain (Analogy is

highly doped P-N junction) where as introduction of R4 which is less highly doped than

drain causes lesser peak electric feild.

So this newly created region should also effect positively to IDV D at Vgs = 0V .

0 2 4 6 8

0

1

2

3

4

5 L_R1=0.1 mL_R2=0.4 mVgs=0VVds=53.5V

Before region 4 After region 4

Elec

tric

Feild

(V/c

m)*

105

Device Length ( m)

(a) Electric Feild

20 40 60 80 100 120 140 160 1800.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

L_R1=0.1 mL_R2=0.4 mVgs=0V

Before region 4 After region 4

I ds (A

/m

)*10

-4

Vds (Volts)

(b) IDV D

Figure 5.19: Comaprision for Vgs = 0V

From Fig. 5.19 it can be seen that there is a good improvement for Vgs = 0V case

as well. The concept of R4 is introduced at this stage so that we can be confident of

solving the problem seen in Fig. 5.17, In depth analysis of length of R4 and its doping

is done in later section.

43

40 60 80 100 120 1400

1

2

3

4

L_R2=0.1 m L_R2=0.7 m

L_R1=0.3 m

L_R1=0.2 m

L_R1=0.1 m

Vg=0V

I ds (A

/m

)*10

-4

Vd (Volts)

Figure 5.20: IDV D Comparision at Vgs = 0V without R4

Above figure shows the normal trend of decreaing snapback point with increase in

L_R1.

ON-state Resistance Ron

Study of Ron is tough at this moment because as seen from Fig. 5.16 all the 3 devices

reach saturation at different value of Vgs hence fixing particular value of Vgs will not be

justifiable hence Ron variation with L_R2 for L_R1 = 0.1µm is only considered.

Above figure shows the normal trend of decreasing Ron with increase in L_R2.

Transition Frequency FT

FT here does not show the same trend as shown by Low PA design. Increase in transcon-

ductance gm is more than increase in capacitance for different L_R2 which causes FT

to increase with L_R2 instead of decrease as seen for the Low PA. So having larger

L_R2 is beneficial in many aspect as seen for Idmax, RON and here by FT as well but

only drawback is having very large L_R2 can decrease your drain voltage safe oper-

ating region. Method to increase FT would be focused on decreasing capacitance and

44

0.1 0.2 0.3 0.4 0.5 0.6 0.7

4.0

4.5

5.0

5.5

6.0

ON

-Res

ista

nce

RO

N (

-m

)*10

4

L_R2 ( m)

L_R1=0.1 m Vgs=6V

Figure 5.21: ON-state resistance

0.1 0.2 0.3 0.4 0.5 0.6 0.72

4

6

8

10

Max

imum

Tra

nsiti

on F

requ

ency

FT m

ax (G

Hz)

L_R2 ( m)

L_R1=0.1 m L_R1=0.2 m L_R1=0.3 m

Vds=28V

Figure 5.22: FTmax Comparison for different L_R1

45

increasing gm.

Maximum Oscillation Frequency Fmax

Fmax does not follows the same trend as of FT.

0.1 0.2 0.3 0.4 0.5 0.6 0.7

10

11

12

13

14

15

16

17

Pe

ak M

axim

um O

scill

atio

n Fr

eque

ncy

F max

(GH

z)

L_R2 ( m)

L_R1=0.1 m L_R1=0.2 m L_R1=0.3 m

Vds=28V

Figure 5.23: Peak Fmax variation

Fmax here show usual trend as expected. On increasing LR(2) Rg decreases but

capacitance increases which cause overall decrease in Fmax.

Conclusion

By analyzing different FoM parameters it is found that devices with L_R1 =0.1 and

0.2µm and L_R2 =0.4, 0.5 and 0.6µm will be used for further analysis.

5.4 Gradient channel or Double diffusion analysis for

LPA and HPA

24 devices(combination of different L_R1 and L_R2) were analyzed in the previous

sections for Low and High Power Amplifier each. Based on the results sample size has

46

been reduced to 6 device each for Low and High PA devices. On these selected devices

gradient channel doping is done as compared to uniform in the previous analysis. Gradi-

ent doping is done such that they still have the same threshold Voltage Vt and then they

are analyzed further. Low PA is analyzed for L_R1 =0.05 and 0.1µm and L_R2 =0.3,

0.4 and 0.5µm. High PA is analyzed for L_R1 =0.1 and 0.2µm and L_R2 =0.4, 0.5

and 0.6µm. It has been showed by (Mohapatra et al., 2005) that single-sided hallow

channel doping offer better dc and high frequency performance.

5.4.1 Analysis

Gradient channel doping

Figure 5.24: Cuts for doping analysis

The 2 arrows in the Fig. 5.24 shows direction of doping concentration measure-

ments. Through the source first P-type doping is done which diffuses in the channel

region as well and then N-type doping of higher concentration is done so that source is

of N-type but both the doping have different diffusion rate so that the channel form a

P-type doping gradient. The effect of this double diffusion is seen through channel as

well as along the height of the source which is indicated by the arrows.

First we will see doping profiles of the low PA devices.

Fig. 5.25 shows channel doping variation for L_R1 = 0.05µm since channel is

very short it is not possible to have high doping in the channel at the source side which

47

decreases towards the drain. When the channel is uniformly doped the doping concen-

tration decreases at a very fast rate due to the influence of highly doped source but due

to double diffusion channel becomes moves uniform as seen in the figure below.

0.00 0.01 0.02 0.03 0.04 0.05-4.5

-4.0

-3.5

-3.0

-2.5

-2.0

-1.5

-1.0

-0.5

0.0

0.5

Dop

ing

Con

cent

ratio

n (c

m-3)*

1017

Distance along the channel ( m)

Nonuniform Uniform

L_R1=0.05 m

Figure 5.25: Doping profile along the device channel

In the Nonuniform case (i.e double diffusion) the background doping concentration

of P-region is kept to be 3.2e17cm−3 where as in the uniform case doping concentration

is 5e17cm−3 so as to maintain approximately same Vth

For L_R1 = 0.1µm double diffusion effect can be seen more clearly.

0.00 0.02 0.04 0.06 0.08 0.10-3.0

-2.5

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

Dop

ing

Con

cent

ratio

n (c

m-3)*

1017

Distance along the channel ( m)

Nonuniform Uniform

L_R1=0.1 m

(a) along channel

0.4 0.5 0.6 0.7 0.8 0.9 1.0-4

-2

0

2

4

6

8

Dop

ing

Con

cent

ratio

n (c

m-3)*

1017

Distance along the device height ( m)

Nonuniform Uniform

L_R1=0.1 m

(b) along source height

Figure 5.26: Doping profile with L_R1 = 0.1µm for low PA

In Fig. 5.26(a) it can be seen that doping concentration is high at the source end

for double diffusion case and then decreases where as it is opposite for the uniformly

doped case. In uniform case P-region doping is 2e17cm−3 whereas for the other case

the background doping is 1e17cm−3. Effect of double diffusion can also be seen in the

Fig. 5.26(b), which shows doping profile along the source height starting from 0.35µm

48

below the oxide and source interface and upto the silicon thickness as shown in the

Fig. 5.24 . The profile shown in Fig. 5.26(b) is useful because it can remove problem

of punch through below the channel as well. Using double diffusion gives flexibility

of having lower background doping which reduces electric field at the region 1 and 2

interface.

Now lets see for high power amplifier.

0.00 0.02 0.04 0.06 0.08 0.10

-5

-4

-3

-2

-1

0

Dop

ing

Con

cent

ratio

n (c

m-3)*

1017

Distance along the channel ( m)

Nonuniform Uniform

L_R1=0.1 m

(a) along channel

0.4 0.5 0.6 0.7 0.8 0.9 1.0

-4

-2

0

2

4

6

8

Dop

ing

Con

cent

ratio

n (c

m-3)*

1017

Distance along the device height ( m)

Nonuniform Uniform

L_R1=0.1 m

(b) along source height

Figure 5.27: Doping profile with L_R1 = 0.1µm for high PA

0.00 0.05 0.10 0.15 0.20

-4

-3

-2

-1

0

1

Dop

ing

Con

cent

ratio

n (c

m-3)*

1017

Distance along the channel ( m)

Nonuniform Uniform

L_R1=0.2 m

(a) along channel

0.4 0.5 0.6 0.7 0.8 0.9 1.0-4

-2

0

2

4

6

8

Dop

ing

Con

cent

ratio

n (c

m-3)*

1017

Distance along the device height ( m)

Nonuniform Uniform

L_R1=0.2 m

(b) along source height

Figure 5.28: Doping profile with L_R1 = 0.2µm for high PA

Here effect of gradient channel doping is more pronounced then that of LPA de-

vices. In the above double diffusion devices for high PA design the background doping

concentration is kept constant at 1e17cm−3. Based on the channel profiles shown above

the basic characteristics for all the 6+6 devices are analyzed again to further narrow

down our search for the best optimized device.

49

Constant Threshold Voltage Vt and IDV G characteristics

Constant Vt of same value is maintained while doing double diffusion as that of uniform

doping. The IDV G characteristics for low PA does not change at all while same is true

for high PA except for L_R1 = 0.2µm where both gm and Idmax increases and this

increase depends on particular doping profile of the channel when DD is done.

0 2 4 6 8 100.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

L_R1=0.05 m L_R1=0.1 m

Vd=3.7V

L_R2=0.5 m

L_R2=0.4 m L_R2=0.3 m

I ds

(A/

m)*

10-4

Vgs (Volts)

Figure 5.29: IDV G of Low PA for L_R1 = 0.05 and 0.1µm

The above characteristics is similar to that obtained for uniform doping so here

double diffusion does not give any sort of advantage.

0 2 4 6 8 100.0

0.5

1.0

1.5

2.0

2.5

3.0

L_R1=0.2 m

L_R1=0.1 m

L_R2=0.4 m L_R2=0.5 m L_R2=0.6 m

Vd=28V

I ds (A

/m

)*10

-4

Vgs (Volts)

(a) gradient doping

0 2 4 6 8 100.0

0.5

1.0

1.5

2.0

2.5

3.0

L_R2=0.4 m L_R2=0.5 m L_R2=0.6 m

L_R1=0.2 mVd=28V

Gradient Channel doping

I ds (A

/m

)*10

-4

Vgs (Volts)

Uniform Channel doping

(b) Gradient and uniform doping

Figure 5.30: IDV G comparison for high PA

For the high PA case L_R1 = 0.2µm gives advantage of high gm and Idmax when

compared to uniform doped case.

50

Breakdown Voltage Vb

For the low PA case the maximum swing of Vd is 7.4V so the Snapback voltage at

highest Vgs of operation should be more than 20% of this swing i.e about 8.88V . Here

from Fig. 5.31(a) and Fig. 5.31(b) we can see the condition is satisfied. As compared

to uniform channel doping breakdown voltages does not change much with Double

diffused doping. So here we do not get any gain or loss for low PA.

0.30 0.35 0.40 0.45 0.5029

30

31

32

33

34

35

36

Brea

kdow

n Vo

ltage

Vbr

k (Vo

lts)

L_R2 ( m)

L_R1=0.05 m L_R1=0.1 m

Vgs=0V

(a) Vgs = 0V

0.30 0.35 0.40 0.45 0.5015

16

17

18

19

20

Snap

back

Vol

tage

(Vol

ts)

L_R2 ( m)

L_R1=0.05 m L_R1=0.1 m

Vgs=2V

(b) Vgs = 2V

Figure 5.31: Breakdown Voltage variation for Double diffused Low PA

For the high PA case maximum swing of Vd is 56.0V so the Snapback voltage at

highest Vgs of operation should be more than 20% of this swing i.e about 67.2V . The

breakdown characteristics for Double diffused device is exactly same as that for uniform

channel devices. So here too there is no gain nor loss. In Fig. 5.32(a) we can see

breakdown voltage is above 100V but safe operating area is only below 53.5V . Also at

higher Vgs = 6V the breakdown voltage is merely around 30V but as we had seen in

previous section this problem can be solved by using region R4.

15 30 45 60 75 90 105 120

0.1

1

10

I ds (A

/m

)*10

-4

Vds (Volts)

Vgs= 0L_R1=0.2 mL_R2=0.5 m

(a) Vgs = 0V

0 15 300

2

4

6

8

10

12

14

16

18

20

I ds (A

/m

)*10

-4

Vds (Volts)

Vgs= 6VL_R1=0.1 mL_R2=0.6 m

(b) Vgs = 6V

Figure 5.32: Breakdown Voltage variation for Double diffused High PA

51

ON-state Resistance Ron

As seen in the figure below, compared to uniform doping double diffusion reduces RON

to certain extend and this gives us a positive gain for implementing double diffusion

method. Reduction in RON is because of reduced channel resistance.

0.3 0.4 0.50.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

ON

-Sta

te R

esis

tanc

e R

ON (

-m

)*10

4

L_R2 ( m)

L_R1=0.05 m (U) L_R1=0.1 m (U) L_R1=0.05 m (DD) L_R1=0.1 m (DD)

Vgs=2V

(a) Low PA

0.4 0.5 0.64.1

4.2

4.3

4.4

4.5

4.6Vgs= 6V

ON

-Sta

te R

esis

tanc

e R

ON (

-m

)*10

4L_R2 ( m)

L_R1=0.1 m (U) L_R1=0.2 m (U) L_R1=0.1 m (DD) L_R1=0.2 m (DD)

(b) High PA

Figure 5.33: ON resistance variation (U-Uniform doping, DD-Double diffusion)

The above figure shows reduction in Ron for both Low and High PA device.

Transition Frequency FT

Transition frequency for Low PA device show a minor decrease for L_R2 = 0.3µm

though it is constant for all other device points. For High PA device it remains almost

constant for L_R1 = 0.1µm but good point is that it increases for L_R1 = 0.2µm. So

on combining both, overall the device FT also has a positive shift.

0.3 0.4 0.515

18

21

24

Max

imum

Tra

nsiti

on F

requ

ency

FT m

ax (G

Hz)

L_R2 ( m)

L_R1=0.05 m (U) L_R1=0.1 m (U) L_R1=0.05 m (DD) L_R1=0.1 m (DD)

Vds=3.7V

(a) Low PA

0.4 0.5 0.64

6

8

10 L_R1=0.1 m (DD) L_R1=0.2 m (DD)

Vds=28V

Max

imum

Tra

nsiti

on F

requ

ency

FT m

ax (G

Hz)

L_R2 ( m)

L_R1=0.1 m (U) L_R1=0.2 m (U)

(b) High PA

Figure 5.34: FTmax variation (U-Uniform doping, DD-Double diffusion)

52

Maximum Oscillation Frequency Fmax

In literature authors try to reduce Rg to further increase Fmax by using different metal

gates.Rg is composed of 2 part, first is the constant polysilicon or metal gate resistance

and other is variable channel resistance which varies with operating point as well as

with frequency. Here also since device operating point is not fixed hence comparing

operating frequency with Fmax would not make sense hence Maximum Fmax plot is

compared with variation in L_R1 and L_R2 .

0.3 0.4 0.5

25

30

35

40

Peak

Max

imum

Osc

illat

ion

Freq

uenc

y F m

ax (G

Hz)

L_R2 ( m)

L_R1=0.05 m (U) L_R1=0.1 m (U) L_R1=0.05 m (DD) L_R1=0.1 m (DD)

Vds=3.7V

(a) Low PA

0.4 0.5 0.610

11

12

13

14

15

Peak

Max

imum

Osc

illat

ion

Freq

uenc

y F m

ax (G

Hz)

L_R2 ( m)

L_R1=0.1 m (U) L_R1=0.2 m (U) L_R1=0.1 m (DD) L_R1=0.2 m (DD)

Vds=28V

(b) High PA

Figure 5.35: Peak Fmax comparison for Uniform channel doping(U) and Double dif-fused doping(DD)

In the figure above we can see that double diffusion is beneficial for low PA design as

it it increase Fmax when compared to uniform doping. For high PA the case is opposite

Fmax actually decreases with double diffusion. So DD has a positive effect on Low PA

and negative on High PA device.

Conclusion

For next analysis: For Low PA we will Analyze 3 devices, (L_R1 = 0.05µm,L_R1 =

0.3µm),(L_R1 = 0.05µm,L_R1 = 0.4µm) and (L_R1 = 0.05µm,L_R1 = 0.5µm).

For High PA we will analyze (L_R1 = 0.1µm,L_R1 = 0.5µm) and (L_R1 = 0.2µm,L_R1 =

0.4µm), so next we will analyze 5 device. Double diffusion is necessary to be used be-

cause it represents the real device, where fabrication of LDMOS is done using DD and

hence it is called LDDMOS. Graded channel doping has a advantage of better linearity

as shown by (Chen et al., 2009)

53

5.5 Introducing region 4 and doping analysis of region

2 and 3

After doing gradient doping or also called double diffusion all the device parameters

were analyzed and 5 devices were selected on the basis of an average best result. For

Low PA we will Analyzed 3 devices, (L_R1 = 0.05µm,L_R1 = 0.3µm),(L_R1 =

0.05µm,L_R1 = 0.4µm) and (L_R1 = 0.05µm,L_R1 = 0.5µm). For High PA we

analyzed (L_R1 = 0.1µm,L_R1 = 0.5µm) and (L_R1 = 0.2µm,L_R1 = 0.4µm).

5.5.1 Analysis

Optimizing region 2&3 doping and introducing region 4

Doping of region 2&3 effects a number of parameters. Increasing the region 2&3 dop-

ing reduces resistance which helps in increasing drain current as well as reducing ON-

resistance which are very important parameters, hence it should be increased as much

as possible but increasing doping decreases breakdown voltage which should be taken

into account.

while designing PA care should be taken that breakdown voltage should not lie in-

side the safe operating area. The safe operating area for low PA is below Vds = 8.88V

and for high PA it is below Vds = 67.2V , we have fixed these values by taking a margin

of 20% from the actual safe operating area.

The Vds safe operating area should be satisfied by all values of Vgs i.e from Vgs =

0 to Vgs = Vmax where Vmax is voltage where current starts to saturate or gm drops

drastically in IDV G characteristic curve.

In Fig. 5.36, 5.37 and 5.38 C refers to cases.

C1: Region 2&3 doping concentration is 1e16cm−3.

C2: Region 2&3 doping concentration is increased to 3e16cm−3.

C3: Region 4 is formed inside region 3. It lies from x = 8µm to x = 9.9µm and has a

doping concentration of 8e16cm−3.

54

0 20 40 60 80 100 120

0

2

4

6

Vgs= 6VVgs= 0V

I ds (A

/m

)*10

-4

Vds (Volts)

C1 C2 C3 C4

Figure 5.36: Drain characteristics for 4 cases for High PA

0 2 4 6 8 10

0

1

2

3

4

5

6

7

Elec

tric

field

(V/c

m)*

105

At top surface along the device length ( m)

Vgs=0V,Vds=55V C1 C2 C3 C4

L_R1=0.1 m,L_R2=0.5 m

(a) Vds = 55

0 2 4 6 8 10

0

1

2

3

4

5

6

7

8

Elec

tric

field

(V/c

m)*

105

At top surface along the device length ( m)

Vgs=0V,Vds=99V C1 C2 C3 C4

L_R1=0.1 m,L_R2=0.5 m

(b) Vds = 99

Figure 5.37: Electric field for 4 cases for High PA

55

C4: A low doped region is formed inside region 3. It lies from x = 2.725µm to

x = 8µm and y = 0µm to y = 0.15µm. It has a doping concentration of 1e16cm−3.

The above cases are applied on the device sequentially.

When device is operated at Vgs = 0, the channel behaves as a high resistance re-

gion and hence most of the Vds applied first drops across the channel region due to this

electric field becomes very high at the junction formed by P-type doping of the chan-

nel region and N-type doping of the region 2&3. Now if we go on increasing Vds the

junction moves through the drift region (R3) towards drain contact. From Fig. 5.36 C1

curve shows that current starts to increase at Vds = 53.5V but actual snapback occurs

above 100V. Hence it is clear that for snapback to occur intial current should be high.

Fig. 5.37(a) and Fig. 5.37(b) shows Electric field distribution at the top interface of

silicon and oxide.

0 2 4 6 8 10

0

1

2

3

4

Elec

tric

field

(V/c

m)*

105

At top surface along the device length ( m)

Vgs=6V,Vds=25V C1 C2 C3 C4

L_R1=0.1 m,L_R2=0.5 m

Figure 5.38: Electric field distribution for High PA at Vgs = 6

When device is operated at high Vgs the channel region has a lot of carriers due to

its operation in deep inversion region, hence its resistance is very low and due to this,

very less voltage drops across the channel region and most of the voltage drops across

the drift region (R3) and hence electric field is very low near the channel and region 2

interface and high at region 3 and drain region interface as seen in Fig. 5.38 .

56

Let us take example of High PA device with L_R1 = 0.1µm and L_R2 = 0.5µm.

After DD region 3 doping concentration is 1e16cm−3. The IDV D characteristic for

this device is plotted in Fig. 5.36 with red curve (C1). As we know our safe operating

region is from Vds = 0V to Vds = 67.2V so their should be no breakdown in this region

for all Vg i.e from Vg = 0V to Vg = Vmax and here Vmax = 6V . For Vg = 0V break-

down start to happen at 53.5V and for Vg = 6V breakdown start at 20V as shown by

C1 curve in Fig. 5.36, hence for both extreme of Vg our safe operating area is effected

so improvement is required.

So we need to solve the above problem and also try to increase the drain current, so

we will first increase the region 3 doping concentration from 1e16cm−3 to 3e16cm−3.

IDV D characteristics after increasing the doping concentration can be seen in Fig.

5.36 by pink curve C2. It is clear from the figure that drain current increases by more

than double and also breakdown voltage at high Vgs improves as well but breakdown

voltage at low Vgs drops from 53.5V to around 40V which is a huge problem. So current

is increasing because resistance of the drift region decreases on increasing doping. The

breakdown at Vgs = 0V decreases because the electric field due to the junction formed

by channel and region 2 increases as can be seen in Fig. 5.37(a) and Fig. 5.37(b). The

electric field at the channel region increases due to the decrease in junction width.

W ∝√

Na +Nd

NaNd

let Nd be doping of the region 2 and Na be that of channel region (R1) and W be the

junction width. So the junction width formed when region 2 is doped with 1e16cm−3

(Nd1) is

W1 ∝√

Na +Nd1

NaNd1

and now when region 2 doping is increased to 3e16cm−3 (Nd2) it becomes

W2 ∝√

Na +Nd2

NaNd2

W1

W2

=

√NaNd2 +Nd1Nd2

NaNd1 +Nd1Nd2

So, now as NaNd2 > NaNd1 so W2 < W1. Also the breakdown voltage at Vgs = 6V

57

increases because of the reduced electric field at the drain region and this reduction in

electric field is due to increase in electric field near the channel region due to the reason

mentioned above and so if electric field increases at a particular region so it has to de-

crease some where else since total voltage is constant which here is 25V as seen in Fig.

5.38 .

Now we have got increased current and also indirectly reduced ON-state resis-

tance but the problem still remains of low breakdown voltages at both Vgs = 0V and

Vgs = 6V . One possible solution is to increase the region 3 length but that will re-

sult in extra resistance and the improvement in current we got will again go down. A

possible solution which we implemented does not reduce drain current but in fact in-

crease breakdown voltage at high Vgs. The solution implemented is quite similar to Low

doped drain (LDD) method used in mosfets to reduce electric field. Here we create a

new region called as region 4 inside the region 3. It lies from x = 8µm to x = 9.9µm

and y = 0µm to y = 1.0µm and has a doping concentration of 8e16cm−3. Due to

the implementation of region 4 breakdown voltage for high Vgs increases from 35V to

around 70V which is a huge improvement as can be seen in Fig. 5.36 by blue curve

C3. Breakdown voltage at Vgs = 0V is approx not effected because region 4 is formed

at drain end and breakdown at Vgs = 0V occurs due to high field around the channel

region which is shown in Fig. 5.37(a) by the electric field curves at Vds = 55V . The

particular doping of 8e16cm−3 obtained from the analysis is shown in the figure below.

As we see in the above figure breakdown voltage or also can be called snapback

voltage first increases with doping and then it decrease, so their exist a particular doping

concentration for which breakdown voltage is maximum and here it comes out to be

8e16cm−3.

As seen in the Fig. 5.40 with increase in doping concentration of region 4 the peak

electric field increases but upto very little extent i.e to say the difference is very less but

on the other hand as seen in Fig. 5.39 with increase in doping of region 4 the current

keeps on increasing, so even if field profile almost remains same, current becomes the

dominant factor for breakdown and hence once current increases too much breakdown

voltage starts to decrease because breakdown is due to impact ionization which happens

due to high field and high current.

58

0 10 20 30 40 50 60 700

2

4

6

8

I ds (A

/m

)*10

-4

Vds (Volts)

R4 doping (cm-3) 3e16 5e16 7e16 8e16 9e16 1e16 2e17

Figure 5.39: region 4 doping analysis for High PA at Vgs = 6

0 2 4 6 8 10

0

1

2

3

4

5

Elec

tric

Fiel

d (V

/cm

)*10

5

At top surface along device length ( m)

Vgs=6V,Vds=35V

R4 doping in (cm-3) 3e16 5e16 7e16 8e16 9e16 1e17 2e17

L_R1=0.1 m,L_R2=0.5 m

Figure 5.40: Electric field profile for High PA at Vgs = 6

59

Now due to the introduction of region 4 problem of breakdown at high Vgs is solved

but still the problem at low Vgs remains to be solved.

It can be seen in Fig. 5.37 that electric field is highest at the junction formed by

channel and region 2 and this high field was formed due to increase in region 2&3

doping concentration i.e from 1e16cm−3 to 3e16cm−3, so in order to decrease this

high field we have to again decrease the region 2&3 doping concentration but if we

try to do so our drain current will decrease. So it was found that instead of decreasing

the concentration in the whole region 2&3 if we reduce the doping from 3e16cm−3 to

1e16cm−3 only in the region x = 2.725µm to x = 8µm and y = 0µm to y = 0.15µm

the breakdown voltage at Vgs = 0V will lie outside the safe operating area, which is

represented by C4 in the above figures, It has been showed by

So after double diffusion the device in hand belonged to case1 i.e C1. Due to the

application of C2, C3, and C4 our device has much higher current with breakdown volt-

ages lying outside the safe operating area.

For Low PA only C2 was applied and its region 2&3 doping concentration was in-

creased from 1e16cm−3 to 6e16cm−3. C3 and C4 was not used here because breakdown

voltages were small and didn’t required to be increased.

These C2, C3 and C4 process were done repeatedly till best doping concentration

or region lengths were found which satisfied all the required conditions.

Once the above procedures were done we tried to reduce the region 3 length of

both low and high PA while maintaining breakdown voltages above the safe operating

area. After doing this low PA device length was reduced by 0.5µm and for high PA de-

vice one was reduced by 2µm (L_R1 = 0.1µm,L_R2 = 0.5µm) and other by 1.5µm

(L_R1 = 0.1µm,L_R2 = 0.5µm). Reducing the region 3 length will improve drain

current, lower the ON-state resistance, lower the capacitance. After doing all the above

processes the Vth of the devices were shifted a little hence channel doping concentration

60

were adjusted in order to get the same Vth as previously.

After doing all the required adjustments the results of the final device was evaluated

and is present below.

IDV G characteristics

0 2 4 6 8 100

1

2

3

4

5

I ds (A

/m

)*10

-4

Vgs (Volts)

L_R1=0.05 m L_R2= 0.3 m L_R2= 0.4 m L_R2= 0.5 m

Vds=3.7V

(a) Low PA

0 2 4 6 8 10 12 140

1

2

3

I ds (A

/m

)*10

-4

Vgs (Volts)

L_R1= 0.1 m, L_R2= 0.5 m L_R1= 0.2 m, L_R2= 0.4 m

Vds=28V

(b) High PA

Figure 5.41: Improved IDV G

The drain current has increased by huge amount for Low PA and that for high PA it

has improved as well. The Vgs operating region has improved for low PA from 2V to

4V and for high PA from 6V to approximately 7V as can be seen in the above figure.

Breakdown Voltage Vb

0 2 4 6 8 100

1

2

3

4

L_R1=0.05 mL_R2=0.3 m

I ds (A

/m

)*10

-4

Vds (Volts)

Vgs=1 to 4V, step=1V

(a) L_R1 = 0.05, L_R2 = 0.3

0 2 4 6 8 100

1

2

3

4

L_R1=0.05 mL_R2=0.4 m

I ds (A

/m

)*10

-4

Vds (Volts)

Vgs=1 to 4V, step=1V

(b) L_R1 = 0.05, L_R2 = 0.4

Figure 5.42: Drain Characteristics IDV D for Low PA

61

0 2 4 6 8 100

1

2

3

4

L_R1=0.05 mL_R2=0.5 m

I ds (A

/m

)*10

-4

Vds (Volts)

Vgs=1 to 4V, step=1V

(a) L_R1 = 0.05, L_R2 = 0.5

0 2 4 6 8 10 12 14 16 18 20 22 24 260

5

10

Vgs= 4V

L_R1=0.05 m L_R2=0.3 m L_R2=0.4 m L_R2=0.5 m

I ds (A

/m

)*10

-4

Vds (Volts)

Vgs= 0V

(b) Breakdown low and high Vg

Figure 5.43: Drain Characteristics IDV D and Breakdown for Low PA

The low PA is biased at Vds = 3.7V and as seen in Fig. 5.42 and Fig. 5.43(a) it can

be operated from Vds = 2V to Vds = 5.4V but by theoretical calculation we taught of

using it from 0V-7.2V, this reduced swing occurs because of high Ron. As can be seen

from the figures breakdown voltages lies outside this Vd swing range.

0 5 10 15 20 25 30 35 40 45 500.0

0.5

1.0

1.5

2.0

2.5

3.0

I ds (A

/m

)*10

-4

Vds (Volts)

Vgs=2 to 7V, step=1V

(a) L_R1 = 0.1, L_R2 = 0.5

0 5 10 15 20 25 30 35 40 45 500.0

0.5

1.0

1.5

2.0

2.5

I ds (A

/m

)*10

-4

Vds (Volts)

Vgs=2 to 7V, step=1V

(b) L_R1 = 0.2, L_R2 = 0.4

Figure 5.44: Drain Characteristics IDV D for High PA

Fig. 5.44(a) and Fig. 5.44(b) shows that high PA device can be operated from

Vds = 8V to Vds = 48V and it is biased at a dc Vds of 28V. Here as well swing is

reduced from theoretical range of Vds = 0V to Vds = 56V it is due to high Ron values.

In Fig. 5.45 it can be seen that the breakdown voltages are lying outside the safe

operating region for high PA i.e 57.6V (20% more than 48V).

ON-state Resistance Ron

Fig. 5.46 shows drastic improvement in ON-state resistance due to the process ex-

plained earlier. Both low and high PA shows great improvements as compared to device

62

0 20 40 60 80 100 120

0.0

0.5

1.0

1.5

2.0

2.5

3.0

L_R1=0.1 m, L_R2=0.5 m L_R1=0.2 m, L_R2=0.4 m

Vgs= 7V

I ds (A

/m

)*10

-4

Vds (Volts)

Vgs= 0V

Figure 5.45: Breakdown at low and high Vg for High PA

0.3 0.4 0.5

0.7

0.8

0.9

1.0

1.1

1.2

1.3

ON

-Sta

te R

esis

tanc

e R

ON (

-m

)*10

4

L_R2 ( m)

Before After

Vgs=2V L_R1=0.05 m

(a) Low PA

0.4 0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

L_R1=0.2 m

L_R1=0.2 m

L_R1=0.1 m

L_R1=0.1 m

ON

-Sta

te R

esis

tanc

e R

ON (

-m

)*10

4

L_R2 ( m)

Before After

(b) High PA

Figure 5.46: ON resistance Comparison

63

obtained after double diffusion. Here (before) refers to device without applying process

C2, C3, C4 and region 3 length shortening, where as (after) refers to having applied all

the above process. It is found that interface charge between field oxide and drift region

can decrease Ron to a sufficient extended (?) .

Transition Frequency FT

0.30 0.35 0.40 0.45 0.50

18

20

22

24

26

28

30

32

34

Peak

Tra

nsiti

on F

requ

ency

FT m

ax (G

Hz)

L_R2 ( m)

After Before

L_R1=0.05 m Vds= 3.7V

(a) Low PA

0.40 0.42 0.44 0.46 0.48 0.506

7

8

9

10

11

12

13

L_R1= 0.2 m

L_R1= 0.2 m

L_R1= 0.1 m

L_R1= 0.1 m

After Before

Peak

Tra

nsiti

on F

requ

ency

FT m

ax (G

Hz)

L_R2 ( m)

(b) High PA

Figure 5.47: FTmax Comparison

FT as well shows great improvements due to the reduction in capacitance for both

high and low PA.

Maximum Oscillation Frequency Fmax

0.30 0.35 0.40 0.45 0.50

28

30

32

34

36

38

40

42

44

46

48

50

52

Peak

Max

imum

Osc

illat

ion

Freq

uenc

y F m

ax (G

Hz)

L_R2 ( m)

After Before

L_R1=0.05 m Vds= 3.7V

(a) Low PA

0.40 0.42 0.44 0.46 0.48 0.5010

12

14

16

18

20

22

L_R1= 0.2 m

L_R1= 0.2 m

L_R1= 0.1 m

L_R1= 0.1 m

After Before

Peak

Max

imum

Osc

illat

ion

Freq

uenc

y F m

ax (G

Hz)

L_R2 ( m)

(b) High PA

Figure 5.48: Peak Fmax comparison

Similarly huge improvements in Fmax as well was found because FT and Fmax are

co-related.

64

Conclusion

After analyzing the above results it is found that for Low PA device with (L_R1 =

0.05µm,L_R2 = 0.3µm) and for High PA device with (L_R1 = 0.1µm,L_R2 =

0.5µm) will be used for further analysis.

5.6 Buried oxide optimization and Gate Isolation oxide

analysis

After doing the analysis presented in the last report two device configurations were

selected one each for LPA and HPA. For LPA device with configuration (L_R1 =

0.05µm,L_R1 = 0.3µm and for HPA(L_R1 = 0.1µm,L_R1 = 0.5µm)are selected.

5.6.1 Box-Oxide thickness optimization

Self heating plays a very important role is deciding the breakdown voltage of LDMOS.

Box-oxide present in the SOI-LDMOS provides a barrier for the heat to flow from the

device active area at the top to the sink at the bottom surface of cubical structure. If

oxide thickness is too large then lot of heat gets trapped which results in high temper-

ature in the active area due to which thermal runaway of parasitic bjt decreases which

causes to decreases in breakdown voltage as parasitic bjt starts conducting at a lesser

drain voltage. If the oxide thickness is too low then capacitance formed by box-oxide

is very large so less voltage is dropped across it due to which rest of the voltage tries to

drop by forming a depletion region above the oxide and hence some active area is lost

due to this depletion and hence breakdown voltage decreases. So the oxide thickness

has to be optimized in-order to be away from both these effects. Below plots shows the

optimized oxide thickness for which breakdown voltage is maximum.

From figure Fig. 5.49(a) it can be seen that for Tbox = 0.2µm operating area is

maximum and for high Vgs i.e. Fig. 5.49(b) snapback voltage is maximum for Tbox =

0.35µm but Tbox = 0.2µm provides a better linearity i.e drain current is almost constant

and does not show decrease because of self heating as shown by curve with Tbox =

0.35µm, hence Tbox = 0.2µm is a much better choice to use.

65

0 200

5

10

I ds

(A/

m)*

10-4

Vds (Volts)

Tbox ( m) 0.1 0.2 0.35 0.5 1.0

(a) Vgs = 0

0 5 10 150

5

10

I ds (A

/m

)*10

-4

Vds (Volts)

Tbox ( m) 0.1 0.2 0.35 0.5 1.0

(b) Vgs = 4V

Figure 5.49: breakdown or snapback voltage changes due to oxide thickness (LPA)

0 20 40 60 80 100

0

5

10

15

20

I ds (A

/m

)*10

-4

Vds (Volts)

Tbox ( m) 0.1 0.2 0.5 0.7 1.0

(a) Vgs = 0

0 20 40 600

5

10

15

20

I ds (A

/m

)*10

-4

Vds (Volts)

Tbox ( m) 0.1 0.2 0.5 0.7 1.0

(b) Vgs = 7V

Figure 5.50: breakdown or snapback voltage changes due to oxide thickness (HPA)

66

For high Power Amplifier clearly it can be seen that Tbox = 0.2µm provides best

result for both low and high Vgs values.

5.6.2 Isolation oxide changed from LOCOS to STI (HPA)

When the above designed amplifiers were used in large signal mode as class AB ampli-

fier, drain current corresponding to HPA showed non-linearity.

(a) Drain current

0.6 0.9 1.2 1.5-0.50

-0.25

0.00

0.25

0.50

I g (A/

m)*

10-4

Time (ns)

Vgs=2+2.5sin( t)

(b) Gate current

Figure 5.51: large signal characteristics (HPA-LOCOS)

As seen in the figure Fig. 5.51(a) circles shows unwanted peaks instead of which

current should be zero as it is used in class AB. These unwanted peaks are due to

parasitic capacitance arising from gate-drain linkage, hence isolation oxide has to be

improved in order to reduce this linkage. Gate current also shows a lot non-linearity

which gives rise to harmonic contents. If unwanted peak of drain current is not reduced

lot of power will be wasted in its harmonics. Reduced parasitic effects were found if

LOCOS isolation was changed to STI.

Depletion

0.00 2.00 4.00 6.00Distance (Microns)

0.00

2.00

4.00

Distance (Microns)

(a) LOCOS

Depletion

0.00 2.00 4.00 6.00Distance (Microns)

0.00

2.00

4.00

Distance (Microns)

(b) STI

Figure 5.52: Isolation techniques to improve linearity

Fig. 5.52(a) and Fig. 5.52(b) shows LOCOS and STI implemented device struc-

tures. when large signal analysis in class AB mode is done for STI implemented device

67

it shows large improvements as seen in Fig. 5.53 .

0.6 0.9 1.2 1.5

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

I d (A/

m)*

10-4

Time (ns)

Vgs=2+2.5sin( t)

(a) Drain current

0.6 0.9 1.2 1.5-0.50

-0.25

0.00

0.25

0.50

I g (A/

m)*

10-4

Time (ns)

Vgs=2+2.5sin( t)

(b) Gate current

Figure 5.53: large signal characteristics (HPA-STI)

As can be seen non-linearity issue is almost completely removed from drain current

as well as from gate current characteristics at the expense of a bit reduced peak current.

So here STI provides a huge advantage as compared to LOCOS mode of Isolation.

This kind of issue is not seen for LPA hence its design is kept same using LOCOS

technology.

Comparision of Ac and DC characteristics for before(LOCOS) and after(STI) non-

linearity improvement

0 2 4 6 8 100.0

0.5

1.0

1.5

2.0

2.5

3.0

I ds (A

/m

)*10

-4

Vgs (Volts)

Linearity correction before after

(a) IDVG

0 20 40 60 80 1000

2

4

6

8

Vgs=0V

Vgs=7V

I ds (A

/m

)*10

-4

Vds (Volts)

Linearity Correction before after

(b) IDVD

Figure 5.54: DC characteristics comparison before and after STI (HPA)

The IDVG and IDVD characteristics both show decrease in current but safe operat-

ing area is almost the same, hence it is not much of a concern.

So here we see that peak FT and peak Fmax has improved at the expense of little

reduce in drain current and increase in RON . Reduce in current is because adding oxide

68

0.0000 0.0001 0.0002 0.0003 0.0004 0.00050.0

0.3

0.6

0.9

1.2

1.5

Peak

Fre

quen

cy (G

Hz)

A ABBAB

RO

N (

-m

)*10

4

RON

0

4

8

12

16

20

24

28

FT Fmax

Figure 5.55: Comparison of RON , FT and Fmax B-before A-after STI

on the current path has increased its effective resistance and since drain current has

reduced it increases the RON .

Now since our device is ready with good linearity, DC and AC characteristics we look

at its power amplifier implementation in circuit domain.

69

CHAPTER 6

Power Amplifier Circuit Implementation and Analysis

6.1 Introduction

After designing the device to meet device specifications like breakdown voltage, FT and

Fmax as well maximized drain current and minimized Ron as much as possible, we will

characterize the device for circuit simulation. The designed devices are used in class

AB power amplifier circuit for both LPA and HPA.

for LPA in order to be used it in class AB mode biasing points chosen are Vgs =

0.7V and Vgs = 1.3V , two basing points are chosen just to see difference caused in

gain, PAE and linearity on changing dc biasing point. Both biasing points denote class

AB operation.

Similarly for HPA two biasing points chosen are chosen e.g. Vgs = 2.0V and Vgs =

2.5V . Higher biasing points in both cases are chosen as points where ∂3Id∂V 3

gs≈ 0 so that

input non-linearities are reduced.

The operating frequency used here is 2.35GHz (midpoint of 2.3-2.4GHz) and all the

simulations done here are mixed mode analysis in medici. LPA is intended for 28dBm

and HPA for 50dBm RF output power.

6.2 Active Computational Load Pull Test (CLP)

Active Computational Load Pull Test (CLP) provides a complete circuit environment

by using matching networks in the form of voltage sources both at the input and output.

This active CLP is analogous to Load Pull Test done in circuit simulators to get optimum

load conditions for highest PAE or Gain while satisfying maximum allowed swing at

the drain terminal. Here in Active CLP optimum load is forced at the drain by having an

Ac voltage source. The CLP simulation technique is first developed for CAD software

b (Blakey et al., 1996) and (Loechelt and Blakey, 2000), while Linkoping University

has developed this technique further in TCAD (Jonsson et al., 2003).

+− Vdc_drain

Vac_drain

Vac_gate

+− Vdc_gate

D

G

S

LDMOS

Figure 6.1: Active CLP system

The drain terminal is biased at a fixed Dc voltage 3.7V for LPA and 28V for HPA.

The drain Ac source has a maximum voltage swing which is allowed by its safe operat-

ing area i.e. amplitude of 1.7V for LPA and 20V for HPA. The frequency of both the Ac

sources at the gate and drain are kept at 2.35GHz and 180o out of phase. Since the drain

Ac source is operating at 2.35GHz the drain terminal acts like an Ac short for other

frequency voltages, hence no harmonic voltages can be found at the drain terminal but

it may not be completely true if load was an RLC circuit though we try to eliminate

these harmonics by using a tank network while designing matching circuits. Gate is

biased at a fixed Dc voltage depending upon the class of amplifier to be used, here we

will use the amplifier in class AB for both LPA and HPA. The amplitude of the gate

Ac source can be changed from zero upto a voltage where 1dB compression of output

power occurs with respect to input power.

Large signal simulations are then performed in time domain and by extracting gate and

drain currents various parameters are found such as efficiency, output power, gain and

impedences.

The time domain characteristics are used in matlab to convert in to frequency domain

by taking fast fourier transform (FFT). Using these frequency domain values various

parameters are found as follows.

ZL(f) =VL(f)

IL(f)

ZL is the output large signal matching impedance. VL(f) is drain voltage IL(f) is the

71

drain current at frequency f Hz.

P (f) =1

2([V (f)][I(f)]∗)

P (f) is power at frequency f Hz.

PAE =Pout(f)− Pin(f)

Pdc

PAE is power added efficiency and Pdc is dc power.

Gain =Pout(f)

Pin(f)

Gain represents power gain.

Active CLP extracts large signal parameters efficiently in a short time. The most

important advantage of Active CLP is that it can be used for new devices to test its

capability as a power amplifier at the TCAD level without doing actual fabrication or

circuit modeling, which opens opportunity for large number of devices, materials and

configurations to be tested for improved power amplifier performance at TCAD level

itself.

Optimum impedance for getting highest PAE or gain can be found out by changing

the amplitude of drain Ac source and/or by changing its phase with respect to gate Ac

source instead of having fixed 180o out of phase as shown by (Kashif et al., 2008).

-11 -10 -9 -8 -715

20

25

30

35

Vgs=1.3V (dc)Vgs=0.7V (dc)

PAE Gain

Pout [dBm]

PAE

[%]

16

18

20

22

24

26

Gain [dB]

(a) LPA

-4 -3 -2 -1 0 1 2 3

5

10

15

20

25

30

35

40

45

50

55

Vgs=2.5V (dc)

Vgs=2.0V (dc)

PAE Gain

Pout [dBm]

PAE

[%]

20

25

30

35

40

45

50

Gain [dB]

(b) HPA

Figure 6.2: PAE and Gain at Matched Condition using Active CLP

Device’s are gate biased at particular voltage as shown in Fig. 6.2 and Ac gate volt-

age amplitude is increased from low to high value. The drain is dc biased at 3.7V and

28V for LPA and HPA respectively. The drain Ac source phase is maintained at 180o

72

out of phase with gate Ac source where as its amplitude is fixed at 1.7V and 20V for

LPA and HPA respectively. The device width is 1µm .

Here one things has to be kept in mind that for every gate amplitude the device is run-

ning in matched conditions i.e drain amplitude and phase is fixed and hence matched

load obtained for each gate amplitude would be different and would be the most opti-

mum one for that particular gate amplitude.

6.3 Changing from fixed drain Ac source to RLC net-

work

Now device width has to be increased so as to match the output power requirement

which is 28dBm for LPA and 50dBm for HPA also at the same time maximum Ac gate

voltage has to be found for each dc basing at which 1dB compression occurs and width

should be such that output power requirement is satisfied at this 1dB compression point.

So this becomes a very mechanical process in TCAD simulator where as in circuit sim-

ulator this can be optimized readily but we are in the device design phase and do not

have verilog code for the designed structure so circuit simulation cannot be done hence

TCAD itself has to be used. The approach followed to obtain 1dB compression and

device width is as follows.

1. We will first fix the dc operating conditions i.e for LPA [Vgs = 0.7V and 1.3V ,

Vds = 3.7V ], for HPA[Vgs = 2.0V and 2.5V , Vds = 28.0V ] here two Vgs values are

used both of them are for class AB but lower Vgs will give higher PAE where as higher

Vgs will give higher linearity which can be used later for further studies.

2. The Ac drain amplitude is fixed at a particular values such that Vds(dc) + Vds(ac)

should lie in the safe operating area, here Ac amplitude is 1.7V for LPA and 20V for

HPA. Phase is 180o out of phase with gate Ac source.

3. Assume any higher Ac gate amplitude such that Vgs(dc) + Vgs(ac) should lie in the

safe operating area.

4. Now perform large signal simulation under Active CLP condition and keep on in-

creasing the width till output power conditions are met at that Ac gate amplitude used.

5. Once width is found extract load impedance and make a matching circuit as shown

in the figure 3.3.

73

6. Perform large signal simulations with width fixed to value found in the previous step

and changing the gate Ac amplitude for low to highest value possible without crossing

the safe operating area and plot RF Pout variation with RF Pin in dBm and see the Ac

gate amplitude value where 1dB compression point is occuring.

7. Now fix the Ac gate amplitude to a value obtained in the previous step and increase

width till output power requirement is satisfied in Active CLP system and after get-

ting required power again extract load impedance and then use RLC matched circuit

and plot RF Pout variation with RF Pin to see whether power condition is meeting at

1dB compression point. Iterate this step till 1dB compression point and required output

power is matched.

+−

+−

Matching

Network

Vdc_drain

Vac_gate

Vdc_gate

L1

C1

C2

L2

R=50ΩLDMOS

D

G

S

Figure 6.3: Power Amplifier setup

In the Fig. 6.3 C1 and L1 forms a tank circuit tuned at 2.35GHz so that it acts as

open circuit for voltages at 2.35GHz and short circuit for other voltages, this feature in

Active CLP is provided by the drain Ac source. Large C2 is used to provide dc isolation

to the load. Load impedance found from Active CLP contains both real and imaginary

parts, L2 models the imaginary part where as the matching network models the real

part.

Fig. 6.4 clearly shows that output power requirement of 28dBm is met at 1dB com-

pression point. Two bias points are used for LPA because it will be useful later for the

study of intermodulation. Gate bias point closer to Vth has more non-linearity as com-

pared to one away from it.

Similarly for HPA Fig. 6.5 shows the output power requirement of 50dBm is met at

1dB compression point.

74

-6 -4 -2 0 2 4 6 8 1018

19

20

21

22

23

24

25

26

27

28

29

30

P ou

t [dB

m]

Pin [dBm]

Vgs= 0.7+1.25sin( t)

(a) Vgs = 0.7

-6 -4 -2 0 2 4 6 8 1018

19

20

21

22

23

24

25

26

27

28

29

30

31

P out [

dBm

]

Pin [dBm]

Vgs= 1.3+1.05sin( t)

(b) Vgs = 1.3

Figure 6.4: Pout variation with Pin for LPA(Legend corresponds to 1dB compressionpoint)

10 12 14 16 18 20 22 24 26 28 30 3238

39

40

41

42

43

44

45

46

47

48

49

50

51

52

P out [

dBm

]

Pin [dBm]

Vgs= 2.0+2.5sin( t)

(a) Vgs = 2.0

10 12 14 16 18 20 22 24 26 28

37383940414243444546474849505152

P out [

dBm

]

Pin [dBm]

Vgs= 2.5+2.25sin( t)

(b) Vgs = 2.5

Figure 6.5: Pout variation with Pin for HPA (Legend corresponds to 1dB compressionpoint)

75

The both cases of LPA and HPA the higher biasing point corresponds to voltage at

which non-linearity due to input is minimum i.e. voltage at which third differential of

Ids with Vgs becomes close to zero so IMD would be less.

18 19 20 21 22 23 24 25 26 27 28 290

5

10

15

20

25

30

35

Vgs=1.3V (dc)

Vgs=0.7V (dc) PAE Gain

Pout [dBm]

PAE

[%]

20

21

22

23

24

25

Gain [dB]

(a) LPA

36 38 40 42 44 46 48 50 520

5

10

15

20

25

30

35

40

45

PAE Gain

Pout [dBm]

PAE

[%]

21

22

23

24

25

26

27

28

Vgs=2.5V (dc)

Vgs=2V (dc)

Gain [dB]

(b) HPA

Figure 6.6: PAE and Gain variation with RF Output Power

Fig. 6.6 shows PAE and Gain variation with Output RF Power. Points on or just

right to the black vertical line are 1dB compression points. They satisfy the power re-

quirements and have high gain, PAE needs to be improved a little more.

The plots below shows large signal waveforms at 1dB compression point.

5 6 7 8 9 10 11 12-2

-1

0

1

2

3

4

5

G

G

DD

Voltage Current

Time (sec)*10-10

Volta

ge [V

]

0.0

0.5

1.0

1.5

Current [A]

(a) LPA

5 6 7 8 9 10 11 12

0

10

20

30

40

50

G

G

D

Voltage Current

Time (sec)*10-10

Volta

ge [V

]

-5

0

5

10

15

20

25D

Current [A]

(b) HPA

Figure 6.7: Large Signal Characteristics with Active CLP at 1dB compression point

In Fig. 6.7 large signal simulations are done using Active CLP technique. LPA

waveforms are quite well behaved but for HPA drain current waveform goes below

zero, which should not happen and it occurs because of parasitic effects.

Now as seen in Fig. 6.8 waveforms are plotted at 1dB compression point by using

actual rlc network instead of using Active CLP system, so this represents more real

nature of implementation. Here we can see a little non-linearitity has been introduced

76

1.32 1.33 1.34 1.35 1.36 1.37 1.38 1.39 1.40-1

0

1

2

3

4

5

G

G

DD

Voltage Current

Time (sec)*10-8

Volta

ge [V

]

0.0

0.5

1.0

1.5

Current [A]

(a) Vgs = 0.7

1.32 1.33 1.34 1.35 1.36 1.37 1.38 1.39 1.40-1

0

1

2

3

4

5

G

G

D D

Voltage Current

Time (sec)*10-8

Volta

ge [V

]

0.0

0.5

1.0

1.5

Current [A]

(b) Vgs = 1.3

Figure 6.8: Large Signal Characteristics with RLC network at 1dB compression point(LPA)

because we are no more using ideal drain Ac source.

3.03 3.04 3.05 3.06 3.07 3.08 3.09 3.10

0

5

10

15

20

25

30

35

40

45

50

GG

D

D Voltage Current

Time (sec)*10-8

Volta

ge [V

]

-10

-5

0

5

10

15

20

25

30

Current [A]

(a) Vgs = 2.0V

1.32 1.33 1.34 1.35 1.36 1.37 1.38 1.39 1.40

0

5

10

15

20

25

30

35

40

45

50

G

G

D

D Voltage Current

Time (sec)*10-8

Volta

ge [V

]

-10

-5

0

5

10

15

20

25

30

Current [A]

(b) Vgs = 2.5V

Figure 6.9: Large Signal Characteristics with RLC network at 1dB compression point(HPA)

Fig. 6.9 shows waveforms for HPA. As compared to Active CLP non-linearity has

increased but a good point is drain current peaking below zero has reduced by using rlc

network as compared to when Active CLP system was used.

Table 6.1: Summary of PAE and Gian at 1dB compression point.

at 1dB compression PAE(%) Gain[dB]Vgs = 0.7V (LPA) 30.76 21.49Vgs = 1.3V (LPA) 22.48 22.69Vgs = 2.0V (HPA) 42.12 24.75Vgs = 2.5V (HPA) 37.8 25.75

77

6.4 Two-tone Intermodulation Analysis

Two-tone linearity analysis as described in chapter 3 is evaluated here for the power

amplifier designed above all the simulations are done in TCAD. Non-linearity has been

analyzed in TCAD by (Kashif et al., 2010) as well .

Test is done on the power amplifier setup shown in Fig. 6.3 by having an addi-

tional RF Ac power source in series with the first at the gate input. Source1 (First

tone) has a voltage signal A(sin(2πf1t)) and Source2 (second tone) has a voltage sig-

nal A(sin(2πf2t)), where f1=2.35GHz and f2=2.4GHz . So total RF voltage at the gate

is A[(sin(2πf1t) + sin(2πf2t)]. Here amplitude A is increased from low value to high

and output and input power are measured. Pin refers to input power at f1, Pout refers

to RF output power at f1, Pout(3rd harmonic) refers to power at 2f1 − f2 or 2f2 − f1.

So the 3rd harmonic lies at frequency 2.3GHz and 2.45GHz, here we have considered

2.3GHz because it lies adjacent to our band (2.3-2.4GHz). Here the difference between

f1 and f2 is 50MHz, high difference value is selected only because of computational

purpose as it takes huge amount of time in TCAD simulator as the value of difference

is decreased, but still 50MHz is a reasonable value to understand 3rd harmonic Inter-

modulation (IM3).

-20 -15 -10 -5 0 5 10-50

-40

-30

-20

-10

0

10

20

30

40

50

P1dB(-5, 21)

IM3(5, 31.5)

Out

put P

ower

[dBm

]

Pin [dBm]

Pout

Pout (3rd harmonic)

(a) Vgs,dc = 0.7V

-20 -15 -10 -5 0 5 10 15

-50

-40

-30

-20

-10

0

10

20

30

40

50

P1dB(-2.47, 23)

IM3(9.56, 35.84)

Out

put P

ower

[dBm

]

Pin [dBm]

Pout

Pout (3rd harmonic)

(b) Vgs,dc = 1.3V

Figure 6.10: 3rd harmonic Inter-modulation Analysis for LPA

In Fig. 6.11(b) 3rd harmonic power shows a dip which is a favorable for our design.

This dip may be because of 2 reasons, first it may be because of graded channel as

mentioned by (Chen et al., 2009) or due to presence of bias dependent sweet-spots as

shown by (van der Heijden et al., 2002) and (Fager et al., 2002) .

ACPR is the ratio between the total power adjacent channel (intermodulation signal)

78

0 5 10 15 20 25 30-20

-10

0

10

20

30

40

50

60

70

P1dB(14.96, 43.8)

IM3(20.23, 49.23)

Out

put P

ower

[dBm

]

Pin [dBm]

Pout

Pout (3rd harmonic)

(a) Vgs,dc = 2.0V

0 5 10 15 20 25 30-30

-20

-10

0

10

20

30

40

50

60

P1dB(16.1, 44.64)

IM3(25.42, 54.83)

Out

put P

ower

[dBm

]

Pin [dBm]

Pout

Pout (3rd harmonic)

(b) Vgs,dc = 2.5V

Figure 6.11: 3rd harmonic Inter-modulation Analysis for HPA

to the main channel’s power (useful signal). Here Pout(3rd harmonic at 2.3GHz) is the

adjacent channel power and Pout (at 2.35GHz) is the useful signal. For LTE standard

ACPR should be below -33dBc.

Table 6.2: ACPR at 1dB compression point.

at 1dB compression ACPR (dBc)Vgs = 0.7V (LPA) -25Vgs = 1.3V (LPA) -30Vgs = 2.0V (HPA) -23.8Vgs = 2.5V (HPA) -33.57

6.5 Performance over the band 2.3-2.4GHz

The design is intended to provide a reasonable PAE and Gain over the whole LTE band

of 2.3-2.4GHZ . The above device and power amplifier were designed at 2.35GHz . Let

us analyze this 2.35GHz power amplifier over the whole band .

As seen in Fig. 6.12 PAE and Gain remains almost constant over the whole band,

hence the designed PA is suitable for LTE applications.

79

2.30 2.32 2.34 2.36 2.38 2.4022

23

24

25

26

27

28

29

30

31

32

RED -> (Vgs,dc= 0.7V)BLUE -> (Vgs,dc= 1.3V)

Frequency [GHz]

PAE

[%]

20.0

20.5

21.0

21.5

22.0

22.5

23.0

23.5

24.0

Gain [dB]

(a) LPA

2.30 2.32 2.34 2.36 2.38 2.40

24

28

32

36

40

44

RED -> (Vgs,dc= 2.0V)BLUE -> (Vgs,dc= 2.5V)

Frequency [GHz]

PAE

[%]

23.0

23.5

24.0

24.5

25.0

25.5

26.0

26.5

27.0

Gain [dB]

(b) HPA

Figure 6.12: PAE and Gain analysis over the entire LTE band

80

CHAPTER 7

Conclusion and Scope of future work

7.1 Findings of the thesis

In this work we clearly see that LPA does not match up with industry used handset

PAs. This is reason today handsets does not have LDMOS PAs, other material and

technology provide much better solution than LDMOS.

Whereas in case of HPA, LDMOS has been the the main driver for high volume

base station applications. As compared to industry PAs our designed PA has very close

match and shows its potential to be used in base stations for long time. Till now LDMOS

have been operated in class AB mode but now Doherty amplifiers are being used to

obtain high efficiency at the cost of linearity and gain reduction (Theeuwen and Qureshi,

2012).

Introduction of region 4, STI, multi-level doped drift region, box oxide thickness

optimization and graded channel clearly has positive impact on the design of power

LDMOS transistor.

Computational load pull (CLP) has shown path for designing both device and circuit

in TCAD and analyze material or technology potential before fabrication and compact

modeling is mature.

Table 7.1: Circuit Level Parameter comparision with Industry reference PA.

at 1dB compression PAE (%) Gain (dB) ACPR (dBc)Vgs = 0.7V (LPA) 30.76 21.49 -25Vgs = 1.3V (LPA) 22.48 22.69 -30

SKYWORKS (LPA) ≈ 36 27-30 ≤ −33Vgs = 2.0V (HPA) 42.12 24.75 -23.8Vgs = 2.5V (HPA) 37.8 25.75 -33.57

Infineon (HPA) 46-52 15.5-16.5 ≤ −33

Specification for LPA is taken from (SKYWORKS) as reference and for HPA is

taken from (Infineon).

Table 7.2: Final device parameters of the designed transistor.

LPA HPABreakdown Voltage (Vb) [V] 21 66

ON-State Resistance (Ron) [Ω− µm] 13250 15386FT [GHz] 33.53 (Vgs = 0.7V ) 14.2 (Vgs = 2.0V )

30.6 (Vgs = 1.3V 11.45 (Vgs = 2.5V )Fmax [GHz] 30.22 (Vgs = 0.7V ) 10 (Vgs = 2.0V )

26.94 (Vgs = 1.3V 9.13 (Vgs = 2.5V )

Table 7.3: State-of-art Class AB HPA based on LDMOS devices.

Freq Pout G PAE/ηd Ref(GHZ) (dBm) (dB) (%) Year

2.69 36 12.6 39/44 (Li et al., 2010)2.14 53.58 18.58 54.38/ (Zhou et al., 2011)

As compared to state-of-art industry and publish papers our designed class AB high

power amplifier meets all specifications and has significantly high gain as compared to

others though PAE is a bit low but comparable to the state of art PAs. Our designed

HPA shows great potential for being used in doherty amplifier mode as it has very high

gain.

Finally our designed HPA for LTE (2.3-2.4GHZ) at 100W output power shows po-

tential to be used in base stations and other applications where high power is required.

7.2 Future work

• LPA transistor can be designed without using drift region i.e. region 3.

• Ron of HPA transistor needs to be further reduced by using different structuralchanges mention in literature.

• Gate biasing point analysis can be done because PAE, gain and IMD all dependson dc biasing points.

• Analysis of changing phase and magnitude of drain ac source in CLP can be doneto get different loads values for maximum PAE and maximum gain possible.

• Dhorety amplifier can be built in TCAD and analyzed though the computationtime increases with increasing number of transistors.

82

APPENDIX A

A SAMPLE APPENDIX

Just put in text as you would into any chapter with sections and whatnot. Thats the end

of it.

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