current status and outlook for euv mask international workshop on euv lithography (june 18, 2015...
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2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
Current Status and outlook for EUV mask
Takashi Kamo Toshiba Corporation Semiconductor & Storage Products Company
2 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
Outline
[1] Introduction
[3] EUVL Extension (1) Challenges for EUVL Caused by 3D Mask Effect (2) Etched ML Mask
[2] Defect Management (1) EUV Blank/Mask Infrastructure (2) Defect Management for HVM
[4] Summary
3 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
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2012 2014 2016 2018 2020 2022 2024
Hal
f p
itch
[n
m]
Year of production
DRAM metalMPU metalFlash gate
Scaling Road Map
Ref: ITRS 2013 Edition
ArF-i multiple patterning
EUVL
4 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
E-chuck
Current EUV Mask Structure and Challenges
Back-side
Coating
Low Thermal
Expansion
Material (LTEM)
Multilayer
Capping Layer
Pellicle ?
Absorber Stack
Absorber Defect
“clear” “opaque”
Multilayer Defect
(Phase Defect)
Particle
Defect
Defect
Mask yield & defect inspection/review infrastructure is key challenges for HVM insertion.
5 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
Outline
[1] Introduction
[3] EUVL Extension (1) Challenges for EUVL Caused by 3D Mask Effect (2) Etched ML Mask
[2] Defect Management (1) EUV Blank/Mask Infrastructure (2) Defect Management for HVM
[4] Summary
6 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
Blank/Mask Defect Inspection Infrastructure
illuminated
Actinic BI (EIDEC/Lasertec)
EB PI (EIDEC/EBARA)
Blank Inspection (BI) Pattern Inspection (PI)
MAGICS (Lasertec) NPI-7000 (Nuflare)
PEM (Projection Electron Microscope) technique
KLA 7xx(KLA-T)
Teron6xx(KLA-T)
Actinic Pattern/Blank Inspection
hp16nm
HVM
and b
eyond
193nm wavelength
199nm wavelength
Com
merc
ially
ava
ilable
266nm/ 355nm/ 532nm wavelength
H. Watanabe, EUVL symposium 2013
R. Hirano, EUVL symposium 2013
T. Yamamoto, EUVL symposium 2013
ABI meets requirements of hp16nm HVM
http://www.nuflare.co.jp/
http://www.kla-tencor.com/
http://www.lasertec.co.jp/
7 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
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0 1 2 3 4 5 6 7 8 9 10 11 12 M
ask
Yie
ld (
Y)
[%]
Mean Defect Counts (λ) [pcs/plate]
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Mask
Yie
ld (
Y)
[%]
Mean Defect Counts (λ) [pcs/plate]
Dependency on pattern variation (Zero Defect Yield)
Dependency on acceptable defect counts (Bright Field)
Estimation from Poisson Distribution
Mask Defect Yield vs Defect Counts
Mean defect counts Estimated yield of mask defect (Bright Field)
0.5 60%, 99.99% (if 4 defects are accepted)
0.001 99.9%
0.0001 99.99% HVM
Pilo
t
8 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
Blank Defect Roadmap and Blank Supply Chain
Supply chain management with blank supplier is necessary.
ML Blank Defect Roadmap by Blank Supplier
Blank Supply Chain
Mask Shop
mask
mask fabricationblank selection
Defect
map
Blank Suppliers
blank
Device Maker
chip layout, defect acceptable area/ count
blank fabrication
Redundancy Acceptable Area
Redundancy NOT Acceptable Area
by courtesy of HOYA
9 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
Blank Defect Mitigation by Pattern Shift
40nm Defect
24nm Defect
hp64nm L/S (4x)
+/- 12nm +/- 20nm
Position Accuracy Requirement of Blank Defect
Target: 20nm(3σ)
Pattern shift
covering blank defect with absorber
Absorber
Blank defect
ML Impact on wafer printability will be reduced by
Method of Blank Defect Mitigation
Position Accuracy in Blank Defect Mitigation with Pattern Shift
Origin of position error: Position accuracy(BI, EB writer), Alignment error including FM reading
Blank Defect Map with FM Blank Defect Position error
Current blank defect position error of DUV BI is >100nm. Blank defect position error is to be reduced to within 20nm (3σ) with ABI tool.
DUV blank inspection
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-144-112 -80 -48 -16 16 48 80 112 144
Fre
qu
en
cy
Position Error [nm]
Position accuracy: > 100nm(3σ)
10 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
EUV Mask Defect QA Flow and Challenges
Mask Shop Wafer Fab
PI PI WI Dual Pod
If NG, mask cleaning
Exposure
RiskRisk
EUV mask flow without pellicle
Dual Pod
Front: <0.01 pcs/pass(@>60nm) Back: <0.01 pcs/pass(@>4um)
Front: <0.5 pcs/pass(@>60nm) Back: <0.5 pcs/pass(@>4um)
Dual Pod
EUV mask handling with dual pod shows encouraging results for the devices in which redundancy is applicable.
Mask
Dual Pod RSP200
plate automatic
transfer
(N=50)
Wafer Fab. Mask Shop
Round trip
shipment
Particle Adder Check
Risk
11 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
EUV Mask Defect QA Flow and Challenges
Mask Shop Wafer Fab
Pellicle
mount
Dual Pod WI Dual Pod Exposure
API Pellicle
mountable
PI
EUV mask flow with pellicle Cost
Cost
Interchangeable pellicle concept is proposed by ASML to meet multiple inspection schemes (DUV, EB, API).
Severe particle management is still necessary for EUV mask with pellicle because EUV pellicle proposed by ASML has a gap between mask pattern surface and pellicle frame.
New EUV pellicle system attachable only in exposure tool is preferable from the mask fabrication viewpoint.
ASML(SPIE2015, PMJ2015)
APIIf NG, mask cleaning
12 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
EB Inspection for Particle Monitor
PSL dispended blank
PEM (Projection Electron Microscope) can detect 20nm PSL with high throughput (1H@100mmx100mm□).
Model EBEYE M (EBARA)
EBeyeM is to be used for particle inspection in EUV mask handling.
20nm PSL 25nm PSL
30nm PSL 40nm PSL 40nm PSL
100nm PSL 100nm PSL
Patterned EUV mask
25nm size
SEM Review
13 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
EUV Mask Infrastructure Readiness
hp2xnm hp1xnm
Multilayer Blank Inspection
DUV Actinic
Pattern Inspection
DUV EB Actinic
Particle Inspection
DUV/EB EB
Defect Repair EB Repair EB Repair
Mask Defect QA SEM + Litho. Simulation
SEM + Litho.
Simulation AIMS-EUV
ready
under developing
14 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
Outline
[1] Introduction
[3] EUVL Extension (1) Challenges for EUVL Caused by 3D Mask Effect (2) Etched ML Mask
[2] Defect Management (1) EUV Blank/Mask Infrastructure (2) Defect Management for HVM
[4] Summary
15 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
Challenges for 0.33NA EUVL Caused by 3D Mask Topology
ASML(BACUS2014)
As target pattern shrinks, the hurdles induced by mask 3D topology go higher in 0.33NA EUVL system.
16 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
Challenges for High-NA EUVL and Solution Resolution
6inch mask Full-field
X Mag. = 9/12inch Mask
- Low exposure throughput - Stitching technology
- Infrastructure for large mask
FF(26x33)
(6 or 8) HF
(16.5x26) QF
(13x16.5)
or X Mag. = 6inch Mask (5 or 8)
High-NA EUVL trade off
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V-line H-lineN
ILS
EU
V
Bett
er
Wors
e
mask 3D effect
NA=0.5, CRA=8deg
EUV mask
CRA
EUV light
EUV mask
- High-NA by increasing CRA (>7deg) leads to large mask 3D effect
hp10nm
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V-line H-line
NIL
S
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V-line H-lineN
ILS
Ta based absorber
Etched Multilayer
lower mask 3D effect
EU
V
Bett
er
Wors
e
mask 3D effect B
ett
er
Wors
e
EU
V
NA=0.5, CRA=8deg
hp10nm
Etched multilayer mask can solve high-NA EUVL trade off (full-field, 6inch mask, high wafer resolution).
17 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
NXE3300 Exposure Result (Etched ML Mask vs Conv. Mask)
H-V CD bias imec/ASML/Zeiss (PMJ2015)
Best focus shift
Lower mask 3D effects of etched ML mask has been demonstrated in 0.33NA exposure system.
18 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
Challenges for Etched Multilayer Mask
ML
Substrate
Illustration and X-SEM image of etched ML mask pattern of hp 40nm (corresponds to hp10nm on wafer)
- Mask CD/ profile control - ML pattern collapse durability against mask cleaning - Defect inspection - Repair of ML pattern intrusion defect - ..........
Substrate
40nm
Ru-capped 40 pair ML (280nm)
As etched
19 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
Cleaning Durability of Etched ML Pattern
・・・OK
・・・NOT OK
160 120 100 80 72 64 56 48 44 40
Iso. Trench
Dense Trench
Iso. Line
Designed Width [nm]
40nm
80nm 72nm
Isolated/dense 40nm trench pattern is obtained, however, isolated 72nm line is collapsed due to low cleaning durability.
Collapsed !
40nm
100nm 64nm
Collapsed ! OK OK
OK
OK
Target @2018 0.33NA Target @2015 Durable Feature Size after Cleaning
Top down SEM images after mask cleaning
20 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
Root Cause of Pattern Collapse and Solution
Solution:
- Reducing 40 ML pairs to 20 ML pairs which correspond to the same aspect ratio of durable mask topology
80nm
40 ML pairs 280nm
Aspect Ratio = 3.5
40nm
20 ML pairs 140nm
Aspect Ratio = 3.5
Durable Min.
Feature Size after
Cleaning
Root Cause of ML Pattern Collapse:
- Large bending force caused by high aspect ratio of ML pattern during mask cleaning
40nm
40 ML pairs 280nm
Aspect Ratio = 7
= Same Aspect Ratio
21 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
Cleaning Durability of Etched 20ML Pattern
160 120 100 80 72 64 56 48 44 40
Iso. Trench
Dense Trench
Iso. Line
Designed Width [nm]
・・・OK
・・・NOT OK
40nm
64nm 56nm
OK
40nm
72nm 48nm
Collapsed ! OK OK
OK
OK
Durable minimum size is improved to 56nm at isolated line. 0.33NA CD target @2015 is achieved by simply reducing ML pairs.
Durable Feature Size after Cleaning Target @2018 0.33NA Target @2015
improved
Top down SEM images after mask cleaning
22 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
-60000 -40000 -20000 0 20000 40000 60000
-60000
-40000
-20000
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20000
40000
60000
-5.0
-4.0
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CD Uniformity of Dense Trench
hp50nm
Current etched ML mask CD performance catches up EUV mask requirement @2015.
3sigma = 2.4nm
Target @2015(0.33NA) Current Capability
CD Uniformity ≤ 2.4 nm 2.4 nm (120mm□)
CD Linearity ≤ 3.6 nm(CD 62nm up) 2.3 nm
80nm 100nm 48nm
CD Uniformity and Linearity of Etched 20ML Mask
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CD
MT
T [n
m]
Designed Width [nm]
CD range = 2.3nm (62nm up) 4.9nm (40nm up)
CD Linearity of Dense Trench
3.6nm @CD62nm↑
80nm 100nm 48nm
23 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
Current Status and Outlook
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Ma
sk
min
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ea
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siz
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]
Year of Production
Mask minimum feature sizeCD uniformityLinearity
CD
un
ifo
rmit
y,
Lin
ea
rity
[n
m]
0.33NA High-NA *
EUV mask requirement (Edited from ITRS 2013*)
Current status
Target @2015 for 0.33NA
Continuous improvement is required in order to apply etched ML mask to EUVL production.
*) Requirement of etched ML mask for high-NA is extrapolated value of 0.33NA.
Current etched ML mask CD performance catches up EUV mask requirement of 0.33NA @2015.
Target @2018
24 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
Outline
[1] Introduction
[3] EUVL Extension (1) Challenges for EUVL Caused by 3D Mask Effect (2) Etched ML Mask
[2] Defect Management (1) EUV Blank/Mask Infrastructure (2) Defect Management for HVM
[4] Summary
25 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)
Summary
EUVL Extension
Defect Management
Etched ML mask is effective in EUVL extension and is ready for 0.33NA exposure.
Next Step is to clear the hurdle of defect (inspection and repair).
Supply chain management with blank supplier is necessary.
Mask handing with dual pod shows encouraging results for the particle requirements of the devices in which redundancy is applicable.
Severe particle management is still necessary for EUV mask with pellicle because EUV pellicle proposed by ASML has a gap between mask pattern surface and pellicle frame. New EUV pellicle system attachable only in exposure tool is preferable from the mask fabrication viewpoint.
EBEYE M (EB inspection tool) is to be used for particle inspection (~20nm size) in EUV mask handling.
26 2015 International Workshop on EUV Lithography (June 18, 2015 @Maui, Hawaii)