CptS 260 Intro to Computer ArchitectureWeek 10.2 – 10.3Wed 2013/03/20

Fri 2013/03/22

MIPS CPU:

Simple Datapath

MIPS CPU: Simple Datapath

• 1 cycle perinstruction

Topics

• [P&H11] Chapter 4.1 – 4.4

• HW5 Quicksort (addendum): brutepart.asm• HW6 Simple Datapath

• Instruction Memory (vs Data Memory)

• Control Lines vs Data Lines• ALU Control

Reading

Class Web(this weekend)

Today

Instruction Types

• R-type arithmetic-logical add, sub, srl, sll“3-register” and, or, xor

• I-type arithmetic-logical addi, ori, …“immediate” branch beq, bne, …

load / store lw/lh/lb, sw/sh/sb• J-type jump j, jal, jalr

bits

type 6 5 5 5 5 6

R-type op rs rt rd shamt funct

I-type op rs rt 16-bit immediate

J-type op 26-bit address

6 5 5 5 5 6

R op rs rt rd shamt funct

I op rs rt 16-bit immediate

J op 26-bit address

Simple Datapath : Instruction Memory

6 5 5 5 5 6

R op rs rt rd shamt funct

I op rs rt 16-bit immediate

J op 26-bit address

• All instructions 32-bit = 4 bytes

• Default action: $pc += 4 (bytes)

• Instruction mem . “separate from” data memory

R-type: 3 registers

6 5 5 5 5 6

R op rs rt rd shamt funct

I op rs rt 16-bit immediate

J op 26-bit address

• 2 ALU operands• 1 dest. register

1000

001

rsrt

rd

funct

• funct field determines ALU operation

I-type: Load/Store

• lw $rt, imm($rs)• sw $rt, imm($rs)

00

1/01/0

0/11

1/0

rsrt

large dots are electrical junctions

(choice points)

16-bit offset(2nd ALU operand)

6 5 5 5 5 6

R op rs rt rd shamt funct

I op rs rt 16-bit immediate

J op 26-bit address

no dot meansdisconnected

lw

sw

I-type: Branch

• beq rs, rt, LABEL0100

000

rsrt

16-bit LABEL

6 5 5 5 5 6

R op rs rt rd shamt funct

I op rs rt 16-bit immediate

J op 26-bit address

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