Considerations for operation of CMOS integrated circuits outside their

cataloged temperature

Mohammad M. Mojarradi, Elizabeth Kolawa, Benjamin Blalock2,

Jet Propulsion Laboratory, California Institute of Technology, 4800 Oak Grove Drive, Pasadena, CA 91109

2 Department of Electrical and Computer Engineering, University of Tennessee, TN 37966

- 2

Titan in situ

Large Satellites:

Europa Lander

Primitive Bodies:Comet/Asteroid Sample

Return

Neptune and Triton Jupiter Deep Probes

Inner Planets:Venus surface sample

return

Gas Giants

Solar System Exploration Missions

- 3

0 250- 250 500Temperature ( C)

Pressure ( bars)

1000

100

10

1.0

0.1

0.01

Jupiter Probes

Venus Surface Exploration

CNSR

Europa Surface and Subsurface

Titan In-Situ

0 250- 250Temperature ( C)

Radiation( MRad)

10

1.0

0.1 Jupiter Probes

Europa Surface and Subsurface

Titan In-Situ

Earth

Earth

Venus Surface Exploration

CNSR

Pressure vs. Temperature Radiation vs. Temperature

500

Temperature, Pressure, and Radiation

- 4

Low Temperature Cycling300Krad20-1206. Mars Surface Expl.

6 Mrad

6 Mrad

Radiation

100

1.5

90

100

High Pressure(bar)

2-10% Methane CloudsSolid/liquid surface

-1805. (Titan In-Situ)

Sulfuric acid clouds at 50 km97% CO2 at the surface

4603. Venus In-Situ Expl.

Other Environmental Conditions

High Temp( C )

Low Temp( C )

Mission

350-1807. JIMO (with probes)

Dust- 1404. Comet Sample Return

380-1402. Jupiter Multi-Probes

-1701. Aitken Basin Sample Return

Extreme Environment Conditions Solar System Missions

Challenge: All Solar System Exploration in-situ missions have to survive in extreme temperature, pressure, and radiation environments.

- 5

300

400

500

200

25

100

Temperature (C)

Technological Limits for Components

Hard solders melt at ~ 400 C

Soft solders melt at about ~180 CConnector problems start at ~150 C

TFE Teflon degenerates at 370 CSilicon electronics can’t

operate above 350 C

Water boils @ 1 atm at 100 C

Terrestrial Applications

Geothermal

Airplane

Military

Automotive

Venus

Jupiter Probes

Enhanced Oil Recovery

NA

SA N

eeds

Geothermal

Limit of commercial and military applications is currently about 350 C

Oil WellsGas

Extreme high temperature/high pressure environments are unique to

NASA missions

High Temperature Limits of Conventional Components

Magnets and actuators operational limit is ~ 300-350 C

CMOS For HT Electronics

Silicon On Insulator Clearly Outperforms

- 7

Components needing development to survive and operate in 460 C/90 bar Venus environment:Sample acquisition (drilling from bedrock, 10-20 cm):

•Actuators•Actuator Electronics and Packaging (Drivers)•Cabling and Connectors

Sample Handling and Transfer Mechanism:•Permanent Magnets

Sensors:•Temperature, Pressure, Position etc.•Fiber-optic bundles •Sensor’s Interface Electronics and Packaging (low noise preamplifiers)

Energy Storage:•BatteriesSample Acquisition

Minimize number of interconnections to avoid

potential thermal and pressure leaks

460 C

Venus Exploration - Hybrid Solution

Major flight system components (avionics, telecom, power distribution, advanced science instruments etc. ) are kept in controlled, conventional thermal-pressure

environment that standard components can be used. Sample acquisition system, in-situ sensors, and basic driving and sensor interface electronics are located outside and

exposed to extreme harsh environment (460 C/90 bar).

Avionics, Telecom, PMAD and Instruments in Thermally Controlled

Environment

~ 50 C/1 bar

- 8

Electronics Temperature and Thermal Control Mass

Environmental Temperature Requirement for Electronics, C

Ther

mal

Con

trol M

ass,

kg

50 250 450

• Venus In-Situ Explorer Mission• 3 hour descent and 1 hour on surface• Passive thermal control• Total mass: 150 kg for 50 C electronics

50

25

PCM

PCMLess Insulation

- 9

SILICON ON INSULATOR TECHNOLOGY

Buried SiO2 Insulating Layer Provides The Following Benefits

– 30% To 40% Faster Circuits– 30% To 40% Lower Power– Better Isolation For Mixed Signal ASICs– High Reliability – No latch-up– High Temperature Operation : 225°C continuous

and excursions to 300°C– Improved Sensor Accuracy And Stability

DigitalSOI CMOS

MixedMode

Sensors

Hi TempElectronics

System on a Chip

Integrated Hi TempSensor Systems• ASICs & Memories

• DoD And Commercial Applications

• 0.8 And 0.35 Micron Features

• IN PRODUCTION SINCE 1995

SOI CMOS

Bulk CMOS

N+

S DG

N+

Silicon Substrate

SiO2

Region of high capacitance substantially reduced by buried oxide layer

Bulk CN+ N+

S DG

SiO2

Silicon Substrate

N+N+

Silicon Substrate

- 10

Bulk Vs. SOI Cross-Section

Bulk

SOIP+ N+ N+

Silicon Substrate

0.3µm

Buried Oxide

P+

Trench Refill

N+ P+

N LDD

BSQ

Reflow Glass

1st Metal

2nd Metal

0.4µm

N+ N+

Silicon SubstrateField Oxide

P+

N LDD

BSQ

Reflow Glass

1st Metal

2nd Metal

P+P+N+

N-Well

- 11

30025020015010010 -6

10 -5

10 -4

10 -3

10 -2

10 -1

10 0

10 1

TEMPERATURE (°C)

DR

AIN

LE

AK

AG

E (A

/sq.

cm.)

BULK

SOI

Junction Leakage vs Temp.

SOI has >10x less leakage than Bulk

SOI vs. Bulk Leakage and Delay (1.2μ Process)

- 12

Electro-Migration Lifetime vs. Current Density

TEMPERATURE (°C)

LIFETIME(YRS)

0

1

10

100

150 170 190 210 230 250 270 290 310 330 350

AlCu:1mA/ /µm2

AlCu:.5mA/ /µm2

W:1mA/ /µm2Failure = 10% Increase

in Stripe ResistanceTime for 1%of the parts

to failW:2mA/ /µm2

Commercial Parts:Est. for 5 mA/µm2

> 5 Year Lifeat 225°C

Now

Future

- 13

High-temp. Issues & Mitigation Approaches

Junction Leakage• Junction leakage doubles every 10°C (above ≈170°C)• Use SOI processes – full oxide isolation

Sub-threshold transistor leakage• Threshold voltage has a negative temperature coefficient typically –2mV/°C.

Standard SOI processes leak badly above 200°C due to sub-threshold conduction.

• Re-target room-temp. Vt’s to compensate– Trade-off vs. drive current, voltage head-room.– One reason why 5V process persists for HT vs. 3.3, 2.5, 1.8.

Electro-migration• Aluminum inter-connect migration exponentially related to temperature• Design to more conservative design rules

– Wider metal traces / more vias and contacts– OR reduce the operating frequency (digital circuits)

• OR develop alternative inter-connect metalization (e.g., Tungsten)

- 14

High-temp. Issues & Mitigation Approaches

Reduced mobility vs. Temperature• Reduces digital drive currents, analog gain (gm)• Use larger devices for digital logic (or de-rate speed at HT)• Temperature compensate bias currents to stabliize gain vs.

temp. (increases power consumption at high temp.)

Bias voltage drift with temperature• Mobility and Vt drift with temperature may cause wide range of

bias voltage variation, eating into common-mode input range or output range

• Use “Zero Temperature Coefficient” biasing– Play Vt shift against mobility shift to stabilize bias voltages– Requires good models over temp.

- 15

Current HTMOS Standard Electronic Products

Product # Function Die SCPHT1104 Quad Op Amp Now NowHT1204 Quad Switch Now NowHT506 16:1 Analog Mux Now NowHT507 8:2 Analog Mux Now NowHT6256 256K Bit SRAM Now NowHT83C51 8 Bit Micro Controller Now NowHT2080 80K Gate Digital Array Now* Now*HT2160 160K Gate Digital Array Now* Now*HTCCG Crystal Clock Generator Now NowHTPLREG +5, +10 Or +15V Voltage Regulator Now NowHT574 12 Bit A/D Converter Now NowHTANFET Power FET Now NowHT6656 256K Bit ROM Now Now

Products in Red are 5V, 0.8μ SOI4 High Temp. ProcessProducts in Black are 1.2μ 10V-Linear High Temp. Process

- 16

Summary SOI CMOS for HT

• SOI CMOS is widely recognized as the most viable near-term solution for extending operating temperature for integrated circuits above 175°C

• SOI CMOS is capable for analog/mixed-signal signal conditioning and control applications

• For high power-density actuator/driver applications SOI is at a disadvantage relative to SiC

• Minor modifications to SOI processes are needed to extend temperature range for complex IC’s beyond 200°C

• Complete solutions are required: Analog/mixed-signal in addition to digital

• Exploiting synergy between SOI for rad-hard DoD and SOI for high-temp. down-hole applications will benefit both user communities

- 17

- 18

Mars Missions

Networks of Microprobes

SampleReturn

Canisters

Multiple sample returns withhighly capable landers/rovers

Science Micromissions

Aerobots

Mars Ascent

Vehicles

Mars Outposts

• Highly diverse spacecraft (size, power, mobility, lifetime, …)

• Globally distributedmissions

• Complex and demandingsurface and orbital operations

• Evolving capabilities

Airplanes

Balloons

- 19

Motivation for Low Temperature CMOS

• NASA plans to launch a long range rover for exploring the surface of Mars by 2009

• The temperature on Mars can vary from −120°C to +20 °C depending on time of day and location

• A major challenge for Mars rover missions is developing robust instrumentation and control electronics that can function properly over a broad temperature range.

- 20

Can we use commercial electronics for direct use in Mars? 85C>T>-120C

Key Challenges in Electronics:

• Commercial Off The Shelf analog electronics (transistors, amplifiers, ADC’s…) are designed and tested down to –55C. These parts have unknown electrical characteristics at temperatures lower than –55C.

• Complex programmable digital circuits Field Programmable Gate Arrays (FPGAs) may have issues with Clock Tree, Anti Fuse technology , On board RAM, PLL, Setup and Hold times.

• The reliability of both analog and digital commercial CMOS components at lower than –55C is generally unknown.

• There are no design rules or simulation models for fabrication of electronics components operating at –120C

- 21

25C

-120C

HCS114MS Hex Inverter Power-On Reset IS-705RH

WDI ~ 2.1 sec. to reset

PFI -1 20 C

WD

I 0CW

DI -12 0C

WDI ~1.42 sec. to reset

WDI Time to Reset (sec.)

0

1

2

3

4

5

6

-200 -150 -100 -50 0

Temperature (C)

Tim

e to

Res

et (s

ec.)

Experimental Results –Hex Inverter and Power-on Reset Circuit

- 22

5W DC-DC Converter 15W DC-DC Converter15 Watt DC/DC Converter - Cold Test

0

100200

300

400

500600

700

-200 -150 -100 -50 0 50

Temp. (C)

Iout

(mA)

15 Watt DC/DC Converter - Cold Test

0

1

2

3

4

5

6

-200 -150 -100 -50 0 50

Temp. (C)

Vou

t (V

)

Device failed at slightly colder than -120 °C

5 Watt DC/DC Converter - Cold Test

646647648649650651652653654655

-200 -150 -100 -50 0 50

Temp. (C)

Iout

(mA)

5 Watt DC/DC Converte r - Cold T est

4.934.94

4.954.96

4.974.98

4.995

-200 -150 -100 -50 0 50

Te m p. (C)

Vout

(V)

Below -150 °C the device took noticeably longer to come out of inhibit mode

• 5W converter functioned down to -160C.

• 15W converter only functioned down to -130C.

Experimental Results – Interpoint DC-DC Converter

- 23

6484 - RAD 25 °C

6484 - RAD -120 °C6484 – Plastic -120 °C

6484 – Plastic 25 °C

6484 - RAD -165 °C

OPAMP worked down to -165 Deg C

Experimental Results – OPAMP LM 6484

- 24

% Error vs. Temp

0

0.2

0.4

0.6

0.8

1

1.2

1.4

-200 -150 -100 -50 0 50 100

Temp. (C)

% E

rror

% error

AD 9225 Internal Vref vs. Temp.

1.985

1.99

1.995

2

2.005

2.01

-200 -100 0 100

Temp. (C)

Inte

rnal

Vre

f (V )

Internal Vref (V)

• The AD9225 analog-digital converter (12-bit) yielded 11-bit resolution at -80 °C and 10-bit resolution down to -168 °C.

• This performance meets the needs of the actuator task

• After cold soaking for 5 minutes at -160 °C, Vref stabilized and output had 1.2 % error.

Experimental Details – ADC 9225

- 25

ADC performance after 500 minutes of soak at –120C suggests that further cold temperature analysis is needed

Avg. % Error vs. Soak Time (-120 C)

00.20.40.60.8

11.21.41.61.8

60 110 160 210 260 310 360 410 460

Soak Time (minutes)

% E

rror

Stand-alone VREF vs. Soak Time

1.208

1.20851.209

1.20951.21

1.21051.211

1.2115

0 50 100 150 200 250 300 350 400

Soak Time (min)

Stan

d-al

one

VRE

F (V

)

Input Current vs. Soak Time (VIN = ~ 1.5 V) @

00.010.020.030.040.050.060.070.08

0 100 200 300 400 500

Soak Time (mi

• Vref and input currents increased after 200 minutes of operation at –120C.

• There may be a potential long term reliability problem for continuous operation under cold temperature.

• Will do long term cold temperature soak

Experimental Results – ADC 9225

- 26

-40 to +85

-55 to +125

Temp (°C)

No

*Yes

†TMR

144 Thin Quad FP

208-Pin Ceramic Quad FP

Package

NoNo48 KA54SX32A

100No108 KRT54SX72S

Radiation (TID) (Krad)

RAMDensity(SystemGate)

ACTEL FPGA

-40 to +100

-55 to +125

Temp (°C)

No

No

†TMR

240-Pin High Heat Dissipation Quad FP

228-Pin Ceramic Quad FP

Package

NoYes661 KXCVR600

100Yes661 KXQVR600

Radiation (TID) (Krad)

RAMDensity(SystemGate)

FPGA Xilinx

Commercial Actel FPGA (A54SX32A) results: Digital logic functioned down to –165C. Power cycling functioned to -165 C

Commercial Xilinx FPGA (XCVR600) results: Digital logic (program load at 0C) functioned down to –165 C. Power cycling, initialization current increased from 10 mA at 0C to 800 mA at –40C.

Experimental Results – FPGA

- 27

Power and Switching FETsP Channel - IRHNA597260 International Rectifie PASS at -165 CN Channel - IRHNA57260SE International Rectifie PASS at -165 CRIC7113L4 - High / Low Gate Dri International Rectifie PASS at -165 CJANSR2N7262 International Rectifie PASS at -165 CIRHG597110 International Rectifie PASS at -165 CIRHG57110 International Rectifie PASS at -165 CIRHNJ57034 International Rectifie PASS at -165 CIRHNJ597034 International Rectifie PASS at -165 COP-AMP / Discrete Transistors / FETSU430-2 Vishay PASS at -165 C2N3811 Microsemi PASS at -165 CLM394CH National SemiconducPASS at -165 CFPGAXQVR600-CB228 (QPro Virtex 2 XilinxXCV600-5HQ240I Xilinx 800 mA at -40CRT54SX72S-1CQ208-1 ActelA54SX32A-144 Actel PASS at -165 C

Voltage Regulator / Power Supply / ReferenceHS‐117RH (adjustable) Intersil Died at ‐130 CSMSA2805S / OO / HO / HR / HK Interpoint PASS at ‐170 CLM184‐1.2 National Semiconduct PASS at ‐165 CA to DAD9225AR Analog Devices PASS at ‐165 CInvertersHCS14MS Intersil PASS at ‐120 CPower On ResetIS‐705RH Intersil PASS at ‐170 CLevel ShifterCD40109BDMSR Intersil PASS at ‐165 CResolverCT5028‐2‐I (Preliminary Info) AeroflexNew Parts Additions

• Tested 22 components down to -165C

• 2 components failed

TCRE Experimental Results Summary

What if COTS Fail

Is Custom Mixed Signal ASICS for Cold Temperatures and Option?

- 29

Why is cold silicon cool ?

• Improved transport properties- higher mobility (μ ~ T-1.5) and saturation velocity (+ 50-100%)- velocity overshoot in ultra-short devices

• Better subthreshold swing (S ~T)• Reduced leakage current (I ~ e-E/kT)• Reduced electromigration & interconnect resistance• Possible combination CMOS + superconductors• Lower thermal noise• Improved thermal conductivity of silicon• Ideal for quantum and single-electron devices• Improved speed for cryogenic operation

- 30

Threshold Voltage

At low T:• Fermi level increases• Threshold voltage increases• Depletion depth extends• Double slope: transition from partial to full depletion

dVT/dT = 1.9 mV/K (PD, α = 1) or 0.6 mV/K (FD, α = 0)

⎟⎟⎠

⎞⎜⎜⎝

⎛++×

Φ= 2

2 ox

it

ox

DFT

CqD

CC

dTd

dTdV α

- 31

Drive Current

• Drain current can increase or decrease at low-T• Impact of device architecture (inversion or accumulation

mode, LDD, …)• Competing mechanisms

- mobility, threshold voltage, series resistance (all increasingat low-T)

- 32

Impurity Freeze-Out

• 77 K : weak freeze-out- RSD increases ⇒ LDD optimization- lateral field decreases ⇒ less impact ionization

• 30 K : strong freeze-out- field-effect ionization (via VG and VD)- ID(VG) curves may change according to VD

• SOI-like kink even in bulk MOSFETs• Fully-depleted SOI MOSFETs

- naturally kink free- suppressed kink-related excess noise

• Forget about body contacts

- 33

Hot Carrier Injection

Cuses• Caused by large electric field at the drain of the MOSFET• Significantly impacts NMOS more than PMOS since mobility, mean

free path, ionization rate for e− >> holes• HCI is supposed to be max. when VGS = VDS/2 for NMOS [1]• Low temperature operation of the device further degrades the

device characteristics

Impacts• With an increase in the drain voltage, HCI increases causing an

increase in the reverse-biased body-drain diode current⎯this reduces the output impedance of the MOSFET

• For a given device and drain current, lifetime α W×(ID)k, i.e. a wider device offers increased lifetime [2]

• No avalanche breakdown observed in SOI5 measurements for VDS = 5V

- 34December 10-12, 2003 PRE-DECISIONAL DRAFT: For Planning and Discussion Purposes Only 12

Mars Science Laboratory

MSL Focused Technology

• Anticipated life test of SOI CMOS TransistorsChannel Length Dependence – Idsat

100 years

• For digital application: 0.35 µm produces 12 years of life

0.6 µm produce 70 years of life

• For analog applications other parameters like Gm and Vth need to be evaluated

Modeling Life Cycle of CMOS MOSFETs function of L

- 35

Overview of Available SOI

NA1.2 V0.13 μmTSMC SOI CMOS

NA1.2 V0.13 μmIBM SOI CMOS

NAThick oxide (5 V)3.3 V0.35 μmHoneywell MOI5

300 krad1.8 V0.15 μmHoneywell SOI7

1 Mrad2.5 V0.25 μmHoneywell SOI6

2 Mrad20 V LDMOS3.3 V0.35 μmHoneywell SOI5

2 Mrad40 V LDMOS5 V0.8 μmHoneywell SOI4

Total DoseHigh voltage optionOperating voltage

Feature sizeProcess & Vendor

- 36

CMOS Device Design Considerationsfor Cold Temp CKTS

Increase in dynamic range and achievable resolution

Decreases with Decreasing temperature

Thermal Noise

Increased noise corner at low temperatures, reduces expected gains in dynamic range at low temperatures

Relatively Constant with temperature

1/f Noise

Increased intrinsic speed and transconductance

Increases with Decreasingtemperature

Mobility (μ)

Reduced ICMR in amplifiers, reduced dynamic range for analog switches

Increases with Decreasingtemperature

Threshold (VTO)

Effect on Analog Circuit Performance

Variation with TemperatureDevice Parameter

Summary of Important CMOS Temperature Characteristics

- 37

Robust LVCCM Biasing

• The VGS-multiplier is a new LVCCM bias technique developed at Univ. of Tennessee

• The salient feature of the VGS-multiplier is that it is guaranteed to maximize the VDS on both the top and bottom device in the mirror –independent of bias current, temperature, or any other circuit or environmental characteristics

R

R

R

IBIAS

IOUT

M1

M2

VGS-Multiplier Concept Transistor Level VGS-Multiplier

+

-

R

R

R

- 38

LVCCM Biasing for Extreme Env.

• Simulated performance over broad temperature range

- 39

Ping-Pong Op-Amp

• White noise is reduced at low temperatures, however 1/f noise is only weakly dependent on temperature, therefore the noise corner will increase with reduced temperature

• Ping-pong op-amps reduce 1/f noise by using auto-zeroing – thus they can increase dynamic range for systems with a high noise corner

- 40

Ping-Pong Op-Amp

• Plot showing measured noise-shaping of ping-pong op-amp– Ping-pong correction reduces the 1/f noise power because 1/f noise is correlated, however low frequency white

noise is increased because of noise folding– Net effect: Dynamic range is increased for systems where low-frequency noise dominates dynamic range (e.g.

gated-integrator)

- 41

Rail-to-Rail I/O Op-Amp

• Design Highlights– 1st stage is fully differential, rail-to-rail ICMR w/ regulated gm and

constant slew rate, CT CMFB– 2nd stage is a Class-AB driver with low quiescent current for good power

efficiency

MOI5 Op-Amp Schematic (LVCCM biasing not shown)

- 42

Rail-to-Rail I/O Op-Amp

MOI5 Op-Amp : Measured THD vs. Temperature

40

45

50

55

60

65

70

75

113 133 153 173 193 213 233 253 273 298

Temperature (K)

THD

(dB

)

12 Bit Linearity

10 Bit Linearity

8 Bit Linearity

Measurement Notes:Av = +1Vin = 3V p-p @ 8kHz11 Harmonics Measured

- 43

Commercial Electronics For Extr. Env.Summary

• COTS can provide functionality for a wider range of temperature, from 27°C to –175°C in the cold side. Mars and other NASA missions to cold environments may be able to use these COTS.

• Commercial foundries such as Honeywell PD SOI 0.35um technology + Cold temperature design rules can produce cold temperature specific mixed signal electronics

• Honeywell HT SOI CMOS offers integrated electronics solutions that work to> 200C

• For higher temperature environments, mass of the mission life is defined by the performance of the thermal system defines the life of the missions