conferencia
TRANSCRIPT
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© Digital Integrated Circuits2nd Introduction
Digital Integrated Digital Integrated
CircuitsCircuitsA Design PerspectiveA Design Perspective
Introduction to DesignIntroduction to Design
José Leonardo Simancas GarcíaElectronic Engineer
March 4, 2010
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© Digital Integrated Circuits2nd Introduction
What is this conference all about?What is this conference all about?
� Introduction to digital integrated circuits.� CMOS devices and manufacturing technology.
CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Sequential circuits. Arithmetic, interconnect, and memories. Programmable logic arrays. Design methodologies.
� What will you learn?� Understanding, designing, and optimizing digital
circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability
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Digital Integrated CircuitsDigital Integrated Circuits
� Issues in digital design� The CMOS inverter� Combinational logic structures� Sequential logic gates� Design methodologies� Interconnect: R, L and C� Timing� Arithmetic building blocks� Memories and array structures
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IntroductionIntroduction
� Why is designing digital ICs different today than it was before?
� Will it change in future?
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The First ComputerThe First Computer
The BabbageDifference Engine(1832)
25,000 partscost: £17,470
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ENIAC ENIAC -- The first electronic computer (1946)The first electronic computer (1946)
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The Transistor RevolutionThe Transistor Revolution
First transistorBell Labs, 1948
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The First Integrated Circuits The First Integrated Circuits
Bipolar logic1960’s
ECL 3-input GateMotorola 1966
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Intel 4004 MicroIntel 4004 Micro--ProcessorProcessor
19711000 transistors1 MHz operation
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Intel Pentium (IV) microprocessorIntel Pentium (IV) microprocessor
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MooreMoore’’s Laws Law
�In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. �He made a prediction that semiconductor technology will double its effectiveness every 18 months
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MooreMoore’’s Laws Law
16151413121110
9876543210
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
LOG
2 O
F T
HE
NU
MB
ER
OF
CO
MP
ON
EN
TS
PE
R IN
TE
GR
AT
ED
FU
NC
TIO
N
Electronics, April 19, 1965.
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Evolution in ComplexityEvolution in Complexity
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Transistor CountsTransistor Counts
1,000,000
100,000
10,000
1,000
10
100
11975 1980 1985 1990 1995 2000 2005 2010
8086
80286i386
i486Pentium ®
Pentium ® Pro
K1 Billion 1 Billion
TransistorsTransistors
Source: IntelSource: Intel
ProjectedProjected
Pentium ® IIPentium ® III
Courtesy, Intel
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MooreMoore’’s law in Microprocessorss law in Microprocessors
40048008
80808085 8086
286386
486Pentium® proc
P6
0.001
0.01
0.1
1
10
100
1000
1970 1980 1990 2000 2010Year
Tra
nsis
tors
(M
T)
2X growth in 1.96 years!
Transistors on Lead Microprocessors double every 2 yea rsTransistors on Lead Microprocessors double every 2 yea rs
Courtesy, Intel
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Die Size GrowthDie Size Growth
40048008
80808085
8086286
386486 Pentium ® proc
P6
1
10
100
1970 1980 1990 2000 2010Year
Die
siz
e (m
m)
~7% growth per year~2X growth in 10 years
Die size grows by 14% to satisfy Moore’s LawDie size grows by 14% to satisfy Moore’s Law
Courtesy, Intel
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FrequencyFrequency
P6Pentium ® proc
48638628680868085
8080800840040.1
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Fre
quen
cy (
Mhz
)
Lead Microprocessors frequency doubles every 2 yearsLead Microprocessors frequency doubles every 2 years
Doubles every2 years
Courtesy, Intel
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Power DissipationPower Dissipation
P6Pentium ® proc
486
3862868086
80858080
80084004
0.1
1
10
100
1971 1974 1978 1985 1992 2000Year
Pow
er (
Wat
ts)
Lead Microprocessors power continues to increaseLead Microprocessors power continues to increase
Courtesy, Intel
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Power will be a major problemPower will be a major problem
5KW 18KW
1.5KW 500W
40048008
80808085
8086286
386486
Pentium® proc
0.1
1
10
100
1000
10000
100000
1971 1974 1978 1985 1992 2000 2004 2008Year
Pow
er (
Wat
ts)
Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitive
Courtesy, Intel
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Power densityPower density
400480088080
8085
8086
286 386486
Pentium® procP6
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Pow
er D
ensi
ty (
W/c
m2)
Hot Plate
NuclearReactor
RocketNozzle
Power density too high to keep junctions at low tempPower density too high to keep junctions at low temp
Courtesy, Intel
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Not Only MicroprocessorsNot Only Microprocessors
Digital Cellular Market(Phones Shipped)
1996 1997 1998 1999 2000
Units 48M 86M 162M 260M 435M Analog Baseband
Digital Baseband
(DSP + MCU)
PowerManagement
Small Signal RF
PowerRF
(data from Texas Instruments)(data from Texas Instruments)
CellPhone
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Challenges in Digital DesignChallenges in Digital Design
“Microscopic Problems”• Ultra-high speed design• Interconnect• Noise, Crosstalk• Reliability, Manufacturability• Power Dissipation• Clock distribution.
Everything Looks a Little Different
“Macroscopic Issues”• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability• etc.
…and There’s a Lot of Them!
∝∝∝∝ DSM ∝∝∝∝ 1/DSM
?
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Productivity TrendsProductivity Trends
1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
2003
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2005
2007
2009
10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Logic Tr./ChipTr./Staff Month.
xxx
xxx
x
21%/Yr. compoundProductivity growth rate
x
58%/Yr. compoundedComplexity growth rate
10,000
1,000
100
10
1
0.1
0.01
0.001
Logi
c T
rans
isto
r pe
r C
hip
(M)
0.01
0.1
1
10
100
1,000
10,000
100,000
Pro
duct
ivity
(K)
Tra
ns./S
taff
-M
o.
Source: Sematech
Complexity outpaces design productivity
Com
plex
ity
Courtesy, ITRS Roadmap
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Why Scaling?Why Scaling?
� Technology shrinks by 0.7/generation� With every generation can integrate 2x more
functions per chip; chip cost does not increase significantly
� Cost of a function decreases by 2x� But …
� How to design chips with more and more functions?� Design engineering population does not double every
two years…
� Hence, a need for more efficient design methods� Exploit different levels of abstraction
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Design Abstraction LevelsDesign Abstraction Levels
n+n+S
GD
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
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Design MetricsDesign Metrics
� How to evaluate performance of a digital circuit (gate, block, …)?� Cost� Reliability� Scalability� Speed (delay, operating frequency) � Power dissipation� Energy to perform a function
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Cost of Integrated CircuitsCost of Integrated Circuits
� NRE (non-recurrent engineering) costs� design time and effort, mask generation
� one-time cost factor
� Recurrent costs� silicon processing, packaging, test� proportional to volume
� proportional to chip area
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NRE Cost is IncreasingNRE Cost is Increasing
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Die CostDie Cost
Single die
Wafer
From http://www.amd.com
Going up to 12” (30cm)
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Cost per TransistorCost per Transistor
0.00000010.0000001
0.0000010.000001
0.000010.00001
0.00010.0001
0.0010.001
0.010.01
0.10.111
19821982 19851985 19881988 19911991 19941994 19971997 20002000 20032003 20062006 20092009 20122012
cost: cost: ¢¢--perper --transistortransistor
Fabrication capital cost per transistor (Moore’s law)
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YieldYield
%100per wafer chips ofnumber Total
per wafer chips good of No. ×=Y
yield Dieper wafer Dies
costWafer cost Die
×=
( )area die2
diameterwafer
area die
diameter/2wafer per wafer Dies
2
××π−×π=
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DefectsDefects
α−
α×+= area dieareaunit per defects
1yield die
α is approximately 3
4area) (die cost die f=
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Some Examples (1994)Some Examples (1994)
$4179%402961.5$15000.803Pentium
$27213%482561.6$17000.703Super Sparc
$14919%532341.2$15000.703DEC Alpha
$7327%661961.0$13000.803HP PA 7100
$5328%1151211.3$17000.804Power PC 601
$1254%181811.0$12000.803486 DX2
$471%360431.0$9000.902386DX
Die cost
YieldDies/wafer
Area mm2
Def./ cm2
Wafer cost
Line width
Metal layers
Chip
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ReliabilityReliability――
Noise in Digital Integrated CircuitsNoise in Digital Integrated Circuits
i(t)
Inductive coupling Capacitive coupling Power and groundnoise
v(t) VDD
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DC OperationDC Operation
Voltage Transfer CharacteristicVoltage Transfer Characteristic
V(x)
V(y)
VOH
VOL
VM
VOHVOL
fV(y)=V(x)
Switching Threshold
Nominal Voltage Levels
VOH = f(VOL)VOL = f(VOH)VM = f(VM)
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Mapping between analog and digital signalsMapping between analog and digital signals
V IL V IH V in
Slope = -1
Slope = -1
V OL
V OH
Vout
“ 0” VOL
VIL
VIH
VOH
UndefinedRegion
“ 1”
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Definition of Noise MarginsDefinition of Noise Margins
Noise margin high
Noise margin low
VIH
VIL
UndefinedRegion
"1"
"0"
VOH
VOL
NMH
NML
Gate Output Gate Input
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Noise BudgetNoise Budget
� Allocates gross noise margin to expected sources of noise
� Sources: supply noise, cross talk, interference, offset
� Differentiate between fixed and proportional noise sources
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Key Reliability PropertiesKey Reliability Properties
� Absolute noise margin values are deceptive� a floating node is more easily disturbed than a
node driven by a low impedance (in terms of voltage)
� Noise immunity is the more important metric –the capability to suppress noise sources
� Key metrics: Noise transfer functions, Output impedance of the driver and input impedance of the receiver;
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Regenerative PropertyRegenerative Property
v0
v1
v3
finv(v)
f (v)
v3
out
v2 in
Regenerative Non-Regenerativev2
v1
f (v)
finv(v)
v3
out
v0 in
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Regenerative PropertyRegenerative Property
A chain of inverters
v0 v1 v2 v3 v4 v5 v6
2
V (
Vol
t)
4
v0
v1v2
t (nsec)0
2 1
1
3
5
6 8 10Simulated response
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FanFan--in and Fanin and Fan--outout
N
Fan-out N Fan-in M
M
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The Ideal GateThe Ideal Gate
Ri = ∞Ro = 0Fanout = ∞NMH = NML = VDD/2g = ∞
V in
V out
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An OldAn Old--time Invertertime Inverter
NM H
V in (V)
V
o u t
( V )
NM L
VM
0.0
1.0
2.0
3.0
4.0
5.0
1.0 2.0 3.0 4.0 5.0
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Delay DefinitionsDelay Definitions
Vout
tf
tpHL tpLH
tr
t
V in
t
90%
10%
50%
50%
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Ring OscillatorRing Oscillator
v0 v1 v5
v1 v2v0 v3 v4 v5
T = 2 × tp × N
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A FirstA First--Order RC NetworkOrder RC Network
vout
vin C
R
tp = ln (2) τ = 0.69 RC
Important model – matches delay of inverter
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Power DissipationPower Dissipation
Instantaneous power: p(t) = v(t)i(t) = Vsupplyi(t)
Peak power: Ppeak= Vsupplyipeak
Average power:
( )∫ ∫+ +
==Tt
t
Tt
t supplysupply
ave dttiT
Vdttp
TP )(
1
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Energy and EnergyEnergy and Energy--DelayDelay
Power-Delay Product (PDP) =
E = Energy per operation = Pav × tp
Energy-Delay Product (EDP) =
quality metric of gate = E × tp
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A FirstA First--Order RC NetworkOrder RC Network
E0 1→ P t( )dt0
T
∫ Vdd isupply t( )dt0
T
∫ Vdd CLdVout0
Vdd
∫ CL Vdd• 2= = = =
Ecap Pcap t( )dt0
T
∫ Vouticap t( )dt0
T
∫ CLVoutdVout0
Vdd
∫12---C
LVdd• 2= = = =
vout
vin CL
R
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SummarySummary
� Digital integrated circuits have come a long way and still have quite some potential left for the coming decades
� Some interesting challenges ahead� Getting a clear perspective on the challenges and
potential solutions is the purpose of this book
� Understanding the design metrics that govern digital design is crucial� Cost, reliability, speed, power and energy
dissipation