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Microprocessor (COM 9323) Lecture 2: Review on Intel Family Ahmed Elnakib, PhD Assistant Professor, Mansoura University, Egypt 1 Feb 17 th , 2016

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Page 1: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

Microprocessor (COM 9323)

Lecture 2: Review on Intel Family

Ahmed Elnakib, PhD

Assistant Professor, Mansoura University, Egypt

1Feb 17th, 2016

Page 2: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

Text Book/References

Textbook:1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition,

Barry B. Brey, Prentice Hall, 2009

2. Assembly Language for x86 processors, 6th edition, K. R. Irvine, Prentice Hall, 2011

References:1. Computer Architecture: A Quantitative Approach, 5th edition, J. Hennessy, D. Patterson,

Elsevier, 2012.

2. The 80x86 Family, Design, Programming and Interfacing, 3rd edition, Prentice Hall,

2002

3. The 80x86 IBM PC and Compatible Computers, Assembly Language, Design, and

Interfacing, 4th edition, M.A. Mazidi and J.G. Mazidi, Prentice Hall, 20032

Page 3: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

Lecture Objectives1. Provide an overview of the various 80X86 and Pentium family members

2. Define the contents of the memory system in the personal computer

3. Convert between binary, decimal, and hexadecimal numbers

4. Differentiate and represent numeric and alphabetic information as integers, floating-point, BCD, and ASCII data

5. Understand basic computer terminology (bit, byte, data, real memory system, protected mode memory system, Windows, DOS, I/O)

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Page 4: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

Brief History of the Computerso1946 The first generation of Computer ENIAC (Electrical and Numerical

Integrator and Calculator) was started to be used based on the vacuum tube technology, University of Pennsylvania

o1970s entire CPU was put in a single chip. (1971 the first microprocessor of Intel 4004 (4-bit data bus and 2300 transistors and 45 instructions)

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Page 5: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

Brief History of the Computers (cont’d)oLate 1970s Intel 8080/85 appeared with 8-bit data bus and 16-bit

address bus and used from traffic light controllers to homemade computers (8085: 246 instruction set, RISC*)

o1981 First PC was introduced by IBM with Intel 8088 (CISC**: over 20,000 instructions) microprocessor

oMotorola emerged with 6800. Apple Macintosh computers started to use 68000 series of microprocessors.

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*RISC: Reduced Instruction Set Computers **CISC: Complex instruction set computers

Page 6: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

8085 Intel Microprocessor

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o 16 bit address bus to select an address between 64kbyte memoryo 8 bit data bus to fetch 8 bits to its internal registers

Page 7: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

Simple Microprocessor Architecture

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Page 8: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

Early 8-bit Microprocessors

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o Only Intel and Motorola (IBM also

produces Motorola-style

microprocessors) continue

successfully to create newer and

improved versions of the

microprocessor

o Motorola has sold its

microprocessor division, named

now Freescale Semiconductors.

o Inc. Zilog still manufactures microprocessors, but remains in the background,

concentrating on microcontrollers and embedded controllers (Z-80, a

machine language compatible with 8085) instead of general-purpose

microprocessors.

Page 9: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

Intel Microprocessors Family till 2001

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Page 10: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

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Page 11: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

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Page 12: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

Intel Microprocessor core (P) versions

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Page 13: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

13

GenerationFirst

introducedProminent consumer CPU brands

Linear/physical address space

Notable (new) features

1st

1978 Intel 8086, Intel 8088 and clones16-bit / 20-bit

First x86 microprocessors

1982

Intel 80186, Intel 80188 and clones, NEC V20/V30

Hardware for fast address calculations, fast multiplication and division

2nd Intel 80286 and clones16-bit ((14+16)-bit segmented) / 24-bit

MMU, for protected mode and a larger address space

3rd (IA-32) 1985 Intel 80386 and clones, AMD Am386

32-bit ((14+32)-bit segmented) / 32-bit

32-bit instruction set, MMU with paging, PGA132 socket

3rd/4th 1992 Cyrix Cx486SLC, Cyrix Cx486DLCL1 cache and pipelining introduced into the 386 platform, PGA132 socket

4th (FPU) 1989 Intel 80486 and clones, AMD Am486RISC-like pipelining, integrated x87 FPU (80-bit), on-chipcache, PGA168 socket

4th/5th 1997Am5x86, Cyrix 5x86, Pentium OverDrive

Partial Pentium's specification brought into the 486 platform

5th 1993 Pentium, Pentium MMX, Rise mP6Superscalar 64-bit databus, faster FPU, MMX (2× 32-bit),Socket 7

5th/6th 1996

AMD K5, Cyrix 6x86, Cyrix MII, Nx586 (1994), IDT/Centaur-C6, Cyrix III-Samuel (2000), VIA C3-Samuel2 / VIA C3-Ezra (2001)

Discrete microarchitecture (µ-op translation)

Page 14: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

14

GnerationFirst

introducedProminent consumer CPU brands

Linear/physical address space

Notable (new) features

6th

1995 Pentium Pro32-bit ((14+32)-bit segmented) / 36-bit physical (PAE)

µ-op translation, conditional move instructions, Out-of-orderregisterrenaming, speculative execution, PAE (Pentium Pro), in-package L2 cache (Pentium Pro), Socket 8

1997 Pentium II/III, Celeron, XeonSSE (2× 64-bit), on-die L2 Cache (Mendocino, Coppermine),SLOT 1 or Socket 370

1997 AMD K6/2/III, Cyrix III-Joshua (2000)32-bit ((14+32)-bit segmented) / 32-bit

On-die L2-Cache (K6-III, Cyrix III Joshua), 3DNow!, no PAE support, Super Socket 7 (K6-2)

6th/7th 2003Pentium M, VIA C7 (2005), Intel Core(2006)

32-bit ((14+32)-bit segmented) / 36-bit physical (PAE)

Optimized for low thermal design power, four pumped FSB

7th

1999 Athlon, Athlon XPSuperscalar FPU, wide design (up to three x86 instr./clock),Slot A or Socket A

2000 Pentium 4Deeply pipelined, high frequency, SSE2, hyper-threading,Socket478

Brands of processors implementing the x86 instruction set (x86 History)

Page 15: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

GenerationFirst

introducedProminent consumer

CPU brandsLinear/physical address space

Notable (new) features

7th/8th

(x86-64)2005

Pentium 4 Prescott F/506/516/5x1/6xx,Celeron D 3x1/3x6/355, Pentium D

64-bit / 36-bit physical

EM64T technology introduced, very deeply pipelined, very high frequency, SSE3, LGA 775 socket, CMP

8th (x86-64)

2003Athlon 64, Athlon 64 X2 (2005), Sempron(2004), Opteron

64-bit / 40-bit physical

AMD64 processor (excluding 32-bit Sempron), on-die memory controller, HyperTransport, CMP, virtulisation(AMD-V) on some models, Socket 754/939/940 or AM2 socket

2006 Intel Core 264-bit / 36-bit physical

Intel 64 processor, low power, multi-core, lower clock frequency, SSE4 (Penryn), wide dynamic execution, µ-op fusion, macro-µ-op fusion, virtulisation (Intel VT) on some models

2007AMD Phenom, AMD Phenom II (2008)

64-bit / 48-bit physical

Monolithic quad-core, SSE4a, HyperTransport 3, AM2+ orAM3 socket

2008 VIA Nano64-bit / 36-bit physical

Out-of-order, superscalar, 64-bit (integer CPU), hardware-based encryption; very low power; adaptive power management 15

Brands of processors implementing the x86 instruction set (x86 History)

Page 16: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

16

GenerationFirst

introducedProminent consumer CPU

brandsLinear/physical address space

Notable (new) features

8th/9th

2008

Intel Core i3, Core i5 and Core i7(Nehalem/Westmere)

64-bit / 36-bit physical

QuickPath, native memory controller, on-die L3 cache, modular, Intel HD Graphics introduced onto CPU chip (Clarkdale), LGA 1366 (Nehalem) or LGA 1156 socket

Intel AtomIn-order but highly pipelined, very-low-power, some models (Diamondville) with 32-bit (integer CPU), on-die GPU (Penwell, Cedarview)

2011

AMD APU C, E and Z Series (Bobcat) Out-of-order, 64-bit (integer CPU), on-die GPU; low

power (Bobcat), Socket FM1 (Desktop)AMD APU A and E Series (Llano) 64-bit / 48-bit

physical

9th(GPGPU)

2011

AMD APU A Series (Bulldozer, Trinity and later)

SSE5/AVX (4× 64-bit), highly modular design, integrated on-die GPU, Socket FM2 or Socket FM2+

Intel Core i3, Core i5 and Core i7 (Sandy Bridge/Ivy Bridge)

64-bit / 40-bit physical

Internal Ring connection, GPGPU, LGA 1155 socket

2013Intel Core i3, Core i5 and Core i7(Haswell/Broadwell)

64-bit / 44-bit physical

AVX2, FMA3, TSX, BMI1, and BMI2 instructions, LGA 1150socket

Brands of processors implementing the x86 instruction set (x86 History)

Page 17: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

17

GenerationFirst

introducedProminent consumer

CPU brandsLinear/physical address space

Notable (new) features

10th

(SoC,MIC)2015/2016

Intel Core i3, Core i5 and Core i7(Skylake/Kaby Lake/Cannonlake)

Out-of-order, 64-bit (integer CPU), AVX3, integrated on-die southbridge, integrated on-die x86 MIC array GPU

Others

2000Transmeta Crusoe, Transmeta Efficeon

32-bit ((14+32)-bit segmented) / 32-bit

VLIW design with x86 emulator, on-die memory controller

2001Intel Itanium IA-32 compatibility mode

32-bit ((14+32)-bit segmented) / N/A

EPIC architecture with an on-package engine (pre-2006 chips, later using IA-32 Execution Layer) that provides backward support for most IA-32 applications

2012 Intel Xeon Phi (Larrabee)(MIC pilot) Many Integrated Cores (62), In-order P54C with x86-64, very wide vector unit, LRBniinstructions (8× 64-bit)

Brands of processors implementing the x86 instruction set (x86 History)

Page 18: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

Report 02: Due to Feb. 25th , 8.30 AM

o Individually

o Use the internet to make a report on I3, I5, and I7 technology

o Report will be delivered by hand before the lecture

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Page 19: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

19Computer Architecture

Page 20: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

The Memory Map in Personal Computers

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o Real (conventional Memory):1. TPA: Transient Program Area2. System Memory

o XMS: Extended memory Area

Page 21: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

TPA: Transient Program Area

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o Holds the DOS (disk operating system) operating system and other programs that control the computer system

oThe TPA is a DOS concept and not really applicable in Windows

oThe TPA also stores any currently active or inactive DOS application programs

oThe length of the TPA is 640K bytes

Available for application programs

Page 22: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

TPA: Interrupt vector

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o Interrupt vector: access features of DOS, basic I/O system (BIOS), and applicationsoThe system BIOS is a collection of programs

stored in either a read-only (ROM) or flash memory that operates many of the I/O devices connected to your computer system. oThe system BIOS and DOS communications

areas contain transient data used by programs to access I/O devices and the internal features of the computer system. These are stored in the TPA so they can be changed as the DOS operates.

Page 23: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

TPA: IO.SYS

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o IO.SYS: a program that loads into the TPA from the disk whenever an MSDOS system is started.

oThe IO.SYS contains programs that allow DOS to use the keyboard, video display, printer, and other I/O devices often found in the computer system.

o The IO.SYS program links DOS to the programs stored on the system BIOS ROM.

Page 24: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

TPA: Drivers

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oThe size of the driver area and number of drivers changes from one computer to another

oDrivers are programs that control installable I/O devices such as a mouse, disk cache, hand scanner, CD-ROM memory (Compact Disk Read-Only Memory), DVD (Digital Versatile Disk), or installable devices, as well as programs.

o Installable drivers are programs that control or drive devices or programs that are added to the computer system.

Page 25: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

TPA: COMMAND.COM

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oControls the operation of the computer from the keyboard when operated in the DOS mode

oThe COMMAND.COM program processes the DOS commands as they are typed from the keyboard. For example, if DIR is typed, the COMMAND.COM program displays a directory of the disk files in the current disk directory

Page 26: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

System Area

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o The DOS system area, although smaller than the TPA, is just as important.

oThe system area contains programs on either a read-only memory (ROM) or flash memory, and areas of read/write (RAM) memory for data storage.

Page 27: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

System Area MAP

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o The first area of the system space contains video display RAM and Video control programs on ROM or flash memory.

o The size and amount of memory used depends on the type of video display adapter attached to the system

o Display adapters generally have their video RAM located at A0000H–AFFFFH, which stores graphical or bit-mapped data, and the memory at B0000H–BFFFFH stores text data

o The video BIOS, located on a ROM or flash memory, is at locations C0000H–C7FFFH and contains programs that control the DOS video display

o BIOS System ROM: controls the operation of the basic I/O devices connected to the computer system.

This area is used for theexpanded memory system (EMS)

Page 28: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

Windows XP System Map

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o The Windows TPA is the first 2G bytes of the memory system from locations 00000000H to 7FFFFFFFH.

o The Windows system area is the last 2G bytes of memory from locations 80000000H to FFFFFFFFH

oWindows 64 ( a part of Windows Vista) supports up to 8G bytes of Windows memory

Page 29: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

I/O Space

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o The I/O (input/output) space in a computer system extends from I/O port 0000H to port FFFFH. (An I/O port address is similar to a memory address, except that instead of addressing memory, it addresses an I/O device.)

o The I/O devices allow the microprocessor to communicate between itself and the outside world.

o The I/O space allows the computer to access up to 64K different 8-bit I/O devices, 32K different 16-bit devices, or 16K different 32-bit devices.

o The 64-bit extensions support the same I/O space and I/O sizes as the 32-bit version and does not add 64-bit I/O devices to the system.

Page 30: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

I/O Space in PC

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oFigure shows the I/O map found in many

personal computer systems.

oTo view the map on your computer in Windows:

go to the Control Panel, Performance and Maintenance,

System, Hardware tab, Device Manager, View tab,

then select resources by type and click on the plus next

to Input/Output (I/O)

Page 31: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

I/O Space in PC

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oGenerally, I/O addresses between 0000H and 00FFH address components on the main board of the computer

o Addresses between 0100H and 03FFH address devices located on plug-in cards (or on the main board)

oThe remaining area is available I/O space for expansion that extends from I/O port 0400H through FFFFH

Page 32: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

Decimal and Binary number systems

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oThere is a speculation of the fact that Humans use base 10 system is becausethey have 10 fingers. But there is no speculation behind the fact that thecomputers use binary system.

oThe binary system is used in computers, because 1 and zero represent thetwo voltage levels of on and off.

oThere are 10 digits in Decimal system: 0,1,2,3,4,5,6,7,8,9

oThere are only 2 digits in Binary system: 0,1 (Binary digits are referred as bits)

Page 33: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

Converting from decimal to binary

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Page 34: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

Converting from binary to decimal

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Page 35: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

Hexadecimal Number system

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(base 16 number system) is used as a convenient representation of binary numbers.

Page 36: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

Conversion from Decimal to Hexadecimal

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Page 37: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

Hexadecimal to Decimal and Decimal to Hexadecimal

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Page 38: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

Addition and subtraction in binary numbers

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Page 39: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

Addition and subtraction in hex numbers

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Page 40: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

ASCII Code (American Standard Code for Information Interchange)

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o “A” is ASCII code 41H, and the lowercase letter “a” is ASCII code 61H

o To obtain 01H, type a Control-A; a 02H is obtained by a Control-B, and so on.

o0DH: The carriage return code (CR); Enter key: to return the cursor to the left margin

o0AH: The line feed code (LF), which moves the cursor down one line.

7 bit code

Page 41: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

Extended ASCII Code (ox80-0xFF)

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oUnicode 16 bit:(0000-00FF is the ASCII code; 0100H–FFFFH, are used to store allspecial characters from many worldwide character sets)

Page 42: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

Terminology

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1 Petabyte is 250 Bytes1 Extabyte is 260 Bytes

Page 43: Communication Theory II - ECED Mansoura · PDF fileText Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey,

Questions

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