combinational circuits

VLSI training 1 ttm inc.,

Combinational Circuits


Block Diagram

• A block diagram should show all inputs and outputs , the building

blocks and their function names , and the data flow paths ( the logic

signals).

- The internal details of each block need not be shown.

- Related logic signals are combined together and drawn with a double

or heavy line, known as a bus

• Example: Min/Max Circuit Comparator

Mux

Mux

Mux

X

Y

Z

MIN/MAX

X>Y

max(X,Y)

min(X,Y)


Signal Names and Active Levels

• Input and output signals should be labeled either by variable names

(X,Y, A,...) ,or by names that reflect actions or conditions (ENABLE,

REQUEST, /READY, ERROR, PAUSE).

• Active level : active high. or active low.

• The signal is asserted when it is in its active level and negated ( or

deasserted ) when its not in its active level.

• Active low signal has a prefix of / as part of the variable name.

• Example :

- ERROR is active high means there is an error when the signal is

HIGH ( logic 1).

- /READY is active low means the data is ready when the signal is

LOW ( logic 0).


Active Levels for Pins

• In logic gates and logic structures the inversion bubble

indicates the active level of the signal

• Examples:

- 2-to- 4 Decoder

- /EN is active low

- A and B are active high

- /Y0, /Y1, /Y2,/Y3 are active low

EN

A

B

Y0

Y1

Y2

Y3

/ EN

A

B

/ Y0

/ Y1

/ Y2

/ Y3


Timing Diagrams

Delay depends on

- Internal circuit structure

- Logic Family type

- Source Voltage

- Temperature

IN

/ENABLE

OUT Logic

Circuit IN

/ENABLE

OUT tOUT

IN

/ENABLE

OUT tOUTmin

tOUTmax


Propagation Delay

• The delay time between input transitions and the output

transitions due to the propagation delay of the the logic

gates.

• tp of a signal depends on the signal path inside the logic

circuit

• For a logic gate tpLH may not equal tpHL

• tp is specified in the manufacturer data sheets of the IC’s

• To find tp for a signal, add the propagation delays of all

gates along the path of the signal


Decoder Multiple-input / multiple-output device.

Inputs ( n ) are less than outputs ( m ).

Converts input code words into output

code words.

One-to-One mapping :

- Each input code produces only one

output code.

Input codes :

- Binary Code

- Gray Code

- BCD Code

- Your Code !

input

code

enable

inputs

output code DECODER


Binary Decoder

n-to-2^n decoder : n inputs and 2^n outputs.

Input code : Binary Code.

Output code : 1-out-of-2^n , One output is asserted for each input

code.

Example : n=2, 2-to-4 decoder

Inputs Outputs

EN I1 I0 Y3 Y2 Y1 Y0

0 x x 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

Logic Diagram???

EN

I0

I1

Y0

Y1

Y2

Y3


A 3-to-8 decoder Truth table

Inputs Outputs

G1 /G2A /G2B C B A /Y7 /Y6 /Y5 /Y4 /Y3 /Y2 /Y1 /Y0

0 x x x x x 1 1 1 1 1 1 1 1

x 1 x x x x 1 1 1 1 1 1 1 1

x x 1 x x x 1 1 1 1 1 1 1 1

1 0 0 0 0 0 1 1 1 1 1 1 1 0

1 0 0 0 0 1 1 1 1 1 1 1 0 1

1 0 0 0 1 0 1 1 1 1 1 0 1 1

1 0 0 0 1 1 1 1 1 1 0 1 1 1

1 0 0 1 0 0 1 1 1 0 1 1 1 1

1 0 0 1 0 1 1 1 0 1 1 1 1 1

1 0 0 1 1 0 1 0 1 1 1 1 1 1

1 0 0 1 1 1 0 1 1 1 1 1 1 1


Logic design using Decoders

• Advantages :

- Flexibility

- Multiple-output Logic functions

• Disadvantages :

- Complexity : for large number of inputs

( 5-variable Function with 3 minterms !

F= AB’CD’E + A’BC’DE+A’BCDE’ )


Seven-Segment Displays

• Displays decimal numbers and some characters

• LED (Light Emitting Diode ) or

LCD (Liquid Crystal Display)

• LED type

- Common Anode (CA) /Common Cathode (CC) type

- CA : requires Active Low inputs (a driver with Active Low outputs )

- CC : requires Active High inputs (a driver with Active High outputs )

a

b

c

d

e

f

g a

b

c

d

e

f

g

a

b

c

d

e

f

g


Seven-Segment Decoders/Drivers

• Input Code : BCD Code

Output Code : Seven-Segment Code

• Truth Table for Active High Seven-Segment Decoder/Driver

Input Output

D C B A a b c d e f g

0 0 0 0 1 1 1 1 1 1 0

0 0 0 1 0 1 1 0 0 0 0

0 0 1 0 1 1 0 1 1 0 1

0 0 1 1 1 1 1 1 0 0 1

0 1 0 0 0 1 1 0 0 1 1

0 1 0 1 1 0 1 1 0 1 1

0 1 1 0 0 0 1 1 1 1 1

0 1 1 1 1 1 1 0 0 0 0

1 0 0 0 1 1 1 1 1 1 1

1 0 0 1 1 1 1 0 0 1 1

a

b

c

d

e

f

g


Encoders

• Multiple-input/multiple-output device.

• Performs the inverse function of a Decoder.

• Outputs ( m ) are less than inputs ( n ).

• Converts input code words into output

code words.

input

code

output

code

ENCODER


Binary Encoder

• 2^n-to-n encoder : 2^n inputs and n outputs.

• Input code : 1-out-of-2^n.

• Output code : Binary Code

• Example : n=3, 8-to-3 encoder

Inputs Outputs

I0 I1 I2 I3 I4 I5 I6 I7 Y0 Y1 Y2

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 1 0 0 0 1 0 0

0 0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 1 1 1 1

I1

I2

I3 Y1

Y2 I4

I5

I6

I0

Y0

I7

Binary encoder


Priority Encoder • Assign priorities to the inputs

• When more than one input are asserted, the output generates the code

of the input with the highest priority

• Priority Encoder :

H7=I7 (Highest Priority)

H6=I6.I7’

H5=I5.I6’.I7’

H4=I4.I5’.I6’.I7’

H3=I3.I4’.I5’.I6’.I7’

H2=I2.I3’.I4’.I5’.I6’.I7’

H1=I1. I2’.I3’.I4’.I5’.I6’.I7’

H0=I0.I1’. I2’.I3’.I4’.I5’.I6’.I7’

IDLE= I0’.I1’. I2’.I3’.I4’.I5’.I6’.I7’

- Encoder

Y0 = I1 + I3 + I5 + I7

Y1 = I2 + I3 + I6 + I7

Y2 = I4 + I5 + I6 + I7

I1

I2

I3 Y1

Y2 I4

I5

I6

I0

Y0

I7

Binary encoder

I1

I2

I3

I4

I5

I6

I0

I7

Priority Circuit

H1

H2

H3

H4

H5

H6

H0

H7

IDLE

I1

I2

I3

I4

I5

I6

I0

I7

Y1

Y2

Y0

IDLE

Priority encoder


Encoder Application (Monitoring Unit)

Encoder Controller

Machine

Code Action

Machine 1

Machine 2

Machine n

Alarm

Signal

Contoller

Response


BCD Encoder (Application)

BI b

c

d B

C

7-segment

decoder

e

f

g

a

D

A

Idle

I1

I2

I3

Y1

Y2

I4

I5

I6

I0

Y0

I7

BCD encoder

Y3

I8

I9

+5V

Switch 0

Switch 9


Three State Buffers/Drivers

• A buffer/inverter with enable input

Buffer Buffer Inverter Inverter

Active High Enable Active Low Enable Active High Enable Active Low Enable

• The output is floating ( High Impedance, Hi-Z ) when the enable input is

deasserted ( The input is isolated from the output )

• Application:

Controlling the access of a single line/bus by multiple devices


8 data sources sharing one line

G2A

Y0

Y1

Y2

Y3

A

B

74x138

Y4

Y5

Y6

Y7

C

G2B

G1

P

Q

R

S

T

U

V

W

/SEL P

/SEL Q

/SEL T

/SEL U

/SEL V

/SEL W

/SEL S

/SEL R

EN1

/EN2

/EN3

S2

S1

S0


Multiplexers

• Multiplexing : Transmitting large number of signals over a small

number of channels or lines

• Digital multiplexer (MUX ) : Selects one of many input lines and

directs it to a single output.

• Selection lines control the selection of a particular input

• n selection lines, 2^n inputs , single output.

• Example : 4-to-1 line multiplexer :

Function Table :

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

4 1

MUX

I0

Y

S1 S0

Inputs Output

Select

I1

I2

I3


Realization of 4:1 MUX using 2:1 MUXes :

I0 0

1

S0

S0

I1

I2

I3

0

1

0

1

S1

Y


Demultiplexers

• Demultiplexer (DMUX) performs the opposite function of a MUX.

• A digital Demultiplexer receives input data on a single input and

transmits it on one of 2^n possible outputs according to the value of

the n select inputs

• MUX/DMUX are used in data transmission

Source Destination

MUX DMUX

A

B

C

A

B

C

Select Select

BUS


Using Decoders as DMUX

• A DMUX has the same structure of a Decoder with enable input.

• Decoder can be used as a DMUX by connecting the input data to the

enable input.

• Example :

2-to-4 Decoder can be used as 1-to-4 DMUX

EN

I0

I1

Y0

Y1

Y2

Y3

S1

S0

INPUT

D0

D1

D2

D3


Adders/Subtractors

• Half Adder

• Full Adder

• Ripple Adder

• Carry look-ahead adder

• Full Subtractor

• Ripple Subtractor

• Adder/Subtractor Circuit


Ripple Adder

• Cascade n Full Adders to get n-bit binary Adder

X Y

COUT CIN S

X Y

COUT CIN S

X Y

COUT CIN S

X0 Y0 X1 Y1 X(n-1) Y(n-1)

S0 S1 S(n-1)

COUT CIN


Ripple Subtractor

• Cascade n Subtractors to get n-bit binary Subtractor

• D= X-Y

X Y

BOUT BIN D

X Y

BOUT BIN D

X Y

BOUT BIN D

X0 Y0 X1 Y1 X(n-1) Y(n-1)

D0 D1 D(n-1)

BOUT BIN


Using Adder as a Subtractor

• X,Y are n-bit unsigned binary numbers

• Addition : S = X + Y

• Subtraction : D = X - Y = X + (-Y) =

= X+ (Two’s Complement of Y)

= X+ (One’s Complement of Y) + 1

= X+ Y’+ 1

• Ripple Adder can be used as a subtractor by inverting Y and setting the

initial carry ( CIN ) to 1


Carry Look-ahead Adder

•

• CLL: Carry Look-ahead Logic

• I0=C0

I i ????????

X Y

CLL

S

X Y

CLL

S

X Y

CLL

S

X0 Y0 X1 Y1 X(n-1) Y(n-1)

S0 S1 S(n-1)

I 0 I (n-1) I 1

Carry Look-ahead Adder Units

COUT


Carry Look-ahead Logic • We need to provide an expression for the ci in the Carry Lookahead Logic

Unit

• Question : when does the Full adder produce carry ??

Answer :

If both Xi and Yi equal 1 ( carry is generated)

OR....

If Ci=1 and either Xi or Yi equal 1 ( carry is propagated )

• In Boolean algebra the above statement is expressed as :

Ci+1= (Xi.Yi)+ (Xi+Yi).Ci { Compare to : COUT=XY+X CIN+Y CIN}

• Let gi= Xi.Yi

pi= Xi+Yi

Ci+1= gi+pi.Ci


Carry Look-ahead Logic

• Ci+1= gi+pi.Ci gi=Xi.Yi pi=xi+yi

- C1=g0+p0.C0

- C2=g1+p1.C1 = g1+p1.(g0+p0.C0)

= g1+p1g0+p1.p0.C0

- C3= g2+p2.C2 = g2+p2.(g1+p1g0+p1.p0.C0)

= g2+p2.g1+p2.p1.g0+p2.p1.p0.C0

- C4= .................

• C1, C2, C3, ..... are generated with almost the same amount of delay

combinational circuits

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