cms l1 global muon trigger update - hephy€¦ · cern/ep l1 global muon trigger update 4 trigger...

CMS L1 Global Muon Trigger UpdateHannes Sakulin, CERN / EP

Trigger Meeting, CPT Week, CERN

6th November, 2001

VME 6U

6U crate

Monitoring PC

Private PC

cooling

cooling

cooling

cooling

DAQ-PC

VME 9UGT crate

GMT

GT

URL of this presentation: http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalMuonTrigger/trans/GMT-CPTWeek06Nov2001.pdf

Hannes SakulinCERN/EP L1 Global Muon Trigger Update 2 Trigger Meeting, CPT Week

CERN, 6th November 2001

CMS Level-1 Trigger

RPCCaloTrigger DTBX CSC

PACTPattern

Comparator

TRACOTrack Correlator

Trigger Server

DTBarrel

Track Finder

Wirecards

Stripcards

Motherboard

CSCEndcap

Track Finder

DTSorter

CSCSorter

RPCSorter

CALReadout

Regional CALOTrigger

GLOBAL MUON TRIGGER

GLOBAL L1 TRIGGER

GLOBAL CALORIMETER

TRIGGER

4+4 � 4 � 4 �

4 �

MIP &quiet bits

(2x 252)

HEPHY Vienna

HEPHY Vienna

HEPHYVienna

Bologna Rice

Florida

BariBristol

BTIBunch & Time ID

WarsawWisconsin

L1 Accept ………… max. 100 kHz

Pipe-lined

40 MHz



SRK LUT

0

1

2

3

4

5

1

1

1

SRK LUT

01

23

45

11

1

4 DTbrl

4 RPCbrl

4 RPCfwd

4 CSCfwd

matching, finding pairs

calculating single rank

merging parameters

selector (ghost suppression)

forward sorter

global sorter

matching, finding pairs

calculating single rank

merging parameters

selector (ghost suppression)

barrel sorter

best 4 muons, whole detector

�,QSXWV��ELW�I��ELW�K��ELW�S

7��

��ELW�FKDUJH��ELW�TXDOLW\

�2XWSXW��ELW�φ��ELW�η��ELW�S

7��

��ELW�FKDUJH��ELW�TXDOLW\��ELW�0,3��ELW�,VRODWLRQ�

�)XUWKHU�,QSXWV�0,3�DQG�4XLHW�%LWV�RI��FDORULPHWHU�UHJLRQV

Principle of the GMT

→ increase efficiency→ reduce ghosts→ reduce trigger rate by

improving pT assignment→ add MIP & ISO bits from

calorimeterBest 4 �



The Global Trigger Rack

A.Taurok 22.10.2001

Global Trigger

Rack

6U+3U fan_unit

9U+ 3U fan_unit

6U+3U fan_unit

3U cooling

3U cooling

3U cooling

3U cooling

3U PC

3U PC

3U PC

4 Tracker Emulators

Private Monitoring &

Test boards

GMT, GT, TCS

Conversion boards

(Fast signals,...)

Ethernet

2 S-links

JTAG

PCI-VME link

36 ch_links MIP/QUIET bits

18 ch_links Calo trigger data *

16 DT,CSC,RPC muon cables

*) 6 groups, 1group= 4 objects

on 3 Chann_links

+ 1 group free

32 TTC_data (L1A,cmd)

VME 6U

6U crate

Monitoring PC

Private PC

cooling

cooling

cooling

cooling

DAQ-PC

32 Fast Signal cables

2 opt. DAQ links

JTAG & Test PC

Monitoring PC

VME 9U

GT crate



GMT in the Global Trigger Crate

�1GMT Logic Board (front panel 4 slots wide)�3 PSB boards to receive calorimeter information

32 chan parallel12+12 ISO

11 RO_links

8 RPC muons4 DT muons

4 CSC muons

4TAU4fwJET4 Calo*

4 Calo*=total ET, ETmiss

Nr_jetsA, Nr_jetsB

L1 GLOBAL TRIGGER9U Crate

MIP+ISO=252x2 bits =18 chan(16 bits) + 18 chan(12 bits)

24 ch ISO/MIP 4IEG4EG4JET

READOUT_links

TTCfibre

4MUONS parallel

FAST SIGNALSand others

CLOCK,BCRES,RO-bus

6+6 ISO

12 chISO/MIP

ConversionCrate 6U

DAQSlink

4 free4 not used

3 VME+ 1free

slots

EVMSlink

to 32TTCvi

Sept 01

128 Algo+8 FinOR

LVDS toChannel Link

conversion

L1A, CMD32 cables

12 ChannLinks

PSB12

GTL32

GTL32

PSB12

PSB12

PSB12

PSB12

PSB12

TIM FDL L1Aout

Global Trigger

GTFETCS

GT-part of

TriggerControl

GMT

4 slots

Global Muon Trigger

32x L1A,Cmd

128 Algo



PSB 6 channel prototype

Prototype available



Single board Global Muon TriggerFront panel

VME

VME

LVDS receivers

FINALGMT

SORTER

4 muons26x4 bits

VMEIntfc

180 pins

144 pins

52 pins

16 pins

16 pins

max=476 pins

4µµµµ CSC

4µµµµRPCfwd

4µµµµRPCbarr

4µµµµ DT

VME/ROP

GMT-INFPGA

4µµµµ

synchronisation,readout,

...

fwd_LOGIC FPGA

MATCH& PAIRLOGIC

SingleRank

LOGIC

ηηηη convers.

MATCH& PAIRLOGIC

ηηηη convers.

barrel_LOGIC FPGA

assignedISO/MIP bits

4µµµµ fwd

4µµµµ barr

GMT-INFPGA

4µµµµbarrel

PROJECTIONFPGA

VME/ROP

VME/ROP

forwardPROJECTION

FPGA

DAQreadout

P1/P2

JTAG, Clock

MUONMERGER

&fwd

SORTER

L1A,..

16 SCSI-2

fwd: (180MIP+180 ISO)/2

barr: (144 MIP+144 ISO)/2

MIP+ QUIET bitReformatting

CSC/DTcancel out

canc.

SingleRank

LOGIC

MUONMERGER

&fwd

SORTER

10 pins

80MHzGTLp

ChLink

ROPFPGA

GMT single-board solution

Latency: 14 bx

Logic design close to completion



GMT Logic FPGA

Rankassignment

unit

Match logic

Muon extend (RPC)

Muon merger unitSort stage 1

η1

η2

φ1

φ2SUB(mod 144)

LUTMaxDisPair

16x

16x

16x

1x

6

6

8

8

4

3

3

16x6

empty-IJ

16

4

4DT-

matched

RPC-matched

pairmatrix

η1

η2

φ1

φ2

SUB(mod 144)

LUTMaxDisPair16x

16x 16x 1x4(6)

8

8

4 4

3

3

16x6

16

16x

16

DT-is-dup

pairmatrix

16

4

4

4

cancel-decision

1x

4 456(60)

4(6)

CSC η/φ DT-is-matched

CSC-is-matched

pT,q

LUT5

6/7

3

pT

η

q

η,φLUT

6

8φ

8

7

2

2

1x

1x

8x

cancel-DT

cancel-DT or pair

cancel-RPC

4

4

4->1MUX

136(4x34)

136(4x34)

136(4x34)

136(4x34)

very-lowquality flag

Eta-convert & charge valid

92(4x23)

4x

4x92(4X23)

92/96(4X23/24)

1

MIP/ISO (from CaloPro chip)

8

4

4x

4

DT-matched

96/1004x24/25

96(4X24)

24

RPC4 µ

4 µDT

8

2

8

GMT logic FPGA

RPC

DTor

pairs

8->1MUX

4x

sort by rank

32

32

ranksRPC

ranksDT or pairs

selectbits

Merge ranks

Assign quality

Merge η

MergepT

8

2

34

pTmix LUT5

55

pT

pT

4 muout

88

e.g. plus 20

isMatched==1

4x

Hannes Sakulin, CERN, 25.10.2001

3

Merge φMUX2->1

DT

RPCDTpT, η, φ

qch

chargeLUT 2 ch

MIP/ISO

qq LUT

sort rank8

MUX2->1

ch

η

φ

1x

η,qLUT3

Rankcomb.LUT

2

2

1

empty-ifrom pT

8x

5

16x 164

sortrank

disablehot region

8

8

empty-IJ

MQLUT

MQLUT

4

4

DT/CSC cancel-out unit

DT-is-empty

CSC-is-empty

4

6

1

2

1

1

1

1

6

Rankcomparator

array

Rankoffsetadders

+

>

pTcomparator

array

>pT

MUX3->1

8

8

MUX3->1

5

1

fine

Mergecharge

smart charge LUT2

22

MUX3->1

2

Eta-convert & charge valid

MIPMerge

MIPMIP mixLUT1

1

1

MUX3->1

1

ISOMerge

ISOISO mixLUT1

1

1

MUX3->1

1

η,φinhibit LUTs

4x

η,φinhibit LUTs

6

8

4x

6

8

2

2

Logic design close to completion



Beam Halo Muon Trigger

� GMT input� CSC halo muon candidates flagged by a halo-bit

(halo muons are not seen by RPC)

� GMT operation & output to Global Trigger� give high priority (rank) to halo muons� assign special quality code

� Global Trigger runs algorithms to trigger calibration events� type 1: trigger on halo muon in one endcap� type 2: trigger on halo muon found in both endcaps

topological condition: match φ and possibly |η| or radiusopen question of timing

� trigger only on type 2 halo muons to reduce the rate if necessary

� Beam Halo trigger is possible during normal physics data taking (from point of view of GMT)



ID Task Name

1 GMT Conceptual Design

2 GMT simulation, logic design

3 GMT FPGA design

4 GMT production

5 GMT available

6 Finish delivery

7 Online Software

8 Finish commissioning

1/11

25/2

1/7

H2 H1 H2 H1 H2 H1 H2 H1 H2 H1 H2 H1 H2 H1 H2

98 1999 2000 2001 2002 2003 2004 2005

�

GMT Hardware schedule

� Milestones / Plans:� 2001 Logic design, ORCA + VHDL Simulation� Dec 2001 Logic design finished

� 2002 VHDL Simulation, Design of FPGA chips

� Dec 2002 FPGA design finished

� 2003 Production of VME 9U Boards

� 2004/05 Integration tests, production of spare boards



Progress in 2001 & Plans for 2002

� Progress in 2001:� Logic design close to completion

• Chip Models selected (mostly Virtex II), Interconnections defined• Design compacted (external RAMs moved into big FPGAs)• Detailed GMT design document

� Improvement of functionality• DT/CSC cancel-out unit (improved performance in barrel/endcap overlap region)

� in parallel: • ORCA Simulation extended and improved• Continuous studies to optimize GMT design parameters and performance

� VHDL behavioral level simulation has started

� Plans for 2002:� continue VHDL simulation of FPGA chips� VHDL simulation of GMT board� Synthesis / design of FPGAs� in parallel further studies with ORCA



(units)genη0 0.5 1 1.5 2 2.5

Eff

icie

ncy

(%

)

0

20

40

60

80

100

DTBX

CSC

RPC

GMT

/ GeV/ccutTSingle muon p

10 12 14 16 18 20 22 24 26 28 30

GeV

/ccu

tT

Sym

met

ric

di-

mu

on

p

2

4

6

8

10

12

14

L1 single and di-muon trigger rates

7 6 5

43 kHz

4.53.5

2 kHz

2.5 kHz

1.5 kHz

1 kHz

Simulation resultsmuon 2001 production, ORCA 5.1.2

(GeV/c)cutTmuon p1 10

Tri

gg

er R

ate

(Hz)

1

10

102

103

104

105

106

GenDT + CSCRPCGMT-optGMT re-tuned

|< 2.5ηwhole detector: 0 < |¾ Single muon trigger rate for L=2x1033

at 20 GeV/c : 1.4 kHz

(GeV/c)cutT,1muon p

4 6 8 10 12 14 16 18 20

Trig

ger

Rat

e / H

z

1

10

102

103

GenDT + CSCCSCRPCGMT (re-tuned)GMT from ghosts

from 1 eventµGMT 2 from 2 events in 1 bxµGMT 2

4 GeV/c≥ T,2Di-muon Rates - p

¾ Di-muon trigger rate for L=2x1033

pT,2 ≥ 4 GeV/c, at 4 & 4 GeV/c: 700 Hz

¾ Single muon / di-muon combined trigger rates for L=2x1033

¾ Efficiency versus η, 96.3 % overall



Conclusion

� Progress in hardware design as planned� logic design almost completed

• FPGAs selected• design compacted & improved

� new solution with 1 logic board

� trigger on halo muons is possible during normal physics running (from GMT point of view)

� Planned R&D in 2002� VHDL simulation of FPGAs and board

� design of FPGAs

� Simulation results with 2001 muon production� pT-cut was lower than in last year’s production

� improved CSC trigger & GMT can cope with higher background rate� updated results with higher statistics expected by the end of the year

cms l1 global muon trigger update - hephy€¦ · cern/ep l1 global muon trigger update 4 trigger...

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