cms l1 global muon trigger update - hephy · hannes sakulin cern/ep l1 global muon trigger update 2...

CMS L1 Global Muon Trigger UpdateHannes Sakulin, CERN / EP

Trigger Meeting, CMS Week, CERN

4th December, 2001

URL of this presentation: http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalMuonTrigger/trans/GMT-CMSWeek04Dec2001.pdf

VME 6U

6U crate

Monitoring PC

Private PC

cooling

cooling

cooling

cooling

DAQ -PC

VME 9UGT crate

G

M

T

GT

��Hardware statusHardware status��Thoughts on haloThoughts on halo

triggerstriggers��Simulation Simulation

Hannes SakulinCERN/EP L1 Global Muon Trigger Update 2 Trigger Meeting, CPT Week

CERN, 4th December 2001

CMS Level-1 Trigger

RPCCaloTrigger DTBX CSC

PACTPattern

Comparator

TRACOTrack Correlator

Trigger Server

DTBarrel

Track Finder

Wirecards

Stripcards

Motherboard

CSCEndcap

Track Finder

DTSorter

CSCSorter

RPCSorter

CALReadout

Regional CALOTrigger

GLOBAL MUON TRIGGER

GLOBAL L1 TRIGGER

GLOBAL CALORIMETER

TRIGGER

4+4 � 4 � 4 �

4 �

MIP &quiet bits

(2x 252)

HEPHY Vienna

HEPHY Vienna

HEPHYVienna

Bologna Rice

Florida

BariBristol

BTIBunch & Time ID

WarsawWisconsin

L1 Accept ………… max. 100 kHz

Pipe-lined

40 MHz



SRK LUT

0

1

2

3

4

5

1

1

1

SRK LUT

01

23

45

11

1

4 DTbrl

4 RPCbrl

4 RPCfwd

4 CSCfwd

matching, finding pairs

calculating single rank

merging parameters

selector (ghost suppression)

forward sorter

global sorter

matching, finding pairs

calculating single rank

merging parameters

selector (ghost suppression)

barrel sorter

best 4 muons, whole detector

�,QSXWV��ELW�I��ELW�K��ELW�S

7��

��ELW�FKDUJH��ELW�TXDOLW\

�2XWSXW��ELW�φ��ELW�η��ELW�S

7��

��ELW�FKDUJH��ELW�TXDOLW\��ELW�0,3��ELW�,VRODWLRQ�

�)XUWKHU�,QSXWV�0,3�DQG�4XLHW�%LWV�RI��FDORULPHWHU�UHJLRQV

Principle of the GMT

→ increase efficiency→ reduce ghosts→ reduce trigger rate by

improving pT assignment→ add MIP & ISO bits from

calorimeterBest 4 �



GMT in the Global Trigger Crate

�1GMT Logic Board (front panel 4 slots wide)�3 PSB boards to receive calorimeter information

32 chan parallel12+12 ISO

11 RO_links

8 RPC muons4 DT muons

4 CSC muons

4TAU4fwJET4 Calo*

4 Calo*=total ET, ETmiss

Nr_jetsA, Nr_jetsB

L1 GLOBAL TRIGGER9U Crate

MIP+ISO=252x2 bits =18 chan(16 bits) + 18 chan(12 bits)

24 ch ISO/MIP 4IEG4EG4JET

READOUT_links

TTCfibre

4MUONS parallel

FAST SIGNALSand others

CLOCK,BCRES,RO-bus

6+6 ISO

12 chISO/MIP

ConversionCrate 6U

DAQSlink

4 free4 not used

3 VME+ 1free

slots

EVMSlink

to 32TTCvi

Sept 01

128 Algo+8 FinOR

LVDS toChannel Link

conversion

L1A, CMD32 cables

12 ChannLinks

PSB12

GTL32

GTL32

PSB12

PSB12

PSB12

PSB12

PSB12

TIM FDL L1Aout

Global Trigger

GTFETCS

GT-part of

TriggerControl

GMT

4 slots

Global Muon Trigger

32x L1A,Cmd

128 Algo



PSB 6 channel prototype

Prototype available



Single board Global Muon TriggerFront panel

VME

VME

LVDS receivers

FINALGMT

SORTER

4 muons26x4 bits

VMEIntfc

180 pins

144 pins

52 pins

16 pins

16 pins

max=476 pins

4µµµµ CSC

4µµµµRPCfwd

4µµµµRPCbarr

4µµµµ DT

VME/ROP

GMT-INFPGA

4µµµµ

synchronisation,readout,

...

fwd_LOGIC FPGA

MATCH& PAIRLOGIC

SingleRank

LOGIC

ηηηη convers.

MATCH& PAIRLOGIC

ηηηη convers.

barrel_LOGIC FPGA

assignedISO/MIP bits

4µµµµ fwd

4µµµµ barr

GMT-INFPGA

4µµµµbarrel

PROJECTIONFPGA

VME/ROP

VME/ROP

forwardPROJECTION

FPGA

DAQreadout

P1/P2

JTAG, Clock

MUONMERGER

&fwd

SORTER

L1A,..

16 SCSI-2

fwd: (180MIP+180 ISO)/2

barr: (144 MIP+144 ISO)/2

MIP+ QUIET bitReformatting

CSC/DTcancel out

canc.

SingleRank

LOGIC

MUONMERGER

&fwd

SORTER

10 pins

80MHzGTLp

ChLink

ROPFPGA

GMT single-board solution

Latency: 14 bx

All logic functions defined



GMT Logic FPGA

Rankassignment

unit

Match logic

Muon extend (RPC)

Muon merger unitSort stage 1

η1

η2

φ1

φ2SUB(mod 144)

LUTMaxDisPair

16x

16x

16x

1x

6

6

8

8

4

3

3

16x6

empty-IJ

16

4

4DT-

matched

RPC-matched

pairmatrix

η1

η2

φ1

φ2

SUB(mod 144)

LUTMaxDisPair16x

16x 16x 1x4(6)

8

8

4 4

3

3

16x6

16

16x

16

DT-is-dup

pairmatrix

16

4

4

4

cancel-decision

1x

4 456(60)

4(6)

CSC η/φ DT-is-matched

CSC-is-matched

pT,q

LUT5

6/7

3

pT

η

q

η,φLUT

6

8φ

8

7

2

2

1x

1x

8x

cancel-DT

cancel-DT or pair

cancel-RPC

4

4

4->1MUX

136(4x34)

136(4x34)

136(4x34)

136(4x34)

very-lowquality flag

Eta-convert & charge valid

92(4x23)

4x

4x92(4X23)

92/96(4X23/24)

1

MIP/ISO (from CaloPro chip)

8

4

4x

4

DT-matched

96/1004x24/25

96(4X24)

24

RPC4 µ

4 µDT

8

2

8

GMT logic FPGA

RPC

DTor

pairs

8->1MUX

4x

sort by rank

32

32

ranksRPC

ranksDT or pairs

selectbits

Merge ranks

Assign quality

Merge η

MergepT

8

2

34

pTmix LUT5

55

pT

pT

4 muout

88

e.g. plus 20

isMatched==1

4x

Hannes Sakulin, CERN, 25.10.2001

3

Merge φMUX2->1

DT

RPCDTpT, η, φ

qch

chargeLUT 2 ch

MIP/ISO

qq LUT

sort rank8

MUX2->1

ch

η

φ

1x

η,qLUT3

Rankcomb.LUT

2

2

1

empty-ifrom pT

8x

5

16x 164

sortrank

disablehot region

8

8

empty-IJ

MQLUT

MQLUT

4

4

DT/CSC cancel-out unit

DT-is-empty

CSC-is-empty

4

6

1

2

1

1

1

1

6

Rankcomparator

array

Rankoffsetadders

+

>

pTcomparator

array

>pT

MUX3->1

8

8

MUX3->1

5

1

fine

Mergecharge

smart charge LUT2

22

MUX3->1

2

Eta-convert & charge valid

MIPMerge

MIPMIP mixLUT1

1

1

MUX3->1

1

ISOMerge

ISOISO mixLUT1

1

1

MUX3->1

1

η,φinhibit LUTs

4x

η,φinhibit LUTs

6

8

4x

6

8

2

2

All logic functions defined



ID Task Name

1 GMT Conceptual Design

2 GMT simulation, logic design

3 GMT FPGA design

4 GMT production

5 GMT available

6 Finish delivery

7 Online Software

8 Finish commissioning

1/11

25/2

1/7

H2 H1 H2 H1 H2 H1 H2 H1 H2 H1 H2 H1 H2 H1 H2

98 1999 2000 2001 2002 2003 2004 2005

�

GMT Hardware schedule

� Milestones / Plans:� 2001 Logic design, ORCA + VHDL Simulation

� Dec 2001 Logic design finished• logic functions defined “up to the last bit”.• chip types, bus widths, LUTs, registers, read-out processing,… defined.

� 2002 VHDL Simulation, Design of FPGA chips� Dec 2002 FPGA design finished� 2003 Production of VME 9U Boards

� 2004/05 Integration tests, production of spare boards



Progress in 2001 & Plans for 2002

� Progress in 2001:� All logic functions defined

• Chip Models selected (mostly Virtex II), Interconnections defined• Design compacted (external RAMs moved into big FPGAs)• 50-page internal GMT design document + drawings

� Functionality improved• DT/CSC cancel-out unit (improved performance in barrel/endcap overlap region)

� Simulation studies• ORCA Simulation extended and improved (calo projection, cancel-out unit, …)• studies to optimize GMT design parameters and performance

� Plans for 2002:� continue VHDL simulation of FPGA chips� VHDL simulation of GMT board� Synthesis / design of FPGAs� in parallel further studies with ORCA



Beam Halo Muon Trigger

�The situation� halo muons are seen by CSC, only (flag indicates halo muon)

� 4 bunch crossings delay between the two endcaps

� read-out will only work correctly in one half of the detector, where halo muon is moving away from interaction point

� do we need matching between the endcaps for alignment?



Beam Halo Muon Trigger

� Possible algorithms (from GMT point of view)A) no matching between endcaps

A1) Change read-out to read CSC data also from 4 bx earlier (if halo trigger)A2) get 2 L1 accepts within 4 bx (can interfere with other triggers)

B) Matching without direction-information• GMT stores all halo muons in pipeline and matches with halo muons 4 bx later• works if we want to trigger only on matched halo muons (both endcaps)

• if we also want to trigger on unmatched halo muons we get double triggers

C) Matching with direction information• we get direction information from CSC: fromIP / toIP• GMT stores toIP halo muons in pipeline and matches with fromIP halo muons

4 bx later

• can trigger on matched and/or unmatched halo muons

�



Simulation:re-processing of Muon 2001 Production

� Monte Carlo production (Pythia 6.152, CMSIM 121)� using Pythia default normalization

� lower pT-cut (p-cut) in forward region (now p > 3.5 GeV/c, in 2000: pT>1.5 GeV/c)

� increased η-range up to in CMSIM(now 5.5, in 2000: 2.5)

� muons in pile-up vetoed� LHC luminosity L = 2x1033 cm-2s-1

� new (Nov 2001): increased statistics

� L1 Trigger simulation (ORCA 5.3.1)� new CSC Trigger Primitives (since ORCA 5.1.2)

� updated CSC Track Finder (since ORCA 5.1.2)� updated Global Muon Trigger (since ORCA 5.1.2)� new with respect to last processing

• DT re-digitized, updates in CSC Trigger and CSC Track Finder

� RPC: without noise and neutral background simulation

Sample Lint / nb-1 Events in luminosity

mu_MB1mu_pt1 0.0247 231k (x1.5) mu_MB1mu_pt4 0.4071 107k (x2) mu_MB1mu_pt10 2.81 41k W_1mu 2856. 43k Z_1mu 2336. 50k mu_MB2mu 0.2935 32k (x3)

background samples – 2001 muon production



threshold / GeV/cµTp

0 10 20 30 40 50 60 70

inte

gra

ted

rat

e / H

z

10-1

1

10

102

103

104

105

106

generated rates

MB pt1 MB pt4MB pt10WZ

Generated rates

~200 Hz in year 2000 production(scaled to L=2x1033)

L=2x1033 cm-2 s-1



(GeV/c)cutTmuon p1 10

Tri

gg

er R

ate

(Hz)

1

10

102

103

104

105

106

|< 2.5ηwhole detector: 0 < |

GenDT + CSCRPCGMT Sep2001 tuningGMT Nov2001 tuning

|< 2.5ηwhole detector: 0 < |

L1 single muon trigger rates samples: pt1, pt4, pt10, W, Z

75 kHz DAQ5.5 kHz @ 12 GeV/cScaled from TDR: 10.6 kHz



L=2x1033 cm-2 s-1



(units)genh0 0.5 1 1.5 2 2.5

Eff

icie

nc

y(%

)

0

20

40

60

80

100

DTBX

CSC

RPC

GMT

(units)genh0 0.5 1 1.5 2 2.5

Eff

icie

nc

y(%

)

0

20

40

60

80

100

DTBX

CSC

RPC

GMT

| (units)trigη|0 0.5 1 1.5 2 2.5

)η=

16 G

eV/c

(kH

z/u

nit

cu

tT

Tri

gg

er R

ate

for

p

0

1

2

3

4

5

6 DT+RPCCSC+RPC

DT Q1DT Q2DT Q3DT Q4

DT Q5DT Q6DT Q7

CSC Q1CSC Q2CSC Q3RPC Q0

RPC Q1RPC Q2RPC Q3Generated

OR

| (units)trigη|0 0.5 1 1.5 2 2.5

)η=

16 G

eV/c

(kH

z/u

nit

cu

tT

Tri

gg

er R

ate

for

p

0

1

2

3

4

5

6 DT+RPCCSC+RPC

DT Q1DT Q2DT Q3DT Q4

DT Q5DT Q6DT Q7

CSC Q1CSC Q2CSC Q3RPC Q0

RPC Q1RPC Q2RPC Q3Generated

new cut

Nov 2001 Re-tuning of GMT algorithm

�

L1

sin

gle

mu

on

tri

gg

er r

ates

(p

T>

16 G

eV/c

) GMT Sep2001 tune

GMT Nov2001 tune

eff = 96.5 %

eff = 96.9 %

(*)efficiency to find muon of any pT in flat pT sample

L1

effi

cien

cy

L=2x1033 cm-2 s-1



L1 di-muon trigger ratessamples: pt1, pt4, pt10, 2mu_pt1, GMT Nov 2001 tune

(GeV/c)cutT,1muon p

0 2 4 6 8 10 12 14 16

(G

eV/c

)cu

tT

,2m

uo

n p

0

2

4

6

8

10

12

14

16

1100 1000

800 600

400 300 200

100

50

1200

trigger rates in Hz

upper threshold

low

er th

resh

old L=2x1033 cm-2 s-1



L1 di-muon trigger rates, pT,2 � 4 GeV/c samples: pt1, pt4, pt10, 2mu_pt1, GMT Nov 2001 tune

(GeV/c)cutT,1muon p

4 6 8 10 12 14 16 18 20

Tri

gg

er R

ate

/ Hz

1

10

102

103

GenDT + CSCCSCRPCGMTGMT from ghosts

from 1 eventµGMT 2 from 2 events in 1 bxµGMT 2

4 GeV/c≥ T,2Di-muon Rates - p

L=2x1033 cm-2 s-1



L1 single & di-muon trigger ratessymmetric di-muon cut, GMT Nov 2001 tune

/ GeV/ccutTSingle muon p

10 12 14 16 18 20 22 24 26 28

GeV

/ccu

tT

Sym

met

ric

di-

mu

on

p

2

4

6

8

10

12

14

6.0 5.0

4.0

3.5

3.0 2.5

2.0

1.5

1.0

L1 single and di-muon trigger rates

7.0

trigger rates in kHz

binning

75kHzDAQ

25kHzDAQ

37.5kHzDAQ

50kHzDAQ

L=2x1033 cm-2 s-1



/ GeV/ccutTSingle muon p

10 12 14 16 18 20 22 24 26 28

GeV

/ccu

tT

up

per

di-

mu

on

p

4

6

8

10

12

14

7.0

6.0

5.0

4.0

3.5 3.0

2.5

2.0

1.5

1.0

L1 single and di-muon trigger rates, lower di-muon cut: 3.0 GeV/c

L1 single & di-muon trigger ratesasymmetric di-muon cut, GMT Nov 2001 tune

trigger rates in kHz

low

er th

resh

old

3 G

eV/c

binning

L=2x1033 cm-2 s-1



Conclusion

� Progress in hardware design as planned� all logic functions defined

• design compacted & improved• new solution with one logic board

� Planned R&D in 2002� VHDL simulation of FPGAs and board� design of FPGAs

� Trigger on halo muons: � GMT can provide matching between endcaps with delay� possible during normal physics running

� Simulation results with 2001 muon production� results with increased statistics for low luminosity scenario� GMT re-tuned to increase efficiency in the overlap region� pT-cut was lower than in last year’s production� improved CSC trigger & GMT can cope with higher background rate

cms l1 global muon trigger update - hephy · hannes sakulin cern/ep l1 global muon trigger update 2...

Documents