csc muon trigger - annual review
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CSC Muon Trigger - Annual Review. Jay Hauser, with many slides from Darin Acosta and Paul Padley Personnel: Professors Darin Acosta (Florida), Robert Cousins (UCLA), Jay Hauser (UCLA), Paul Padley (Rice), Jaybus Roberts (Rice) Postdocs - PowerPoint PPT PresentationTRANSCRIPT
September 21, 2004CMS Annual Review
1CSC Muon Trigger
CSC Muon Trigger - Annual ReviewJay Hauser, with many slides from Darin Acosta and Paul Padley
Personnel: Professors
Darin Acosta (Florida), Robert Cousins (UCLA), Jay Hauser (UCLA), Paul Padley (Rice), Jaybus Roberts (Rice)
Postdocs Sang-Joon Lee (Rice), Holger Stoeck (Florida), Slava Valouev (UCLA), Martin von der Mey (UCLA),
Yangheng Zheng (UCLA) Graduate Students
Khristian Kotov (Florida), Jason Mumford (UCLA), Bobby Scurlock (Florida) Engineers
JK Smith (UCLA), Alex Madorsky (Florida), Mike Matveev (Rice), Alex Tumanov (Rice-software) Collaborating engineers (PNPI)
Victor Golovtsov, Lev Uvarov
Outline: Status of Boards Test Beam 2004 Results Experience and Plans for Production Testing Plans for Integration and Slice Tests Schedule and Milestones
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2CSC Muon Trigger
CSC Muon Trigger Scheme
CSC
CFEBCFEBCFEB CFEB
ALCT1 of 24
CFEB
1 of 2
LVDB
1 of 5
1 of 5
Anode Front-end Board
Cathode Front-end Board
Anode LCT Board
MPC
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
CCBC
ONTROLLER
Peripheral Crate on iron disk (1 of 60)
Trigger Timing & Control
CSC Track-Finder Crate (1)
Trigger Motherboard (9)
DAQ Motherboard (9)Clock Control Board
Optical link
In underground counting room
On detector
Muon Portcard (1)
Trigger Primitives
3-D Track-Finding and Measurement
Sector Processor (12)Muon
Sorter (1)
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3CSC Muon Trigger
On-chamber CSC Trigger Electronics
Comparator ASICs – DONE. Compare pulse heights from
adjacent strips to find position of muon to ½-strip
15000 16-channel ASICS on CFEB boards (OSU)
ALCT Boards – DONE. Finds tracks among anode hits,
stores data for readout 468+spares boards of 3 types
(288-, 384-, 672-channel) Virtex 600E and 1000E FPGAs
CERN/UCLA
CFEB:OSU
UCLA/UF
CSC
CFEBCFEBCFEB CFEB
ALCT1 of 24
CFEB
1 of 2
LVDB
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4CSC Muon Trigger
CSC Peripheral Crates in UXC55
MPC
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
CCB
CONTROLLER
Clock Control Board (CCB)
TRIG Motherboard (TMB)
DAQ Motherboard (DMB)
Muon Port Card (MPC)
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5CSC Muon Trigger
Trigger Motherboard Receives CFEB comparator hits, ALCT stubs, RPC hits. Generates Cathode LCT, matches ALCT with CLCT, outputs LCTs to
backplane, stores data for readout. Passed Nov. ’03 ESR. Built 32 TMB2004 with mezzanine XC2V4000 FPGAs (468 required).
Xilinx XC2V4000Mezzanine board
CFEB Input connectors
UCLA
RAT BoardReceives ALCTAnd RPC data
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Mezzanine card (same as ALCT)
TLK2501 serializers
Optomodules(1.6 Gbit/s)
Muon Port Card
Rice
Sorts up to 18 LCTs from 9 chambers and transmits best 3 via optical links to Track-Finder crate
60 required for CMS operation
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CSC Track-Finder Crate
SR /
SP
SR /
SP
SR /
SP
SR /
SP
SR /
SP
SR /
SP
SR /
SP
SR /
SP
SR /
SP
SR /
SP
SR /
SP
SR /
SP
CC
B
SB
S 6
20 C
ontr
olle
r
Sector Receiver/Processor
Clock and Control Board
Muon Sorter
From MPC (chamber 4)
From MPC (chamber 3)
From MPC (chamber 2)
From MPC (chamber 1B)
From MPC (chamber 1A)
To DAQ
MS
Single Track-Finder Crate Design with 1.6 Gbit/s optical linksCustom 6U GTLP backplane for interconnections
Second generation
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SP2002 Main Board (SR Logic)
PLL patch
Optical Transceivers 15 x 1.6
Gbit/s Links
Front FPGA
TLK2501 Transceiver
Phi Local LUT
Eta Global LUT
Phi Global LUT
SR Logic
Florida
To/from custom GTLP backplane
Mezz card:Xilinx Virtex-2 XC2V4000~800 user I/O
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GTLP backplaneinterface
Virtex-2 mezzanine card (same as SP)
LVDSdriversand SCSI-3connectors
Muon Sorter
Rice
Sorts up to 36 muons from 12 SP’s and transmits best 4 to GMT Only 1 needed in CMS
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CSC Test Beam Studies 2003 and 2004 2003
ALCT and CLCT trigger studies (threshold scans, HV scans, angle scans, rate scans)
Good trigger efficiency and DAQ capability results. Problems with synchronization of MPC-SRSP optical links.
Successful patches to TTC clock stability were found. Results validated peripheral crate trigger electronics prior to ESR.
2004 - ongoing First looks at RPC input to TMB for ghost-busting. Optical link sync. fix (QPLL) validated. Data inputs to SRSP validated. Outputs of SRSP validated. Results validated MPC and SRSP prior to PRR.
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June 25ns Beam Test (Muon Slice Test)
4 CSC chambers 1 RPC chamber 2 peripheral crates Track Finders with full logic, L1A generation, DAQ readout Multiple chambers, crates synchronized QPLL-generated 80 MHz clocking over backplane for MPC
ME 1/1
ME 1/2
ME 2/2
ME 3/2
RE1/2
Peripheral Crate #1 ME1/1+ME1/2
Peripheral Crate #2 ME2/2+ME3/2
RPC Link board Crate
Each has 2 TMB, 1 MPC
SP1 SP2MS
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Sector Processor BX Distribution
LHC-like bunch structure during synchronous running
Trigger rates at X5A during spill Muons: 310 kHz Pions: >100 kHz
48 BX
Some random triggers, mostly @ spill start
Many spills
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Time Alignment of CSC data in Track-Finder
Able to get all trigger data from multiple chambers and crates on same BX (at least for some runs):
Issue with anode timing for this chamber
Run 293
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SP: ORCA vs. Hardware Check
Check logged outputs of SP with ORCA emulation based on inputs
Correlations of track , between 2 stations, and track type agree perfectly
Checked with 150K events
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Track-Finder Beam Test Results Fully operational CSC TF tested with full data format Agreement between the output of the SP with a simulation
based on the logged inputs is 100% Agreement between the recorded trigger primitive data
(TMB) and received SP data is at the level of 99.7%, but worse for some chambers and runs
Same level of agreement as obtained from the Sep.’03 beam test Likely to be due to DAQ issues from peripheral crates (data
corruption from high rates) The SP in conjunction with a specially modified CCB was
able to self-trigger the experiment (including RPC) Muon Sorter winner bits appear to be properly recorded New DT/CSC transition card works
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MPC Status and Production Plans
70 MPC boards will be built and assembled (including spares) 6 boards were built in 2002 Need to make ~20 changes in schematic/layout, add 4-5 small chips to
VME interface. List of changes is being prepared. In-house testing
Will use two crates and run testing patterns from TMBs through MPC to SP Software is under development (including convenient GUI) Burn in 24 hours at 60..70 C then test again (intend to use OSU oven)
Schedule: Oct-Dec 2004: Make schematic/layout changes and build 3 sample boards Oct-Dec 2004: Order all components Jan-Feb 2005: Assemble/Test 3 sample boards
Need to test this sample with 9 TMB’s in the production peripheral crate
March 2005: If OK fabricate the rest (67 boards) Apr-Aug 2005: Assemble and test 67 boards
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SP Production and Test Schedule Schematics for final design modifications completed Routing modifications submitted to vendor, about 2 weeks to complete Production to commence in November:
Will assemble 2 boards first as pre-production prototypes and test before launching full production (12 SR/SP + 4 spares + parts for 3)
Tests of initial samples expected to take 1 month Rest of production completed by Feb.’05
Bench testing of SP production boards completed by Apr.’05: Full-speed internal testing using 256-deep FIFOs on inputs and outputs Optical link loopback testing
Full TF crate system tests with Muon Sorter completed by June ’05 Ready for tests at CERN June ‘05
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CCB Status and Production Plans
70 boards will be built and assembled (including 15% spares) 6 boards were built in spring of 2004, all with TTCrq mezzanines Expect TTCrq mezzanine cards to arrive from CERN by December Need to make ~10 minor changes in schematic/layout. Do not expect to
add or remove any active components on board. In-house testing:
Need just a short chain (TTCvi/vx+CCB+MT) to test the functionality May use small 9U crate and run a program similar to irradiation test Burn in 24 hours at 60..70 C then test again (intend to use OSU oven)
Schedule: Sep-Nov 2004: Make schematic/layout changes and build 3 sample boards Sep-Nov 2004: Order all components December 2004: Assemble/Test 3 sample boards January 2005: If OK fabricate the rest 67 boards Feb–Jun 2005: Assemble and test 67 boards
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MS Status and Production Plans 1 board needed in final system. 4 boards were built in 2003, 3 mother boards are completely
assembled, 2 are bench-tested with mezzanine cards Need more tests with at least 2 SP and/or 12 Muon Tester cards (until
December of 2004) Need to test with the GMT receiver card (never been done before).
This fall or early next year? Plan to complete all tests by summer 2005. Based on results, decide if the PCB should be rebuilt (currently have 5-
6 minor PCB fixes).
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Plans for Integration and Slice Tests
Integration with HCAL at H2 starts in 2 weeks (October) Last planned test beam time (ever?)
1/05-6/05? Slice Test on surface at SX5 Frank Geurts is our resident Slice Test coordinator Use 2 or 3 full CSC peripheral crates, covering 2 stations x 60o Schedule depends on services (LV, HV, readout room,…) at SX5 Scope depends on the schedule of central DAQ group
9/05 Commissioning begins in UX5 Integration with CMS-wide systems important for Track Finder: Slow
controls (downloading), database, connection to Global Muon Trigger, software framework, time synchronization studies
1/1/07 Commissioning ends at UX5
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CSC Trigger FY03-05 L2,3 Milestones - I
Finish Proto. 2 Test Finish MPC Proto. 2 Test Finish SR/SP Proto. Test Finish Backplane Proto. 2 Test Finish CCC Proto. 3 Test Finish Sorter Proto. Test
Current10/30/04 conservative10/30/04 full-crate test10/30/0410/30/0410/30/0410/30/04 GMT integration?
Previous (last yr AR)2/28/049/30/031/30/042/28/04√ 2/28/04 GMT integration?
Finish Final Design Finish MPC Final Design Finish SR/SP Final Design Finish Backplane Final Design Finish CCC Final Design Finish Sorter Final Design
Current12/30/04 conservative12/30/0410/30/0410/30/0411/30/0412/30/04 GMT integration?
Previous (last yr AR)7/30/043/31/047/30/047/30/047/30/047/30/04
Begin Production Begin MPC Production Begin SR/SP Production Begin Backplane Production Begin CCC Production Begin Sorter Production
Current11/1/04 Parts ordered10/1/0411/1/0411/1/049/1/0410/1/04
Previous (last yr AR)8/1/044/1/048/1/048/1/048/1/048/1/04
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CSC Trigger FY03-05 L2,3 Milestones - II
Finish Production Finish MPC Production Finish SR/SP Production Finish Backplane Production Finish CCC Production Finish Sorter Production
Begin Installation Begin MPC Installation Begin SR/SP Installation Begin Backplane Installation Begin CCC Installation Begin Sorter Installation
Finish Installation Finish MPC Installation Finish SR/SP Installation Finish Backplane Installation Finish CCC Installation Finish Sorter Installation
Previous3/31/053/31/053/31/053/31/053/31/053/31/05
4/1/054/1/054/1/054/1/054/1/054/1/05
5/1/055/1/055/1/055/1/055/1/055/1/05
Current8/30/058/30/05 Partial by 5/30/054/30/054/30/056/30/05 partial by 5/30/053/31/05
6/1/05 at Bldg. 904, SX56/1/05 at SX5, Bldg. 904?6/1/05 at Bldg. 9046/1/05 at Bldg. 9046/1/05 at Bldg. 9046/1/05 at Bldg. 904
2/1/06 occupancy USC559/1/05 at SX52/1/06 occupancy USC552/1/06 occupancy USC552/1/06 occupancy USC55 2/1/06 occupancy USC55
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CSC Trigger FY03-05 L2,3 Milestones - III
Begin System Tests Begin MPC System Tests Begin SR/SP System Tests Begin Backplane System Tests Begin CCC System Tests Begin Sorter System Tests
Finish System Tests Finish MPC System Tests Finish SR/SP System Tests Finish Backplane System Tests Finish CCC System Tests Finish Sorter System Tests
Previous6/1/056/1/056/1/056/1/056/1/056/1/05
9/30/059/30/059/30/059/30/059/30/059/30/05
Current6/1/05 at Bldg. 9046/1/056/1/056/1/056/1/056/1/05
5/30/06 at USC555/30/06 at USC555/30/06 at USC55 5/30/06 at USC55 5/30/06 at USC55 5/30/06 at USC55
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Current Status of CSC Trigger Elements – Quick Summary
CSC on-chamber: DONE. Endcap peripheral crate: in or nearing production
TMB Trigger Motherboard – in production, 32 out of 468 built MPC Muon Port Card – ready for production CCB Clock & Control Board – ready for production
Track Finder crate in counting house: nearing production SRSP Sector Processor/Receiver – nearly ready for production CSC Muon Sorter – prototype=final board? Backplane – nearly ready for production
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CSC Triggering on Day 0 Synchronization:
Unclear whether cosmic muons will be useful underground. Anode and cathode clocks synchronized for communications by
programmed front-end pulse injection and other techniques such as CRC checks.
Fine (2ns step) delay of anode data needs colliding beams and LHC clock. A few seconds of collisions should suffice, analysis time=total time.
Need several settings per ALCT since TOF etc vary. Global CSC data alignment accomplished by comparing data to LHC BX
gaps. May take several hours. Local or global DAQ okay. Chamber alignment and Track Finder coincidences:
Start with “open trigger”, safe mode, and run Track Finding algorithm & check
Open trigger = 1-3 stations per 60o sector in coincidence Cross-checks:
Chamber level: DAQ versus Trigger paths Chamber level: RPC versus CSC paths. Physics level: e.g. high PT jet triggers yield some punchthrough, decay
muons
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Conclusions The CSC electronics are in very good shape:
Test beam showed that the entire chain of CSC trigger electronics work very well together under “battle conditions”
Production starts soon for Track Finder (MPC, SP) boards Final prototypes are being tweaked for minor issues.
Plenty of work ahead on the software side for calibration, synchronization etc.
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Backup Slides to Follow
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25 ns Structured Beam LHC-like bunch structure during
synchronous running
Trigger rates at X5A during spill Muons: 310 kHz Pions: >100 kHz
CSC readout system is designed for a L1A*LCT rate at LHC design luminosity of order 5 kHz
924 BX (sometimes)
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First DT/CSC Integration Tests
DT TF transition card CSC TF transition card
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DT/CSC Transition Card Test In June ‘04 we tested a new
DT/CSC transition card for the Track-Finder
New design solves connector space problem
Tester board allows loopback test without DT Track-Finder
Data pumped from input FIFO to output FIFO on SP
Data test succeeded, except for 1 broken backplane pin
Next step: Second integration test with DT
TF (Oct.’04 or later)
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SP2002 Track-Finder Logic
Xilinx Virtex-2 XC2V4000~800 user I/O
Track-Finding logic operates at 40 MHz
Frequency of track stub data from optical links
About 50% of chip resources (LUTs) used
SP2002 mezzanine card
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Test Beam 2004 DAQ Configuration
DMB/TMBMPCCCB
Peripheral Crate(s)
data to BigPhys
DDU(CCB)
(FED Crate)
XDAQWIN
CFEB
ALCT
SPCCB
TrackFinder Crate
Run Control
VME
Local DAQ PC
Local DAQ PC
CFEB
ALCT
CFEB
ALCT
CFEB
ALCT
Configuration commands distributed via XDAQ. Event-building tested
Raw file
Raw file
“geurts1”
“acosta1”
ddu???.dat.bin orRunNum???Evs*.bin
SP_DDU_DAQ_run????.dat
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Interface Tests MPC to SR/SP
Validated with optical link tests on bench and at beam tests Two MPCs (two crates) to SR/SP demonstrated @ beam test ‘04
SR/SP to Muon Sorter Test Data successfully sent from SP to Muon Sorter on bench and
received properly. Read-back of winner bits also correct. Tested 10/12 slots on custom GTLP backplane
Tested at beam test ’04, read back of winner bits OK Clock and Control Board (TTC interface)
Both CCB2001 and CCB2004 (with TTCRq) tested and work with SR/SP
DT/CSC Data Exchange Test Demonstrated to work during Sept’03 in both directions, with only a
few minor problems with swapped bits, connectors, and dead chips New transition card designed and tested in loop-back mode
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End of Backup Slides