closed-form critical conditions of subharmonic oscillations for buck converters

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  • IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 60, NO. 7, JULY 2013 1967

    Closed-Form Critical Conditions of SubharmonicOscillations for Buck Converters

    Chung-Chieh Fang

    AbstractBased on a general critical condition of subharmonicoscillation in terms of the loop gain, many closed-form critical con-ditions for various control schemes in terms of converter param-eters are derived. Some previously known critical conditions be-come special cases in the generalized framework. Given an arbi-trary control scheme, a systematic procedure is proposed to de-rive the critical condition for that control scheme. Different controlschemes share similar forms of critical conditions. For example,both control and proportional voltage mode control have thesame form of critical condition. A peculiar phenomenon in averagecurrent mode control where subharmonic oscillation occurs in awindow value of pole can be explained by the derived critical con-dition. A ripple amplitude index to predict subharmonic oscilla-tion proposed in the past research has limited application and isshown invalid for a converter with a large pole comparable to theswitching frequency.

    Index TermsCritical condition, DC-DCpower conversion, har-monic balance, instability, subharmonic oscillation.

    I. INTRODUCTION

    C RITICAL conditions of subharmonic oscillation havebeen reported for some control schemes: (peak) currentmode control (CMC) [1], average CMC (ACMC) [2], voltagemode control (VMC) without considering the effect of equiva-lent series resistance (ESR) [3], [4], and control [5]. Theseconditions are generally obtained case by case.In [6], subharmonic oscillation is analyzed in a nonlinear

    system perspective, and the critical condition is obtained sys-tematically. Similar analysis is applied to variable-switching-frequency buck converter [7]. This paper continues to answersimilar questions for the fixed frequency case:1) There exists a peculiar phenomenon in ACMC such thatsubharmonic oscillation occurs in a window value of pole[8]. Is there a general theory to explain this phenomenon?Does it also exist in other cases?

    2) It is hypothesized in [3], [4] that the signal ripple ampli-tude can predict the occurrence of subharmonic oscillation.Does it have limited application only in some particularcases?

    3) Some VMC and CMC control schemes may seem dif-ferent, but do they share the same or similar form of criticalcondition?

    4) Type-II or type-III compensators are popular in industry.How to obtain the associated critical conditions?

    Manuscript received June 01, 2012; revised September 11, 2012; acceptedOctober 17, 2012. Date of publication January 21, 2013; date of current versionJune 24, 2013. This paper was recommended by Associate Editor T.-J. P. Liang.The author is with Sunplus Technology, Hsinchu 300, Taiwan (e-mail:

    fangcc3@yahoo.com).Color versions of one or more of the figures in this paper are available online

    at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TCSI.2012.2230498

    Fig. 1. A VMC buck converter with a compensator .

    By applying harmonic balance [6], [9][11], many new criticalconditions for particular control schemes are obtained.The remainder of the paper is organized as follows. A unified

    VMC/CMC switching model and harmonic balance analysis areapplied in Sections II and III. Section IV applies the analysis tovarious control schemes. Section V focuses on a case occurringfrequently in industry. Conclusions are collected in Section VI.

    II. UNIFIED VMC/CMC SWITCHING MODEL

    Consider a VMC buck converter shown in Fig. 1, whereis the source voltage, is the diode voltage, is the outputvoltage, is the reference voltage, is the feedback signal,and is the compensator transfer func-tion. Denote the cycle period as , the switching frequency as

    and let . The sawtooth signal in VMC andthe compensating ramp in CMC is modeled [9], [12] as the sameramp signal (varying from to ). Denote the ramp am-plitude as and the ramp slope as .Let the ESR be . Let . For , .Let the dc resistance of the inductor be . From [1], the powerstage -to- transfer function is

    (1)

    For CMC, a control signal controls the (peak) inductor cur-rent . Let , then . Thepower stage -to- transfer function is

    (2)

    Let . Since is a square wave, foreither VMC or CMC, the buck converter can be modeled as aswitching model in Fig. 2, where the offset of is implicitlyadjusted by . The square-wave generator has a gain ,and the loop gain is . An equivalent nor-malized model for Fig. 2 is shown in Fig. 3.

    1549-8328/$31.00 2013 IEEE

  • 1968 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 60, NO. 7, JULY 2013

    Fig. 2. Unified VMC/CMC switching model.

    III. CRITICAL CONDITION IN L-PLOT OR S-PLOT

    The critical condition based on harmonic balance [6],[9][11] is briefly reviewed. Define an F-transform ofas

    It is a function of many converter parameters. Define thisfunction as an L-plot . For , the loop gain

    , then define an S-plot (validfor ) as . From [6], the critical conditionis

    (3)

    The S-plot shows the minimum ramp slope to stabilize the con-verter. For , and the L-plot also predictsthe minimum ramp slope. Generally, the region with or

    is stable. The condition (3) is for trailing-edge mod-ulation (TEM) [9]. For leading-edge modulation (LEM, lesscommon in practice), as proved in [13], the critical conditionrequires replacing by in (3). This paper focuses onTEM only, except in Example 2.Let and be the pole and zero of , respectively. Let

    and . Starting from a simplest case, let. From [6],

    (4)

    Expand by Taylor series , where, and

    by the LHospitals rule. A plot ofis shown in Fig. 4, where for

    and . The right straight-line edge in Fig. 4 is.

    Letbe a correction term. A plot of is shown in

    Fig. 5. For , . For , ,and , linearly proportional to .Based on partial fraction decomposition, the F-transforms of

    typical loop gains are shown in Table I, each containing partialterms of . Once the high-frequency form of is ob-tained, the critical condition is readily obtained from Table I.This technique is applied next to various control schemes.

    Fig. 3. An equivalent normalized switching model.

    Fig. 4. Plot of for case .

    Fig. 5. Plot of the correction term .

    TABLE IF-TRANSFORM OF TYPICAL LOOP GAIN

  • FANG: CLOSED-FORM CRITICAL CONDITIONS OF SUBHARMONIC OSCILLATIONS FOR BUCK CONVERTERS 1969

    IV. APPLICATIONS TO VARIOUS CMC/VMC SCHEMES

    A. Peak CMC: CaseFrom (2), at high frequency, , and

    , which is of case and it leads to the critical condi-tion [6], , or equivalently,

    (5)

    With no ramp , the critical point is .

    B. ACMC With PI Compensator: CaseHere, the inductor current is fed back through a resistor

    and a PI compensator , then

    (6)

    which is of case . From Table I, the critical condition is

    (7)

    agreed with [2, Eq. 4.6]. For , from (7), the ramp sloperequired to avoid the subharmonic oscillation is

    (8)

    which is similar to (5) for peak CMC.

    C. VMC With PI Compensator and : CaseUsing the above PI compensator,

    (9)

    which is of case with . From Table I, the criticalcondition in terms of L-plot is

    (10)

    For , case is close to (a special case of ). For, using is more accurate than using [7].

    Example 1: Consider a VMC PI buck converter with, , , ,, , , and .

    This is an counter-example of the ripple index hypothesis [3],which expects occurrence of subharmonic oscillation for any. The L-plot (Fig. 6) shows that subharmonic oscillation does

    not occur for any . The converter is stable. This is confirmedby the sampled-data analysis, which shows three stable polesaround 0.99, 0.99 and 0. Here, , which explains theinaccuracy of the ripple index. As a side note, if, a slow-scale instability occurs with two unstable poles at

    , also not predicted by the slow-scale stability indexproposed in [3].

    D. PVMC: Four Possible Cases , , , andIn proportional VMC (PVMC), the voltage loop has a gain. One has and . Four cases are

    analyzed to see the effects of and on the stability.

    Fig. 6. L-plot based on (10) in solid line shows no occurrence of subharmonicoscillation (due to ). In contrast, the ripple index [3] (dashed line) wronglypredicts an occurrence of subharmonic oscillation.

    1) General PVMC, Case : From (1),

    (11)

    which is of case with and. From Table I, the critical condition is

    (12)

    Other PVMC critical conditions are special cases of (12).For , . Case becomes , and (12) becomes

    (13)The critical point is denoted with a star superscript. Asdecreases, increases, and increases according to (13).Example 2. (Small Leads to Large .): Consider a PVMC

    LEM buck converter [14]: , ,, , , and . The switching

    condition or leads to

    (14)

    which is the familiar condition if . Theplots of (13), with replaced by for LEM, are shown inFig. 7. The intersection of (13) and (14) leads to .Decrease from 25 to 5. The plots of (13) for 25 and

    20 are close to each other because is small. Each intersectswith (14) around . For , becomessignificant. As decreases, increases, agreed with [14].2) PVMC With and , Case : For(with large , and small and ), . Case

    becomes , and (12) becomes

    (15)The term with can be ignored only if . Notethat such a term is also included in (5) and (8) for CMC.

  • 1970 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 60, NO. 7, JULY 2013

    Fig. 7. The plot of (13) (solid line) for , 20, 15, 10, and 5. Its intersec-tion with (14) (dashed line) is . As decreases, increases.

    3) Control, Case , Same as PVMC: As reported in[6], (15) for PVMC is applicable to the const

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