clic_ild vertex detector modules and s tave layout

mini workshop on engineering aspects of the CLIC vertex detectors

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CLIC_ILD vertex detector modules and stave Layout

Mathieu Benoit

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Introduction• A more detailed description of the vertex detector layout is needed to drive the

R&D ongoing on : – Sensor and modules – Cooling studies– Signal and power distribution– Mechanical support

• Module dimensions are driven by Front-End and Sensor production capabilities – Chip has a maximum die size (2.2 x 2.2cm2)– Sensor has maximum length

• Stave layout is driven by : – Need for hermeticity – Module size – Occupancy in the layers (fixed radius)– Lorentz angle – Material budget

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MODULE LAYOUT

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Module Layout• Module dimensions are

constrained by the size of the front-end– We suppose 512x512 pixel Timepix-like

chips

– 20x20 um pixel pitch

– Modules per ladder must be an odd number (middle of a module at Z=IP)

– Following CLIC_ILD CDR simulation layout, Ladder Length = 26.0 cm• L=NbChip*(pitch) + (NbChip -

1)*ChipGap + 2*GR• 5x(1.024)+4*0,005+2*0.001= 5.160 cm• 5x5.16cm = 25.8cm

6’’ Wafer, divided in squares of 1.029 x 1.029 cm2

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Module Layout (2)

We try to stay as close as possible to the CLIC_ILD CDR layout, whith 2 different type of modules, for layer 1+2, and layer 3+4+5+6, located at fixed radius

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Physics and Detectors CDR ,Lucie LINSSEN, Akiya MIYAMOTO, Marcel STANITZKI, Harry WEERTS

https://edms.cern.ch/file/1180032/4/cliccdr_PhysicsDetectors_onlineversion.pdf

https://edms.cern.ch/file/1180032/4/cliccdr_PhysicsDetectors_onlineversion.pdf


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Module Layout (3)Type 1x5 chipsModule Parameter valuepixel per chip (X) 512pixel per chip (Y) 512pixel pitch (mm) 0,02

chip per module (x) 5

chip per module (y) 1Edge Width (mm) 0,1

Interchip distance (mm) 0,05Length (mm) 51,6Width (mm) 10,44

Type 2*5 chipsModule Parameter valuepixel per chip (X) 512pixel per chip (Y) 512pixel pitch (mm) 0,02chip per module (x) 5chip per module (y) 2Edge Width (mm) 0,1Interchip distance (mm) 0,05Length (mm) 51,6Width (mm) 20,73

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Module Layout (4)• Inter-Chip regions

45x45 um pixels at the corners

20x45um pixel between set of 2 chips

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Module Layout (5)

FE

sensor

FE

Bonding

• Interconnection between chips would make use of the TSV technology to bring read-out and power pads to the backside of the chip

• DC/DC Converter storage capacitor can be distributed on the back of the chip on the Redistribution Layer (RDL)

beam

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RDLTSVPads


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BARREL LAYOUT

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Barrels layout

CDR layout has been selected taking into account slightly wider module than what is proposed here. We need to modify slightly the radius to keep hermeticity, number of ladders (set of modules)

Not mentionned here is the tilt angle of the modules with regard to the vertex radius, usually set by lorentz angle

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The CLIC ILD CDR Geometry for the CDR Monte Carlo Mass Production, A. Munnich, A. Sailer

https://edms.cern.ch/document/1134612




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Lorentz angle• It is a usual practice in vertex design to tilt modules with

regard to the particle direction to account for Lorentz angle and minimize cluster size

B= 5THolesElectronsDrift

EReco hit

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Lorentz angle

B= 5THolesElectronsDrift

E

Reco hit

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Lorentz angle in CLIC_ILD• Lorentz angle depends on mobility which depends on Electric

field and eventually on dopant concentration

• In a 50um 10kOhmcm p-type wafer, 10V bias, E≈[1600,2700]V/cm– Vary with resistivity, bias voltage

• In a planar sensor, E is proportional to V applied– V applied is proportional to thickness2 (Full depletion voltage)– For thin sensor, at full depletion voltage, Electric field is very low– To be investigated : How much over Full depletion can we apply voltage

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Lorentz angle in CLIC_ILD

10V 80V (?)

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Lorentz angle in CLIC_ILD

10V 80V (?)

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Lorentz angle in CLIC_ILD (summary)

• Following the sensor specification, lorentz angle will be large in CLIC_ILD

• It is not possible to specify at this point very precisely the characteristics of the sensor to be used – Unknown resistivity, thickness– Possible operation voltage

• Best strategy is to deal with this at the hit reconstruction level, by taking into account measured angle (cosmics ? Runs w/o B Field?)

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Barrel layout (layer 1+2)

• CLIC_ILD MC Model Layer 1+2 are octodecagons (18)– Radius = 31.0, 32.87 mm– Length = 260 mm (25 chips + 2 mm tolerance)– Width (ladder) = 11.5 mm (all considered active)

• Real Module and Layer (assuming 5x1 modules)– Radius = ??– Length 258 mm (5x 5x1 chip modules)– Width (ladder) = 10.44 mm (10,24 mm active)

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• To ensure hermeticity, layer 1+2 need to be placed closer to IP than MC model– Option 1:

• Radius(layer 1) = 29 mm (31mm before)• Radius(layer 2) =30.87mm (32.87mm before) • To avoid volume overlap, slightly tilt the ladders (here 1.5°)

– Option 2: • Tilt sensors by lorentz angle (ex: 15 deg)• Add 1-2 ladders (here , 2-> Icosagon !)• Move back to larger radius (here 31.221 mm)

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Barrel layout (layer1+2, option 1)

An option to option 1: Shifting layer 2 vs layer 1 (here 1mm), ladder per ladder to avoid overlapping gaps

Single hitsDouble layer, holding on the same mechanical structure not shown here

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Single hits

In this option we maintain the larger radius, but increase overlap, further optimisation is needed

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• CLIC_ILD MC Model Layer 3+4 are tridecagons (13)– Radius = 44.0, 45.87 mm– Length = 260 mm (25 chips + 2 mm tolerance)– Width (ladder) = 22.5 mm (all considered active)

• Real Module and Layer (assuming 5x2 modules)– Radius = ??– Length 258 mm (5x 5x2 chip modules)– Width (ladder) = 20.73 mm (20.53 mm active)

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• Radius(layer 1) = 41.65 mm (44 mm before)• Radius(layer 2) = 43.516 mm (45.87 mm before) • To avoid volume overlap, slightly tilt the ladders (here 1.5°)

– Option 2: • Tilt sensors by lorentz angle (ex: 15 deg)• Add 1-2 ladders (here , 2-> pentadecagon !)• Move back to larger radius (here 45.647 mm)

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Single hits

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• CLIC_ILD MC Model Layer 3+4 are heptadecagons (17)– Radius = 58.0, 59.87 mm– Length = 260 mm (25 chips + 2 mm tolerance)– Width (ladder) = 22.5 mm (all considered active)

• Real Module and Layer (assuming 5x2 modules)– Radius = ??– Length 258 mm (5x 5x2 chip modules)– Width (ladder) = 20.73 mm (20.53 mm active)

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• Radius(layer 1) = 54.91 mm (58 mm before)• Radius(layer 2) = 56.782mm (59.87 mm before) • To avoid volume overlap, slightly tilt the ladders (here 1.5°)

– Option 2: • Tilt sensors by lorentz angle (ex: 15 deg)• Add 1-2 ladders (here , 2-> enneadecagon !)• Move back to larger radius (here 58.418 mm)

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Barrel layout (layer 5+6, option 1)

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Barrel layout (layer 5+6, option 2)

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Full Barrel (option 1)

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SiD like design • Symmetric layout• Unregular hit distance to IP


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DISK LAYOUT

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Disk layout

Wheels in CLIC_ILD CDR layout consist of 3 identical double-layers

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The CLIC ILD CDR Geometry for the CDR Monte Carlo Mass Production, A. Munnich, A. Sailer





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Wheel layout (2)• The wheel active area spans

from R=33 to R=102mm H=69 mm in CLIC_ILD CDR layout

• To use module like building block, the best option is 6x2 modules – H=61.89 mm < CDR layout– Dimension could be adjusted a

bit making use of elongated pixels

Type 2*6 chipsModule Parameter valuepixel per chip (X) 512pixel per chip (Y) 512pixel pitch (mm) 0,02chip per module (x) 6chip per module (y) 2Edge Width (mm) 0,1Interchip distance (mm) 0,05Length (mm) 61,89Width (mm) 20,73

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Wheel layout, the quadrature of the circle (option 1)

• Module based layout • 15 modules per layer, 30 for a double

layer

• Each module tilted by 24° with regard to previous layer

• Each layer tilted by 12° with regard to other part of double layers

• Each module tilted by 2° with regard to radius to allow overlap

• Possibility to distribute modules along Z to reproduce the helicoidal structure favored for cooling

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Wheel Layout (option 2)

Source : http://www.micronsemiconductor.co.uk/pdf/cat.pdf

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Conclusion• A set of specifications for the modules driven by the acheivable Front-end

and sensor die size has been established– Inactive region must be taken into account in the layout of the ladders, barrel and

disks– Hermeticity of the double layer must be minimized – Lorentz angle in the sensor should be taken into account in the layout of the barrel– Possibility of cableless power distribution and readout should be explored

• Stitching between Front-End and between modules (TSV,RDL)• Integration of components (capacitor, resistance) on Front-End backside

• Disk layout represent a challenge in terms of material budget, hermeticity and mechanical support– Radial distribution of modules (option 1) is far from the ideal in terms of hermeticity

and material budget– Disk like modules could be a solution (one module per wafer, assembly challenging)

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clic_ild vertex detector modules and s tave layout

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