classes of logic circuits sequential mos logicese570/fall2020/handouts/lec... · 2020. 11. 9. ·...

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ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Lec 18: November 9, 2020Sequential Logic, Timing Hazard, Dynamic

Logic

Penn ESE 570 Fall 2020 – Khanna

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Lecture Outline

! Sequential Logic! Timing hazards! Dynamic Logic

2Penn ESE 570 Fall 2020 – Khanna

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Sequential MOS Logic


3

Classes of Logic Circuits

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Combinational Circuits: a. Current Output(s) depend ONLY on Current Inputs.b. Suited to problems that can be solved using truth tables.

Sequential Circuits or State Machines: a. Current Output(s) depend on Current Inputs and Past Inputs via State(s).b. Suited to problems that are solved by completing several steps using current inputs and past outputs in a specific order or a sequential manner.


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Synchronous Discipline

! Add state elements (registers, latches)! Compute

" From state elements" Through combinational logic" To new values for state elements


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Static Bistable Sequential Circuits

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Basic Cross-coupled Inverter

pair

Q

Q


0 1

10

6

2


7


pair

Q

Q


Vi1

Vo1

Vi2

Vo2

7


8


pair

Q

Q


Vo1

Vo2

Vi1=Vo2Vo1=Vi2

Vi1

Vi2

8


9


pair

Q

Q


Vo1

Vi1=Vo2Vo1=Vi2

Vi1V

o2

Vi2

9


10


pair

Q

Q


Vi1, Vo2

Vo1, Vi2

Vi1=Vo2Vo1=Vi2

10


11


pair

Q

Q


Vi1, Vo2

Vo1, Vi2

Vi1=Vo2Vo1=Vi2

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Basic Bistable Cross-coupled Inverter Pair has no means to apply input(s) to change the circuit's State.


pairQ

Q

VOH = VDD

VOL = 0

maintain stable state.STATIC: VDD and GND are required to maintain a stable state.



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3

Basic Sequential Circuits (Cells)

! Latches! Registers


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Latch

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Q =CLK ⋅Q+CLK ⋅ In

! Level-sensitive device! Positive Latch

" Output follows input if CLK high

! Negative Latch" Output follows input if

CLK low


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Register

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! Edge-triggered storage element

! Positive edge-triggered" Input sampled on

rising CLK edge

! Negative edge-triggered" Input sampled on

falling CLK edge


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Shift Register

! How do you make a shift register out of latches?

16Penn ESE 570 Fall 2020 - Khanna

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Positive-Edge Triggered Register

! Build register from pair of positive latches! What happens when f0 is high?! What happens when f1 is high?


QM

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! Build register from pair of positive latches


QM

QM

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4


! Build register from pair of positive latches! What could go wrong if clocks overlap?


QM

QM

19


! Build register from pair of positive latches! Control with non-overlapping clocks


QM

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Non-overlapping Clocks

! Play with in Cadence" Will need for project 2

Penn ESE 570 Fall 2020 - Khanna 21

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Latch

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Q =CLK ⋅Q+CLK ⋅ In

! Level-sensitive device! Positive Latch

" Output follows input if CLK high

! Negative Latch" Output follows input if

CLK low


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QQ

D

CKCK

CK

CK

Static CMOS TG D-LATCH


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Static CMOS TG D-LATCH – 8 Transistors

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8 Transistors


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5

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Static CMOS TG D-LATCH

When CK = 1 output Q = D, and tracks D until CK = 0, the D-Latch is referred to positive level triggered.

When CK → 1 to 0, the Q = D is captured, held (or stored) in the Latch.


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D-LATCH Timing Requirements


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Timing Hazards


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Clocking Discipline

! Follow discipline of combinational logic broken by registers

! Compute " From state elements" Through combinational logic" To new values for state elements

! As long as clock cycle long enough," Will get correct behavior


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Latch Timing Issues


Worst case delays

Minimum delays

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Latch Timing Issues


! tsu = time data (D) must be valid before CLK edge! tplogic = worst case propagation delay of logic! tc-p = worst case propagation delay of latch

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Latch Timing Issues


! tcdregister = minimum propagation delay of latch! tcdlogic = minimum propagation delay of logic! thold = time data (D) must stay valid after CLK edge

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Timing Example


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Timing Example


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Timing Example


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Timing Example


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Clocking Highlights

! Clock discipline simplifies logic composition" Abstracts many internal timing details" Just concerned with making clock period long enough

! Breaking logic up with registers allows circuit to run at high frequency " Inputs decoupled from outputs

! Design Discipline – keeping data stable around clock edge" Setup, hold time – determined by latch circuit" Worst case and minimum Clk#Q delay for latch


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7

System Timing Constraints


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Latch Timing Metrics


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Mux Based Latches

! Change the stored value by cutting the feedback loop


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PassT Implementation of Mux


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Tx Gate Implementation of Mux


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Controller/Controlled ET Flip Flop


ControllerControlled

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Controller/Controlled Implementation


Controller Controlled

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Controller/Controlled Implementation


Controller Controlled

Controller transparentControlled hold

Controller hold

Controlled transparent

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Timing Properties

! Assume propagation delays are tpd_inv and tpd_tx, and that the inverter delay to derive !clk is 0

! Set-up time - time before rising edge of clk that D must be valid" tsu = 3 * tpd_inv + tpd_tx

! Propagation delay - time for QM to reach Q" tc-q = tpd_inv + tpd_tx

! Hold time - time D must be stable after rising edge of clk" thold = zero


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Setup Time Simulation


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Setup Time Simulation


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Dynamic Logic


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9

Logic Comparison Overview


DYNAMIC LOGIC GATES: valid logic level are not steady-state op points and depend on temporary storage of charge on parasitic node capacitances. Outputs are generated in response to input voltage levels and a clock. Requires periodic updating or refresh.

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Logic Comparison Overview


DYNAMIC LOGIC GATES: valid logic level are not steady-state op points and depend on temporary storage of charge on parasitic node capacitances. Outputs are generated in response to input voltage levels and a clock. Requires periodic updating or refresh.

CSM1

BL

WL

CBL

WL

X

BL

VDD-VT

VDD/2

VDD

GND

Write "1" Read "1"

sensingVDD/2

DV VBL VPRE– VBIT VPRE–( )CS

CS CBL+------------------------= =

Write: CS is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitance

Voltage swing is small; typically around 250 mV.

bit bit_b

N1

N2P1

A

P2

N3

N4

A_b

word

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Comparison of Logic Implementations

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Y

Ratioed


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52

Y

Ratioed


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53

Y

Ratioed


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54

Y

Ratioed

1

11

VDDmore robust


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10

Dynamic CMOS Precharge

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VDD

A

CK

Mp

Me

Z


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Dynamic CMOS Precharge

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Z

Z

of C is complete


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Dynamic (Clocked) Logic: Example

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CK = 0 => Z = ?CK = 1 => Z = ?


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Comparison of Static and Dynamic Logic

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ADVANTAGES ?

DISADVANTAGES ?


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59

60



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Cascaded Dynamic Logic


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Domino Logic


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Requirements

! Single transition" Once transitioned, it is done # like domino falling

! All inputs at 0 during precharge" ‘Outputs’ pre-charged to 1 then inverted to 0

" I.e. Inputs are pre-charge to 0

! Non-inverting gates


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12

Cascaded Domino CMOS Logic Gates


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propagating


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propagating


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Ideas

! Synchronize circuits" to external events (eg. Clk)" disciplined reuse of circuitry

! Leads to clocked circuit discipline" Uses state holding element (eg. Latches and registers)" Prevents

" Timing assumptions" (More) complex reasoning about all possible timings

! Dynamic/clocked logic" Only build/drive one pulldown network" Fast transition propagation" Domino Logic allows for cascading


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Admin

! Proj 1 out" Due 11/15

! 2 baseline designs (CMOS and pass)" Pick one to optimize and layout

! Proj 1 doesn’t require the output flip flop" will need it eventually for proj 2 so you can add it if you

want and we can give feedback


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classes of logic circuits sequential mos logicese570/fall2020/handouts/lec... · 2020. 11. 9. ·...

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