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Circuit solutions towards 100 Mcps per pixel in pixel

detectors for X-rays

11th International Meeting on Front-End Electronics

22 May 2018, Jouvence, Quebec province, Canada

Authors: Kłeczek R., Gryboś P., Szczygieł R.

Corresponding author: [email protected]

Circuit solutions towards 100 Mcps per pixel in pixel detectors

Agenda of the presentation

Agenda:

1) General considerations:

• pulse pile-up,

• charge sharing,

• ballistic deficit,

• dead time behaviour models of readout electronics.

2) Photon counting pixel readout ASICs.

3) PXF40 prototype ASIC:

• overview,

• implementation details,

• theoretical considerations,

• measurements results.

5) Conclusions.

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4) Strategies for boosting count-rate performance:

• instant retrigger technology,

• pile-up trigger method,

• counting and integrating in a pixel,

• reset functionality,

• cross detection method,

• new technologies.

General considerationsPhoton counting detectors at high X-ray flux

How to deal with high X-ray flux?

Reduction of a single SPC pixel

dimensions to handle a lower intensitity

of incoming photons

Faster signal processing

(shorter peaking time/pulse width)

How to deal with pulse pile-up?

Charge sharingNoise increase and loss of charge-to-

conversion gain

3 / 27

General considerationsPulse pile-up

Due to the stochastic nature of the photon impinging to a detector it may happen that the signals in the

processing channel due to two or more consecutive photons overlap, what is called a pulse pile-up effect.

Energy-resolving photon counting pixel with three energy bins with pulse pile-up – Lee D., 2017 [1].

In case of the pulse pile-up a photon-counting pixel is unable to detect each photon, what results in a loss of

counts - dead time losses.

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In case of the pulse pile-up an energy-resolved photon-counting pixel is unable to properly assign photon energy

to the correct bin, what results in a distortion of the pulse amplitude measurements.

General considerationsCharge sharing

Charge sharing occurs when charge generated by a photon

in the vicinity of the pixel’s border is collected by two or

more different detector electrodes and processed in part by

two or more independent pixels.

5 / 27

Simulated spectra at different pixel pitches for 80 keV photons

detected on a 2mm thick CdTe sensor (-800 V). 100e- r.m.s. noise

in the channel – Ballabriga R., 2016 [2].

The fraction of a single pixel affected by the charge sharing effect in terms of the

pixel pitch.

High X-ray flux degrades the energy spectrum,

because larger pixels suffer from pulse pile-up,

while smaller pixels from charge sharing effect.

The charge sharing effect.

General considerationsBallistic deficit

The fundamental limitation of count-rate

performance stems from photon detection speed of

a detector, which is related to charge carriers

mobility and finite transfer time to reach the

electrode from the interaction point.

6 / 27

The simulated CSA output for input charge qin = 2200 e- for different

waveforms’ shapes of input charge pulse qin – Kleczek R., 2015 [3].

The input charge qin source parameters [3].

The CSA output waferorms parameteres for different signals

shapes of input charge qin [3].

When the readout electronics peaking time tp is not

longer than the detector charge collection time tc,

the readout electronics output amplitude is

proportional only to a fraction of generated charge

qin – ballistic deficit. This may impact on the system

energy resolution.

Simplified model of input charge pulse.

General considerationsDead time behaviour models of readout electronics

Count rate performance for two models of dead time losses

for τ = τP = τNP = 100 ns.Estimation of 10% dead time loss input rate parameter.

The minimum time separation is required for two pulses arriving on the pixel to be distinguished correctly. This

minimum time separation is called the dead time τ.

Two dead time behaviour models for

counting systems are commonly used:

- paralyzable model

- non-paralyzable model

To compare count-rate performance of the existing solutions the 10% dead time loss input rate metrics is used,

which is defined as input pulse rate at which the output count-rate NOUT = 0.9∙NIN.7 / 27

Photon Counting Pixel Readout ASICsCount-rate performance comparison

8 / 27

Comparison of counting pixel chips in submicron technology – part 1.

Photon Counting Pixel Readout ASICsCount-rate performance comparison

9 / 27

Comparison of counting pixel chips in submicron technology – part 2.

Photon Counting Pixel Readout ASICsASICs performance comparison

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Count rate / area versus power / area performance of the presented ASICs: a) full-scale version, b) magnified version.

Due to lack of power consumption data in the graphs are not included: (2) Siemens PC, (4) DxRay-Interon, (5) ChromAIX2, (9) XCounter.

a) b)

11 / 27

PXF40 prototype ASICASIC overview

Photo of the prototype ASIC with

attached detector. Simplified block diagram of

prototype ASIC.

Block diagram of the presented readout

front-end electronics analog part.

This PXF40 with pixel pitch of 100 µm is designed for testing different circuitry:

- new blocks for fast signal processing operating in the SPC mode (occupy silicon area of 50 µm × 50 µm),

- modified blocks for inter-pixel communication mode to eliminate the effects of charge sharing.

The fast signal processing path consists of a CSA, a comparator, and a 24-bit ripple counter.

This prototype ASIC was presented at the International Image Sensor Workshop, Hiroshima, 30 May – 2 June, 2017

and currently is submitted to the IEEE Journal of Solid-State Circuits.

PXF40 prototype ASICImplementation details

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Architecture of the CSA blocks: core amplifier, feedback capacitance,

discharge and leakage current compensation.

Depending on the CSA input transistor M1

current IDM1 value for the effective CSA

feedback resistance RF of the order of MΩ, the

input stage operates in the following modes:

- FAST mode: IDM1 ≈ 20 µA (GBW = 5.3 GHz),

- FAST_HC mode with Higher Current value:

IDM1 ≈ 60 µA (GBW = 8.4 GHz).

The CSA capacitance block core is a set of

seven MOM type capacitors (one for CF1 and six

for CF2) of 1.2 fF each. The capacitor CF1 = 1.2

fF is fixed, while the value of the capacitor CF2can be programmed in the range from 1.2 fF to

1.2 + (0.6; 1.2; 2.4) fF.

The CSA discharge block is based on the

Krummenacher feedback structure. The discharge

current IKRUM can be changed up to 300 nA

(allowing a stable circuit operation), what gives

effective resistance RF values down to 0.6 MΩ.

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PXF40 prototype ASICTheoretical considerations

( )bass

TsT

++=

2

0

( )

2

4

2

4sinh

2

2

2

0

ba

tba

e

TtT

ta

−

−

⋅=

−

CSA output waveforms for the CSA in the FAST_HC

and FAST modes – post-layout simulations.

Simplified model of the presented CSA stage.

Measured count rate performance for the CSA in the

FAST mode for IKRUM = 230 nA.

The CSA transmittance function T(s) can be expressed as:

The CSA output pulse response

shape can be controlled by the

a and b coefficient values:

( )

2

4

2

4sin

2

2

2

0

ab

tab

e

TtT

ta

−

−

⋅=

−

( ) ( ) ( )RF

F

ss

RsT

ττ ⋅+⋅⋅+=

11

The CSA output pulse response shape

can be controlled by the a and b

coefficient values:

−

−=

−−FR

tt

FR

F

F

inout ee

C

qV

ττ

τττ

The CSA output pulse shape,

amplitude and noise performance can

be controlled by changing the ratio

τF/τR.

For the phase margin around 50º, the

τR should be at least three times

smaller than τF.

The prototype ASIC measured performance in terms of operation mode and IKRUM current.

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PXF40 prototype ASICMeasurements results

The pixels’ analog parameters (charge gain kq and noise ENC) were measured for three different IKRUM current

settings (which set the discharge feedback structure effective resistance RF):

- IKRUM = 60 nA (according to simulation RF ≈ 2.9 MΩ),

- IKRUM = 140 nA (RF ≈ 1.3 MΩ),

- IKRUM = 230 nA (RF ≈ 0.9 MΩ).

Under nominal power supply voltages, the power consumption per single channel is about 45 µW for the FAST

and 100 µW for the FAST_HC mode.

The pixel-to-pixel offset spread of the whole IC pixel matrix before the correction was σ = 10.6 mV, and after

correction it was reduced to σ = 0.5 mV.

During the measurement, the 320 µm thick detector was biased up to 150 V and holes were collected by the

readout channels. The 8 keV energy beam used in the IC characterization process was provided by the 9 kW

X-ray source. The photons flux uniformly illuminated 6 rows of the IC pixel matrix.

Signal waveforms illustrating instant retrigger technology. The registered counts are shown for paralyzed (red) and retriggered (green) counting mode [14].

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Overcoming of the paralyzation pile-up effect by retroactively partitioning the comparator pulse into a

sequence of nominal single photon pulses by re-evaluating its output after an adjustable delay of time.

This delay before re-evaluation is slightly higher than the duration of the pulse for a single photon to

compromise between noise immunity and double-count detection resolution.

Strategies for boosting count-rate performance

Instant retrigger technology – Pilatus3 – Loeliger T., 2012 [14], IBEX – Bochenek M., 2018 [6]

This technique is an effective approach for imaging with monochromatic photon beams, like available at the

synchrotron radiation facilities.

The measured typical count rate characteristics of PILATUS3 x-

ray detectors in conventional paralyzed counting mode (red) and in

retriggered counting mode (green) with instant retrigger capability

(Continuous source, photon energy 8 keV, mid gain, threshold

energy 4 keV) [14].

IBEX: Count rate curve measured at the PX II beamline with 16 keV

photons and a low gain setting, with and without retrigger enabled

(the energy threshold is set to half the incoming beam energy) [6].

Instant retrigger technology results in non-paralyzable counting and improves count-rate performace.

IBEX in the non-paralyzable case (retrigger enabled) achieves the output count-rate approximately 10 Mcps/pix.

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Instant retrigger technology – Pilatus3 – Loeliger T., 2012 [14], IBEX – Bochenek M., 2018 [6]


Pile-up trigger method – Siemens PC – Kappler S., 2011 [20]

17 / 27

This method is based on paralyzable rising-edge counter and it motivated by the observation that a ROIC

with a set higher threshold is capable of counting higher X-ray fluxes.

Counter signal as a function of the X-ray tube current for three

different counter thresholds [20].

Peak position of the counter signal as a function of the counter

threshold [20].

This number of counts N consists of linearly combining the information from the counter associated with the

spectral threshold NS (set at the energy of interest) with information of a counter associated to a threshold NP set

above the beam energy (paralyzes only at a higher count-rate):

This method is unambiguous up to highest X-ray fluxes that occur outside the object and at the object boundaries.

Additionally, it features full spectra sensitivity in the low-flux regime inside the object.

N = NS + w ∙ NP ; where w – admixture weight


Counting and integrating in a pixel – CIX – Kraft E., 2007 [10, 13]

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This approach combines of charge integration and photon counting in every single pixel.

Dynamic range of the photon counter, tested with 2.1 fC input pulses. Gray lines:

response to pulses of equidistant spacings (superposition of the all measurements

in all pixels), full count efficiency is achieved up to the steep decline which

marks the maximum the count rate at about 12 MHz [10].

Schematic structure of a pixel cell allowing simultaneous counting

of individual photons and integration of the total signal current [13].

This method overcomes the limitations of the individual schemes (photon counting and integrating mode) and

allows simultaneous measurement of absorbed photon flux and deposited energy.

The two channels are combined into a single pixel using a special feedback circuit which provides input

signal replication.

This combination does not only extend the dynamic range beyond the limits of the respective concepts, it also

yields additional spectral information in terms of mean photon energy in the region where both operating ranges

overlap.


Reset functionality – ERPC ASIC – Gustavsson M., 2012 [21], Xu. Ch., 2013 [22]

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Overview of an ASIC channel [22].

Energy is measured by the use of a digital peak detector.

When the lowest threshold (COMP0) detects hit the

signal is sampled every clock cycle during a programmed

time. When the input signal to any comparator exceeds

the threshold, a digital register is set. After the

programmed time, a counter associated to the highest

detected threshold is increased.

The count-rate performance can be improved by speeding up the return to baseline, what can be

achieved by applying a reset function to an analog block.

This technique is really useful in high-rate energy-resolving photon counting ASICs, where high flux of photons

are expected and additionially the peaking time tp cannot be too short (due to nonzero duration of the detector

current from a single event).

Schematic of the analog channel [22].

Procedure for detecting pulse amplitude. In this case, counter

3 is incremented. CLK indicates negative clock edges [21].

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After the turn on the COMP0 (the lowest threshold), for a set duration of time TS the processed signal is

sampled. Then, after incrementation of the counter related with the highest threshold which was passed

by the pulse height, the reset is activated for a given time duration TR.

Count rate linearity of an individual ASIC channel equivalent to an

individual detector segment in a segmented silicon strip detector for 120 kV

x-rays with sample time TS = 60 ns and reset time TR = 20 ns [22].

Filter output (dashed) as a result of three close input pulses (dotted).

With the filter reset mechanism, the filter output is shorted a certain time

after pulse detection (at the “ticks”) resulting in the solid curve. Note that

the first two solid peaks are similar in amplitudes and that we are able to

detect also a smaller pulse after a strong one (third peak) [21].

Implementation of the reset functionality results in ×2.2 count-rate improvement compared to the conventional

case. The observed rate versus the true rate becomes the non-paralyzable case.

Sample time TS should make the comparators read after the peak is passed and reset time TR should make sure

that the pulse has decayed below the lowest threshold before detecting a new event.


Reset functionality – ERPC ASIC – Gustavsson M., 2012 [21], Xu. Ch., 2013 [22]

The usage of this technique in very high count-rate application is questionable due to „long lasting” transients

(from nanoseconds input pulse processing time point of view).


Cross detection method – ECPC – Lee D., 2017 [1]

21 / 27

CDM is an innovative method to reduce count loss from pulse pile-up in a photon-counting pixel while

maintaning the pulse processing time.

Outputs of the PC pixel with a comparator (a) and the PC pixel with a CDM logic (b).

The photon-counting pixel with CDM

is able to detect incident photons

regardless of any pulse pile-up

occuring at the signal processing

channel.

The CDM photon-counting pixel can

be implemented by adding a buffer, a

capacitor, and resistors (copy logic)

to the conventional pixel.

The copy logic output VCCSA is a copy

of VCSA with an output level shift

(offset voltage) and a delay time.

When the VCSA and VCCSA are compared

crossing points are generated (when

one pulse exceeds the other pulse).

The counter counts the incident hits

using the generated transition without

any loss even at pulse pile-up.

22 / 27

The measured count rates with pulse processing time of 500 ns

with 10 mV offset voltage at VCCSA, threshold voltage of 910 mV.

The all-pass filter topology is used for the copy logic to adjust delay time. The offset voltage is tunable by

adjusting the effective input transistor size by external voltage.

The copy logic for VCCSA signal.

Without the offset voltage and the delay time, the comparator output VCDM changes the output state under the

presence of noise even when no input is applied to VCCSA.

The maximum count rates were tested with pulse processing time of 500 ns. The measured maximum count rate

without CDM was 3.1 Mcps at threshold voltage of 910 mV at the comparator. The maximum count rate of the

CDM logic reached 9.3 Mcps with the same effective threshold, 10 mV offset in VCCSA, so the maximum count rate

is increased by approximately three times without shortening the pulse processing time.

This is an atractive method for high count-rate energy-resolved photon counting ASICs. The usage of it for very

high count-rate photon counting ASICs should be considered.


Cross detection method – ECPC – Lee D., 2017 [1]

23 / 27


Possibilities – new technologies

CSA output waveforms for the CSA in the FAST mode in 40 nm

CMOS technology – schematic-level simulations.

CSA output waveforms for the CSA in 28 nm CMOS technology –

schematic-level simulations.

40

nm

CM

OS

28

nm

CM

OS

10% dead time loss input

rate per pixel

PXF40:

Max input count rate

per pixel= 44 Mcps/pixel

= 12.24 Mcps/pixel

Th

e s

am

e p

ow

er

co

nsu

mp

tion

We believe that as a result of this technology

migration the count rate performance can be

increased about 30-40%.

24 / 27


Conclusions

1) The fundamental limitation of readout electronics count-rate performance stems from detector properties

(finite charge collection time, charge sharing, detector saturation under high X-ray flux regime).

2) The photon counting ASICs were presented and compared in terms of 10% dead time loss input rate

parameter. However, one should be aware that pixel count-rate performance is influenced by threshold voltage,

impinging photons energy, power consumption level and making such comparison is difficult.

3) The methods to increase count-rate performance were presented: instant retrigger technology, pile-up

trigger method, counting and integrating in a single pixel, reset functionality and cross detection method.

4) There are a lots of ASICs with maximum output count rate per pixel parameter values exceeding

1 Mcps/pixel. The fastest reported 10% dead time loss input rate per pixel parameter value is 12.24 Mcps/pixel

for the PXF40 prototype ASIC.

5) Nanometer technologies are promising in term of achieving very high count rate performance.


References

[1] Lee D., et al., "Energy-correction photon counting pixel for photon energy extraction under pulse pile-up", NIM A, vol. 856, June2017, pp. 36-46.

[2] Ballabriga R., et al., "Review of hybrid pixel detector readout ASICs for spectroscopic X-ray imaging", 2016 J. Inst. 11 P01007.

[3] Kleczek R., et al., “Charge sesnsitive amplifier for nanoseconds pulse processing time in CMOS 40 nm technology”, Proc. of MixedDesign of Integrated Circuits & Systems (MIXDES), 2015, Torun, Poland.

[6] Bochenek M., et al., “IBEX: Versatile Readout ASIC with Spectral Imaging Capability and High Count Rate Capability”, IEEE Trans.Nucl. Sci., DOI: 10.1109/TNS.2018.2832464.

[4] Kleczek R., et al., “Ultrafast signal processing readout front-end electronics in CMOS 40 nm technology for hybrid pixel detectorsoperating in Single Photon Counting mode”, Proc. of 2017 International Image Sensor Workshop, Hiroshima, 30 May – 2 June, 2017.

[10] Kraft E., et al., “Counting and Integrating Microelectronics Development for Direct Conversion X-ray Imaging”, PhD dissertation,University of Bonn, Germany, 2007.

[11] Grybos P., et al., “32k Channels readout IC for single photon counting detectors with 75 µm pitch, ENC of 123 e− rms, 9 e− rmsoffset spread and 2% rms gain spread”, IEEE Trans. Nucl. Sci., vol. 63, no. 2, April 2016, pp. 1155-1161.

[12] Ullberg Ch., et al., “Photon counting, dual energy X-ray imaging at CT count rates: measurements and implications of in-pixelcharge sharing correction”, Proc. SPIE. 10573, Medical Imaging 2018: Physics of Medical Imaging.

[8] Steadman R., et al., "ChromAIX2: A large area, high count-rate energy-resolving photon counting ASIC for a Spectral CTPrototype", NIM A, vol. 862, 2017, pp. 18-24.

[9] Steadman R., et al., "ChromAIX: Fast photon-counting ASIC for Spectral Computed Tomography", NIM A, vol. 648, August 2011,pp. S211-S215.

[5] Kraft E., et al., “Experimental evaluation of the pile-up trigger method in a revised quantum-counting CT detector”, Proc. SPIE.8313, Medical Imaging 2012: Physics of Medical Imaging.

[7] Barber W. C., et al., “Energy-resolved photon-counting x-ray imaging arrays for clinical K-edge CT”, Proc. of 2011 IEEE NuclearScience Symposium Conference Record, 23-29 October 2011.

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References

[18] Frojdh E., et al., “Count rate linearity and spectral response of the Medipix3RX chip coupled to a 300µm silicon sensor under highflux conditions”, 2014 JINST 9 C04028.

[19] Panguad P., et al., "XPAD3: A new photon counting chip for X-ray CT-scanner", NIM A, vol. 571, 2007, pp. 321-324.

[16] Dinapoli R., et al., "EIGER characterization results", NIM A, vol. 731, 2013, pp. 68-73.

[15] Szczygiel R., et al., “FPDR90—A Low Noise, Fast Pixel Readout Chip in 90 nm CMOS Technology”, IEEE Trans. Nucl. Sci., vol. 58,no. 3, June 2011, pp. 1361-1369.

[17] Szczygiel R., et al., “A Prototype Pixel Readout IC for High Count Rate X-Ray Imaging Systems in 90 nm CMOS Technology”, IEEETrans. Nucl. Sci., vol. 57, no. 3, June 2010, pp. 1664-1674.

[14] Loeliger T., et al., "The new PILATUS3 ASIC with instant retrigger capability", Proc. of Nuclear Science Symposium and MedicalImaging Conference (NSS/MIC), 27 October – 3 November, 2012, Anaheim, USA.

[13] Kraft E., et al., “Counting and Integrating Readout for Direct Conversion X-ray Imaging: Concept, Realization and First PrototypeMeasurements”, IEEE Trans. Nucl. Sci., vol. 54, no. 2, April 2007, pp. 383-390.

[20] Kappler S., et al., “Quantum-counting CT in the regime of count-rate paralysis: introduction of the pile-up trigger method”, Proc.SPIE. 7961, Medical Imaging 2011: Physics of Medical Imaging.

[21] Gustavsson M., et al., “A High-Rate Energy-Resolving Photon-Counting ASIC for Spectral Computed Tomography”, IEEE Trans.Nucl. Sci., vol. 59, no. 1, February 2010, pp. 30-39.

[22] Xu Ch., et al., “Evaluation of a Second-Generation Ultra-Fast Energy-Resolved ASIC for Photon-Counting Spectral CT”, IEEETrans. Nucl. Sci., vol. 60, no. 1, February 2013, pp. 437-445.

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Thank you for your attention!

Acknowledgments:

• The PXF40 project was supported by the National Science Centre, Poland, under contract UMO-

2013/09/B/ST7/01627.

• The author would like to thank Polish Ministry of Science and Higher Education for financial support in the year

2018 for presenting this work on the 11th International Meeting on Front-End Electronics conference.

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the presented table should be updated or there are other existing circuits solutions that should be ranked

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