circuit level models of cmos technology transistors prof. john choma, jr. university of southern...

Circuit Level Models Of CMOS Circuit Level Models Of CMOS Technology TransistorsTechnology Transistors

Prof. John Choma, Jr.

University of Southern CaliforniaDepartment of Electrical Engineering-Electrophysics

University Park: MC: 0271Los Angeles, California 90089-0271

213-740-4692 (USC )626-915-0944 (FAX )

818-384-1552 (CELL )[email protected]

Fall 2001 Semester

Circuit Level Models Of CMOS Circuit Level Models Of CMOS Technology TransistorsTechnology Transistors




213-740-4692 (USC )626-915-0944 (FAX )

818-384-1552 (CELL )[email protected]

Fall 2001 Semester

EE 348: Lecture #04EE 348: Lecture #04

Canonic Cells OfAnalog MOS/CMOS Technology




213-740-4692 (USC )626-915-0944 (FAX )818-384-1552 (CELL )

[email protected] [email protected]

Spring 2003 Semester

Canonic Cells OfAnalog MOS/CMOS Technology




213-740-4692 (USC )626-915-0944 (FAX )818-384-1552 (CELL )

[email protected] [email protected]

Spring 2003 Semester

University of Southern California/Choma

EE 348, Spring 2003: Lecture #04 2

Lecture OverviewLecture OverviewLecture OverviewLecture Overview

Common Source Amplifier Model Low Frequency Performance High Frequency Performance

Broadband RF Amplifier Transfer Function I/O Impedances Design Scenario

Source Follower Model High Frequency Compensation

Common Gate Model High Frequency Performance Cascode Configurations

Common Source Amplifier Model Low Frequency Performance High Frequency Performance

Broadband RF Amplifier Transfer Function I/O Impedances Design Scenario

Source Follower Model High Frequency Compensation

Common Gate Model High Frequency Performance Cascode Configurations



CMOS Common Source AmplifierCMOS Common Source AmplifierCMOS Common Source AmplifierCMOS Common Source Amplifier

Assumptions Transistors Are Saturated: Transistor Drain And Source Series Resistances Are Negligible

Objectives Voltage Gain Transfer Function Frequencies Of Poles And Zeros

Assumptions Transistors Are Saturated: Transistor Drain And Source Series Resistances Are Negligible

Objectives Voltage Gain Transfer Function Frequencies Of Poles And Zeros

gg s hn1 o bias hn2V V V V V V

V g g

R s

V s

V b ia s

C l

V o

V d d

Schem atic Diagram

M 1

M 2

R s

V s

C l

V o s

AC Schem atic Diagram

M 1

M 2



CMOS Small Signal ModelCMOS Small Signal ModelCMOS Small Signal ModelCMOS Small Signal Model

Capacitances For Deep Submicron Technology Input Capacitance (Tens Of fF): Feedback Capacitance (Few fF): Output Capacitance (Tens -To- Hundreds Of fF):

Resistance Parameter (A Few -To- Tens Of K):

Capacitances For Deep Submicron Technology Input Capacitance (Tens Of fF): Feedback Capacitance (Few fF): Output Capacitance (Tens -To- Hundreds Of fF):

Resistance Parameter (A Few -To- Tens Of K):

i gs1 ols1C C C

o o1 o2r r r

o db1 db2 gd2 old2 lC C C C C C

R s

V s

V s

C l

V o s

AC Schem atic Diagram

M 1

M 2V o s

g Vm 1 1 r o

C f

C i C oV 1

R s

Sm all Signal M odel

f gd1 old1C C C



CMOS Amplifier Voltage GainCMOS Amplifier Voltage GainCMOS Amplifier Voltage GainCMOS Amplifier Voltage Gain

PoleRelationships

Zero

Zero Frequency Gain Magnitude

PoleRelationships

Zero

Zero Frequency Gain Magnitude

V s

V o s

g Vm 1 1 r o

C f

C i C oV 1

R s

vfos

vs

1 2

sA (0 ) 1

zVA ( s )

V s s1 1

p p

vv 2

A (0 ) 1 csA ( s )

1 as bs

f

f m1

C1c

z g

s i o o o m1 o s f1 2

f fs i o o

1 2 i o

1 1a R C r C r 1 g r R C

p p

C C1b R C r C 1

p p C C

v m1 oA (0 ) g r



CMOS Amplifier Time ConstantsCMOS Amplifier Time ConstantsCMOS Amplifier Time ConstantsCMOS Amplifier Time Constants

Time Constant Due To Poles (“a”) Sum Of Open Circuit Time Constants With Source Nulled Time Constant Of Any One Capacitor Is Computed With All Other

Capacitances Open Circuited And With Source Signal Nulled Time Constant Due To Zeros (“c”)

Sum Of Open Circuit Time Constants With Response Nulled Time Constant Of Any One Capacitor Is Computed With All Other

Capacitances Open Circuited And With Response Nulled Foregoing Is General Time Moment Theory For Any nth Order

Circuit

Time Constant Due To Poles (“a”) Sum Of Open Circuit Time Constants With Source Nulled Time Constant Of Any One Capacitor Is Computed With All Other

Capacitances Open Circuited And With Source Signal Nulled Time Constant Due To Zeros (“c”)

Sum Of Open Circuit Time Constants With Response Nulled Time Constant Of Any One Capacitor Is Computed With All Other

Capacitances Open Circuited And With Response Nulled Foregoing Is General Time Moment Theory For Any nth Order

Circuit

V s

V o s

g Vm 1 1 r o

C f

C i C oV 1

R s

vv 2

A (0 ) 1 csA ( s )

1 as bs

v m1 oA (0 ) g r

s i o o o m1 o s f

f m1

a R C r C r 1 g r R C

c C g



0

V o s

g Vm 1 1 r oV 1

R s

Due To C i

0

V o s

g Vm 1 1 r oV 1

R s

Due To C o

0

g Vm 1 1 r oV 1

V xR s

Due To C f

I x

I x

I x

V o s

Time Constant Due To PolesTime Constant Due To PolesTime Constant Due To PolesTime Constant Due To Poles

1ti s

x

i ti i s i

VR R

I

a R C R C

osto o

x

o to o o o

VR r

I

a R C r C

xtf o m1 o s

x

f tf f o m1 o s f

VR r 1 g r R

I

a R C r 1 g r R C

a

ai +

ao +

af



Time Constant Due To ZerosTime Constant Due To ZerosTime Constant Due To ZerosTime Constant Due To Zeros

V s

0

g Vm 1 1 r oV 1

R s

Due To C i

V s

0

g Vm 1 1 r oV 1

R s

Due To C o

V s

g Vm 1 1 r oV 1

V xR s

Due To C f

I x

I x

I x

0

c

ci +

co +

cf

1ni

x

i ni i

VR 0

I

c R C 0

nox

o no o

0R 0

I

c R C 0

xnf m1

x

f nf f f m1

VR 1 g

I

c R C C g



Bandwidth EstimationBandwidth EstimationBandwidth EstimationBandwidth Estimation

Approximate Bandwidth (B) Assume |cB| << 1 (Frequency Of Zero Is Much Larger Than B) Assume bB2 << 1 (Frequency Of High Frequency Pole Is Large)

Comments Crude First Order Bandwidth Estimate

Requires Real Poles OnlyRequires Nominally Dominant Pole Frequency Response

Practical Design GuidelineMay Not Be Supremely Accurate Bandwidth Estimate But Small “a” Is A

Necessary (But Not Sufficient) Condition For Broadband ResponseAn Examination Of The Constituent Terms Of “a” Identifies Energy

Storage Elements/Time Constants That Dominantly Limit Theoretically Achievable 3-dB Bandwidth

Approximate Bandwidth (B) Assume |cB| << 1 (Frequency Of Zero Is Much Larger Than B) Assume bB2 << 1 (Frequency Of High Frequency Pole Is Large)

Comments Crude First Order Bandwidth Estimate

Requires Real Poles OnlyRequires Nominally Dominant Pole Frequency Response

Practical Design GuidelineMay Not Be Supremely Accurate Bandwidth Estimate But Small “a” Is A

Necessary (But Not Sufficient) Condition For Broadband ResponseAn Examination Of The Constituent Terms Of “a” Identifies Energy

Storage Elements/Time Constants That Dominantly Limit Theoretically Achievable 3-dB Bandwidth

os vv 2

s

V A (0 ) 1 csA ( s )

V 1 as bs

v

v 2

A (0 ) 1 j cA ( j )

1 b j a

v vA ( jB ) A (0 ) 2

i o f1 2

1 1 1B

a a a a1 p 1 p



Frequency Response MetricsFrequency Response MetricsFrequency Response MetricsFrequency Response Metrics

CriticalFrequencyRelationships

Unity GainFrequency - u

Pole Dominance Metric kp = p2/u

kp > 1 Implies Amplifier Is A Dominant Pole Circuit

CriticalFrequencyRelationships

Unity GainFrequency - u

Pole Dominance Metric kp = p2/u

kp > 1 Implies Amplifier Is A Dominant Pole Circuit

V s

V o s

g Vm 1 1 r o

C f

C i C oV 1

R s

vfos

vs

1 2

sA (0 ) 1

zVA ( s )

V s s1 1

p p

v m1 o u v 1 p 2 uA (0 ) g r A (0 ) p k p @ @

s i o o o m1 o s f1 2

f fs i o o f f m1

1 2 i o

1 1R C r C r 1 g r R C

p p

C C1R C r C 1 z C g

p p C C



Negligible Feedback CapacitanceNegligible Feedback CapacitanceNegligible Feedback CapacitanceNegligible Feedback Capacitance

Poles

Zero At Infinity

Unity Gain Frequency For p2 >> p1

Pole Dominance Metric

Comments Negligible Feedback

Presumption Valid When No Feedback Capacitance Is Appended Pole Dominance Requires gm1Rs < Co/Ci

Dominant Pole Response Requires kp > 1Typical For First Stage; Atypical For Interstages

Unity Gain Frequency Is Effectively The Ratio Of Driver Transconductance -To- Output Capacitance Ratio

Poles

Zero At Infinity

Unity Gain Frequency For p2 >> p1


Comments Negligible Feedback

Presumption Valid When No Feedback Capacitance Is Appended Pole Dominance Requires gm1Rs < Co/Ci

Dominant Pole Response Requires kp > 1Typical For First Stage; Atypical For Interstages

Unity Gain Frequency Is Effectively The Ratio Of Driver Transconductance -To- Output Capacitance Ratio

s i o o o m1 o s f s i o o1 2

1 1R C r C r 1 g r R C R C r C

p p

1 o o

2 s i

p 1 r C

p 1 R C

f fs i o o s i o o

1 2 i o

C C1R C r C 1 R C r C

p p C C

u v 1 m1 oω A (0)p g C

o2p

u m1 s i

Cpk

ω g R C@



Significant Feedback CapacitanceSignificant Feedback CapacitanceSignificant Feedback CapacitanceSignificant Feedback Capacitance Poles/

Zero

Unity Gain Frequency


Comments Significant Feedback

Presumption Valid When Feedback Capacitance Is Appended, As In Pole Splitting Compensation

Pole Dominance Requires Large Source Resistancekp > 1Typical For Interstage; Atypical For Front End First Stage

Unity Gain Frequency Is Determined By Time Constant Formed Of Source Resistance And Feedback Capacitance

Poles/Zero

Unity Gain Frequency


Comments Significant Feedback

Presumption Valid When Feedback Capacitance Is Appended, As In Pole Splitting Compensation

Pole Dominance Requires Large Source Resistancekp > 1Typical For Interstage; Atypical For Front End First Stage

Unity Gain Frequency Is Determined By Time Constant Formed Of Source Resistance And Feedback Capacitance

s i o o o m1 o s f m1 o s f 11 2

1 1R C r C r 1 g r R C g r R C 1 p

p p

f fs i o o

1 2 i o

C C1R C r C 1

p p C C

f fi o

i o

2 m1 f

C CC C 1

C C1

p g C

m1 sp

o i i

f o r

g Rk

C C C1

C C C

f m1 f m1 s uz g C g R ω

us f

1ω

R C



Frequency Response: UnstableFrequency Response: UnstableFrequency Response: UnstableFrequency Response: Unstable

A (0)v

u v/A (0 ) k p u

k o u

u

0

| |A (j ) v (in dB )

6 dB /O c tave

12 d B /O c ta ve

6 dB /O c tave

Potentially Unstable BecauseSecond Pole Lies At Frequency That Is Smaller Than Unity GainFrequency; That Is, kp < 1

v vf o uos

vs v

1 2 u p u

s sA (0 ) 1 A (0 ) 1z k ωV

A ( s )V A (0 )ss s s1 1 1 1

p p ω k ω

u v 1

2 p u

f o u

ω A (0 )p

p k ω

z k ω



Frequency Response: StableFrequency Response: StableFrequency Response: StableFrequency Response: Stable

A (0)v

u v/A (0 )

k p u k o u

u

0

| |A (j ) v (in dB )

6 dB /O c tave

12 d B /O c ta ve

6 dB /O c tave

Likely To Be Stable BecauseSecond Pole Lies At Frequency That Is Larger Than Unity GainFrequency; That Is, kp > 1

v vf o uos

vs v

1 2 u p u

s sA (0 ) 1 A (0 ) 1z k ωV

A ( s )V A (0 )ss s s1 1 1 1

p p ω k ω

u v 1

2 p u

f o u

ω A (0 )p

p k ω

z k ω



R s s

R o

R i

R s

R f

V s R l

+ V g g

V d d

V o

R in

R o u t

R f

R in

V s

V o s

g Vm 1 R o

R s sV 2

R s

R i

b m 2g V R l

R o u t

I

V 1

Match-Terminated Common SourceMatch-Terminated Common SourceMatch-Terminated Common SourceMatch-Terminated Common Source

Assumptions Very Large Transistor Channel Resistance Low Frequency Considerations Only For Initial Study Biasing Network Has Been Simplified To Expedite Analyses

Match Termination Circuit Can Be Designed For Rin = Rout When Rs = Rl

Match Termination Implies Rs = Rin = Rout = Rl R Match Termination Useful For Cascaded Stages

Assumptions Very Large Transistor Channel Resistance Low Frequency Considerations Only For Initial Study Biasing Network Has Been Simplified To Expedite Analyses

Match Termination Circuit Can Be Designed For Rin = Rout When Rs = Rl

Match Termination Implies Rs = Rin = Rout = Rl R Match Termination Useful For Cascaded Stages



Match-Terminated ConceptMatch-Terminated ConceptMatch-Terminated ConceptMatch-Terminated Concept

Terminations Single Stage: Rs = Rin = Rout = Rl R Cascade: For All Three Stages, Rs = Rin = Rout = Rl R

Comments Loading Effects On Each Stage Effectively Eliminated Reminiscent Of Transmission Line Loaded In Its Characteristic Impedance Results In Maximum Power Transfer At All I/O Ports

Terminations Single Stage: Rs = Rin = Rout = Rl R Cascade: For All Three Stages, Rs = Rin = Rout = Rl R

Comments Loading Effects On Each Stage Effectively Eliminated Reminiscent Of Transmission Line Loaded In Its Characteristic Impedance Results In Maximum Power Transfer At All I/O Ports

R

V sR

V o

R

M a tchTerm in a tedA m p lifie r

R

R

V sR

V o

R


R R


R R


R

Gain: Av = Vos/Vs

Gain: Vos/Vs = Av3



Match-Terminated AnalysisMatch-Terminated AnalysisMatch-Terminated AnalysisMatch-Terminated Analysis

Critical Parameter IsGf = 1/Rf

Performance Indices

Return Ratios RT: Thévenin Resistance Seen

By Rf With Vs = 0 RTO: Thévenin Resistance Seen

By Rf With Vos = 0

Critical Parameter IsGf = 1/Rf

Performance Indices

Return Ratios RT: Thévenin Resistance Seen

By Rf With Vs = 0 RTO: Thévenin Resistance Seen

By Rf With Vos = 0

TO s l fov f s l os

s T s l f

T l fin f l ino

T l f

T s fout f s outo

T s f

1 R R ,R RVA G ,R ,R A

V 1 R R ,R R

1 R 0,R RR G , R R

1 R ,R R

1 R R ,0 RR G , R R

1 R R , R

R f

R in

V s

V o s

g Vm 1 R o

R s sV 2

R s

R i

b m 2g V R l

R o u t

I

V 1



I/O ImpedancesI/O ImpedancesI/O ImpedancesI/O Impedances

Straightforward Substitution Of Results Into I/O Equations

Comments If Ri = Ro And Rs = Rl , Rin Rout

More Commonly, Ri >> Rs And Ro >> Rl

Then Ri = Rin = Rout = Rl R Requires Rf = gmeR2

Note That Match Terminated Assumption Mandates R << Rs, Rl

Straightforward Substitution Of Results Into I/O Equations

Comments If Ri = Ro And Rs = Rl , Rin Rout

More Commonly, Ri >> Rs And Ro >> Rl

Then Ri = Rin = Rout = Rl R Requires Rf = gmeR2

Note That Match Terminated Assumption Mandates R << Rs, Rl

R s s

R o

R i

R s

R f

V s R l

+ V g g

V d d

V o

R in

R o u t

f o lin i

me o l

f i sout o

me i s

R R RR R

1 g R R

R R RR R

1 g R R



Match-Terminated GainMatch-Terminated GainMatch-Terminated GainMatch-Terminated Gain

Straightforward Substitution Of Results Into Gain Equation

Design Calculate gme For Desired Gain And Required Match Resistance Calculate Rss Based On Requisite gme

Calculate Required Rf Based On Required R And Computed gme

Straightforward Substitution Of Results Into Gain Equation

Design Calculate gme For Desired Gain And Required Match Resistance Calculate Rss Based On Requisite gme

Calculate Required Rf Based On Required R And Computed gme

R s s

R o

(b ig )

R i

(b ig )

R

g Rm e

2

V s R

+ V g g

V d d

V o

R

R os mev

s

V g R 1A

V 2

m

meb m ss

gg

1 1 λ g R @



Z o u t

(b - a )R(b - a )R

a

R

Inductive Output ImpedanceInductive Output ImpedanceInductive Output ImpedanceInductive Output ImpedanceMatch Terminated Output Impedance

Inductive Because Of Gate-Source Capacitance, Cgs

Potentially Troublesome With Capacitive Loads

Computation R Is Zero

FrequencyOutput Impedance

a: Time Constant Of Cgs With CurrentIx Constrained To Zero

b: Time Constant Of Cgs With VoltageVx Constrained To Zero

InductiveIf b > a

Match Terminated Output Impedance Inductive Because Of Gate-Source Capacitance, Cgs

Potentially Troublesome With Capacitive Loads

Computation R Is Zero

FrequencyOutput Impedance

a: Time Constant Of Cgs With CurrentIx Constrained To Zero

b: Time Constant Of Cgs With VoltageVx Constrained To Zero

InductiveIf b > a

R s s

R o

(b ig )

R i

(b ig )

R

g Rm e

2

+ V g g

V d d

V x

Z o u t

I x

C g s

effL b a R

xout

x

V 1 bsZ R

I 1 as



Inductance ComputationInductance ComputationInductance ComputationInductance Computation

ComputationsComputations

R f

g Vm y

R s sV 2

R

b m 2g V

I x

C g s

I y

V y

= g Rm e

2

V x

Effective Inductance Effective Inductance

2me ss

ss gsme me

effm ss

3me gs 2v

eff gsme v

g R RR R C

1 g R gL

1 g R

g R C 2 A 1L R C

1 g R 2 A 1

x

x

y gsssgs

y me b m ssI 0

y me ss gsb m ssgs gs

y m ss me m ssV 0

V CR Ra C

I 1 g R 1 1 λ g R

V 1 g R R C1 λ g Rb C RC

I 1 g R g R 1 g R



Comments On Inductive OutputComments On Inductive OutputComments On Inductive OutputComments On Inductive Output

Presumptions Very Large Channel Resistance (Reasonable For 50 Load) Very Large Input Port Resistance, Ri (Reasonable For 50 Load) Very Large Output Port Resistance, Ro (Reasonable For 50 Load) Negligible Gate-Drain Capacitance (Reasonable For Self-Aligning

Gate Technology And Possibly For Common Gate Cascode) Drain-Bulk Capacitance Absorbed Into Load Termination

Output Port Inductance Effective Inductance Estimate Is Low By About 20% -To- 30% Due

To Foregoing Presumptions Magnitude Is Generally Below A Nanohenrie Or So Can Cause Ringing/Settling Time Problems For Inappropriate

Capacitive Loads Incurs Non-Match-Terminated Conditions At Very High Signal

Frequencies

Presumptions Very Large Channel Resistance (Reasonable For 50 Load) Very Large Input Port Resistance, Ri (Reasonable For 50 Load) Very Large Output Port Resistance, Ro (Reasonable For 50 Load) Negligible Gate-Drain Capacitance (Reasonable For Self-Aligning

Gate Technology And Possibly For Common Gate Cascode) Drain-Bulk Capacitance Absorbed Into Load Termination

Output Port Inductance Effective Inductance Estimate Is Low By About 20% -To- 30% Due

To Foregoing Presumptions Magnitude Is Generally Below A Nanohenrie Or So Can Cause Ringing/Settling Time Problems For Inappropriate

Capacitive Loads Incurs Non-Match-Terminated Conditions At Very High Signal

Frequencies



R s R s

V s V s

R l

g o

C l

C oC g d

V o

V o s

V d dZ in Z in

Z o u t g Vm a b m bg V R l

C g s

V aV i

Z o u t

V b

Source FollowerSource FollowerSource FollowerSource Follower

Model Modifications

Simplified Model

Model Modifications

Simplified Model

o l sbC C C

a i os

b os

V V V

V V

b m bg VV b

b mg g Vm a

V o s g Vm i

V o s g Vm o s g Vm i

V o s g m

R s

V sC oC g d

V o s

Z in

g Vm i R ll

C g s

V i

outo b m

ll out l

osv m ll

s b

1R

g 1 λ g

R R R

V (0) 1A (0) g R

V (0) 1 λ

@



Source Follower ModelSource Follower ModelSource Follower ModelSource Follower Model

Source Follower

Common Source

Observation Topologically Identical Models Gain And Pole Frequency Expressions Derive From Respective

Common Source Results With Mere Changes In Circuit Branch Variable Notations

Source Follower

Common Source

Observation Topologically Identical Models Gain And Pole Frequency Expressions Derive From Respective

Common Source Results With Mere Changes In Circuit Branch Variable Notations

R s

V sC oC g d

V o s

Z in

g Vm i R ll

C g s

V i

V s

V o s

g Vm 1 1 r o

C f

C i C oV 1

R s



Source Follower GainSource Follower GainSource Follower GainSource Follower Gain Transfer Function

Poles And Zeros

Approximation

Transfer Function

Poles And Zeros

Approximation

v fosv

s

1 2

A (0) 1+s ZV (s)A (s)

V (s) s s1+ 1+

p p

ll o s gd ll m ll s gs1 2

gs gsll o s gd

1 2 gd o

gs

f m

1 1R C R C R 1 g R R C

p p

C C1R C R C 1

p p C C

C1

z g

Note Left Half Plane Zero

v m llb

ll l out lo b m

1A (0) g R

1 λ

1R R R R

g 1 λ g

bll o s gd ll s gs

1 2 b

λ1 1R C R C R R C

p p 1 λ



o gsbll o s gd ll s gs ll o gs

1 2 b 1 b m

gs gsll o s gd s ll o gs gd

1 2 gd o

s o gs gd o m s

2 gs o gs o T

C Cλ1 1 1R C R C R R C R C C

p p 1 λ p 1 λ g

C C1R C R C 1 R R C C C

p p C C

R C C C C g R1

p C C C C ω

Dominant Output Port CapacitanceDominant Output Port CapacitanceDominant Output Port CapacitanceDominant Output Port Capacitance

Approximate Pole And Zero Frequencies

Pole Dominance (p2 >> p1) Requires Implications

Small Source ResistanceLarge Device Unity Gain Frequency

Approximate Pole And Zero Frequencies

Pole Dominance (p2 >> p1) Requires Implications

Small Source ResistanceLarge Device Unity Gain Frequency

gs

f m

C1

z g

mT

gs gd

gω

C C

2

2m m s

T b s ogs o o

g g Rω 1 λ R C

C C C



Response CompensationResponse CompensationResponse CompensationResponse Compensation

TransferFunction

Feedforward Capacitive Compensation Incorporate Capacitance Cc Across Gate-Source Terminals Choose Cc Such That Cc + Cgs >> Co

May Be Difficult For Large Source-Bulk Or Load Capacitances Requires Negligible Threshold Modulation Factor

Gain And Bandwidth (B) Results

TransferFunction

Feedforward Capacitive Compensation Incorporate Capacitance Cc Across Gate-Source Terminals Choose Cc Such That Cc + Cgs >> Co

May Be Difficult For Large Source-Bulk Or Load Capacitances Requires Negligible Threshold Modulation Factor

Gain And Bandwidth (B) Results

gs

v f b mv

gs o m s o

1 2b m T gs o

sC11

A (0) 1+s Z 1 λ gA (s)

s s s C C sg R C1+ 1+ 1 1p p 1 λ g ω C C

b

vm s o

T c gs o

1 1 λA (s)

sg R C1

ω C C C

c gs oT

m s o

C C CωB

g R C



Compensated FollowerCompensated FollowerCompensated FollowerCompensated Follower

Transfer Function

Net Output Port Capacitance

Effect Of Feedforward Capacitance Is Effectively To Bypass Transistor At High Signal Frequencies

Transfer Function

Net Output Port Capacitance

Effect Of Feedforward Capacitance Is Effectively To Bypass Transistor At High Signal Frequencies

o l sb1 db2 gd 2C C C C C

R s

V s

C l

V o

V d d

Z o u t

V b ia s

C c

V s s

M 1

M 2

b

vm s o

T c gs o

1 1 λA (s)

sg R C1

ω C C C



Follower Output ImpedanceFollower Output ImpedanceFollower Output ImpedanceFollower Output Impedance

Dominant Pole/Zero Approximation

Compare Pole/Zero Time Constants Inductive Impedance Requires b > a Capacitive Impedance Requires a > b Calculate “a” As Sum Of Open Circuit

Time Constants With Ix = 0 Calculate “b” As Sum Of Open Circuit

Time Constants With Vx = 0

Dominant Pole/Zero Approximation

Compare Pole/Zero Time Constants Inductive Impedance Requires b > a Capacitive Impedance Requires a > b Calculate “a” As Sum Of Open Circuit

Time Constants With Ix = 0 Calculate “b” As Sum Of Open Circuit

Time Constants With Vx = 0

R s

V d d

Z o u t

C c

V s s

M 1

R s

C s bC g d

V x

g Vm i

I x

R o u t

C + Cc g s

V i

V x

I x

xout out

x

V 1 bsZ R

I 1 as

Z o u t

(b - a )R o u t

(b - a )R o u t

a

R o u t

eff outL b a R

outb m o b m

1 1R

1 λ g g 1 λ g



Time Constants — ZTime Constants — ZoutoutTime Constants — ZTime Constants — Zoutout

Due To Zero

Due To Pole

EffectiveInductance

Inductive Condition Satisfaction Likely

For Large Source Resistance Satisfaction Likely For Gate-Source Compensation Capacitance

Due To Zero

Due To Pole

EffectiveInductance

Inductive Condition Satisfaction Likely

For Large Source Resistance Satisfaction Likely For Gate-Source Compensation Capacitance

sbm s

c gs

Cg R 1

C C

Z o u t

(b - a )R o u t

(b - a )R o u t

a

R o u tR s

V d d

Z o u t

C c

V s s

M 1

I x

V x

s gd c gsb R C C C

s gd c gs out sb m s out c gsa R C C C R C 1 g R R C C

2eff out out m s c gs sb

L b a R R g R 1 C C C



C oC g d g Vm i R ll

C + Cc g s

V i

V i

I x

I x

C l

V d dZ in

C c

V s s

M 1

M 2V b ia s

V o s

V o

Source Follower Input AdmittanceSource Follower Input AdmittanceSource Follower Input AdmittanceSource Follower Input Admittance

Input Admittance

Voltage Ratio

Effective Input Capacitance

Input Admittance

Voltage Ratio

Effective Input Capacitance

x gd i gs c gs i os

x osin gd c gs ieff

i i

I sC V s C C C V V

I VY s C C C 1 sC

V V

bos

m s os

T c gs o

1 1 λV (s)

sg R CV (s)1

ω C C C

s

os os

i i bR 0

V V 1

V V 1 λ

bieff gd c gs

b

λC C C C

1 λ



I o

I o s

I o s

Z in

R l R l

R l

R sI + IQ s

V s s

V b ia s

V d d

Z o u t

C l

C o

C o

C iV i

V i

g Vm a

(1 + )g V b m i

b m ag V g o

g o

I s R s

V

a

V

b

V o s

V o s

C i

V i

I s R s

V

a

V

b

I 1 I 2

V o s

g Vo o sg i

I 1 I 2V i

g Vi i g o

Common Gate AmplifierCommon Gate AmplifierCommon Gate AmplifierCommon Gate Amplifier

o db gd l

i sb gs

i a b

os os l

C C C C

C C C

V V V

V I R

1 b m i o i os

2 b m i o os i

i o b m

I 1 λ g V g V V

I 1 λ g V g V V

g g 1 λ g

@



Common Gate Model/PerformanceCommon Gate Model/PerformanceCommon Gate Model/PerformanceCommon Gate Model/PerformanceI o

Z in

Z in

Z o u t

R l

R sI + IQ s

V s s

V b ia s

V d d

Z o u t

C l

V i

I o s

R lC o

V o s

V i

I s R s C i g R Io l o s

g Vi i g o

g i

o io ioi

s o l io s l

lin

i i l

sout

o o s

I A (s) A (s)A (s)

I 1 g R A (s) 1 T(s, R , R )

1 T(s, 0, R )1Z (s) =

g sC 1 T(s, , R )

1 T(s, R , 0)1Z (s) =

g sC 1 T(s, R , )

sii

i s

i o b m

loo

o l

s l o l io

RR

1 g R

g g 1 λ g

RR

1 g R

T(s, R , R ) = g R A (s)

@

@

@



Common Gate Gain ParametersCommon Gate Gain ParametersCommon Gate Gain ParametersCommon Gate Gain Parameters

Open Loop Gain Magnitude: |Aio(jω)| < 1 Dominant Pole Most

Likely Is Established By Co

Loop Gain Magnitude < 1 Magnitude Is Actually

Much Smaller ThanOne And Smaller YetAt High Frequencies

Closed Loop Gain

Open Loop Gain Magnitude: |Aio(jω)| < 1 Dominant Pole Most

Likely Is Established By Co

Loop Gain Magnitude < 1 Magnitude Is Actually

Much Smaller ThanOne And Smaller YetAt High Frequencies

Closed Loop Gain

Z in Z o u t

I o s

R lC o

V o s

V i

I s R s C i g R Io l o s g Vi i g og i

o l

i s

i s o loio

s ii i oo og R 0

g R 1

1 g R 1 g RIA (s)

I 1 sR C 1 sR C

i s o l

i s o ls l o l io

ii i oo o

g R g R

1 g R 1 g RT(s, R , R ) = g R A (s) =

1 sR C 1 sR C

i s

cl ioi s o l oo o

g RA (s) A (s)

1 g R 1 g R 1 sR C



Common Gate I/O ImpedancesCommon Gate I/O ImpedancesCommon Gate I/O ImpedancesCommon Gate I/O Impedances Input Impedance

OutputImpedance

I/O Impedances Are Both Capacitive And Approximately Dominant Pole Frequency Functions

Input Impedance

OutputImpedance

I/O Impedances Are Both Capacitive And Approximately Dominant Pole Frequency Functions

sii

i s

loo

o l

RR

1 g R

RR

1 g R

@

@

o l i inin

in il o o li

oo o i

o l o lin

i o b m b m

1 g R g Z (0)Z (s)

1 sZ (0)C1 sR C 1 g RsC

1 sR C g

1 g R 1 g R 1Z (0)

g g 1 λ g 1 λ g

i s o outout

out os i i so

ii i o

o b m s b m si sout

o o o

1 g R g Z (0)Z (s)

1 sZ (0)C1 sR C 1 g RsC

1 sR C g

1 g 1 λ g R 1 λ g R1 g RZ (0)

g g g



Common Gate SummaryCommon Gate SummaryCommon Gate SummaryCommon Gate Summary

Current Gain Frequency Response Less Than Unity Current Gain Magnitude At All Frequencies Dominant Pole Is Established By Net Output Port Capacitance

Input Resistance Is SmallOutput Resistance Is Very Large

I/O Impedances Low Frequency Input Impedance Is Small Low Frequency Output Impedance Is Very Large Both I/O Impedances Are Strongly Capacitive Input Impedance Is Capacitive Only To The Extent That The

Transistor Gate Is Biased By A Low Impedance Supply

Principle Applications Current Buffer With Capacitive I/O Ports Common Source-Common Gate (CS-CG) Cascode

Useful In Transconductor CircuitsNot As Effective As Bipolar Cascode Because Of Very Small Gate-

Drain Capacitance Of Common Source Driver

Current Gain Frequency Response Less Than Unity Current Gain Magnitude At All Frequencies Dominant Pole Is Established By Net Output Port Capacitance

Input Resistance Is SmallOutput Resistance Is Very Large

I/O Impedances Low Frequency Input Impedance Is Small Low Frequency Output Impedance Is Very Large Both I/O Impedances Are Strongly Capacitive Input Impedance Is Capacitive Only To The Extent That The

Transistor Gate Is Biased By A Low Impedance Supply

Principle Applications Current Buffer With Capacitive I/O Ports Common Source-Common Gate (CS-CG) Cascode

Useful In Transconductor CircuitsNot As Effective As Bipolar Cascode Because Of Very Small Gate-

Drain Capacitance Of Common Source Driver



CS—CG Cascode ArchitectureCS—CG Cascode ArchitectureCS—CG Cascode ArchitectureCS—CG Cascode Architecture

Performance Results Derive From General Common Gate Disclosures; Note Substitutions Below

Dominant Pole Likely Established At High Impedance Output Port

Performance Results Derive From General Common Gate Disclosures; Note Substitutions Below

Dominant Pole Likely Established At High Impedance Output Port

Z o u tR l

R s

V s s

V b ia s

V d d

Z o u t

C l R l C o

V o s

g o 1

g Vm 2 a g o 2

V s

V o

M 1

M 2

b 2 m 2 ag V

g Vm 1 s

I o s

V a

s m1 s m m2 o o2 s o1

os os l b b2 o l db2 gd 2

I = g V g = g g = g R = 1 g

V = I R λ = λ C = C C C



Cascode Circuit PerformanceCascode Circuit PerformanceCascode Circuit PerformanceCascode Circuit PerformanceVoltage Gain

About The SameAs For CommonSource Alone

Gate-DrainCapacitance Of M1 IsSmall, TherebyMitigating Miller EffectOn Cgd1

OutputResistance Very Large M2 Channel Resistance Multiplied By Approximately gm2/go1

Pole

If Rl Is Resistance Of Current Source, p Is Very Small Result Is Integrator Having Approximate Unity Gain Frequency Equal

To Gain-Bandwidth Product

Voltage Gain About The Same

As For CommonSource Alone

Gate-DrainCapacitance Of M1 IsSmall, TherebyMitigating Miller EffectOn Cgd1

OutputResistance Very Large M2 Channel Resistance Multiplied By Approximately gm2/go1

Pole

If Rl Is Resistance Of Current Source, p Is Very Small Result Is Integrator Having Approximate Unity Gain Frequency Equal

To Gain-Bandwidth Product

l out o l o1

= R R C R Cp

o2 b2 m2 b2 m2out

o2 o1 o2 o1

g 1 g 1 g1 1R = 1 1

g g g g

os l m1os os vv m1 l

s m1 s s

m1 l o2 lv m1 l

o1

o2 b2 m2

I R gV I A (0)A (s) = = = g R =

sV g V I 1 +p

g R 1 g RA (0) = g R

g1

g 1 g



Wilson Current AmplifierWilson Current AmplifierWilson Current AmplifierWilson Current Amplifier

Assumptions All Transistors Biased In Saturation Regime Aspect Ratio

Assumptions All Transistors Biased In Saturation Regime Aspect Ratio

Evaluate Performance Current Gain Input Resistance Output Resistance

Evaluate Performance Current Gain Input Resistance Output Resistance

M 1

M 2

M 3

R l

R s

I +

Is

Q

I 2

I 1

I o

V d d

V 1

V 2

R in

R o u t

1 1 2 2

2Q oQ2 2

3 3 1Q 1Q

W L = W L

I IW Lη = =

W L I I@



Model ManipulationModel ManipulationModel ManipulationModel Manipulation

Circuit Equations

Diode M2 Modeled ByTwo Terminal Net Conductance

Circuit Equations

Diode M2 Modeled ByTwo Terminal Net Conductance

M 2

M 3

I 1 s

I 1 s

V 1 s

V 1 s

I 2 s

V 2 s

g Vm 3 2 s g o 3 g m 2 g o 2

V 2 sI 2 s

I 1 sV 1 s

g o 3 g + gm 2 o 2

V 2 sI 2 s

g Im 3 2 s

g + gm 2 o 2

m31s o3 1s 2s

m2 o2

2s2s

m2 o2

gI = g V I

g g

IV =

g g



I 1 s

V 1 s

g o 3

g o 3

g + gm 2 o 2

g + gm 2 o 2

g Im 3 2 s

g Im 3 o s

g + gm 2 o 2

g + gm 2 o 2

M 1

R l

R s

R s

I s

I s

I o

V d d

R in

R o u t

I 2 s

R o u t

R lg Vm 1 a g o 1b 1 m 1 bg V

I o s

I = I2 s o s

V b

R in

V a

Wilson Small Signal ModelWilson Small Signal ModelWilson Small Signal ModelWilson Small Signal Model

Feedback



Wilson Small Signal PerformanceWilson Small Signal PerformanceWilson Small Signal PerformanceWilson Small Signal Performance

Current Gain Determined By

Relative DeviceGeometries

Best Suited ForCurrent SignalProcessing

I/O Resistances Small Input

Resistance Very Large Output

Resistance Excellent Current

Sink

Current Gain Determined By

Relative DeviceGeometries

Best Suited ForCurrent SignalProcessing

I/O Resistances Small Input

Resistance Very Large Output

Resistance Excellent Current

Sink

os io m2i

s m3m3io

m2 o2

m1 s o3 s m1 sio

o1 b1 m1o1 l

m2 o2

I A gA = = η

I gg1 A

g g

g R 1 g R g RA =

2g 1 λ g1 g R

g g

@

b1in

m1 m2 m1

b1 m1m1 s

m2 m1 sout

o1 o1

1 λ1 2ηR

g g g

1 λ g1 g R

g 2 g RR

g g



CS—Wilson CascodeCS—Wilson CascodeCS—Wilson CascodeCS—Wilson Cascode

Dominant Pole Established At High Resistance Output Port

Functions As A Cascode With Current Gain Allows Load Resistance To Be Reduced By Factor Of Wilson Current Gain

To Get Voltage Gain Equal To Conventional Cascode Lower Load Resistance Spells Lower Output Port Time Constant And

Hence, Increased Bandwidth, To The Extent That Output Port Capacitance Establishes Dominant Pole

Dominant Pole Established At High Resistance Output Port

Functions As A Cascode With Current Gain Allows Load Resistance To Be Reduced By Factor Of Wilson Current Gain

To Get Voltage Gain Equal To Conventional Cascode Lower Load Resistance Spells Lower Output Port Time Constant And

Hence, Increased Bandwidth, To The Extent That Output Port Capacitance Establishes Dominant Pole

M 1

M 2

M 3

M 4

R l

R s

I 4

I o

V d d

V s

V s s

I 3

I 2

Small Signal Equations

Low Frequency Voltage Gain

Small Signal Equations

Low Frequency Voltage Gain

4s 3s m4 s

os 2s 3s

I I g V

I I ηI

os m2m4 l m4 l

s m3

V gηg R g R

V g



Bandpass Low Noise Common SourceBandpass Low Noise Common SourceBandpass Low Noise Common SourceBandpass Low Noise Common Source

Inductors Assuming Infinite Q (Only In Academe), They Contribute No Noise Real Inductors Have Finite Q And Finite Self Resonant Frequency

Input Topology Allows Input Impedance Match To Source Resistance Maximum Power Transfer Critical Because Of Low RF Signal Power Match Is Only Bandpass → OK For Low Noise RF Applications

Inductors Assuming Infinite Q (Only In Academe), They Contribute No Noise Real Inductors Have Finite Q And Finite Self Resonant Frequency

Input Topology Allows Input Impedance Match To Source Resistance Maximum Power Transfer Critical Because Of Low RF Signal Power Match Is Only Bandpass → OK For Low Noise RF Applications

L s s

L s s

L g g

L g g

R s

R sV s

V s V s s

I o u t

C s b

C g s

ig a

C g d

C d bg vm b b a

v g a

r o

v

b a

T gks( ) ig a

Z in

Z in

I o u t

gdg

gs

Ck 1

C@

BiasingNot Shown



Bandpass Model ModificationsBandpass Model ModificationsBandpass Model ModificationsBandpass Model Modifications Ignore Gate-Drain Capacitance

Self-Aligning Gate Technology Possible Use Of Common Gate Cascode Small Device Thickness (W) Note kg = 1

Inductors Account For Winding Resistance (Finite Q) Ignore Self Resonance In Lgg (Analytical Tractability) Include Self Resonance In Lss

Capacitance Across Terminals Of Inductor WindingAbsorb Capacitance Into Csb; Replace Csb By Css > Csb

Miscellany Ignore Channel Resistance, ro (Reasonable For Typical Loads) Ignore Cdb By Ultimately Absorbing It Into Load Termination

Objective Demonstrate Bandpass Nature Of Amplifier Demonstrate Match Terminated Input (Signal) Port

Ignore Gate-Drain Capacitance Self-Aligning Gate Technology Possible Use Of Common Gate Cascode Small Device Thickness (W) Note kg = 1

Inductors Account For Winding Resistance (Finite Q) Ignore Self Resonance In Lgg (Analytical Tractability) Include Self Resonance In Lss

Capacitance Across Terminals Of Inductor WindingAbsorb Capacitance Into Csb; Replace Csb By Css > Csb

Miscellany Ignore Channel Resistance, ro (Reasonable For Typical Loads) Ignore Cdb By Ultimately Absorbing It Into Load Termination

Objective Demonstrate Bandpass Nature Of Amplifier Demonstrate Match Terminated Input (Signal) Port



Source Terminal ImpedanceSource Terminal ImpedanceSource Terminal ImpedanceSource Terminal Impedance

Source Lead Impedance Source Lead Impedance

Parameters Undamped Resonance

Quality Factor

Comments Desire Infinitely Large

Undamped Resonant Frequency

For ωs → ∞

Parameters Undamped Resonance

Quality Factor

Comments Desire Infinitely Large

Undamped Resonant Frequency

For ωs → ∞

sss ss

1ω

L C

ss ss

ss 2

s s s

sR 1 Q

ωZ (s)

s s1 + +

Q ω ω

ss ss s sss

sZ (s) R Q sL

ω

ss sss sss

ss ss

L Cω LQ

R R L s s

L g g R g g

R s

V s

C s s

C g s

i g a

g vm b b a

v g a

R s s

v

b a

T s( )i g aZ in

I o u t

Z s s



Modified RF Bandpass ModelModified RF Bandpass ModelModified RF Bandpass ModelModified RF Bandpass Model

Source Lead Current

Max Zss

Approximation

Small InductanceHigh Quality Factor (Low Rss)Connect Bulk To Source (λb = 0)

Input Port Impedance

Source Lead Current

Max Zss

Approximation

Small InductanceHigh Quality Factor (Low Rss)Connect Bulk To Source (λb = 0)

Input Port Impedance

m gs Tg g

mb ss

1 g sC ωI I I 1

1 g Z s

mb b m ss ss ssg λ g R C L

2 2ss s s ss s s ss ss ss ss

Z (jω ) Q R Q 1 Q R L R C

Tin gg gg ss

gs

ω1Z (s) sL R 1 Z

sC s

L g g R g g

R s

V s

C g s I g

g Z Im b s s T s( )I gZ in

I o u t

Z(s

)ss

I

V g

ss ss

ss 2

s s s

sR 1 Q

ωZ (s)

s s1 + +

Q ω ω



T ssss T ss ss

in gg gg 2gs

s s s

ω RR ω L sL

1 sZ (s) sL RsC

s s1

Q ω ω

RF Input PortRF Input PortRF Input PortRF Input Port

Input Impedance

Assume Large ωs

Small Inductance Connect Bulk To Source Terminal

Input Impedance

Assume Large ωs

Small Inductance Connect Bulk To Source Terminal

in gg ss T ss gg ss T ssgs

in inin

1 1Z (s) R R ω L s L L ω R

s C

1R sL

sC

@T s( )I gL in R in

R s

V s

C in I g

Z in

V g

I o u t

in gg ss T ss T ss

in gg ss

gsin

T ss gs

R R R ω L ω L

L L L

CC

1 ω R C



Input Port MatchingInput Port MatchingInput Port MatchingInput Port Matching

Resonate Lin And Cin With CarrierFrequency, ωc, Of Signal

Match Input Resistance WithSource Resistance Matching Accomplished Via Lss

Low Noise, Since No Resistance Is Explicitly Used For Matching Since Lss Is Used For Resistance Match, Lgg Affords Additional

Design Degree Of Freedom For Setting Center Frequency

Resultant I/O Relationships

Resonate Lin And Cin With CarrierFrequency, ωc, Of Signal

Match Input Resistance WithSource Resistance Matching Accomplished Via Lss

Low Noise, Since No Resistance Is Explicitly Used For Matching Since Lss Is Used For Resistance Match, Lgg Affords Additional

Design Degree Of Freedom For Setting Center Frequency

Resultant I/O Relationships

T ss gs

cgg ss gs

1 ω R Cω

L L C

s gg ss T ss T ssR R R ω L ω L

s sg

cc

c

V 2RI

ωω1 jQ

ω ω

Tout g

ωI j I

ω

T s( )I gL in R in

R s

V s

C in I g

Z in

V g

I o u t

2c in in

c c in s

ω L C 1

Q ω L 2R

out T cc

s s

I ω ω(jω ) j

V 2R



L s s

L d d

L g g L g g

R s R s

V s V s

V s s

I o u t

I o u t

V o u t

V o u t

C g s

C o

I g

T s( )I g

Z in Z in

V d d

Z(s

)ss Z

(s)

dd

Basic RF AmplifierBasic RF AmplifierBasic RF AmplifierBasic RF Amplifier

Approximate Model Large ro

Small Cgd

Small gmb

Zdd Is Same Form As Zss

Q Of Inductor (Resistance Rdd) Drain-Bulk And Output Port Capacitances (Cdd = Cdb + Co)

Approximate Model Large ro

Small Cgd

Small gmb

Zdd Is Same Form As Zss

Q Of Inductor (Resistance Rdd) Drain-Bulk And Output Port Capacitances (Cdd = Cdb + Co)

Biasing IsIncomplete

dd dd

dd 2

d d d

sR 1 Q

ωZ (s)

s s1 + +

Q ω ω

ddd dd

d ddd

dd

1ω

L C

ω LQ

R

Zin = Rs @ ω = ωc



RF Amplifier GainRF Amplifier GainRF Amplifier GainRF Amplifier Gain

Gain Relationships

Voltage Gain

Design Options Double Tuning Single Tuning Butterworth, Tchebyschev, Bessel Or Other Optimization

Gain Relationships

Voltage Gain

Design Options Double Tuning Single Tuning Butterworth, Tchebyschev, Bessel Or Other Optimization

L g g

R s

V sI o u t

V o u t

C g s I g

T s( ) I g

Z in

Z(s

)ss Z

(s)

dd

gout out out

s out g s

IV V I

V I I V

s sg

cc

c

V 2RI

ωω1 jQ

ω ω

Tout g

ωI j I

ω

out ddT

s s cc

c

V (jω) Z (jω) 1j

V (jω) 2R ωω1 jQ

ω ω



2out d ddT

s s c dc d

c d

V (jω) Q Rω 1 1j

V (jω) ω 2R ω ωω ω1 jQ 1 jQ

ω ω ω ω

Comments On RF Design OptionsComments On RF Design OptionsComments On RF Design OptionsComments On RF Design Options

I/O Gain

Single f Tuning ωd = ωc

Difficult To ImplementParametric UncertaintiesGate-Drain Feedback Capacitance Renders Port Tuning Non-Independent

Gain At Signal Carrier Frequency

Double Tuning Optimize Pole Locations For Butterworth Or Other Response Form ωc ≠ ωd; Qc ≠ Qd

Difficult To Implement Reliably On Chip For Foregoing Reasons

Single (Input Port) Tuning Ensure ωd Large In Comparison With Highest Frequency Of Interest Requires Very Small Geometry Device Because Of CdB

I/O Gain

Single f Tuning ωd = ωc

Difficult To ImplementParametric UncertaintiesGate-Drain Feedback Capacitance Renders Port Tuning Non-Independent

Gain At Signal Carrier Frequency

Double Tuning Optimize Pole Locations For Butterworth Or Other Response Form ωc ≠ ωd; Qc ≠ Qd

Difficult To Implement Reliably On Chip For Foregoing Reasons

Single (Input Port) Tuning Ensure ωd Large In Comparison With Highest Frequency Of Interest Requires Very Small Geometry Device Because Of CdB

2out c d ddT

s c c s

V (jω ) Q Rωj

V (jω ) ω 2R



L s s

L d d

L g g

R s

V s

V s s

V o u t

C o

C b

Z in

V d d

M 1

M 2M 3

R p

R b

Circuit Implementation Of RF CellCircuit Implementation Of RF CellCircuit Implementation Of RF CellCircuit Implementation Of RF Cell Transistor M1

Basic Transconductor Bulk Transconductance Is

Mitigated Transistor M2

Common Gate Cascode Mitigates Miller Multiplication

Of Cgd In M1 Must Have Large W For

Low Transconductance Transistor M3

Sets Biasing For M1 Behaves As Current Mirror Since, Assuming Ideal Inductors,

Gate-Source Biasing Of M1 And M3 Are Identical Note No Bias Current Through Resistor Rb

Stage Engineering Operates At Low Biasing Voltages Can Be Realized Differentially

Transistor M1 Basic Transconductor Bulk Transconductance Is

Mitigated Transistor M2

Common Gate Cascode Mitigates Miller Multiplication

Of Cgd In M1 Must Have Large W For

Low Transconductance Transistor M3

Sets Biasing For M1 Behaves As Current Mirror Since, Assuming Ideal Inductors,

Gate-Source Biasing Of M1 And M3 Are Identical Note No Bias Current Through Resistor Rb

Stage Engineering Operates At Low Biasing Voltages Can Be Realized Differentially

circuit level models of cmos technology transistors prof. john choma, jr. university of southern...

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