chapter 3 - analog integrated circuit design by john choma

LECTURE SUPPLEMENT #3 . . . [LS #3]

CHAPTER #03

Bipolar Junction Transistor Models and Biasing Circuits

Dr. John Choma Professor of Electrical Engineering

University of Southern California Ming Hsieh Department of Electrical Engineering

University Park: Mail Code: 0271 Los Angeles, California 90089–0271

213–740–4692 [USC Office] 213–740–7581 [USC Fax] 818–384–1552 [Cell] [email protected]

PRELUDE: In this chapter, we develop the circuit level models and study the associated volt-ampere characteristics of the bipolar junction transistor (BJT). Although these models are not defini-tively derived, the physical properties on which they are premised are discussed thoroughly. These discussions are couched in a largely engineering fashion that exploits many of the pre-cepts set forth in the preceding chapter on semiconductor PN junction diodes. The models and their engineering implications are then used to forge practical network topologies and corresponding design guidelines for bipolar technology biasing circuits.

June 2013

Chapter 3 BJT Models & Biasing

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3.1.0. INTRODUCTION

The successful realization of reliable and reproducible analog signal processors that boast predictable I/O performance relies on the availability of meaningful and mathematically tractable circuit level models for the active devices utilized in these networks. The electrical properties that these models must emulate include both the static and high frequency volt-ampere characteristics, as well as the impact exerted on these characteristics by device operating temperature. The formulation and application of accurate models capable of relating observable electrical performance to pertinent physical phenomenology comprise daunting challenges in light of the complexities of semiconductor device physics and the somewhat vagarious nature of integrated circuit processing. The use of supremely accurate device models can be relegated to definitive computer-aided circuit investigations. Nevertheless, the models exploited by circuit designers in pre-computer-aided studies must be sufficiently comprehensive to convey an in-sightful understanding of the relationship between the performance characteristics of the devices and the circuit topologies configured in a design exercise.

In this chapter, we focus our attention on the silicon monolithic bipolar junction transis-tor (BJT). Our circuit level ruminations span understanding BJT performance at high signal frequencies through formulating efficient and reliable biasing for linear signal processing applications.

Figure (3.1). (a). The schematic symbol and simplified cross section of the NPN bipolar junction transistor

(BJT). (b). Schematic symbol and simplified physical abstraction of the PNP BJT. The cross section diagrams are not drawn to scale.

BJTs come in two flavors: NPN and PNP. In Figure (3.1a), we display the schematic symbol and simplified cross section of the NPN bipolar junction transistor, which is the principle

E

E

C

C

BB

Emitter(N+)

Base(P)

Collector(N)

Ve Vc

V e V c

(a).

E

E

C

C

BB

Emitter(P+)

Base(N)

Collector(P)

Ve Vc

V e V c

(b).

Xe Xb Xc

Xw

Xw

V b

V b


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type of BJT exploited in the signal flow paths of broadband analog networks. Figure (3.1b) ab-stracts the PNP transistor. In each of these devices, a BJT is seen as an amalgam of two PN junction diodes, which arguably suggests the prudence of the time we devoted to studying the PN junction diode in the preceding chapter. As is evident in the figure at hand, one of the two dio-des implicit to a BJT is formed by the emitter and base semiconductor volumes, while the other is fashioned with the collector and base regions.

In each of the transistors depicted in Figure (3.1), the emitter region is very heavily doped to an impurity concentration approaching the solid solubility limit of silicon; that is, the doping concentration is very nearly the maximum that can be received by silicon. The average dopant concentration in the base layer is typically five to six orders of a magnitude less than that of the emitter, while the collector is doped to an impurity concentration that is one or two orders of a magnitude less than that of the base. For minimal geometry transistors intended for high fre-quency circuit applications, the emitter length, Xe, is generally under a micron, the base width, Xb, is two-tenths of a micron or smaller, and the collector length, Xc, is often as large as tens of microns. On the other hand, the feature thickness, Xw, of the transistor is generally under a mi-cron, and the thickness, say Wb (dimension perpendicular to the page face), which is a designable geometric parameter in integrated circuit design, is at least as large as Xw. In monolithic technologies, the geometric parameter, Wb, is commonly referred to as the emitter finger length. It is worthwhile recanting that a micron (μm) is 10−4 cm, and the average thickness of a human hair is around 75 μm. Thus, the width if a typical BJT base is less than (1/375)th the thickness of an average human hair, which this author used to have in abundance.

The PN junction diode studied in the preceding chapter is a two-terminal element for which only a single current and a single voltage are necessary to define its volt-ampere proper-ties. In contrast, the BJT is fundamentally a three-terminal device (actually four terminals in its monolithic embodiment, which entails a substrate that is not shown in the subject figure) for which at least two independent voltages and two independent currents are required to character-ize its electrical behavior. In the NPN structure of Figure (3.1a), one of the current variables is the emitter current, Ie, which is displayed as a positive current flowing out of the transistor. Posi-tive collector current and base current, Ic and Ib, respectively, flow into the device. On the other hand, the PNP device shows positive emitter current as flowing into the transistor and positive collector and base currents flowing out of the device. In both cases, Kirchhoff happily radiates

e c bI I I , (3-1)

which affirms that only two of the three transistor terminal currents are independent electrical variables.

The diagrams in Figure (3.1) also delineate an internal emitter-base junction voltage, Ve, and an internal base-collector junction voltage, Vc. Both of these voltages are interpreted as positive variables when the potential on the p-side of the applicable junction is larger than the potential on the n-side. The resultant internal collector to emitter voltage, Vb, of the NPN transis-tor is

b e cV V V . (3-2)

An identical voltage relationship applies for the emitter to collector voltage of the PNP device.

3.2.0. EBERS-MOLL MODEL

To first order, the static volt-ampere characteristics of either an NPN or a PNP bipolar


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junction transistor follow the dual Ebers-Moll relationships[1],

c cc rr bc

b be bc

I I I I,

I I I

(3-3)

which by (3-1) implies an emitter current, Ie, of

e c b cc rr beI I I I I I . (3-4)

In (3-3), current Icc is given by

e f T e f TV n V V n V

cc e s sI A J 1 I 1 ,e e

(3-5)

where

e b wA W X (3-6)

is the carrier injection area of the emitter-base junction. Like the injection area of a PN junction diode, Ae is the cross section area pierced by mobile charge carriers that are motivated to pene-trate the junction interface between the emitter and base volumes. Continuing with (3-5), Js is the saturation current density of the transistor, Is = AeJs is the corresponding saturation current, and nf is the injection coefficient of the emitter-base junction. Finally,

jT

kTV

q (3-7)

is our familiar Boltzmann voltage, with Tj representing the absolute temperature of the emitter-base junction. The saturation current density, Js in (3-5), and hence the actual saturation current, Is, is strongly affected by the operating temperature of the junction. As witnessed in conjunction with PN junction diodes, the numerical value of Js nominally doubles to quadruples for each ten degrees centigrade rise in the operating temperature of the emitter-base PN junction.

The current component, Icc, in (3-3) through (3-5) is known as the forward transport current of the BJT. When the emitter-base junction of an NPN device is suitably forward biased (Ve > 0), electrons from the emitter are injected into the base region. In tandem with this elec-tron transport, holes are injected from the base to the emitter. However, the junction current manifested by injected holes is smaller than is the junction current arising from injected electrons because the emitter region is doped to a concentration that is far larger than the impurity concentration indigenous of the base dopant. The phrase, “suitably forward biased,” is taken to mean that in addition to the requirement of a positive junction voltage, Ve must be at least as large as the turn on, or threshold, voltage, Veon, of the emitter-base junction. We recall that for a junction of p-type and n-type silicon semiconductors, this threshold voltage is about 700 mV.

Our tacit examination of (3-3) and (3-4) confirms that Icc is a component of collector current Ic and emitter current Ie, but it does not contribute to base current Ib. We can therefore attribute the forward transport current of an NPN transistor to those electrons that are injected into the base region from the emitter site and thence swept from the base and into the collector. Thus, once the injected charges are transported to the collector volume, no net change in charge is incurred in the base due to the forward transport current. Accordingly, the physical mechan-isms contributing to current Icc do not influence the measurable base current, Ib.

The transport from emitter to collector of injected minority carriers in the base is ren-dered plausible and likely by the relatively low impurity concentration and narrowness of the base region. In particular, low base region doping tends to limit the level to which base region holes can recombine with injected electrons therein. There simply is insufficient numbers of free


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base region holes to recombine with a significant percentage of electrons injected from the emit-ter. Such global transport is further encouraged by the built-in potential manifested at the base-collector junction, which effectively acts as an intrinsic junction reverse bias. This potential gives rise to an intrinsic field, directed from the collector to the base, which attracts to the collec-tor the minority carriers (electrons in an NPN device) within the narrow confines of the base vo-lume. An additional reverse bias (Vc < 0) imposed by external means across the base-collector junction serves to further promote the likelihood of emitter to collector charge transport.

Most of the carrier injection across the forward biased emitter-base junction of an NPN BJT is comprised of electrons. Nonetheless, a comparatively low level of hole injection from base to emitter prevails, thereby giving rise to a base and emitter current manifested by injected holes. Analogous base and emitter current components are realized in NPN transistors from the recombination of injected electrons with base region holes. And like the former current compo-nent, this recombination component is limited by the relatively low dopant concentration in, and narrowness of, the base volume. The net current arising from hole injection and hole-electron recombination mechanisms arising from a forward biased emitter-base junction is Ibe, which is given by

e f T e f TV n V V n Vcc e s sbe

f f f

I A J II 1 1 .

β β βe e (3-8)

The fact that the form of this expression mirrors the static volt-ampere relationship of a tradi-tional diode is hardly surprising in that the emitter and base volumes shown in Figure (3.1) coa-lesce to form a classic PN junction diode. The effective saturation current of this intrinsic diode is Is /βf. In concert with our discussion herewith, we note in (3-3) and (3-4) that current Ibe af-fects only the BJT base and emitter currents. In (3-8), βf, the forward short circuit (meaning Vc = 0) base to collector transport current transfer ratio, is generally of the order of one hundred in conventional bipolar processing technologies. It is important that we understand that whether through hole injection or via hole-electron recombination, current Ibe reduces the number of in-jected carriers available for ultimate transport into the collector. Thus, for example, the implica-tion of βf = 100 in (3-8) is a net emitter to collector transport current loss, or reduction, of 1%.

Returning to (3-3) and (3-4), the current component, Irr, is given by

c r T c r TV n V V n Vrr e s sI A J 1 I 1 ,e e (3-9)

while current Ibc is

c r T c r TV n V V n Ve s srrbc

r r r

A J III 1 1 .

β β βe e (3-10)

With Vc Vcon, which denotes the threshold voltage of the base-collector junction diode, majority carriers in the collector region are injected into the base region where they become minority carriers. Recombination in this so-called reverse direction is more probable than in the formerly considered forward direction because the base region is doped to a higher impurity concentration than is the collector. Current Ibc reflects this reverse recombination phenomena, as well as the effects of holes injected into the collector across a forward biased base-collector junction. Parameter βr is the reverse short circuit (meaning Ve = 0) base to emitter transport current trans-fer ratio. Owing to the likelihood of enhanced recombination in reverse operation, βr is substan-tially smaller than is its forward counterpart, βf. The current, Irr, represents the effects of collector-injected minority carriers that are swept from the base and into the emitter by the built-in potential at the emitter-base junction or by an imposed reverse bias therein. In (3-9) and (3-10), nr is the injection coefficient of the base-collector PN junction. Generally, nr and nf in (3-5)


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and (3-9) are taken as identical constants. Both of these metrics are only slightly larger than un-ity.

Similar statements can be proffered for the current components, Icc, Irr, Ibe, and Ibc, of a PNP bipolar junction transistor. In the PNP device, Icc and Irr are measures of injected holes that are transported from emitter to collector and from collector to emitter, respectively. Similar to the NPN device, Ibe represents the recombination and base to emitter electron injection current. In the PNP case, recombination is attributed to base region electrons that recombine with holes injected from the emitter. On the other hand, Ibc is the current arising from base region electrons that recombine with holes injected into the base from the collector. Current Ibc also reflects elec-tron injection into the collector across a forward biased base-collector junction.

3.2.1. PHYSICAL INTERPRETATION OF THE EBERS-MOLL MODEL

Before proceeding further, an engineering discussion of the salient physical features of the four bipolar currents, Icc, Ibe, Irr, and Ibc may prove useful to the goal of assimilating a tho-rough understanding of BJT operation. To this end, we shall focus on the NPN embodiment in Figure (3.1a), with the understanding that subject to an interchange of the charge terms, “hole” and “electron,” and a few other clarion changes, our discourse applies equally well to PNP BJTs. (1). In the so-called normal forward, or normal active, mode of BJT operation, we forward bias

the emitter-base junction through the application of an external static voltage that forces the emitter-base junction potential, Ve, to exceed its threshold level, Veon. We should interject that prior to any applied biasing voltage, the emitter, base, and collector regions lie in an equilibrium state that is characterized by charge neutrality. In addition to forward biasing the emitter-base junction, we apply a zero or reverse bias across the base-collector PN junc-tion. Even at zero base-collector junction bias, we know from our PN junction diode studies that a built-in junction potential and corresponding electric field, directed from the collector to the base, is established at equilibrium. The intensity of this field, which increases with imposed reverse bias across the base-collector junction, exerts an attractive force on those electrons that are injected into the base volume from the emitter region. Thus, most of the electrons that find themselves proximate to the geometric base-collector junction are likely to be sucked into, and ultimately transported through, the collector.

(2). A forward bias applied across the emitter-base junction facilitates the injection of electrons from the emitter volume to the base region. Accompanying this electron injection is hole injection from the base to the emitter volumes. However, electron injection dominates over its hole counterpart due to the fact that the emitter volume is far more heavily doped with donor impurities than the base is doped with acceptor atoms. Nevertheless, for every hole that relocates from the base to the emitter, the initial charge neutrality is upset in both the base and the emitter regions. The departed positively charged holes leave behind a net negative ionic charge owing to acceptor donor atoms that have graciously allowed their va-lence band holes to vacate and seek their electronic fortune elsewhere. We may restore charge neutrality in the base by extracting electrons from the base through the base terminal. This electron extraction gives rise to a current flowing into the base. In the emitter, each in-jected hole increases the charge therein by an amount that is effectively equal to a positive electron. We may therefore restore emitter charge neutrality by providing the emitter region with a suitable number of electrons, thereby establishing a current flowing out of the emit-ter. (a). However, it is far more likely that hole-electron recombination occurs in the emitter,


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because the emitter is doped so heavily with donor atoms. Under the recombination scenario, injected holes are effectively eaten by electrons, thereby neutralizing the in-jected hole charge. But nonetheless, the electrons that recombine with the injected hole comprise lost negative charge that leaves in its wake positively charged, ionized donor atoms. This positive charge can be neutralized in a fashion that is similar to the aforementioned electrons being inserted into the emitter volume through the emitter terminal. Of course, the current resulting from these inserted electrons flows out of the emitter lead.

(b). In summary, hole injection from the base to the emitter manifests a base current flow-ing into the base region. This current reestablishes charge neutrality in the base by extracting electrons to cancel the negative ionic charge left in the wake of hole injec-tion. Once the holes reach the emitter volume, emitter current flows out of the emitter to sustain charge neutrality. This situation is true whether recombination, which is the likely event, takes place or whether the hole avoids recombination and magically sur-vives in the emitter volume. In either case, electrons must be brought in either to re-place the electrons that recombine with injected holes or to offset the positive charge of holes that steadfastly elude being eaten by electrons.

(3). For electrons that find themselves injected into the base, three issues are immediately interesting. The first and most obvious of these issues is that the emitter volume is now charged positively by the loss of those injected electrons. This charge must be neutralized by inserting electrons into the emitter, thereby bringing about a current that flows out of the emitter terminal. In the base region, where there are injected electrons, two possible circumstances prevail. First, electrons can recombine with holes in the base, thereby requir-ing, in the interest of sustaining charge neutrality, electrons to be extracted through the base contact and lead. Resultantly, a base current is caused to flow into the base region. But the second circumstance is more likely. This is to say, that as opposed to recombination, in-jected electrons are likely to be transported across the base and thence into the collector vo-lume. Our view that this second situation is more likely than hole-electron recombination derives from the fact that there are simply not a lot of holes in the base that can capture swift moving electrons (electrons boast high mobility) for recombination purposes. Moreover, the base is a very thin region, which is to say, that as soon as injected electrons navigate through the emitter-base transition layer, they likely experience the influence of the attractive force associated with the collector to base electric field established in the base-collector depletion zone. In either the recombination or the transport case of emitter-injected electrons, a cur-rent flows out of the emitter. Under the less likely recombination scenario, charge neutrality is restored by extracting electrons from the base volume, thereby incurring base current flow into the base region. In the transport situation, no base current is needed to sustain charge neutrality in the base, since injected electrons are themselves extracted by their field-in-duced transport into the collector. In this latter case, electrons must be extracted from the collector, which means that collector current flows into the collector volume.

(4). The preceding two items pertain exclusively to the forward active situation that is defined by a forward biased emitter-base junction and a base-collector junction that is not forward biased. The engineering consideration of this particular operational state leads to the following conclusions. (c). First, current Ibe is a current that, in concert with (3-3) and (3-4), affects only the net

emitter and base currents. It is caused by hole recombination with emitter electrons that are injected from the emitter to the base, electron recombination with holes injected


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from the base to the emitter, and/or holes injected from the base into the emitter, where they survive without recombining with emitter region electrons.

(d). Second, Icc is a forward transport current that, in accord with (3-3) and (3-4), affects only the emitter and the collector currents. It is manifested by electrons that are in-jected from the emitter to the base and are then transported completely through the base volume and into the collector.

(e). We can now appreciate the significance of the forward beta, βf. Since, Ibe = Icc/βf, (1/βf) is indicative of the percentage of the forward transport current that is effectively lost through hole-electron recombination.

(5). A similarly experiential discovery of the significance of current components Irr and Ibc re-quires the consideration of a transistor operated in so-called inverse mode. This mode is the converse of the forward active condition in that now, we forward bias the base-collector junction, while applying zero or reverse bias across the emitter-base junction. In other words, the inverse mode can be thought of as the operating condition that happens when the collector and emitter leads are interchanged. The current conditions that apply in inverse mode are simply the reverse of those that have been delineated for the forward active condi-tion. In other words, instead of electron injection from emitter to base, we now observe electron injection from the collector to the base. The details are left as an exercise for the reader but in summary, the following statements can be made. (f). Current Ibc is a current that, in concert with (3-3) and (3-4), affects only the collector

and base currents. It is caused by hole recombination with electrons that are injected from the collector to the base and/or electron recombination with holes injected from the base to the collector. Hole recombination with injected electrons is the more likely scenario in that the base region is more heavily doped with acceptor atoms than the collector volume is doped with donor impurities. Stated quite simply, electrons coming across from the lightly doped collector encounter a relatively dense sea of base region holes that are hungry for oppositely charged electrons.

(g). Current Irr is a reverse transport current that, in accord with (3-3) and (3-4), affects only the collector current and the emitter current. It is manifested by electrons that are in-jected from the collector -to- the base and are then transported completely through the base volume and into the emitter. However, the efficiency of this reverse transport is dubious owing to the relatively high density of free holes in the base. In addition, the extremely dense concentration of free electrons in the emitter sets up a barrier for base region electrons that effectively retards and discourages their attraction by the emitter.

(h). Since, Ibc = Irr/βr, (1/βr) is indicative of the factor of the reverse transport current that is lost through hole-electron recombination. Because of the dense hole population in the base and the extremely dense population of free electrons in the emitter volume, reverse beta βr is invariably much smaller than βf. Indeed, βr can be smaller than unity, which is indicative of a recombination current component that is larger than the reverse trans-port current component.

It is worth underscoring that each of the four current components in the Ebers-Moll model of a bipolar junction transistor is directly proportional to the saturation current density, Js. Recall that Js increases dramatically with the operating temperature of the emitter-base junction. Thus, all three transistor currents −emitter current Ie, collector current Ic, and base current Ib− are vulnerable to device temperature increases if the emitter-base and base-collector junction poten-tials, Ve and Vc, respectively, are held fast over temperature. The design lesson we learn from this argument is that temperature insensitivity in bipolar networks requires circuit designs for


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which Ve and/or Vc are allowed to decrease appropriately to compensate for the increased cur-rents incurred by junction temperature rises.

We should additionally note that all of the Ebers-Moll current components are directly proportional to the emitter-base junction area, Ae. This circumstance means that for fixed values of the junction potentials, Ve and Vc, the emitter, base, and collector currents scale linearly with emitter-base junction area. Assume, for example, that the second of two identical transistors has a junction area that is K-times that of the first transistor and that both transistors are excited by identical emitter-base and base-collector junction potentials. Both transistors therefore exhibit the same current densities despite the fact that the second transistor conducts emitter, base, and collector currents that are respectively K-times larger than the corresponding currents of the first device. Since the internal self-heating caused by current conduction is intimately related to cur-rent density, as opposed to actual current level, the proper scaling of monolithic transistors can circumvent performance problems that may be incurred by excessive on-chip thermal gradients. In short, we need fat transistors when large currents must be conducted, just as we require thick wires to power high current appliances, such as microwave ovens and electric clothes dryers.

3.2.2. SILICON GERMANIUM HETEROJUNCTION BJT

The bipolar transistors addressed at this juncture are exclusively conventional, so-called homojunction, BJTs. A popular alternative to the BJT homojunction is the silicon germanium (SiGe) heterojunction bipolar transistor (HBT)[2],[3]. Its popularity stems fundamentally from its ability to process ultra high frequency signals. Indeed, SiGe HBTs offer short circuit, or Norton, current gains whose magnitudes do not degrade to unity until several hundreds of gigahertz1. This capability compares quite favorably with the frequency attributes of homojunction devices for which unity gain frequencies are at best several tens of gigahertz.

In an NPN SiGe HBT, silicon semiconductor is deployed for the emitter and collector regions, while the base volume is formed of germanium. The basic Ebers-Moll model remains applicable for these new generation bipolar transistors. However, the physical implications of the emitter-base heterojunction give rise to significant performance ramifications at the circuit level. On notable performance difference between an NPN BJT homojunction and an NPN SiGe heterojunction derives from the fact that silicon boasts a larger bandgap potential than does germanium. The bandgap disparity between the emitter and base volumes serves to lower the potential barrier that electrons must overcome if they are to succeed in being injected into the base when a suitable forward bias is applied to the emitter-base junction. Simultaneously, the subject bandgap disparity actually raises the potential barrier that holes must overcome if they are to be injected into the emitter. In a word, the emitter-base heterojunction facilitates emitter to base electron injection, but it makes it harder to effect hole injection from the germanium base volume into the silicon emitter region. The relevant immediate impact is that for a given emitter-base junction forward bias, current Ibe is reduced because hole injection from the base to the emitter is virtually eliminated. Current Ibe therefore becomes almost exclusively a recombination current. But since recombination is minimal for a thin base, parameter βf in (3-8) is rendered very large. In particular, it is two to five times larger than the nominal 100 or so quoted for parameter βf in a conventional transistor. This parametric enhancement is important because, as we shall learn shortly, βf is a measure of the achievable gain (and of numerous other performance metrics) for an electronic network realized in bipolar technology.

1 We shall have much more to say about the unity gain frequency metric of a BJT later in this chapter.


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A second feature of a SiGe HBT is that the germanium base is not doped uniformly with acceptor impurities. Instead, the base impurity profile is monotonically graded from a maximum level at the emitter-base junction to a minimum concentration at the base-collector junction. This impurity grading manifests a drift field within the base that enhances the mobility of electrons injected into the base from the emitter. This mobility enhancement supports the very high, short circuit, unity gain frequencies of SiGe HBTs. Aside from facilitating very wide-band frequency responses in SiGe HBT circuits, the aiding of injected electron transport further supports the minimization of base region hole-electron recombination and therefore a maximiza-tion of the value of the gain measure, βf.

The advantages of a SiGe heterojunction over a counterpart BJT homojunction transis-tor continue. The fact that electron injection from the emitter to base is facilitated in SiGe means that the average dopant concentration in the base, which is kept relatively low to enable efficient carrier injection from the emitter to the base, can be made an order of magnitude or two larger than it is in a conventional BJT. The immediate impact of a large average dopant level in the base is that it reduces the base resistance of a BJT. The last contention follows from the fact that resistance in general is directly proportional to resistivity, which in turn is inversely related to dopant concentration. A small base resistance is a significant attribute because it postures at least four circuit level advantages. First, small base resistance reduces the equivalent input noise voltage, which quantifies the smallest possible signal voltage amplitude that can be distinguished by the amplifier from electrical noise and therefore reliably processed. Second, it improves vol-tage gain in that the available gain of several BJT configurations is inversely related to the sum of the Thévenin signal source resistance and the transistor base resistance. Third, small base resistance supports higher bandwidth frequency responses whenever the net effective capacitance observed between the base terminal and ground significantly limits the observed bandwidth. As we explore later in this text, circuit bandwidth is intimately related to the sum of the capacitive constants established in the considered network. At the base port of a BJT, the capacitive time constant turns out to be the product of the capacitance developed at this port and a resistance function that is proportional to the aforementioned sum of Thévenin signal source and base resis-tances. Finally, a small base resistance minimizes an annoying phenomenon known as base conductivity modulation. We shall ultimately demonstrate that such modulation produces a resistance across the output ports of many amplifiers realized in BJT technology. This incurred resistance serves to reduce the achievable voltage gain, as well as incur other performance detri-ments.

The general impression we should carry away from the foregoing discourse is that SiGe HBT technology offers significant performance advantages over most conventional BJT homojunction networks. This opinion is particularly true in the modern epitaxial processing era that succeeds in realizing SiGe HBTs with insignificant manufacturing cost penalties. But there is at least one disadvantage to SiGe technology. In particular, the larger potential barrier effected for hole injection from base to emitter, along with the larger average impurity concentration in the germanium base gives rise to an emitter-base junction turn on potential that is at least 800 mV or so. This 100 mV or so larger than conventional silicon junction turn on voltage means that supply line voltages for SiGe devices may need to be larger than the supply voltages adopted for conventional BJTs. While this detriment may prove insignificant for many prudently designed circuits, it does generally bode poorly for the electronic portability culture in which we are all immersed.


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3.2.3. CIRCUIT LEVEL INTERPRETATION OF EBERS-MOLL MODEL

In consideration of the fact that both the emitter-base and base-collector junctions of a BJT(inclusive of SiGe) are PN junction diodes, the circuit level interpretation of (3-3) and (3-4) are the NPN and PNP model topologies offered in Figure (3.2). In these topologies, diode DBE represents the emitter-base junction diode, while DBC recognizes the base-collector junction as a semiconductor diode. A trivial model modification, which derives from (3-8) and (3-10), ap-pears in Figure (3.3). In particular, (3-8) shows that the forward transport current, Icc, can be written as Icc = βf Ibe. The forward transport component, Icc, of the collector current can therefore be represented as a current controlled current source that is controlled by the current, Ibe, which is conducted by diode DBE. Analogously, (3-10) implies Irr = βr Ibc, thereby suggesting that the reverse transport component, Irr, of the collector current can be represented as a current con-trolled current source that is controlled by the reverse base current component, Ibc, which flows through diode DBC.

Figure (3.2). (a). Ebers-Moll model of the NPN bipolar junction transistor. (b). Ebers-Moll model of the PNP

bipolar junction transistor.

It is instructive to study the Ebers-Moll equations for the two special cases of Ve = 0 and Vc = 0, which implies a short circuit imposed across the base-collector junction. For exam-ple, with Vc = 0, (3-9) and (3-10) give Irr = 0 and Ibc = 0, whence by (3-3) and (3-4),

b be

c cc f be f b

e cc be f be f b

I I

I I β I β I .

I I I β 1 I β 1 I

(3-11)

Equation (3-11) produces the circuit interpretation in Figure (3.4a), where the voltage, Ve, of the indicated battery is presumed larger than the threshold voltage, Veon, of the emitter-base PN junc-

Icc

Icc

Base

Base

Collector

Ibe

IeIe

Ve

IbcIb

Ib

Ic

Vb

Ve

Collector

Ic

Vb

Emitter

Emitter

(a).

BaseIb

Ve

Collector

Ic

Vb

Emitter

(b).

DBE

DB

C

Irr

IrrIcc

Base Collector

Ibe

IeIe

Ve

IbcIb Ic

Vb

Emitter

DBE

DB

C

Irr


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tion. The condition, Ve > Veon, ensures measurable and positive emitter and base currents in the transistor. The diagram in Figure (3.4a) underscores the logic of referring to parameter βf as a short circuit (meaning Vc = 0) base to collector current transfer ratio in that the ratio, Ic /Ib, of collector to base currents in the subject circuit is clearly βf Ibe/Ibe = βf. We also note a resultant ratio of collector current to emitter current of

Figure (3.3). (a). Alternative Ebers-Moll model of the NPN bipolar junction transistor. (b). Alternative

Ebers-Moll model of the PNP bipolar junction transistor.

c

fcf

e fV 0

βIα ,

I β 1

(3-12)

Figure (3.4). (a). An NPN bipolar junction transistor operated with a forward biased

emitter-base junction and a short circuited base-collector junction. Voltage Ve is presumed to be at least as large as the threshold voltage of the emitter-base diode. (b). An NPN BJT operated with a forward biased base-collector junction and a short circuited emitter-base junction. Voltage Vc is at least as large as the threshold voltage of the base-collector diode.

f beI

Base

Base

Collector

Ibe

IeIe

Ve

IbcIb

Ib

Ic

Vb

Ve

Collector

Ic

Vb

Emitter

Emitter

(a).

BaseIb

Ve

Collector

Ic

Vb

Emitter

(b).

DBE

DB

C

r bcI

Base Collector

Ibe

IeIe

Ve

IbcIb Ic

Vb

Emitter

DBE

DB

C

f beI r bcI

Ve

f beI

( +1)If be

Ibe

(a).

Vc

r bcI

( +1)Ir bc

Ibc

(b).


- 199 -

where parameter αf is commonly referred to as the short circuit emitter to collector current trans-fer ratio. This parameter is a measure of the extent of forward recombination in that (3-12) makes clear that the amount of emitter current that does not materialize as collector current and is therefore “lost” in recombination, is (1−αf )Ie. For large βf and therefore for αf approaching un-ity, forward recombination in the base volume is minimal.

In contrast, with Ve = 0, Icc in (3-5) and Ibe in (3-8) are null and resultantly,

b bc

c rr bc r bc r b

e rr r bc r b

I I

I I I β 1 I β 1 I .

I I β I β I

(3-13)

The last result begets the circuit level representation in Figure (3.4b) in which the voltage, Vc, applied from the base to the collector is presumed to be at least as large as Vcon, the threshold voltage of the base-collector diode. We observe in (3-13) that while the base current remains positive and therefore flows into the base of the NPN transistor, the collector and emitter currents are negative quantities. Consequently, the collector current now flows out of the collector, while emitter current flow is into the transistor emitter terminal. In the circuit diagram at hand, parameter βr is recognized as the magnitude of the base to emitter current transfer ratio. The indicated positive value of the applied voltage Vc serves to inject carriers from the collector to the emitter. Most of these injected carriers recombine with holes in the base, while others are transported to the emitter to establish the current, −βrIb. The resultant ratio of emitter current to collector current is

e

e rr

c rV 0

I βα .

I β 1

(3-14)

Since βr is of the order of one or even smaller, at least half of the aforementioned injected carrier population is lost to recombination within the base volume. In (3-14), parameter αr is the short circuit collector -to- emitter current transfer ratio.

3.2.3.1. Forward Active Operation

A bipolar junction transistor is said to operate in its forward active, or linear, regime when its emitter-base junction voltage exceeds the threshold potential (Ve ≥ Veon) of the emitter-base junction and its base-collector voltage is non-positive (Vc ≤ 0); that is the base-collector junction operates at either zero bias or is reverse biased. The transistors in almost all bipolar technology circuits that are designed to operate as viable approximations of linear networks are biased in this operating domain.

Using (3-3),

c f be r bc f b f r bcI β I β 1 I β I β β 1 I , (3-15)

where the base current component, Ibe, is positive for Ve ≥ Veon. Recalling (3-10),

c r T c r Tf r V n V V n Vc f b e s f b co

r

β β 1I β I A J 1 β I I 1 ,

βe e

(3-16)

where

f rco e s

r

β β 1I A J

β

(3-17)


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is termed the collector leakage current. Specifically, Ico is the collector current fashioned by an open circuited base (Ib = 0) and a base-collector junction that is strongly reverse biased (Vc << 0). This current is small since it derives from the minority carrier injection promoted by strong reverse biasing of the base-collector junction.

There are at least two interesting aspects to (3-16). First, with Vc ≤ 0,

cc f b co f bV 0

I β I I β I ,

(3-18)

Figure (3.5). (a). Approximate equivalent circuit of an NPN BJT for the case in which the emitter-base junction

voltage, Ve, is at least as large as the threshold voltage of this junction, and the base-collector junc-tion voltage, Vc, is negative or no larger than zero. (b). Approximate equivalent circuit of a PNP BJT for the case in which Ve is at least as large as the threshold voltage of the junction, and Vc is no larger than zero.

which suggests that to the extent that parameter f is voltage and current invariant and Ico << fIb, the collector current of a BJT operated in the forward active region is directly proportional to its base current; that is, the BJT emulates input base current to output collector current linear-ity. To this end, the BJT might be modeled for Vc ≤ 0 by the simple equivalent circuits provided in Figure (3.5). Moreover, since f is a transistor metric that is significantly greater than one, the linearity between base and collector currents that is inferred by (3-18) establishes a vehicle for the realization of I/O gain from the input base terminal to the output collector terminal. A second point pertinent to (3-18) is that for Vc ≤ 0, current Ibc in (3-10) is essentially zero, which means that the base current component, Ibe, dominantly determines the observed base current, Ib. Accordingly, (3-8) and (3-10) combine to yield

e f T e f T

c

V n V V n Vc f b f be cc e s sV 0

I β I β I I A J 1 I 1 .e e

(3-19)

The last result is interesting in that it shows that in the linear domain, the collector cur-rent of a BJT is determined almost exclusively by the emitter-base junction voltage, Ve. Ac-tually, since Ic ≈ Icc ≈ βf Ibe, Ib ≈ Ibe, and Ie ≈ Icc + Ibe = (βf +1)Ibe for Vc ≤ 0, all three transistor currents, as opposed to the collector current alone, are determined almost exclusively by emitter-base junction voltage Ve. This state of affairs is cause for jubilation since a design scenario in which all three transistor currents are predicated on a single device voltage is easier to embrace analytically than is a situation in which said currents are fixed by a particular combination of two transistor voltages. It is important to understand that the transistor currents are independent of base-collector junction voltage only if the base collector junction is not forward biased. From (3-2), this requirement translates to an internal collector-emitter voltage (or emitter-collector vol-tage in PNP devices), Vb, that must equal, and likely exceed, the emitter-base junction voltage Ve. In short, forward linear active BJT operation requires Vb ≥ Ve ≥ Veon. Thus, for a homojunction BJT, Vb must be at least 700 mV, while a SiGe heterojunction BJT requires that Vb be at least as

f bI

Base Collector

Ibe

Ie

Ve

V 0 c

Ib Ic

Vb

Emitter

(a). (b).

DBE

Base Collector

Ibe

Ie

Ve

Ib Ic

Vb

Emitter

DBE f bI

V 0 c


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large as 800 mV or so.

In summary, the vast majority of BJTs deployed in linear signal processing systems are biased to operate in the forward active domain. Operation in this regime requires an emitter-base junction voltage, Ve, which exceeds the threshold potential of said junction and a base-collector junction voltage, Vc, which is no larger than zero. Equivalently, Vc ≤ 0 implies that the collector to emitter bias, Vb, for an NPN functioning in its forward active region is at least as large as is Veon. We now understand that Ve > Veon and Vc ≤ 0 gives rise to a collector current (Ic) given by (3-19). To the extent that gain parameter βf is a constant, (3-19) confirms that the collector cur-rent is linearly related to base current Ib. Despite this laudable linearity, however, the same equa-tion underscores the unfortunate fact that the collector current remains a nonlinear function of junction voltage Ve.

3.2.3.2. Reverse Active Operation

A bipolar junction transistor operating in its reverse, or inverse, active regime is the converse of forward active transistor operation. In particular, the base-collector junction poten-tial exceeds the junction threshold potential (Vc ≥ Vcon), while the emitter-base junction voltage is non-positive (Ve ≤ 0) in the inverse operating mode Transistors embedded in linear signal processing networks rarely operate as inverse devices. Indeed, device operation in this domain is invariably the result of errors either in biasing or in the electrical connections made to the transis-tor terminals. The most common connection error, especially in discrete component networks, is an inadvertent interchange of collector and emitter terminals. With Vc ≥ Vcon and Ve ≤ 0, (3-3), (3-4), and (3-8) deliver

e f T e r TV n Vf r V n Ve r b e s r b eo

f

β β 1I β I A J 1 β I I 1 ,

βe e

(3-20)

where, with an appeal to (3-17),

f r reo e s co

f f

β 1I A J I

β β

(3-21)

is termed the emitter leakage current. In particular, Ieo is the emitter current observed when the base terminal is open circuited (Ib = 0) and the emitter-base junction is strongly back biased (Ve << 0). We note that Ieo is significantly smaller than the collector leakage current, Ico, in that parameter f is much larger than inverse gain metric r.

With voltage Ve ≤ 0, current Ibe in (3-8) becomes negligible. Accordingly, the base cur-rent, Ib, in reverse active mode is largely determined by the inverse base current component, Ibc. It then follows that the emitter current in (3-20) is set by the base-collector voltage, Vc, and is essentially independent of the emitter-base voltage, Ve. But since Ib ≈ Ibc and Ic = Ie − Ib ≈ −(βr + 1)Ibc with Ve ≤ 0, all currents in a reverse active transistor are effectively determined by only the base-collector junction voltage Vc. Moreover, the pertinent magnitude of the collector cur-rent to base current ratio is seen to be (βr +1), which is far less than the base to collector transfer ratio, βf, evidenced in forward mode. In inverse mode, we note that the collector current to base current ratio is a magnitude that equates to βr. This small ratio (very small in SiGe heterojunc-tion BJTs) is reason enough to forsake reverse active operation in favor of forward active opera-tion.


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3.2.3.3. Transistor Saturation

A BJT operates in saturation when both its emitter-base and base-collector junctions are forward biased. Because of the dual junction forward bias, the base of a transistor is injected with electrons (for NPN) or holes (for PNP) from both the emitter and the collector. All three transistor currents are resultantly influenced by both of the junction voltages, Ve and Vc. Using (3-3), the collector -to- base current ratio in saturation is

r bc cccc r bccf

b be bc bc be

1 β 1 I II β 1 IIβ .

I I I 1 I I

(3-22)

Since the base current components, Ibe and Ibc, are each positive in saturation, the collector cur-rent to base current ratio in (3-22) is clearly smaller than the gain metric, βf. In other words, the collector current to base current ratio always falls below the short circuit current gain, βf, when a BJT operates in saturation. Aside from a dependence of all transistor currents on both transistor junction voltages, the degradation in I/O gain is ample reason to avoid saturation in linear BJT signal processing networks. Another reason to avoid saturation is poor frequency response since a significant amount of time is generally required to transport or otherwise displace the high den-sity of free charge that populates the saturated base. Additionally, and as we shall discuss shortly, saturation incurs current flow in the substrate body of a monolithic transistor, which can cause potentially damaging substrate heating and other detriments.

Finally, the intrinsic collector-emitter voltage in (3-2) is the difference of two positive junction voltages when the subject transistor enters its saturation regime. Because of the doping disparity between the emitter and collector volumes, this difference is always positive. It is nor-mally referenced as the collector-emitter saturation voltage, Vcesat, which is dependent on transis-tor currents and is typically in the range of 50 mV to 300 mV. We can determine this saturation voltage by solving (3-22) for the current ratio, Ibc/Ibe. Denoting this ratio by Xce,

f c bbcce

be r c b

β I IIX ,

I 1 β I I

(3-23)

which is zero if (Ic/Ib) = βf. The latter disclosure is emblematic of our engineering expectations in that (Ic/Ib) = βf in only the forward active regime of operation where the reverse current, Ibc, approaches zero. Since (Ic/Ib) is less than βf in saturation, positive Xce accompanies device saturation. The result at hand, coupled with (3-3) and (3-8), delivers

e f TV n Vce e sb ce be

f

1 X A JI 1 X I 1 ,

βe

(3-24)

whence an emitter-base junction voltage of

f b

e f Tce e s

β IV n V 1 .

1 X A Jln

(3-25)

It is interesting that operation in the saturation domain, where Xce > 0, reduces the emitter-base junction voltage from the level evidenced for a similar base current conducted by a transistor in its forward active domain. This effect is reasonable in light of the fact that in saturation, the base current is partitioned between emitter-base and base-collector current components while in the active domain, the base current is exclusively determined by emitter-base injection phenomena.

Returning to (3-23), (3-3) and (3-10) yield


- 203 -

c r Tce e s V n Vceb bc

ce ce r

1 X A J1 XI I 1 ,

X X βe

(3-26)

which establishes a base-collector junction voltage of

ce r b

c r Tce e s

X β IV n V 1 .

1 X A Jln

(3-27)

Recalling (3-2) and assuming Xce > 0, the collector-emitter saturation voltage, Vcesat, in an NPN unit (or emitter to collector saturation voltage, Vecsat, in a PNP transistor) is

f

r

nf b

ce e scesat e c T cen

ce r b

ce e s

β I1

1 X A JV V V V , X 0 .

X β I1

1 X A J

ln

(3-28)

Using (3-23), it is a simple matter to confirm that gain parameter f is always larger than the product, Xcer, and indeed, it is never equal to Xcer. It follows that the collector-emitter satura-tion voltage in (3-28) is always a nonzero and positive voltage. For the case of identical junction injection coefficients, say nf = nr = n, the small transistor saturation current, AeJs, simplifies (3-28) to

fcesat e c T ce

ce r

βV V V nV , X 0 ,

X βln

(3-29)

which suggests that the saturation voltage is nominally dependent on only the current ratio, (Ic/Ib) (because of parameter Xce), and not on the individual transistor currents, Ic or Ib.

3.2.3.4. Cutoff

There is nothing fundamentally wrong with asserting that a transistor is cutoff when ei-ther its collector current or its emitter current is zero. Formally, however, a transistor is said to be in cutoff when its emitter current, Ie is zero. You are asked to investigate this useless operat-ing case in Problem #3.3.

EXAMPLE #3.1:

In a bipolar transistor technology integrated circuit, PN junction diodes are rea-lized as appropriate connections of BJTs. Three plausible realizations appear in Figure (3.6). For each of these “diodes,” determine the volt-ampere characteris-tic equation, Id -versus- Vd, and give expressions for their effective saturation currents. Assume that the two junction injection coefficients of the transistor are identical and equal to n.

SOLUTION #3.1:

(1). In the interconnection of Figure (3.6a), the base and collector terminals are connected to-gether, thereby constraining base-collector junction voltage Vc to zero and rendering voltage Vd equal to the emitter-base junction voltage, Ve. With Vc = 0, Ibc and Irr in (3-3) are null. Thus, (3-3) and (3-8) provide


- 204 -

Figure (3.6). (a). A diode formed by short-circuiting the base to the collector of an NPN

BJT. (b). A diode formed by short-circuiting the base to the emitter of a PNP BJT. (c). A diode formed by short-circuiting the collector to the emitter of an NPN BJT.

d b c be cc f beI I I I I β 1 I . (E1-1)

Using (3-8) once again, it follows that the volt-ampere characteristic of the subject diode interconnection is

d T d Tf fV nV V nVd e s s

f f

β 1 β 1I A J 1 I 1 .

β βe e

(E1-2)

In this relationship, we witness an effective saturation current, say Io, of

f e s so e s

f f f

β 1 A J II A J .

β α α

(E1-3)

In the preceding two equations, Is = AeJs is, of course, the BJT saturation current correspond-ing to a saturation current density of Js and an emitter-base junction injection area of Ae.

(2). In Figure (3.6b), the base and emitter terminals are tied together, thereby constraining emit-ter-base junction voltage Ve to zero and rendering voltage Vd equal to base-collector junction voltage Vc. With Ve = 0, Ibe and Icc in (3-3) are zero, whence (3-3) and (3-10) yield

d c bc rr r bcI I I I β 1 I . (E1-4)

Using (3-10) the volt-ampere characteristic of the subject diode interconnection is

d T d TV nV V nVr rd e s s

r r

β 1 β 1I A J 1 I 1 ,

β βe e

(E1-5)

and the saturation current follows as

e s sro e s

r r r

A J Iβ 1I A J .

β α α

(E1-6)

(3). In Figure (3.6c), the collector and emitter terminals are interconnected, thereby rendering Vd = Ve = Vc. Accordingly, (3-3), (3-8) and (3-10) combine to give

d b be bcI I I I , (E1-7) and the volt-ampere characteristic of the subject diode interconnection is

d T d TV nV V nVd e s s

f r f r

1 1 1 1I A J 1 I 1 .

β β β βe e

(E1-8)

Clearly, the corresponding saturation current, Io, is

o e s sf r f r

1 1 1 1I A J I .

β β β β

(E1-9)

Vd Vd

Id

Id

Vd

Id

(a). (b). (c).


- 205 -

ENGINEERING COMMENTARY:

The only diode interconnection of the three considered topologies that precludes a forward biased base-collector junction is the configuration of Figure (3.6a). As is demonstrated subsequently, a forward biased base-collector junction can be detrimental in integrated bipo-lar circuits and consequently, the diode configuration of Figure (3.6a) is rightfully deemed the most efficacious of the three considered interconnections.

EXAMPLE #3.2:

A PNP bipolar junction transistor has a forward short circuit current gain, f, of 100 amps/amp, a reverse short circuit current gain, r, of 1.0 amp/amp, an emitter-base junction injection coefficient, nf, of 1.025, and a base-collector junction injection coefficient, nr, of 1.0. When operated at room temperature (27 °C), the collector current, Ic, in a particular circuit is measured to be 2 mA, while the base current is determined to be 200 A. Calculate the emitter-collector saturation voltage, Vecsat. Assume temperature saturation current, Is, of 2 fA at room temperature.

SOLUTION #3.2:

(1). Since Ic/Ib in this example is 2 mA/200A = 10, which is smaller than f, the subject transistor is saturated. For the quoted parameters and Ic /Ib = 10, equation (3-23), which is applicable for NPN and PNP units alike, delivers a recombination current ratio of Xce = Ibc/Ibe = 7.50.

(2). At a junction temperature of Tj = 27 C, the Boltzmann voltage, VT, is VT = 25.89 mV. With Xce = 7.50, (3-28) resultantly delivers an emitter-collector saturation voltage of Vecsat = 85.05 mV.


As confirmed above, the emitter-collector saturation voltage is a small, positive number. We should appreciate, however, that the measured value of this metric is somewhat larger owing to ohmic resistances in the collector and emitter leads of the transistor. The nature and effect of these resistances are addressed shortly.

The fact that Xce is 7.50 indicates that the reverse, largely recombination, current precipitated by base region mobile carriers and collector-injected carriers is 7.5-times larger than the forward recombination current attributed to base region and emitter-injected carriers. In general, Xce > 1 is the norm in that the base region doping concentration is larger than the collector impurity concentration, which in turn is several orders of magnitude smaller than the impurity concentration in the emitter volume.

3.2.4. ENHANCEMENTS TO THE EBERS-MOLL MODEL

Despite its better than half century age, the Ebers-Moll model remains a viable design tool for manually estimating bipolar circuit performance. Viability notwithstanding, numerous enhancements to the model demonstrably improve its accuracy, particularly for scaled, minimal geometry, monolithic bipolar devices. A definitive discussion, yet alone a satisfying mathemati-cal derivation, of all of the modeling improvements promoted by the archival literature in the al-most six decades since the original publication of the seminal Ebers and Moll paper is beyond the scope of this chapter. However, four specific modeling enhancements are potentially vital to support realistic design-oriented analyses of monolithic circuits that exploit state of the art bipo-


- 206 -

lar devices in linear circuit applications. These improvements entail corrections for the transport current in the face of high levels of emitter to base carrier injection, adjustments to the transport current necessitated by base conductivity modulation, parasitic ohmic resistances in the base, emitter, and collector, and incorporation of high frequency effects on the I/O transfer characteris-tics. The consideration of these enhancements in the subsections that follow pertain only to the linear forward active regime of BJT operation (Ve ≥ Veon and Vc ≤ 0) since the focus of this chap-ter, and indeed the majority of this text, is circuit analysis that underpins the design and realiza-tion of linear active networks.

3.2.4.1. High Injection Phenomena

The Ebers-Moll model implicitly presumes low carrier injection conditions. For for-ward active operation, low injection is tantamount to restricting the concentration of injected carriers from the emitter to the base to a level that is significantly smaller than the background impurity concentration in the base volume. As the injected charge level rises toward the level of the base dopant concentration, a high injection condition is initiated, which manifests impaired carrier mobility owing to the traffic jam of minority carriers that arises in the base. One upshot of degraded carrier mobility is an increased likelihood of carrier recombination, thereby resulting in diminished charge transport into the collector volume and hence, a reduced collector current. For the large geometry transistors of decades past and for present day discrete component, off the shelf, transistors, low injection presumptions are suitable. But low injection presuppositions be-come progressively more questionable as transistor geometries shrink to the submicron scale that is commonplace in the monolithic state of the art.

The Gummel-Poon model of a BJT accounts for the foregoing high injection effects by supplanting the transport current, Icc, in (3-5) with a corrected, and indeed reduced, transport cur-rent, Ict. This corrected transport current is given by[4]

cc ccct

cc cc

kf e kf

I II ,

I I1 1

I A J

(3-30)

where Ikf is termed the forward knee current of the bipolar device, and Jkf is the corresponding density of the forward knee current[5]. The knee current parameter is nominally proportional to the average impurity concentration in the base volume. It assumes a barometric stature of measuring the onset of high injection phenomena in the sense that Icc << Ikf is indicative of low injection circumstances. When Icc, which remains given by (3-5), is significantly smaller than Ikf, we see that Ict in (3-30) collapses to the conventional transport current advanced by Ebers and Moll. Engineering logic alone dictates this result. For minimal geometry homojunction transis-tors, current Ikf is in the neighborhood of a few to low tens of milliamperes. Because the base volume of a SiGe HBT is doped higher than is the base volume of a conventional BJT, SiGe heterojunction BJTs boast larger values of parameter Ikf.

We can glean a fundamental understanding of the impact of high injection phenomena on bipolar transistor performance by examining the model in Figure (3.7), which depicts the cor-rected form of the large signal bipolar model. Only an NPN model is drawn since the PNP model is little more than its NPN counterpart with the current directions and voltage polarities reversed. The model clearly establishes a collector current, Ic, of[6]


- 207 -

ccc ct

cc

e kf

II I .

I1

A J

(3-31)

At low injection levels,

Figure (3.7). Linear active region model of an NPN BJT with a

correction adopted for high injection effects on carrier transport. The current, Ict, is given by (3-30). The indi-cated junction voltage, Ve, must be at least as large as the threshold voltage, Veon, of the emitter-base junction.

e f TV n Vc ct cc e sI I I A J ,e (3-32)

where the unity term in the parenthesized quantity on the right hand side of (3-5) is ignored in deference to the requirement that Ve be at least as large as the emitter-base junction threshold potential. On the other hand, at the high levels of carrier injection that attempt to manifest large forward transport currents, Icc, we see that (3-31) approaches

e f TV 2n Vc ct e kf cc e kf sI I A J I A J J .e (3-33)

Note that while the natural logarithm of the low injection collector current in (3-32) rises linearly with Ve /nfVT, the logarithm of the high injection collector current in (3-33) rises less dramatically with voltage Ve. Indeed, the subject logarithmic rate of rise is linear with Ve /2nfVT. It follows that the sensitivity of the collector current to forward emitter-base junction voltage is reduced at the onset of high injection phenomena. This reduced sensitivity at high injection makes engineering sense. Since the traffic jam in the base of injected electrons impairs electron mobil-ity, the prospects for base region recombination are enhanced. Even for those electrons that es-cape recombination, the impaired carrier mobility increases the average time required to transport electrons across a strongly injected base. In effect, we can summarily argue that the transport efficiency of electrons across the base-collector junction under high injection condi-tions no longer matches the emitter to base electron injection efficiency evidenced at low injec-tion.

A related high injection phenomenological effect is an attenuation of the static current transfer ratio, Ic /Ib. Recalling (3-3) and (3-8), the Ebers-Moll, or low injection, BJT model pre-dicts Ic/Ib ≈ f in the linear domain. But noting that Icc = f Ib in this regime, (3-31) predicts

c f

b cc

e kf

I β.

I I1

A J

(3-34)

ctI

Base Collector

Ibe

Ie

Ve

Ib Ic

Emitter

DBE

V 0c

Vb


- 208 -

This current transfer relationship is traditionally symbolized as hFE, which is commonly called the DC beta, or static beta, of a transistor. Somewhat distressingly, we now note that this current transfer ratio is no longer a constant but is, in fact, a nonlinear function of the forward transport current. At this stage of our model refinement, we have

c f fFE

b cc e kf cc kf

I β βh .

I 1 I A J 1 I I

(3-35)

As is demonstrated in discussions surrounding the design of suitable biasing networks for bipolar technology circuits, hFE is a troublesome parameter largely because of its direct dependence on parameter βf. In particular, the numerical value of βf suffers a numerical variance of at least three to one owing to process uncertainties surrounding the realization of a deep submicron base width. The problem stems from the fact that βf is inversely dependent on the base width, whose control at submicron dimensions proves to be a daunting challenge. The early design lesson we should grasp here is that bipolar circuit design should be accomplished to ensure that critical performance metrics are not directly dependent on the vagarious parameter, hFE.

3.2.4.2. Base Conductivity Modulation

The BJT model in Figure (3.7) represents the collector-emitter port of the transistor as an ideal controlled current source, Ict. This collector current is independent of the internal collec-tor-emitter voltage, Vb, and thus, it is therefore independent of the base-collector junction vol-tage, Vc. But the transport efficiency of emitter-injected charge through the base and on into the collector is intuitively promoted by applying a reverse bias across the base-collector PN junction. This junction reverse bias can be achieved through increases in the internal collector-emitter vol-tage, Vb. We assert this recommendation because of (3-2). In that relationship, an increase in voltage Vb presumably incurs an increase in voltage Ve, the forward biasing potential across the intrinsic emitter-base PN junction. To be sure, a modest increase in Ve can be expected. But large changes above the junction threshold level, Veon, are not possible because of the exponen-tial volt-ampere nature of a PN junction diode. Thus, most of the increase afforded to voltage Vb is transferred to increasing (−Vc), which is to say that an increase in Vb is tantamount to an en-hanced reverse bias across the base-collector junction.

The enhanced transport current promoted by increases in voltage Vb is known as the Early effect[7]2. Two engineering reasons serve to explain this transport current phenomenon. First, an increased Vb results in increased reverse bias across the base-collector junction, as noted above. This boost in reverse bias establishes stronger electric fields in the depletion layer surrounding the base-collector junction. In turn, these robust fields exert attractive forces on the mobile carriers that are injected into the base volume from the emitter region. Aside from encouraging charge transport through the base volume and hence, increased collector current, such attractive forces serve to inhibit recombination between emitter-injected and base region carriers. Second, the increased reverse bias at the base-collector junction widens the junction depletion layer about that junction. The immediate result of this depletion zone widening is a narrowing of the neutral base width, which further decreases the likelihood of recombination of injected carriers with majority carriers in the base. Stated quite simply, the charge neutral base volume, where recombination is most likely to occur, is reduced to a base width −commonly called the electrical base width− that is smaller than the geometric base width. Collectively, the

2 The “Early effect” has nothing to do with time. The name of this high injection effects derives from the work of Dr. James Early, who was renowned technical creativity and leadership at Fairchild Semiconductor Corporation.


- 209 -

two reasons we have articulated herewith argue that increased base-collector reverse bias embel-lishes the conductivity of the neutral base so that charge transport through the entire base is correspondingly promoted.

A physically sound model for the foregoing base conductivity modulation, or Early ef-fect, proves too cumbersome for manual estimates of static BJT performance. Instead, an empirical representation of the form,

bcc

af b bc ct ct

af af ctcc kf

VI 1

V V VI I 1 I ,

V V I1 I I

(3-36)

is adopted for circuit level modeling, where Ict is given by (3-31) and voltage Vaf is an experimentally discerned Early voltage parameter, whose value for minimal geometry transistors is typically in the mid tens of volts. In contrast, Vaf can be in the neighborhood of the mid tens to low hundreds of volts in SiGe HBTs. We hasten to interject that the modified volt-ampere model postured by (3-36) is embedded in the basic BJT circuit models that are commonly em-braced by SPICE simulation software. The resultant electrical model for the NPN device is shown in Figure (3.8), where we note that the appended parenthesized term on the right hand side of (3-36) establishes a current-dependent resistance. This resistance, whose value is in-versely proportional to current Ict, is in shunt with the controlled source, Ict, which renders the current source signifying current Ict a non-ideal source. In effect, the collector-emitter port is a Norton equivalent circuit that boasts finite shunt resistance.

Figure (3.8). Linear forward active region model of an NPN BJT with an ac-

count made of both high injection and base conductivity modula-tion (Early effect) phenomena.

We must now update the static current gain of the transistor to the slightly more complicated form,

b bf f

af afcFE

b cc cc

e kf kf

V Vβ 1 β 1

V VIh .

I I I1 1

A J I

(3-37)

Observe that the behavioral expression for the Early effect in (3-36) and in the current gain expression at hand somewhat mitigates the deleterious impact of high injection phenomena, at least insofar as the current transfer ratio is concerned. This observation synergizes with the com-mon circuit design practice of invoking only the Ebers-Moll model to deduce a quick and reasonable first order estimate of static BJT performance.

ctI

Base Collector

Ie

Ve

Ib Ic

Vb

Emitter

DBEVaf

Ict

V 0c


- 210 -

3.2.4.3. Parasitic Resistances

The circuit in Figure (3.8) models only intrinsic transistor action in that the voltages appearing at the terminals of the transistor are identical to internal emitter-base junction voltage, Ve, internal base-collector junction voltage, Vc, and internal collector-emitter voltage, Vb. In practical transistors, these internal voltages couple to the accessible external terminals of the de-vice through series ohmic resistances that are associated with the charge neutral regions of the emitter, base, and collector volumes. In other words, the internal junction voltages link to the corresponding external transistor terminals through resistances.

Figure (3.9). (a). The NPN BJT model of Figure (3.8) embellished by the incorporation of series

resistances re, rb, and rc in the emitter, base, and collector leads, respectively. For most modeling circumstances, resistances re and rc can be ignored. (b). The PNP model counterpart to the NPN model in (a).

The extremely high impurity concentration in the emitter volume, together with its short geometric length, promotes a series emitter resistance, re, that is very small. Values of resistance re that are larger than a few tenths of an ohm are rare. At the collector, a resistance, rc, appears as depicted in the revised model of Figure (3.9), in which both NPN and PNP models are offered in the interest of completeness. Because of the length of the collector region and its low impurity concentration, resistance rc is relatively large. For minimal geometry devices destined for broadband circuit applications, rc is in the range of mid tens of ohms to as much as low hun-dreds of ohms. Both rc and re scale inversely with the emitter-base junction area, Ae, and since both are physical ohmic resistances, both contribute thermal noise to the total integrated output

Base Collector

Ie

Ibe

Ib Ic

Vce

Emitter

DBEVaf

Ict

rc

re

rb

Vbe

(a).

Base Collector

Ie

Ibe

Ib Ic

Vec

Emitter

DBEVaf

Ict

rc

re

rb

Veb

(b).

V

b

V

e

V

b

V

e

ctI

V 0c

V 0c

ctI


- 211 -

noise generated by the biased transistor.

The base resistance, rb, like emitter resistance re and collector resistance rc, is an ohmic element that generates thermal noise and scales inversely with the emitter-base junction area. Owing to the inherently two-dimensional nature of the volt-ampere characteristics in the base region and emitter crowding, rb, is current dependent[8],[9]. The phrase, “emitter crowding,” re-fers to an inability to establish uniformly constant voltage bias across the width of the emitter-base junction of a monolithic device. As a result, carrier injection densities crowd to those por-tions of the emitter-base junction that support comparatively larger forward biasing.

A commonly invoked empirical expression for the base resistance of a bipolar device subjected to emitter crowding is

Figure (3.10). The dependence of the internal base resistance, rb, on the collector current flowing in a bipolar

junction transistor.

bb bm

b bmc rb

r Rr R ,

1 I I

(3-38)

where Ic is the collector current, Irb is an experimentally deduced constant that scales with emit-ter-base junction area, Rbm is the minimum base resistance (typically tens of ohms as extrapolated from high current measurements), and rbb is the zero bias (meaning Ic = 0) value of the measured base resistance. For minimal geometry transistors, current parameter Irb is generally of the order of one-half the transistor forward knee current, Ikf, while resistance rbb can be as large as a few hundred ohms. For the same emitter-base cross section area, Rbm and rbb are smaller in SiGe structures than they are in homojunction transistors since SiGe HBTs boast relatively large do-pant concentrations in their base volumes. Figure (3.10) displays a plot of the normalized base resistance, rb/rbb, versus the normalized collector current, Ic/Irb, for various resistor ratios, rbb/Rbm. Notice that a better than two factor between the actual base resistance, rb, and its zero current value, rbb, is possible for even reasonable values of collector current. Large base resistance

0

0.2

0.4

0.6

0.8

1

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Norm. Collector Current, (I c/I rb )

Norm. Base Resistance, (r b/r bb)

r bb /R bm = 2

r bb /R bm = 4

r bb /R bm = 20

r bb/R bm = 10


- 212 -

generally reflects worst case operating conditions, in the senses of incurring reduced I/O voltage gain, compromised bandwidth, and increased thermal noise contribution to the net integrated out-put noise of a transistor. For this reason, designers executing a pre-computer-aided design assessment typically adopt the conservative worst case condition of allowing the base resistance to equal its zero current value, which by (3-38) and our mathematical powers, is rbb.

3.2.4.4. Transistor Capacitances

A realistic assessment of the impact exerted by high signal frequencies on transistor cir-cuit performance is a challenging undertaking that requires a careful consideration of charge sto-rage and related memory effects that prevail within the semiconductor body of a BJT. At the cir-cuit level, at least three capacitances must be incorporated into the transistor model to establish an upper bound on the deleterious effects that high signal frequencies have on BJT circuit res-ponses. These capacitances are the emitter-base capacitance, Cπ, the base-collector junction depletion capacitance, Cμ, and the substrate depletion capacitance, Cs, as we depict in the high frequency NPN BJT model set forth in Figure (3.11). An analogous model prevails for PNP de-vices, wherein all current directions, all voltage polarities, and all branch diodes are reversed.

Figure (3.11). High frequency model of the NPN BJT. The high frequency model of a PNP BJT is topologically

similar, with the provisos that the connections of both diodes are reversed, all voltage polarities are reversed, and the directions of all currents are reversed. Ordinarily, the substrate terminal is incident with signal ground.

As in the case of a forward biased PN junction diode, a shunt interconnection of two capacitances model the high frequency effects at the forward biased emitter-base junction of a BJT operated in the linear active mode. The dominant component of these two capacitances is the emitter-base diffusion capacitance, Cbe. It is reminiscent of the diffusion component of the net PN junction diode capacitance in that it models the effects of charge stored temporarily in the volume prior to either its transport through the base volume or recombination with free holes that reside in the base volume. This diffusion component, Cbe, of emitter-base junction capacitance is given by

be fe mC τ g , (3-39)

where τfe is the average time required to transport minority carriers through the base region and gm represents the forward transconductance of the BJT. Parameter τfe is naturally affected by the average mobility of the minority carriers that prevail in base region subsequent to their injection from the emitter volume. Since minority carrier mobility diminishes with the increasingly large carrier concentrations that necessarily underpin substantial forward transport current in a BJT, τfe rises with progressively larger collector currents. In short, increased device capacitances and the

ctI

Base Collector

Ie

Ibe

Ve

Ib Ic

Vce

Substrate

DBEVaf

Ict

rc

re

rbb

Vbe

C

C

DSC CsVsc

V 0c

Emitter

Vb


- 213 -

potentially slower circuit response speeds that may accompany this increase are expected when BJTs are conduct relatively large collector currents. The degradation of transport time induced by pronounced carrier concentrations in the base is somewhat mitigated by the imposed base-collector junction reverse bias, which exerts an attractive force on carriers injected into the base from the emitter. Accordingly, a plausible semi-empirical relationship for the effective minority carrier transport time, τfe, in (3-39) is

c kffe fo

b af

1 I Iτ τ ,

1 V V

(3-40)

where τfo is the low current (small Ic) and Vc = 0 value of the minority carrier transport time in the BJT. Observe that the expression in question allows τfe to increase with progressive increases in the collector current, Ic, which is given by (3-31). On the other hand, (3-40) permits τfe to de-crease with increasing Vb, which accounts implicitly for the charge attraction ramifications of reverse bias imposed across the base-collector junction. An important, engineering lesson sur-faces herewith. In particular, increasing Vb reduces τfe, and hence device capacitance Cbe, which conflates with the design goal of faster circuit responses. But Vb increases only if a suitably larger voltage, Vce, biases the collector-emitter terminals of an NPN transistor (Vec for its PNP brethren). In turn and for a given collector current, increased Vce increases the power dissipated in a BJT, which upholds the philosophical banner that the likely price paid for improved circuit response speeds or wider bandwidth is increased circuit power dissipation. In a word, if you want more performance, the cost is more power dissipation, which translates directly to de-creased battery life in portable electronics. Get your battery chargers ready!

Continuing with (3-40), parameter τfo is typically in the range of tens to hundreds of picoseconds for minimal geometry transistors. For silicon-germanium HBTs, fo can be as small as only a few tenths of a picosecond. Since parameter τfo is nominally proportional to the square of base width Xb in Figure (3.1), a progressive narrowing of the base theoretically returns dra-matic dividends insofar as reducing the emitter-base diffusion capacitance, Cbe. There are, how-ever, limits to the tolerable base region narrowness. In particular, too narrow a base promotes a voltage breakdown condition known as punch through. In this undesirable situation, a suffi-ciently lsrge reverse bias imposed at the base-collector junction allows the base side boundary of the base-collector depletion layer to encroach upon, and even coalesce with, the base-side boun-dary of the emitter-base depletion layer.

Finally, the transconductance metric in (3-39) is, using (3-36),

c c c bm

e f T afcc kf

I I I Vg 1 1 .

V n V V2 I I

(3-41)

Assuming that voltage Vb is much smaller than the Early voltage, Vaf, as is often the case in well-designed, high performance BJT networks, (3-36) combines with (3-41) to deliver

cc kfcm

f T cc kf

1 I 4IIg .

n V 1 I I

(3-42)

The last result portrays the forward transconductance as increasing linearly with collector current Ic with a slope, dgm/dIc, of roughly 1/nfVT at the low injection levels implied by Icc << Ikf. Under high injection conditions, transconductance gm continues to increase with Ic, but at a slope, dgm/dIc, that is a factor of two smaller than that which we witness at low current levels. We are lucky, for yet another electronics lesson surfaces for us without additional financial charge.


- 214 -

Specifically, transconductance gm is a measure of attainable I/O gain in a BJT network. In-creased gain potential accrues with increased gm, which mandates robust collector current. But the aforementioned slopes suggest that diminishing returns accrue as currents approach levels commensurate with the high injection state. And, of course, increased collector currents, just like increased collector-emitter voltage, promote the dubious distinction of a circuit that burns more power.

Although the emitter-base junction is forward biased in the linear active mode of BJT operation, a narrow depletion layer nonetheless prevails at this PN junction. Accordingly, the second component of the net emitter-base junction capacitance is the depletion capacitance, Cje, of the junction depletion layer. Under forward biased circumstances, this capacitance, which is analogous to the depletion component of capacitance prevailing in a forward biased PN junction diode, is given approximately by

e

jeoje m

eon

je

CC ,

V1

V

(3-43)

where Cjeo is the zero bias (meaning Ve = 0) value of the junction depletion capacitance, Vje is the built-in potential of the emitter-base junction, and me is the grading coefficient of the subject junction. The potential, Vje, is typically in the range of 800 mV to 900 mV, while parameter me is usually close to 0.5. It is understood that capacitance Cjeo scales linearly with the emitter-base junction area, Ae. In summary, the net emitter-base junction capacitance, Cπ, as delineated in Figure (3.11), is, recalling (3-39), (3-40), (3-41), and (3-43),

e

fo c jeoc c bbe je m

f T kf afcc kfeon

je

τ I CI I VC C C 1 1 1 .

n V I V2 I IV

1V

(3-44)

Since the base-collector junction of a BJT is reverse biased under forward active circumstances, the capacitance, Cμ, in Figure (3.11) is exclusively a depletion capacitance. Accordingly, it is given by the familiar mathematical form,

c

jcoμ m

c

jc

CC .

V1

V

(3-45)

In (3-35), Cjco is the zero bias (meaning Vc = 0) value of the base-collector junction depletion capacitance, Vjc is the built in potential of the base-collector junction (of the order of 700 mV to 800 mV), and mc is the grading coefficient of the junction. Typically, 1/3 ≤ mc ≤ 1/2. Capacit-ance Cjco, like Cjeo, scales linearly with the emitter-base junction area.

3.2.4.5. Substrate Capacitance and Other Monolithic Parasitics

Monolithic technology has swallowed most of the recently developed, low power, state of the art electronic systems. It is easy to understand the popularity −indeed dominance− of inte-grated circuits in light of the increased response speed and enhanced bandwidth, radically dimi-nished size, improved reliability, and a plethora of other advantages that pervade the monolithic


- 215 -

art. But while the positive attributes of integrated circuit technologies outweigh their negative aspects, there are, to be sure, potential shortfalls that must be carefully assessed, understood, and mitigated. One such downside is the high cost of integrated circuit realization. The high cost of manufacturing that first wafer of acceptable high performance chips might not be justified unless the market for the realized circuit chips is sufficiently large. Testing issues are also demanding, largely because the small surface footprints associated with a monolithic realization of an elec-tronic network tempts us to incorporate progressively more features on chip. Many of these additional features commonly address enhanced information processing and transmission requirements, which mandate significantly wide bandwidths that may prove challenging to achieve reproducibly and reliably. These wide bandwidth circuits often prove difficult to test satisfactorily. Other integrated circuit shortfalls, as we shall discuss herewith, embrace substrate parasitics that, in addition to incurring bandwidth degradation, can actually be so severe as to cause catastrophic, thermally induced chip failures. Fortunately, thoughtful design approaches premised on insightfully understood circuit and system concepts usually produce viable, if not creative, solutions to the dilemmas encountered.

Figure (3.12). Simplified cross section representation of a monolithic NPN bipolar junction transistor. The dia-

gram is not drawn to scale. The section of the diagram enclosed by the dotted rectangle is the intrinsic transistor. It corresponds to the cross section abstraction appearing in Figure (3.1a).

We initiate our focus on substrate issues by examining carefully the substrate diode, DSC in Figure (3.11), and its associated substrate capacitance, Cs. To this end, a simplified cross section of an NPN monolithic BJT is provided in Figure (3.12). The vertical part of the diagram enclosed by the dotted rectangle lying directly under the emitter terminal and consisting of the n+-emitter, the p-type base, and the n-type collector is the intrinsic transistor and corresponds to

P-Type Substrate

N+ Buried Layer

N+ TypeEmitter

P-TypeBase

N-TypeCollectorN

+ C

olle

ctor

Con

tact

Silicon Dioxide

P+

Su

bstr

ate

Con

tact

P+

Su

bstrateC

ontact

Substrate Collector Base EmitterSubstrate

IntrinsicTransistor


- 216 -

the simplified BJT structure in Figure (3.1a). Since all terminal contacts are necessarily formed at the surface of the structure, the collector metal contact is incident with a heavily doped dif-fused or implanted collector contact to reduce the parasitic series resistance associated with the collector. A further reduction in this series resistance is fomented by assuring that this n+-collec-tor contact is deep enough to coalesce with the n+ buried layer that abuts the lightly doped intrin-sic collector region. The entire structure rests atop a lightly doped p-type substrate to which electrical accessibility is provided at the surface through dual p+-substrate contacts. Aside from allowing an electrical contact to the substrate foundation of the NPN transistor, these deep sub-strate contacts create a mechanism to isolate the subject NPN device from proximately located other chip transistors. The isolation proves effective if the substrate terminal at the transistor sur-face is incident with the most negative potential afforded by the circuit in which the NPN transis-tor is electrically embedded. This electrical connection ensures nominally non-conductive, re-verse biased PN junctions around the periphery of the NPN unit. In effect, the reverse bias at the collector-substrate junctions renders the NPN transistor a virtual electrical island in a sea of potentially many other active and passive devices that are incorporated on the subject chip. Elec-trical contact is similarly made to the p-type base by doping the base region adjacent to the emit-ter region sidewalls at a level that is higher than the impurity concentration of the intrinsic base immediately below the emitter. In addition to mitigating the effects of work function phenomena between metal contact and semiconductor and reducing the series base resistance, this doping gradient minimizes carrier injection from the emitter to the base along the emitter sidewalls, the-reby rendering the simplistic diagram in Figure (3.1a) reasonably reflective of the transistor ac-tion implied by the cross section under present consideration.

Our study of the diagram in Figure (3.12) reveals that in addition to realizing the de-sired vertical NPN transistor, a parasitic PNP device, QP, is forged with the p-type substrate, the n-type collector and the p-type base. While a parasitic PNP transistor is unquestionably formed, questions can be raised as to whether its emitter is the NPN substrate or the base region of the desired NPN unit. These questions can be answered only when the nature of the electrical connection made to the substrate contact is clarified.

Figure (3.13). (a). Behavioral representation of a monolithic NPN transistor for the case in which the sub-

strate is biased to a potential that is larger than the potential applied to the collector of the NPN device. (b). Behavioral representation of a monolithic NPN transistor for the case in which the substrate is returned to the most negative circuit potential afforded by the circuit into which the NPN transistor is embedded.

Base

Emitter

QP

Collector

Substrate

(a).

Base

Emitter

QP

Collector

Substrate

(b).


- 217 -

To the foregoing end, consider the atypical case in which the substrate is not connected to the most negative of available circuit potentials and instead supports a voltage with respect to ground that is larger than the voltage developed at the collector of the NPN transistor. Because the substrate-collector junction is forward biased, the substrate can rationally be viewed as the emitter of parasitic transistor QP, and the resultant circuit level abstraction becomes the structure we show in Figure (3.13a). The forward bias across the substrate-collector junction allows holes from the substrate to be injected into the NPN collector region, particularly in the substrate-collector junction neighborhood lying to the right of the buried layer. Given that the base-collec-tor junction of the NPN device is reverse biased for forward active operation, the base-collector junction of QP is correspondingly reverse biased. Traditional transistor action through the PNP device is therefore fostered, which means that the base current conducted by the vertical NPN device is perturbed by the collector current of the parasitic PNP transistor. In extreme cases, the observed base current of the vertical NPN transistor may actually flow out of the device, as op-posed to its normal directional flow, which is into the NPN base terminal. Assuming that the DC beta of QP is greater than one, the immediate impact of this enhanced NPN base current is a reduction of the available current transfer ratio, hFE, for the NPN unit. Obviously, the power dissipation of the overall structure increases because the substrate now conducts the current that is demanded by the emitter of transistor QP. This substrate flow can cause potentially damaging heating effects in the relatively high resistivity substrate volume.

When, as is routinely required in linear signal processing applications, the substrate is connected to the most negative circuit potential, the substrate-collector PN junction is reverse biased. Accordingly, the substrate is precluded from serving as a PNP transistor emitter that in-jects holes into the NPN collector, or equivalently, the PNP base. Instead, the substrate acts as the collector region of transistor QP, thereby permitting the base of the NPN structure to be deli-neated as the emitter of QP, as shown in Figure (3.13b). The routine reverse biasing of the base-collector junction of the NPN transistor operated in its forward active mode imposes a reverse bias across the emitter-base junction of transistor QP. Consequently, QP conducts only leakage current and therefore exerts minimal impact on the operation of the target NPN device, least at low signal frequencies. At high signal frequencies, the base-collector depletion capacitance of QP can be absorbed into capacitance Cμ of the NPN transistor. Moreover, the reverse biased PN junction diode observed at the QP emitter-base junction shunts the reverse biased diode evi-denced at the NPN base-collector junction. The reversed biased substrate-collector junction can be modeled as a shunt interconnection of a reverse biased diode, DSC, and the depletion capacit-ance, Cs, associated with the substrate-collector junction. The foregoing capacitance item as-sumes its usual depletion capacitance form,

s

sos m

sc

js

CC ,

V1

V

(3-46)

where Vsc is the reverse biased, and therefore negative, voltage established across the substrate-collector junction, Vjs is the built in potential of said junction, ms is the grading coefficient of the subject junction, and Cso is the Vsc = 0 value of the substrate-collector depletion capacitance. For a properly biased, minimal geometry, high speed NPN transistor, Vjs is in the range of 550 mV to 700 mV, ms is of the order of one-third, and Cso is generally a few femtofarads to tens of femtofa-rads.


- 218 -

The base-collector junction of the NPN transistor is forward biased when this device enters its saturation domain. Correspondingly, the emitter-base junction of the parasitic PNP de-vice in Figure (3.13b) mirrors this forward biasing, which, along with the imposed reverse bias at the substrate-collector junction, forces QP to conduct and actually to function in its forward ac-tive domain. The result is a degraded short circuit current gain in the NPN transistor, whose base must now supply current to the PNP emitter. Aside from degraded current gain, the power dissipation of the entire structure increases and undesirable heating of the substrate is incurred because of the collector current manifested in transistor QP. These observations support our ear-lier contention that BJT operation in saturation must be avoided.

3.3.0. SMALL SIGNAL MODEL

We now know that in order for a bipolar junction transistor to function nominally as a linear signal processor, it must be biased in its forward active domain. As we have previously asserted, the prerequisites that cultivate operation in this linear domain are that the emitter-base junction voltage, Ve, must be at least as large as the junction threshold voltage, Veon, and the base-collector junction voltage, Vc, must be negative or zero. The latter requirement is equivalent to stipulating an internal collector-emitter (or emitter-collector in PNP devices) voltage, Vb, which is equal to or greater than the emitter-base junction voltage, Ve. For monolithic devices, an addi-tional necessity is that the substrate terminal be returned to the most negative potential available in the circuit into which the transistor is embedded. These biasing constraints coalesce to estab-lish a quiescent collector current, say IcQ, and corresponding base and emitter quiescent currents, IbQ and IeQ, respectively. Specifically,

bQ cQ FE

cQ cQeQ bQ cQ FE bQ FE

FE FE

I I h

,I II I I h 1 I h 1

h α

(3-47)

where hFE is given by (3-37), and

cQ FEFE

eQ FE

I hα

I h 1

(3-48)

is nearly unity because hFE >> 1. These three static BJT currents are determined largely by the quiescent emitter-base junction voltage, VeQ, and hence, they are essentially stipulated by the Q-point value of the voltage, VbeQ, applied to the emitter-base terminal. The three BJT currents are far less sensitive to the Q-point collector-emitter terminal voltage, VceQ. From Figure (3.11), we see that voltages VbeQ and VceQ can be expressed as,

beQ bQ bb eQ eQ e

ceQ cQ c bQ eQ e

V I r V I r.

V I r V I r

(3-49)

Since VeQ > Veon and all transistor currents are nonzero and positive in the forward active regime, VbeQ > VeQ > Veon. In actual practice, the Q-point base current and series emitter resistance are so small that VbeQ can be approximated by VeQ. Moreover, recall that the requirement that VcQ, the Q-point value of the internal base-collector voltage, not exceed zero gives rise to the static operating constraint, VceQ VbeQ.

In the forward active domain, the small signal model of either an NPN or a PNP bipolar junction transistor is the structure depicted in Figure (3.14). The subject model is burdened by


- 219 -

two caveats. First, it is presumed that the model is typically exploited to arrive at conservative estimates of bipolar circuit performance. Thus, the current-dependent resistance, rb in (3-38), is supplanted by the maximum anticipated base resistance, rbb, which simplifies relevant circuit analyses in that resistance rbb is current invariant. Second, the substrate is presumed connected to the most negative of available circuit potentials. This means that the substrate-collector PN junction diode, DSC in Figure (3.11), can be ignored for small signal analyses since it is reverse biased and therefore conducts only small leakage currents. In light of the fact that the substrate is connected purposefully to a suitable constant potential that is either circuit ground or a static voltage lying below circuit ground, the substrate lies at signal ground potential. In other words, no signal is supported by the substrate terminal. As witnessed in the small signal model of a PN junction diode, the BJT model at hand is capable of establishing only the appropriate linear interrelationships among the signal components of all node voltage and branch current variables in the transistor model. It cannot predict Q-point voltages and currents. Indeed, the parameters of the small signal model rely a priori on the numerical values of these Q-point currents and vol-tages.

Figure (3.14). Approximate small signal model of either an NPN or a PNP bipolar junction transis-

tor. The model presumes that the transistor undergoing study is biased in its forward active domain, which in turn presupposes that the substrate terminal is incident with the signal ground of the circuit into which the transistor is embedded. In the absence of specific model information, resistances rc and re are often ignored.

In the model of Figure (3.14), rbb, re, and rc, are physical resistances that account for voltage drops incurred by currents flowing in the charge neutral regions of the base, emitter, and collector, respectively. On the other hand, the resistance, rπ, is a mathematical artifact arising from a linear representation of the volt-ampere characteristics indigenous to the emitter-base junction diode. In particular, if the dependence of the forward base current component, Ibe, on internal emitter-base junction voltage is approximated by only the linear terms in its Taylor se-ries expansion about the transistor operating point established in part by Ve = VeQ,

e f TV n Vcc e s bebe beQ e eQ

f f e Q

I A J II 1 I V V .

β β Ve

(3-50)

With reference to Figure (3.14) and our experience with the small signal modeling of the PN junction diode, (Ve − VeQ) in this relationship is the signal-induced change, V, across the internal emitter-base junction terminals and (Ibe − IbeQ) is the corresponding signal induced change, I, in the forward base current. Accordingly, resistance rπ in the subject model derives from

e f TV n V beQbe e s

Qπ e f T f f TQ

II A J1.

r V n V β n Ve

(3-51)

Given that current IbeQ closely approximates the quiescent transistor base current, IbQ, in the li-near forward region of operation, (3-47) combines with (3-51) to deliver

rbb rc

r

re

roC Cs

C

g Vm

Base

Emitter

Collector

Substrate

V

I


- 220 -

f T f T FE f Tπ

beQ bQ cQ

n V n V h n Vr .

I I I (3-52)

We see that for a given quiescent collector current, IcQ, the small signal resistance, rπ, is directly proportional to the gain metric, hFE, whose measured value suffers significant variance due to processing uncertainties. Additionally, the inverse dependence of rπ on Q-point collector cur-rent, along with the direct dependence of Boltzmann voltage VT on absolute temperature, renders it dependent on junction temperature Tj. It is possible to mitigate the temperature dependence of resistance rπ through a biasing design that ensures a quiescent collector current proportional to absolute temperature. This specialized type of bias design is commonly referred to as a PTAT design.

Like rπ, the Early resistance, ro, in Figure (3.14) is also a mathematical artifact. But in contrast to rπ, which derives from a consideration of the volt-ampere characteristics of the emit-ter-base junction, ro pertains to a different volt-ampere consideration. In particular, ro is related to a coefficient in a linear truncation of the Taylor series expansion of the function that relates transistor collector current to internal emitter-base junction voltage, Ve, and collector-emitter vol-tage, Vb. From (3-36) and (3-5), the pertinent two-variable Taylor series expansion of the collec-tor current, Ic, is

c cc cQ e eQ b bQ

e bQ Q

I II I V V V V .

V V

(3-53)

The coefficient of (Ve − VeQ) on the right hand side of this relationship is the Q-point value of the transconductance, gm, which we introduced in (3-41); that is,

cQ cQ bQcm

e f T afccQ kfQ

I I VIg 1 1 .

V n V V2 I I

(3-54)

On the other hand, the coefficient of (Vb − VbQ) produces an expression for the Early resistance ro. In particular, (3-36) yields

cQc ct

o b af bQ afQ Q

II I1,

r V V V V

(3-55)

whence

bQ afo

cQ

V Vr .

I

(3-56)

In most cases, voltage VbQ in (3-54) and (3-56) can be supplanted by the Q-point collector-emit-ter voltage, VceQ, since the quiescent voltage drops in both the collector resistance, rc, and the emitter resistance, re, are usually small enough to justify their tacit neglect. Thus,

cQ cQ ceQm

f T afccQ kf

ceQ afo

cQ

I I Vg 1 1

n V V2 I I.

V Vr

I

(3-57)

Clearly, resistance ro in (3-57) is large for very small collector bias currents, IcQ, as well as for large Early voltages, Vaf. With reference to the small signal model of Figure (3.14), it fol-


- 221 -

lows that at low signal frequencies, where all device capacitances can be ignored, the collector-emitter port of a BJT emulates an ideal voltage controlled current source (VCCS) for low current biasing. However and despite this low frequency VCCS persona of the collector-emitter port, the transistor does not behave as an ideal transconductance element because of the finite input impedance evidenced between the base and emitter terminals. In other words, this VCCS post-ures finite, as opposed to infinitely large, input impedance. This situation encourages representing the collector-emitter output port as a current controlled current source (CCCS) that is controlled by the signal current, I, flowing as shown through resistance rπ. Since the model at hand verifies V = rπ I,

m m π acg V g r I β I , (3-58)

where, by (3-57) and (3-52), the so-called signal beta, or AC beta, βac, of a bipolar junction transistor is

cQ bQac m π FE

afccQ kf

I Vβ g r h 1 1 .

V2 I I

(3-59)

Figure (3.15). Alternative small signal model of the BJT. Note herein that in contrast to the small

signal model in Figure (3.14), the collector-emitter port contains the current con-trolled current source, βacI, whose controlling current, I, is conducted by the model resistance, rπ.

We should take note of the fact that βac, is directly proportional to its static gain counterpart, hFE, which in turn is directly dependent on the vagarious short circuit gain parameter, bf.

Figure (3.15) depicts the alternative CCCS model, for which prudence dictates our underscoring that current I is not the base current at all signal frequencies. In particular, the net signal base current must supply current to the branch represented by resistance r, and the cur-rents conducted by the capacitive formed of Cπ and Cμ. In short, current I in the βacI generator is always only the signal base current component that flows through the resistance, rπ.

EXAMPLE #3.3:

The diode-connected transistor in Figure (3.6a) operates in a circuit that allows the silicon technology transistor to conduct a quiescent collector current, IcQ, of 4 mA. A room temperature (27 °C) characterization of the transistor at hand reveals a maximum base resistance, rbb, of 140 Ω, a nominal series collector resistance, rc, of 20 Ω, and a nominal emitter resistance, re, of 0.9 Ω. Moreover, the DC beta, hFE, of the considered device is found to be at least 120 amps/amp, the knee current, Ikf, is 12 mA, the Early voltage, Vaf, is 45 volts, and the saturation current, Is, is 10 fA. Use these numerical data to compute the low

rbb rc

r

re

roC Cs

C

ac I

Base

Emitter

Collector

Substrate

V

I


- 222 -

frequency small signal parameters of the transistor. Exploit these parameters to determine the low frequency, small signal terminal resistance, say rd, of the diode-connected structure. Assume an emitter-base junction injection coefficient of nf = 1.

SOLUTION #3.3:

(1). In the diode interconnection of Figure (3.6a), the measurable quiescent collector-emitter voltage, Vd, of the transistor is identical to the quiescent base-emitter voltage, say VbeQ. In silicon, VbeQ, and hence voltage Vd, is rarely larger than 800 mV. Owing to the voltages dropped across the internal collector and emitter resistances, the internal Q-point collector-emitter voltage, VbQ, in Figure (3.9a) is therefore in the neighborhood of 800 mV. This collector-emitter potential is assuredly smaller than the forward Early voltage, Vaf = 45 volts. It follows that the collector current in (3-36) is essentially the net transport current, Ict. Setting IcQ = Ict in (3-30), the Q-point Ebers-Moll transport current, IccQ, can therefore be determined. Unfortunately, a quadratic relationship must be solved to arrive at IccQ. The relevant fruit of this admittedly annoying exercise is

cQ kfccQ cQ

kf cQ

I 4II I 1 1 1 7.07 mA .

2I I

(E3-1)

(2). With nf = 1, Is = 10 fA, IccQ = 7.07 mA, and, recalling (3-7), VT = 25.89 mV for a junction temperature of Tj = 300.16 °K, (3-5) gives a Q-point voltage, VeQ, developed across the intrinsic emitter-base junction diode of VeQ = 706.36 mV. Now, for IcQ = 4 mA and hFE = 120 amps/amp, the Q-point base current, IbQ, is IbQ = IcQ /hFE = 33.33 A, while the Q-point emitter current, IeQ, is IeQ = (hFE+1)IbQ = 4.03 mA. These currents, the computed internal emitter-base junction voltage of VeQ = 706.36 mV, the given base resistance of rbb = 140 Ω, and the emitter resistance of re = 0.9 Ω imply, via (3-49), a quiescent base-emitter terminal voltage, VbeQ, of

beQ bQ bb eQ eQ eV I r V I r 714.66 mV . (E3-2)

This voltage is only slightly more than 8 mV above its intrinsic junction voltage counterpart. Since VbeQ is identical to voltage Vd in Figure (3.6a), the internal collector-emitter voltage, VbQ, at the quiescent operating point of the diode-connected transistor is

bQ d cQ c eQ eV V I r I r 631.03 mV . (E3-3)

Note that voltage VbQ is more than 71-times smaller than the forward Early voltage, Vaf, of the transistor, which assuredly validates our previously invoked approximation of IcQ Ict in (3-30).

(3). The foregoing calculations set the table for evaluating the small signal parameters of the considered BJT. Using (3-52), the small signal emitter-base junction resistance, rπ, is rπ = 776.66 Ω. From (3-54) the forward transconductance, gm, is 122.66 mS, and since βac = gmrp, the AC beta of the transistor is βac = 95.26 amps/amp. Finally, VbQ = 631.03 mV, Vaf = 45 V, and IcQ = 4 mA in (3-56) yield an Early resistance, ro, of ro = 11.41 KΩ.

(4). If we lean on Figure (3.15), we can posture Figure (3.16) as the low frequency, small signal model of the diode-connected transistor in Figure (3.6a). All of the device capacitances in the model of Figure (3.15) are tacitly ignored because at present, our interest lies on only low frequency diode characteristics. The desired small signal terminal resistance, rd, derives from the “ohmmeter” voltage to current ratio, Vx/Ix. An analysis of the structure at hand provides

x bb π e xV r r I r I (E3-4)

and


- 223 -

Figure (3.16). Low frequency, small signal model of the diode connected transistor in Figure

(3.6a). The effective, or small signal terminal resistance, rd, of the diode connection is determined via the “ohmmeter” method, which entails a calculation of the voltage to current ratio, Vx /Ix, of our imposed mathematical ohmmeter.

x c x o x ac e xV r I I r I β 1 I r I . (E3-5)

Upon elimination of current I in these two relationships, the terminal resistance, rd, of the diode is readily shown to be

o c bb πxd e

ac ox

o c bb π

r r r rVr r 10.43 ohms .

β rI 1r r r r

(E3-6)

Since ro is a large resistance, (E3-6) can be approximated as

x bb πd e

x ac

V r rr r 10.42 ohms ,

I β 1

(E3-7)

which differs insignificantly from the “exact” result in (E3-6). ENGINEERING COMMENTARY:

The computed small signal diode resistance of 10.43 Ω is comparable to the resistance presented to a circuit by a traditional PN junction diode. This resistance is small because of the large forward transconductance, and hence large AC beta, afforded by a BJT operated at reasonable biasing levels. In stark contrast, the resistance presented by a diode-connected, deep submicron technology MOSFET is ultimately shown to be considerably larger owing to the relatively small forward transconductance typically afforded by a MOS technology transistor.

Figure (3.17). The equivalent circuit in Figure (3.16) with the Early resistance, ro, ignored.

The approximate diode resistance stemming from the tacit neglect of the Early resistance is worthy of further exploration. To this end, the pertinent small signal model is offered in Figure (3.17), wherein the removal of resistance ro postures the controlled current source, βacI, as an ideal current generator that projects infinitely large resistance across the collector-

Vx

Ix

Ix

rbb rc

r

re

roac I

V

I

Ix

Vx

Ix

I

I Ix

I ( +1)Ix ac

Vx

Ix

Ix

rbb rc

r

re

ac I

V

IVx

Ix

I

I Ix

I = ( +1)Ix ac


- 224 -

emitter terminals of the transistor. The series interconnection of the internal collector resistance, rc, with this infinite resistance current source renders rc inconsequential, regardless of its value. Moreover, since the resistance, re, is in series with the port at which the mathematical ohmmeter is applied to evaluate the diode resistance, the resistance, (rbb + rπ) evidenced in the base circuit, is necessarily referred to the emitter. In turn, we know that the emitter conducts a signal current that is larger than the signal current in the base by a factor of (βac + 1). Accordingly, it is reasonable to expect, as is confirmed by (E3-7), that the effective resistance seen in series with re is the resistance observed in the base, scaled by a factor of the base current to emitter current ratio, 1/(ac + 1).

3.3.1. UNITY GAIN FREQUENCY

Sophisticated communication and data processing systems require large bandwidths to process and transmit perpetually increasing amounts of audio, video, or digitized information. It is only natural that engineers tasked with realizing these high performance systems insist on be-ing provided with convenient circuit level metrics that quantify the high frequency capabilities of the active devices available for possible deployment in these systems. A commonly adopted, but not necessarily the meaningful or relevant, metric is the short circuit, unity gain frequency, fT, which is commonly referenced as simply the unity gain frequency.

Figure (3.18). (a). Test circuit used in the measurement of the unity gain frequency, fT, of a BJT. (b). High fre-

quency model of the test structure in (a). (c). The model in (b) simplified by ignoring the collector resistance, rc, and the emitter resistance, re.

In order to facilitate our understanding of the engineering implications of metric fT, we consider the test bipolar cell in Figure (3.18a). In this structure, the transistor, whose emitter is connected to electrical ground, is biased in its linear regime by the quiescent base current, IbQ, and the static voltage source, VceQ. In the interest of analytical simplicity, both the static current source and the static voltage source are treated as ideal sources of energy; that is, no Thévenin

IbQ

Vbe

Ibs

I +

IeQ

es

VceQ

I +

IcQ

cs

Ibs

Ies

Ics

rbb rc

r

re

roC Cs

C

g Vm

V

(a). (b).

Ibs

Ies

Ics

rbb

r C

C

V

I

(c).

g Vm


- 225 -

impedances are identified in conjunction with these energy sources. Transistor operation in its forward active domain relies on selecting voltage VceQ to ensure that it exceeds the quiescent emitter-base voltage, VbeQ. In turn, VbeQ is presumably rendered larger than the turn on voltage of the emitter-base junction by static current IbQ. A sinusoidal test signal with small current amplitude Ibs is applied in shunt with the aforementioned source of static base current. The com-bined action of IbQ and Ibs incurs a net collector current comprised of the superposition of a Q-point current, IcQ, and a signal component, Ics, as we highlight in Figure (3.18a). Similarly, a Q-point current, IeQ, superimposes with a signal current, Ies, in the emitter lead of the transistor.

Before proceeding further, it may be instructive to address our earlier allegation to the effect that the unity gain frequency lacks meaning and relevance as a circuit level figure of merit. To this end the fT test cell in Figure (3.18a) itself offers cause for skepticism. In particular, no rational design engineer is going to design a grounded emitter amplifier in which the collector of the utilized BJT is grounded through the supply line voltage. Aside from offering no possibility of an output signal voltage response at the collector, note that short circuiting the collector to sig-nal ground all but shorts out the transistor substrate capacitance, which can establish a significant time constant at the output port. This shorting, along with remanding the base-collector junction capacitance, Cμ, as a simple base to ground capacitance, has the effect of unrealistically increas-ing the theoretically achievable 3-dB bandwidth of the common emitter stage. A second reason for skepticism associated with the viability of the fT metric, is the applied signal source in the subject test cell is a current, as opposed to the voltage signal that commonly activates a common emitter amplifier. Currents are conducted instantaneously by capacitances; in this case, the base-collector and net emitter-base junction capacitances. Thus, the immediate effect of an input cur-rent signal is to deemphasize the critical importance of the time required to charge these transis-tor capacitances to appropriate signal voltage levels, which in turn liberalizes bandwidth esti-mates. In a word, fT is indeed a measure of bandwidth but unfortunately, it is an overly generous bandwidth measure.

Using the model of Figure (3.14), the small signal equivalent circuit of the test structure in question is the network shown in Figure (3.18b). Since IbQ in Figure (3.18a) is a constant cur-rent source, it does not appear in the small signal model. In effect, IbQ is replaced by an open cir-cuit to reflect the fact that IbQ embraces no signal fluctuations and therefore offers zero signal current value. Similarly, the collector in the equivalent circuit is grounded to the emitter because VceQ is a constant. It is therefore a source of zero signal voltage. Because IbQ and VceQ are necessarily set to zero for small signal analysis purposes, the only current flowing in the collector of the equivalent circuit is the signal component, Ics, of the net collector current. Similarly, the signal emitter current, Ies, is the lone current flowing in the emitter lead of the model.

If we ignore the series collector resistance, rc, and the series emitter resistance, re, we can collapse the model in Figure (3.18b) to the simplified topology presented in Figure (3.18c). Observe that setting rc to zero short circuits the substrate capacitance, Cs, while setting both rc and re to zero imposes a short circuit across the Early resistance, ro. Moreover, ignoring resis-tances rc and re allows the inherently three-pole structure in Figure (3.18b) to be emulated by the simple single pole, or single time constant, circuit in Figure (3.18c). To the latter end, note that the short circuit imposed at the collector port effectively connects capacitance Cμ from base to signal ground and in parallel with capacitance Cπ.

Obviously, the frequency response of the I/O current transfer function, Ics /Ibs, can be extracted from the measurement test cell in Figure (3.18a). Indeed, this transfer function, which


- 226 -

is denoted herewith as β(j), can be determined straightforwardly from the simplified model given in Figure (3.18c). In particular, the model advances

bs π μπ

cs m μ

VI jω C C V

r ,

I g V jωC V

(3-60)

whence

ac μ mm μcs

bs π π μπ μπ

β 1 jωC gg jωCIβ(jω) ,

1I 1 jωr C Cjω C Cr

(3-61)

where (3-59) has been used. This result confirms the anticipated low frequency, short circuit current gain of βac. It also projects a right half plane zero at a frequency of gm /Cμ. The fre-quency of this zero is invariably large owing to the relatively small base-collector depletion capacitance, Cμ, and the usually substantial forward transconductance, gm, of a small geometry BJT that is biased in its forward active domain. For that matter, the frequency, gm /C, is often so large (high tens to low hundreds of giga-radians/sec) as to cast aspersions on the propriety of the simplified high frequency model we have used to generate (3-61). Consequently, we are justi-fied to approximate the last result by the expression,

cs ac

bs β

I ββ(jω) .

I 1 jω ω

(3-62)

In (3-62), the so-called beta cutoff frequency,

βπ π μ

1ω ,

r C C

(3-63)

Figure (3.19). Asymptotic approximation of the frequency response of the

short circuit, grounded emitter, current gain of a bipolar junc-tion transistor.

is recognized as the resultant 3-dB bandwidth of the short circuit, small signal current gain, β(j). The unity gain frequency can now be extrapolated as the gain-bandwidth product, βacωβ, as suggested by the asymptotic frequency response plot given in Figure (3.19). This assertion derives from the fact that at high signal frequencies, (3-62) collapses to

β

ac βω ω

β ωβ(jω) ,

jω (3-64)

(j ) (in dB)

ac (dB)3 dB

0 T

Slope = 20 dB/dec


- 227 -

from which it is apparent that the magnitude of the current gain degrades to one at an approx-imate radial frequency, ωT, which corresponds to frequency fT, of

ac β mT

Tπ μ

β ω gωf .

2π 2π 2π C C

(3-65)

EXAMPLE #3.4:

Under room temperature operating conditions, the high frequency silicon transis-tor in Figure (3.18a) is biased at a collector current, IcQ, of 800 A and a collec-tor-emitter voltage, VceQ, of 2 volts. The transistor has a maximum base resis-tance, rbb, of 360 Ω, a series collector resistance, rc, of 60 Ω, and a series emitter resistance, re, of 1.5 Ω. The short circuit current gain, βf, of the device is 140 amps/amp, the knee current, Ikf, is 10 mA, the Early voltage, Vaf, is 25 volts, and the saturation current, Is, is 6 fA. For the base-collector junction, the capacit-ance-related parameters are Cjco = 5 fF, mc = 1/3, and Vjc = 660 mV; for the emitter-base junction, Cjeo = 1.5 fF, me = 1/2, and Vje = 920 mV. Moreover, the low current, short circuit transit time, τfo, for base region minority carriers is τfo = 2.5 pSEC. The emitter-base junction injection coefficient, nf, can be taken to be one. Use these numerical data to compute the unity gain frequency, fT, at the specified operating point.

SOLUTION #3.4:

(1). Equation (E3-1) in the preceding example defines the quiescent transport current, IccQ, in terms of the Q-point collector current, IcQ. For IcQ = 800 A and Ikf = 10 mA, this relationship gives

cQ kfccQ cQ

kf cQ

I 4II I 1 1 1 1.06 mA .

2I I

(E4-1)

With nf = 1, Is = 6 fA, and, recalling (3-7), VT = 25.89 mV for a junction temperature of Tj = 300.16 K, (3-5) gives a Q-point voltage, VeQ, developed across the intrinsic emitter-base junction of VeQ = 670.47 mV.

(2). Since parameter β, to which the static beta, hFE, is directly proportional is large, the quiescent base current, IbQ = IcQ/hFE, is correspondingly small. Thus, the Q-point emitter current, IeQ, is virtually identical to its collector current counterpart, IcQ. Taking IeQ ≈ IcQ, it follows from Figure (3.11) that the internal collector-emitter voltage, VbQ, is, with VceQ = 2 volts, rc = 60 Ω, and re = 1.5 Ω,

bQ ceQ cQ c cQ eV V I r I r 1.95 V . (E4-2)

In the interest of completeness, we can use (3-37) to enumerate hFE. In particular, for VbQ = 1.95 volts, and βf = 140, hFE = 113.85 amps/amp, which is slightly more than 81% of the Ebers-Moll parameter, βf.

(3). We compute the forward transconductance, gm, with the help of (3-41). For the given and calculated variables,

cQ bQcm

f T afccQ kf

I VIg 1 1 29.22 m .

n V V2 I I

(E4-3)


- 228 -

(4). Recalling (3-40), the effective value, τfe, of the minority carrier transit time is

cQ

kffe fo

bQ

af

I1

Iτ τ 2.505 pSEC

V1

V

(E4-4)

for τfo = 2.50 pSEC. It follows by (3-39) that the emitter-base diffusion capacitance, Cbe, is, for gm = 29.22 mS and τfe = 2.505 pSEC,

be fe mC τ g 73.19 fF . (E4-5)

(5). The remaining device capacitances derive from (3-43) and (3-45). In the former of these two relationships, the emitter-base junction threshold potential, Veon, can be taken as 700 mV, de-spite the fact that the computed value of the emitter-base junction voltage, VeQ, is about 30 mV smaller. Equation (3-43) is, after all, only an approximation of the depletion capacitance evidenced at the forward biased junction. Additionally, capacitance Cjeo is so small that the depletion component of the net emitter-base junction capacitance is doubtlessly inconsequen-tial to the present exercise. Accordingly, with Cjeo = 1.5 fF, Vje = 920 mV, Veon = 700 mV, and me = 1/2,

e

jeoje m

eon

je

CC 3.07 fF .

V1

V

(E4-6)

In order to garner a value of capacitance Cμ in (3-45), the intrinsic base-collector junction voltage, VcQ, must first be computed. Appealing to Figure (3.11),

cQ eQ bQV V V 1.28 volts . (E4-7)

Thus, (3-45) yields

c

jcoμ m

cQ

jc

CC 3.49 fF ,

V1

V

(E4-8)

with Cjco = 5 fF, Vjc = 660 mV, and mc = 1/3.

(6). Recalling that capacitance C is simply the sum of capacitances Cbe in (E4-5) and Cje in (E4-6), (3-65) finally delivers

m m

Tπ μ fe m je μ

g gf 58.32 GHz .

2π C C 2π τ g C C

(E4-9)

Those who may be concerned with the tacit neglect of the right half plane zero in (3-61) can verify that for the stipulated operating point conditions, gm /C 1,332 GHz, which is almost 23-times larger than fT in (E4-9). Consequently, this right half plane zero bodes no substan-tive engineering significance.


The procedure underlying the numerical evaluation of the unity gain frequency of a BJT is computationally intensive. In order to allay any trepidation that may ensue from this computational intensity, the procedure is documented herewith merely to demonstrate the utility of all of the modeling relationships derived to this point. In practice, and as you will be thrilled to learn, operating point printouts accompanying SPICE simulations of BJT cir-cuits include a numerical delineation of fT.

The critical issue at hand is the practical utility of the unity gain frequency metric. In brief, its principle value is to serve as a measure of comparison among devices proposed for


- 229 -

deployment in broadband analog or high-speed digital circuit applications. The rationale sur-rounding this contention is that transistors exemplifying very large values of fT for a specified quiescent operating point can generally be expected to perform more admirably at high signal frequencies than can competitive devices exuding smaller values of the unity gain metric. For example, a transistor boasting fT = 100 GHz is arguably capable of processing more faith-fully very high signal frequencies than can transistors offering fT = 40 GHz.

While the foregoing statement reflects solid engineering rationale, it is important for us to appreciate that with the exception of very specialized circuit topologies, fT is an incredibly optimistic measure of achievable circuit performance at high signal frequencies. It is even more vital that we comprehend the logic that underlies this asserted negativity. In particular, fT is a frequency measure for only the short circuit current gain of a transistor cell whose emitter is grounded. It pertains to a circuit topology whose base is driven by an ideal signal current source, the response to which is a current delivered to a short circuited load termina-tion. As such, the fT metric is effectively a measure of only the time required to transport charge carriers across the base region. To wit, the net applied base current, (IbQ + Ibs), serves to forward bias the emitter-base junction of the subject transistor. This forward biasing pro-motes the injection of charge carriers from the emitter to the base. In turn, such injection gives rise to a net emitter signal current, (IeQ + Ies). Because of the narrowness of the base volume and the reverse bias imposed at the base-collector junction, the preponderance of emitter-injected carriers is transferred to the collector region where they incur a net collector current of (IcQ + Ics). Once the carriers injected into the base are indeed delivered to the collector, the short circuited load imposed at the collector simplifies an assessment of fre-quency response. In particular, the gain metric, β(jω) in (3-61), and frequency metric fT in (3-65) inherently ignore the time required to charge the substrate capacitance and any other capacitances implicit to the actual load that we ultimately append to the collector port. In other words, fT fails to account for the frequency response of the output voltage produced by the applied input current since in effect, the output voltage is clamped to zero by the short cir-cuit imposed at the output port. Moreover, and especially for the case of a first stage in a high performance electronic system, fT is likewise oblivious to the time required to charge in-put port capacitances associated with the utilized transistor. The tacit neglect of capacitive charging times is significant in practical circuits. For example, in a circuit designed to deliver an output voltage response to an applied input signal, the achievable 3-dB bandwidth is rarely larger than about an order of a magnitude smaller than fT.

Potentially notable exceptions to the foregoing assertions are current mode circuits, which ex-tract output responses as signal currents that are applied as currents to succeeding stages. Current mode signal processing is addressed later in this text. But for the moment, observe that in the case of the grounded emitter configuration, the collector is a relatively high imped-ance port owing to the large Early resistance that prevails therein. Accordingly, the collector can be modeled accurately as an almost ideal Norton equivalent network. If the Norton out-put current is then applied to a subsequent amplification stage that features relatively low in-put impedance, a short circuit is effectively approximated at the collector port of the predecessor stage. To the extent that the input port of the first stage boasts low input imped-ance so that large port voltages are precluded, fT becomes a meaningful barometer of high frequency circuit performance. Of course, short circuited input ports in either predecessor or follow on load stages are never precisely realizable. As a result, the achievable bandwidths in prudently designed current mode configurations remain themselves rarely larger than 50% to 60% of the published fT value.

In summary, fT is arguably a viable, and indeed convenient, metric for purposes of compara-tive shopping of transistors earmarked for deployment in high performance, broadband net-works. But except for current mode configurations, which can be adopted only at circuit interstages −stages that include neither the input first stage nor the output last stage− it is a


- 230 -

virtually useless circuit level figure of merit. Its demonstrable circuit impropriety as a high frequency performance measure stems from the fact that the fT measure is oblivious to the time required to charge device and critical circuit capacitances at both input and output am-plifier ports.

Although transistor vendors and process foundries are anxious to quote impressive fT-values to skew the comparative shopping to which our foregoing comments allude, they are reti-cent to underscore the fact that fT varies with collector current. Indeed, fT is a notably sensitive function of the quiescent collector current, IcQ, when IcQ is small, as is typical of circuits con-strained to function at low power levels. In the true spirit of aggressive marketing, quoted unity gain frequency values invariably reflect maximum attainable values, which may unfortunately correspond to collector currents deemed inappropriate for specific applications. To wit, the transistor parameterized in the preceding example generates the fT -versus- IcQ characteristic dis-played in Figure (3.20). A careful examination of the data underpinning this curve reveals that the maximum value, say fTM, of the unity gain frequency is 58.3 GHz, which is achieved at a collector current of IcM = 831.8 μA. Fortunately, the curve at hand displays a rather broad maxi-mum, thereby negating the need to set the quiescent collector current precisely to achieve a unity gain frequency that is within a few percent of its theoretical maximum. Note, however, that it makes little sense to bias the transistor of interest to the right of current IcM in that similar fT-val-ues are achievable at the lower circuit power dissipation associated with current biasing below IcM.

Figure (3.20). The unity gain frequency, fT, plotted as a function of the quiescent collector current,

IcQ, for the transistor studied in Example #3.4. The quiescent collector-emitter voltage of the subject transistor is held at 2 volts.

An analytical delineation of the optimal collector current associated with maximal unity gain frequency is a challenge owing to the dependence of numerous relevant modeling parame-ters on collector current. Nonetheless, we can deduce acceptable approximations to the optimal current and corresponding maximal unity gain frequency. To this end, return to (3-65) and note that the net capacitance, say Cnet, in the denominator on the right hand side is

0

10

20

30

40

50

60

0.010 0.100 0.962 9.618

Un

ity

Gai

n F

req

uen

cy,

f T(G

Hz)

Collector Current, IcQ (mA)

IcM

fTM


- 231 -

mnet π je μ fe jC C C C τ g C , (3-66)

where (3-39) and (3-44) have been used. Moreover, we have introduced the sum total, Cj, of transistor depletion capacitances as

j je μC C C . (3-67)

In the last expression, Cje and Cμ are given by (3-43) and (3-45), respectively. While capacitance Cje is a constant, Cμ is a function of the intrinsic base-collector junction reverse bias, Vc, which depends somewhat on the collector current owing to the presence of series resistances in the collector and emitter leads of the transistor. Because these series resistances are small, this collector current dependence can be ignored, thereby establishing Cj as a constant, independent of quiescent collector current. In particular, the tacit neglect of intrinsic series resistances im-plies that the intrinsic collector-emitter voltage is simply the externally applied collector-emitter voltage, VceQ, whence VcQ equates to the voltage difference, (Veon − VceQ). Moreover, voltage VbQ is presumed to be significantly smaller than the Early voltage, Vaf, so that fe in (3-39) becomes

cQ

kf cQfe fo fo

bQ kf

af

I1

I Iτ τ τ 1 .

V I1

V

(3-68)

The relationship for the unity gain frequency in (3-65) now becomes

m m

Tπ μ cQ

fo m jkf

g gf .

2π C C I2π τ 1 g C

I

(3-69)

At small collector currents, the transconductance parameter, gm in (3-54) collapses to

cQ cQ bQ cQm

f T af f TccQ kf

I I V Ig 1 1 ,

n V V n V2 I I

(3-70)

where we continue to presume that voltage VbQ is much smaller than the Early metric, Vaf. Specifically, transconductance gm, which increases monotonically for all values of the quiescent collector current, IcQ, is seen as increasing linearly with small quiescent collector current IcQ. This simplified transconductance relationship, allows us to couch (3-69) in the form

cQmT

cQ fo cQfo m j f T cQ j

kf f T kf

Igf .

I τ I2π τ 1 g C 2πn V 1 I C

I n V I

(3-71)

Equation (3-71) is arguably valid through the immediate neighborhood of maximum fT in that Figure (3.20) suggests maximal fT is achieved at a collector current that is substantively smaller than the forward knee current of a BJT.

Equation (3-71) affirms the original allegation of a current dependence ascribed to the unity gain frequency metric. Aside from such affirmation, it also highlights two additionally important, design-oriented issues. First, it validates the nominally linear rise of fT with current IcQ that is observed in Figure (3.20) for low collector currents. From (3-71), we note that the slope of this low current rise converges to 1/2πnfVTCj, which means that progressively larger depletion capacitances at either or both transistor junctions slows the current rate of fT ascent to


- 232 -

its maximum value. Second, since (3-71) delivers positive fT for all considered values of IcQ and further yields fT = 0 at both IcQ = 0 and IcQ = ∞, it foretells the existence of an optimal current, say IcM, commensurate with securing maximal unity gain frequency. This optimal current de-rives from constraining to zero the derivative, dfT /dIcQ, in (3-71). The result of this somewhat annoying exercise is

f T kf jcM

fo

n V I CI .

τ (3-72)

Now, if we set IcQ = IcM in (3-71) we arrive at maximum unity gain frequency, say fTM, of

foTM

f T j

fo kf

1 2π τf .

n V C1 2

τ I

(3-73)

We should probably tweet home the fact that the foregoing expression articulates 1/fo as the largest possible radial value of the maximum unity gain frequency. We note further that this maximum fT value is approached when the knee current, Ikf, is large. The last observation sug-gests that high injection breeds diminished frequency response capabilities. This suggestion is reasonable in that high injection creates the proverbial traffic jam of carriers in the base, whereu-pon the mobility of those carriers is degraded.

When (3-72) and (3-73) are applied to the transistor studied in Example #3.4, IcM = 823.3 μA, and fTM = 54.66 MHz. These computations differ from their simulated values by slightly more than 1% and about 6.7%, respectively, which is good enough for government work, while confounding marketing practices.

3.3.2. UNITY POWER GAIN FREQUENCY

The unity gain frequency discussed in the preceding subsection liberally brackets the high frequency response capabilities of a grounded emitter transistor in terms of the frequency response of its short circuit, and therefore maximum, current gain. Although mathematical tractability and ease dictate that the small signal, frequency domain performance of electronic networks be evaluated in terms of either current gain or voltage gain transfer functions, we should record that the primary purpose of active circuits is to amplify signal power. It is there-fore meaningful and sensible to assess high frequency transistor response capabilities in terms of the maximum power gain afforded by the utilized transistor.

To the foregoing end, consider the grounded emitter amplifier of Figure (3.21a) in which the static supply voltages, Vcc and Vbb, combine to ensure that the utilized BJT operates in its forward active regime. The signal source, Vs, is applied to the amplifier input port through a complex series impedance, Zs(jω), which is understood to include the Thévenin impedance of the signal source itself. In response to Vs, which is presumably a small amplitude sinusoid, a signal component, Vos, of the net output port voltage, Vo, is generated. In addition, signal voltage Vs manifests a signal component, Vis, to the net input port voltage, Vi. The amplifier, whose output port is terminated to signal ground in the complex load admittance, Yl(jω), can be represented as a voltage controlled current source, as we suggest in Figure (3.21b). In this Norton representa-tion, Yfe(jω)Vis represents the short circuit, output signal current, while Yoe(jω) is the shunt output admittance associated with the amplifier output port. At the amplifier input port, it is convenient to separate the intrinsic base resistance, rbb, from the net input impedance or admittance. Accor-dingly, the admittance, Yie(jω), is the load presented to the signal source circuit by only the net


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admittance that is pervasive of the branch that shunts the intrinsic emitter-base junction.

Figure (3.21). (a). A grounded emitter amplifier. (b). Voltage controlled current source representation

of the small signal characteristics postured by the I/O ports of the amplifier in (a).

Assuming that the transistor in Figure (3.21a) derives from a monolithic fabrication process, the device equivalent circuit shown in Figure (3.14) launches the small signal amplifier model depicted in Figure (3.22a). Since the Norton equivalent output current, Yfe(jω)Vis in Fig-ure (3.21a), is the current conducted by a short circuited load, the model appropriate to determin-ing Yfe(jω) is the structure given in Figure (3.22b). Observe that the only difference between the topologies of Figures (3.22a) and (3.22b) is that load admittance Yl(jω) in the former diagram is supplanted by a short circuit in the latter figure. From Figure (3.22b), the signal current, Ios, con-ducted by the short circuited load satisfies

os m μ m μI g V jωC V g jωC V . (3-74)

On the other hand, signal voltage V relates to the signal component, Vis, at the network input port as

π π

π π μ π bb

πis π bb π μbbπ π μ

r r1 jωr C C r rV

.rV 1 jω r r C Cr

1 jωr C C

(3-75)

Using the last two expressions, we find that the Norton transadmittance, Yfe(jω), is

μm π

π bb mosfe

is π bb π μ

jωCg r1

r r gIY (jω) .

V 1 jω r r C C

(3-76)

The right half plane zero at gm /Cμ is invariably so large as to lie outside the frequency range over which the transistor model in Figure (3.14) can be presumed valid and is therefore ignored henceforth. Thus, the transadmittance in (3-76) can be approximated at high signal frequencies

Y(j

)oe

Y(j

)ie

Io

Ios

rbb

Vs

Vs

Vbb

Vo

Vos

Vi

+Vcc

Y (j )Vfe is

(a). (b).

Vis

Y(j

)l

Z (j )s

Z (j )s

Y(j

)l


- 234 -

(but not so high as to encroach on the frequency of the aforementioned right half plane zero) as

Figure (3.22). (a). Small signal, high frequency equivalent circuit of the amplifier in Figure (3.21a). (b).

Small signal model used in the evaluation of the forward transadmittance function, Yfe(jω). (c). Small signal model for evaluating the Norton admittance, Yoe(jω), established at the am-plifier output port. (d). Small signal model for evaluating the Norton admittance, Yie(jω), established at the intrinsic emitter-base junction of the utilized transistor.

Ios

Vs

VosVis

(a).

rbb

r roC Cs

C

g Vm

V

Ios

(b).

rbb

r roC Cs

C

g Vm

V

Ix

Vx

(d).

r roC Cs

C

g Vm

V = V

x

Y (j )ie Y

(j)

l

Z (j )s

Vs

Vis

Z (j )s

(c).

rbb

r roC Cs

C

g Vm

V

Ix

Vx

Y (j )oe

Vis

Z (j )s

Vos

Y(j

)l


- 235 -

os m T

feis bbbb π μ

I g ωY (jω) ,

V jωrjωr C C

(3-77)

where

mT

π μ

gω

C C

(3-78)

is the transistor unity gain frequency introduced in (3-65). It is interesting to note that the form of (3-77) implies that the high frequency transadmittance of a grounded emitter BJT amplifier reflects the response properties of an ideal integrator because of the presence of (jω), which corresponds to Laplace operator “s,” in the denominator.

Figure (3.22c) diagrams the equivalent circuit appropriate to evaluating the shunt out-put admittance, Yoe(jω). This structure is the original model in Figure (3.22a) with two modifica-tions. First, the independent signal source, Vs, is set to zero, as is mandated by a Thévenin impedance computation at any network port. Second, the load admittance, Yl(jω), is supplanted by a mathematical ohmmeter that is simulated by the independent current source, Ix. This current forges a voltage, Vx, across, and in disassociated polarity with, current Ix so that the target output admittance, Yoe(j), is simply Ix/Vx. Conventional circuit analysis reveals

x s μ x m μo

1I jω C C V g jωC V ,

r

(3-79)

and

π μ μ xπ bb s

1jω C C V jωC V 0 .

r r R

(3-80)

Inserting the solution for voltage V in (3-80) into (3-79) leads to

π bb s μ m μxoe s μ

x o π bb s π μ

jω r r R C g jωCI 1Y (jω) jω C C .

V r 1 jω r r R C C

(3-81)

For high frequency signal environments where transconductance gm can still be presumed to be substantively larger than the capacitive susceptance, ωCμ, (3-81) reduces to the more compact relationship,

oe T μ s μo

1Y (jω) ω C jω C C .

r (3-81)

We note with considerable interest that the base-collector depletion capacitance, Cμ, generates a conductance (real) component, ωTCμ, to the net shunt output admittance. We may be able to ex-ploit this result when a specific circuit application warrants a lossless reduction in the amplifier output resistance. In particular, placing a capacitor across the base-collector ports of a common source amplifier enhances the value of the base-collector junction depletion capacitance, Cμ. For given or known ωT, we may choose this expanded capacitance value to contrive the additional shunt output conductance (lowered shunt output resistance) that our design environment requires. Observe that the additional conductance has the laudable attribute of burning no signal power since it derives exclusively as the magnitude of a capacitive admittance at frequency ωT. In asserting this claim, we assume, of course, that the capacitance we use is ideal; that is, the capacitance is divorced of any shunt terminal resistance.

Figure (3.22d) is the small signal model for calculating the shunt input admittance, Yie(jω) for the subject grounded emitter amplifier. We recognize that the voltage, Vx, which is


- 236 -

developed across the imposed mathematical ohmmeter, is identical to the signal voltage, V, appearing across the emitter-base junction. A conventional nodal circuit analysis delivers

x π μ μ osπ

s μ os m μo l

1I jω C C V jωC V

r,

1jω C C V g jωC V 0

r Z (jω)

(3-82)

where Zl(jω) is the impedance corresponding to the load admittance, Yl(jω). The elimination of voltage Vos in these two independent relationships leads to

m o lxie π μ

π o l s μ

g r Z (jω)I 1Y (jω) jω C 1 C ,

V r 1 jω r Z (jω) C C

(3-83)

where the indicated approximation exploits the presumption that for all signal frequencies of interest, gm >> ωCμ. At high signal frequencies that do not contradict the last inequality, (3-83) collapses to

μxie m π μ

π s μ

CI 1Y (jω) g jω C C .

V r C C

(3-84)

Figure (3.23). Approximate high frequency, Norton equivalent I/O port model for the grounded emit-

ter amplifier in Figure (3.21a).

As is the case with the shunt output admittance, the base-collector depletion capacitance, C, spawns a small shunt input conductance component in the form of the second term on the right hand side of (3-84). Equation (3-84), along with (3-81) and (3-77), gives rise to the high fre-quency I/O port model we present in Figure (3.23). This topology clearly identifies the net shunt resistances and capacitances at both the input and output ports of the amplifier. In the interest of clarity, we observe that while Yoe(jω) is the net admittance facing the terminating load admit-tance, Yie(j) is not the net input admittance faced by the signal source at the base terminal of the transistor. Instead, the input impedance driven by the applied input signal is [rbb + 1/Yie(jω)].

Ios

T isVj r bb

ro T C

1 C Cs

rbb

C Cr

C + Cs

g Cm

Y (j )ie

Vs

Vis

Vos

Z (j )s

Y(j

)l

Y (j )oe


- 237 -

The prerequisite for maximum power gain in any type of amplifier is the successful realization of conjugate impedance or admittance matches at both the input and the output ports. In particular, the source impedance, Zs(jω), must be the complex conjugate of the net input impedance it faces at signal frequency ω. Concurrently, the load admittance, Yl(jω), must be a conjugate match to the net output admittance that it shunts. Achieving these conjugate matches, particularly over a broad passband of signal frequencies, is hardly a casual walk in the proverbial park on a sunny weekend morning. The requisite engineering tasks entail the design and implementation of appropriate I/O filters that respectively couple the signal source to the input port and the load to the amplifier output port to produce the desired matching. These filters are generally nominally lossless structures, which is to say that their intrinsic branch elements are exclusively inductances and capacitances. As a result, coupling filters do not waste significant amounts of applied signal power prior to being processed for delivery to the load termination. The lossless nature of coupling filters looms significant in many modern communication systems whose received radio frequency signal often projects anemic amplitude. Another issue that we need to address with an incorporation of I/O matching filters is overall network stability. In particular, impedance matching at both the input and output ports for certain types of transistor amplifiers can result in an unstable network in the sense that one or more network poles end up lying in the right half complex frequency plane.

The conjugate admittance match at the output port implies two operational require-ments. First, the shunt conductance component, say Gl, of the load admittance must equate to the real part, or conductance component, of Yoe(j). In particular,

T o μl oe T μ

o o oe

1 ω r C1 1G Y (jω) ω C .

r r RRe

(3-85)

Second, the susceptive component of load admittance Yl(jω) must be inductive to enable its resonance with the net shunt output capacitance, (Cμ + Cs), at the radial signal frequency, ω. The proper selection of a load that satisfies these two design requirements resultantly compacts the output port section shown in Figure (3.23) to the simple topology of Figure (3.24a), which projects an output signal voltage, Vos, of

Figure (3.24). (a). The high frequency output port model of the grounded emitter amplifier in Figure

(3.21a) when the load admittance, Yl(jω), is selected to be a conjugate match to the Norton output admittance, Yoe(jω), in Figure (3.23). (b). High frequency input port model of the grounded emitter amplifier under the condition of a source impedance [Zs(jω)] conjugate match to the net input impedance, rbb + 1/Yie(jω) in Figure (3.23).

T is oeos

bb

ω V RV .

jωr 2

(3-86)

Ios

T isVj r bb

Roe

rbb

Vs

VisVos

Roe

rbb

(a). (b).


- 238 -

The corresponding maximum signal power, say Pomax, delivered to the resistive component of the load that terminates the output port is

22os T is

omax oeoe bb

V ω VP R .

R 2ωr

(3-87)

At the input port, the real part, say Rs, of the effective source impedance, Zs(j), must be set to effect a conjugate match between the source impedance and amplifier input impedance, [rbb + 1/Yie(j)]. With reference to Figure (3.23),

ie π μie2

ie μ ie π μm π μπ s μ

1 jωR C C1 1R ,

Y (jω) C1 1 ωR C Cg jω C Cr C C

(3-88)

where

ac mie

μ μm ac

π s μ π μ

β g1R .

C C1g 1 β

r C C C C

(3-89)

Interestingly, the impedance, 1/Yie(j), is purely imaginary at very high signal frequencies. In particular,

2π μie

2ie π μω large ie π μ

jωR C C1 1.

Y (jω) jω C CjωR C C

(3-90)

Thus, the magnitude of the very high frequency current conducted by resistance r in Figure (3.23) is insignificant to the current conducted by the net shunt input port capacitance, (Cπ + Cμ). This revelation hardly warrants prize paper recognition in view of our understanding that capacitances in the sinusoidal steady state emulate short circuited elements when they are com-pelled to conduct high frequency currents. It follows that the real part of 1/Yie(jω) approaches zero at high frequencies, whence the source resistance, Rs, commensurate with input port imped-ance matching becomes

s bb bb bbie ie

1 1R r r r .

Y (jω) Y (jω)Re Re

(3-91)

Figure (3.24b) shows the immediate ramification of a high frequency input port impedance match, where it is to be understood that the reactive component of the original source impedance, Zs(jω), has been selected to resonate with the net shunt capacitance, (Cπ + Cμ). Such a design tack is tantamount to ensuring that the sum of the reactances associated with Zs(jω) and 1/Yie(jω) is zero at the signal frequency, ω, of interest.

For the maximum power transfer condition implied by (3-91), the maximum signal power, Pimax, delivered to the input port of the grounded emitter amplifier is obviously

2is

imaxbb

VP .

r (3-92)

A combination of this result with (3-87) leads to a maximum power gain, Ap, of


- 239 -

2omax oeT

pimax bb

P RωA ,

P 2ω r

(3-93)

and recalling (3-85),

2

oeT Tp 2

bb bb μ T o μ

Rω ωA .

2ω r 4ω r C 1 1 ω r C

(3-94)

Somewhat disconcertingly, (3-94) shows that the high frequency power gain of a grounded emit-ter amplifier degrades sharply with increasing signal frequency. This observation explains the debilitating pain we experience when we are tasked with the responsibility of achieving substan-tial signal power gain at very high frequencies. Indeed, power gain Ap is inversely proportional to the square of the radial frequency, ω, which means that the power gain frequency response rolls off with increasing frequency at a rate of 40 dB/decade.

A maximum power gain of one effectively defines the practical utility of an amplifier. In other words, the frequency at which unity power gain is achieved effectively defines the maxi-mum frequency for which the amplifier behaves as an active network capable of greater than un-ity gain. This frequency, say ωmax, at which Ap degrades to one is, by (3-94),

Tmax

bb μT o μ

ωω ,

14r C 1

ω r C

(3-95)

or in units of hertz,

max T Tmax

bb μbb μ

T o μ

ω f ff ,

2π 8πr C18πr C 1

2πf r C

(3-96)

where the indicated approximation reflects the presumption, 2fTroCμ >> 1. For the transistor examined in Example #3.4, which at the stipulated operating point has rbb = 360 Ω, Cμ = 3.49 fF, and fT = 58.32 GHz, the preceding equation delivers fmax = 42.86 GHz, which is more than 26% smaller than the fT rating of the device.

When rbbCμ > 1/4ωT, which is a commonly satisfied condition, particularly for SiGe heterojunction bipolar transistors, the unity power gain frequency, fmax, more conservatively brackets the high frequency performance ceiling of a transistor than does the unity current gain frequency, fT. Despite this arguably laudable conservatism, device selection decisions premised on fmax must still be weighed carefully and tempered in light of the myriad of analytical approximations we invoked to preserve our sanity while formulating (3-96). More importantly, the engineering implications implicit to the concept of the unity power gain frequency must be placed into proper perspective. In particular, fmax represents the approximate input signal fre-quency for which the maximum possible power gain of a grounded emitter amplifier degrades to unity. But maximum power gain is realized if and only if conjugate impedance matches prevail between terminating load and amplifier output impedances and between signal source and am-plifier input impedances. Except for certain classes of narrowband, tuned amplifiers, such conju-gate matches are rarely achievable without filtering heroics in broadband architectures. Indeed, most broadband amplifiers, and particularly lowpass amplifiers, do not operate with conjugate impedance matches at I/O ports, which means that these amplifiers do not deliver maximum power gain. In fact, they may be designed expressly for the delivery of maximum voltage or cur-


- 240 -

rent gains or perhaps specific values of these gains. Thus, just like the short circuit figure of me-rit, fT, does not reflect realistic operating conditions, fmax may likewise be somewhat impertinent to a broad range of amplifier topologies. In these cases, the actual achievable bandwidths are generally found to lie in the range of one-fifth to one-third of fmax.

An even more insidious problem is that all grounded emitter amplifiers cannot be de-signed to deliver match terminated maximum power gain. As we briefly mentioned above, some amplifiers are potentially unstable, which is to say that there exists a range of passive load terminations for which self-sustaining oscillations can be supported by the considered network under zero input signal conditions. Potential instability does not surface in the foregoing dis-course because the high frequency models invoked are simplified to an extent that the actual potential instability mechanisms of common emitter units are masked. More complicated high frequency models, which embrace the response ramifications of time delays associated with the forward transconductance and the dynamics observed at junction sidewalls in the complicated two dimensional monolithic macromodel of Figure (3.12), may imply potential instability for certain quiescent operating points. It follows that grounded emitter amplifiers represented by these high level models may be incapable of delivering maximum power gain without risking instability. In these cases, the pertinence of fmax in (3-96) is dubious.

3.4.0. BJT BIASING

As we have already noted, we are compelled to bias analog electronic circuits in order to facilitate nominally linear signal processing of applied input voltage or current signals. In the case of bipolar junction transistors, the biasing problem fundamentally addresses two design-oriented issues. The first of these issues is the selection of a quiescent collector current, IcQ, which is appropriate to the satisfaction of the I/O specifications targeted for the proposed circuit. Such selection must be mindful of the fact that a necessary condition for nominally linear BJT operation that BJTs must be biased in their linear, forward active regimes. Recall that in this operating domain, the base-emitter voltage, Vbe, of each BJT must be sufficiently large to estab-lish, for all pertinent signal levels, an intrinsic junction voltage that is at least as large as the thre-shold potential of the emitter-base junction. Moreover, we must ensure that the intrinsic base-collector junction voltage is negative or at most zero for all time. The latter voltage constraint is satisfied automatically in NPN devices if collector-emitter voltages, Vce, are at least as large as base-emitter voltages, Vbe. In practice, we find it prudent to set the Q-point value of the collec-tor-emitter voltage above the base-emitter voltage by an amount that at least equals the antic-ipated signal swing across the collector-emitter voltage. Assuming a small or zero impedance in the emitter lead, this swing is proportional to the product of the gain magnitude and applied input signal amplitude. Analogous constraints apply to PNP units whose emitter-collector voltages, Vec, must be larger than the emitter-base voltages, Veb, which support the desired quiescent collector currents.

The selection of suitable quiescent collector currents is hardly a visceral engineering exercise. These currents are typically premised on desired circuit gains, since gain is a function of current-dependent device forward transconductance. The quiescent collector current sup-ported by the biasing design might also be chosen in light of considerations surrounding network bandwidth, noise, distortion, power dissipation, or other circuit performance barometers deemed by the circuit designer as critical to a satisfying realization of system performance specifications. In addition to the junction voltage constraints underlying linear domain operation of a BJT, an


- 241 -

important practical issue must be appreciated and addressed by the circuit designer during the collector current selection process. In particular, it makes no sense to bias a BJT at a collector current that exceeds the device knee current. One problem associated with high current biasing is needlessly enhanced power dissipation. Another problem implicit to biasing at or beyond the transistor knee current is that the DC beta, hFE, decreases monotonically with high collector cur-rent levels, thereby compromising the current gain of the network into which the subject transis-tor is connected. While forward transconductance increases monotonically with collector Q-point current, the unity gain frequency, fT peaks at a current that is smaller than the device knee current. The immediate implication of this fact is that biasing the collector at a current to the right of the fT peak produces an fT value that is identical to that forged slightly to the left of the fT peak. Thus, power dissipation budgets, thermal concerns, and even electrical noise considera-tions render high current biasing foolish when suitably lower current biasing results in similar device and circuit performance. Although design generalities in electronics are fraught with engineering peril, the portability culture renders one assertion abundantly clear. In particular, the quiescent collector current of each active device within an electronic network should be chosen as the smallest current level commensurate with nominally linear device operation and both the predictable and reliable satisfaction of all stipulated circuit operating specifications.

The second of the two-step biasing design task derives from the previously espoused fact that the quiescent collector current conducted by a BJT fixes the numerical values of several branch elements in the small signal models of Figures (3.14) and (3.15). It follows that the bias-ing structure must establish each device collector current in a reliable and predictable fashion. In most cases, these collector currents are desirably constant, although in a few, carefully con-trolled, design situations, we may wish them to be linear functions of junction operating tempera-ture. For example, recall from (3-54) that the forward transconductance at low collector currents is proportional to the ratio of quiescent collector current to Boltzmann voltage. Since the Boltzmann voltage is directly proportional to absolute temperature, a temperature invariant gm, which translates to a gain invulnerability to operating temperature, requires a collector current that is likewise proportional to absolute temperature (PTAT).

But temperature is not the only environmental factor that determines design quality. Suppose, for example, that device biasing currents fluctuate as a function of noise coupled parasitically to the static voltage supply line of a circuit. The resultant contamination of such small signal parameters as rπ, Cπ, gm, and ro produce a time varying model for which the chal-lenges associated with executing tractable small signal analytical analysis all but preclude the generation of predictable and reproducible results.

In summary, the biasing problem is seen as generally entailing the implementation of collector currents that are predictable constants. Implicit to the requirement of predictable and reproducible biasing current is that the current in question be rendered as insensitive as possible to the impact exerted on device characterization metrics by the vagarious nature of semiconduc-tor device processing and manufacturing. Stated quite simply, the quiescent collector current, IcQ, of each BJT must be reliably predictable in terms of designable circuit elements. It must usually be appropriately desensitized to temperature, and it must be independent of signal vol-tages, signal currents, and the parametric uncertainties that comprise the implicit baggage of ac-tive monolithic devices.

3.4.1. PASSIVE BIASING NETWORKS

The most straightforward of biasing structures engaged for use in linear signal


- 242 -

processing networks employ only passive elements to realize a desired quiescent collector cur-rent. In the subsections that follow, we examine two passive networks from four distinct perspectives. The first of these design-oriented perspectives is the penchant of the proposed net-work to achieve and sustain a predictable quiescent operating current. Second, we attempt to illuminate the sensitivity of the quiescent current to key transistor parameters. Third, we deter-mine the degree to which the quiescent collector current is affected by increases in the junction operating temperature of the subject bipolar devices. Finally, the dependence of Q-point collec-tor current on signal swings manifested at the collector port is investigated. The last investiga-tion is tantamount to examining the small signal impedance established at the collector port. Since we generally desire a constant collector current and since sources of constant current are characterized by infinitely large terminal impedances, we wish to establish a small signal imped-ance seen looking into the collector terminal of the subject transistor that is ideally infinitely large.

3.4.1.1. World’s Worst BJT Biasing Circuit

The task of developing biasing strategies begins by acquiring an understanding of the two major issues that accompany the task of engineering a bias circuit. These issues, which em-brace quiescent collector current dependence on the static gain parameter, hFE, and the inherently positive temperature coefficient of collector current, are highlighted by the simple biasing cell offered in Figure (3.25a). The circuit at hand uses the voltage divider formed of resistances R1 and R2 to set the quiescent base-emitter voltage, VbeQ, which in turn supports the desired quies-cent collector current, IcQ. Since IcQ is largely determined by the emitter-base junction bias when the transistor operates in its linear domain, it is nominally independent of the collector load resis-tance, Rl, which is selected to satisfy small signal gain or other requirements. However, Rl does set the quiescent collector-emitter voltage, VceQ in accordance with

Figure (3.25). (a). Simple biasing circuit for a bipolar junction transistor. (b). An equivalent representa-

tion of the structure in (a).

cc l cQ ceQV R I V . (3-97)

For a given power supply voltage, Vcc, and a desired quiescent collector current, IcQ, this KVL relationship demonstrates that in view of the fact that VceQ must be sufficiently larger than VbeQ to

I /hcQ FE

R1 Rl

R2

IcQ

IcQ

Vcc

+Vcc

VceQ

h +1FE

R2

hFE

R +R1 2

( )

( )

VbeQ

(a).

I /hcQ FE

Rl

R ||R1 2

IcQ

IcQ

+Vcc

VceQ

h +1FE

hFE

( )VbeQ

(b).


- 243 -

promote BJT operation in its linear regime, large values of Rl must be avoided. In concert with the linear domain requirement, observe that the base current is delineated in Figure (3.25a) as IcQ/hFE, whence an emitter current that is a factor of (hFE +1) larger than the base current.

The application of Thévenin’s theorem to the circuit in Figure (3.25a) results in the equivalent circuit representation that we contrive in Figure (3.25b). In the latter diagram,

cQ2cc 1 2 beQ

1 2 FE

IRV R R V ,

R R h

(3-98)

which delivers

FE 1cQ cc beQ

1 2

h RI V 1 V .

R R

(3-99)

Prior to using this result to assess the quality of the subject biasing circuit, it is important to understand the reason underlying the decision to apply KVL to the base-emitter loop of the cir-cuit, as opposed to using (3-97), which is the fruit of KVL applied to the collector-emitter loop. In particular, (3-97) delivers the irrefutably simpler collector current expression,

cc ceQcQ

l

V VI .

R

(3-100)

While this equilibrium relationship is valid, it conveys the incorrect impression that the quiescent collector-emitter voltage, VceQ, is an independent voltage variable on which the quiescent collec-tor current, IcQ, depends. But (3-33) and (3-36) demonstrate that the collector current of a BJT is only weakly dependent on the internal collector-emitter voltage, Vb, and thus its extrinsic counterpart, VceQ, since the Early voltage, Vaf, is a relatively large voltage metric. Theoretically, the collector current is independent of VceQ if the idealized case of infinitely large Early voltage is adopted. In contrast, (3-33) and (3-36) show a pronounced, exponential dependence of collec-tor current on internal emitter-base junction voltage, Ve, which relates intimately to the base-emitter quiescent voltage, VbeQ. Accordingly, (3-99) propounds a design-oriented, and thus far more relevant, expression for Q-point collector current than does (3-100). In a word, collector-emitter voltage VceQ in (3-100) exerts minimal impact on the quiescent collector current, IcQ, while IcQ in (3-99) is intimately related to the quiescent base-emitter voltage, VbeQ.

Equation (3-99) offers two reasons for nominating the biasing circuit of Figure (3.25a) as the worst in the world. The first of these reasons is the direct dependence of quiescent collec-tor current on the gain metric, hFE. We recall that hFE is directly proportional to the Ebers-Moll current transfer parameter, βf, which, because of its inverse dependence on the narrow width of the base in a bipolar junction transistor, can neither be controlled nor predicted accurately and reliably. Thus, the precise value of hFE for a given transistor is elusive, which renders an accu-rate prediction of IcQ dubious. The upshot of the matter is that conventional monolithic processing, which advances a vagarious nature to hFE, renders impossible the accurate numerical delineation of IcQ in Figure (3.25a).

A second reason motivating a veto of the biasing circuit at hand is unacceptably large temperature sensitivity of the quiescent collector current. Recall from the discussion in Section (3.2.0) and the temperature sensitivity disclosures in the preceding chapter on PN junction diodes that in order to sustain constant current in the face of junction temperature increases, the internal emitter-base (diode) junction voltage must decrease with junction temperature at a nominally constant rate. This requisite decrease in intrinsic emitter-base junction voltage can be semi-empirically translated to a decrease in terminal base-emitter voltage, VbeQ, as


- 244 -

beQ be jΔV S ΔT , (3-101)

where Sbe is a constant of the order of 2 mV/C, and Tj is the change observed in the operating temperature, Tj, of the emitter-base junction. Accordingly, (3-98) provides a collector current temperature coefficient, say i, (since this text is slotted for the university student market, the liberal use of Greek symbols is compelled) of

cQ FE bei

j 1 2

ΔI h Sσ .

ΔT R R (3-102)

The expression at hand shows that the temperature sensitivity factor, Sbe, is amplified by hFE, which while precisely unpredictable, is nonetheless an assuredly large number. The actual temperature coefficient of the quiescent collector current can be expected to be somewhat larger than i in (3-102) owing to the slight dependence on temperature of parameter hFE and the non-zero temperature coefficients associated with the circuit resistors used in the biasing network.

It is important that we supplement, through mere circuit inspection, the temperature sensitivity implications of (3-102) with an engineering appreciation of this important issue. In particular, if hFE is very large, which is to say that the base current in the network shown in Fig-ure (3.25a) approaches zero for finite collector current IcQ, voltage Vbe derives as a simple resis-tive divider off the power line voltage, Vcc. Indeed, this observation is confirmed by (3-98). To the extent that the resistance ratio, R2/R1, is accurately controlled and nominally temperature invariant, and assuming that voltage Vcc is a temperature invariant constant, the base-emitter ter-minal voltage, VbeQ, and hence, the internal emitter-base junction voltage, Ve, are held constant. But we have already witnessed that in order to mitigate the of a BJT saturation current that in-creases with increasing junction temperature, voltage Ve (and hence Vbe) must decrease at roughly a temperature rate of 2 mV/°C. Unfortunately, the divider in the subject circuit sustains constant VbeQ. This means that the collector current is free to increase with temperature in accor-dance with the degree to which the transistor saturation current is sensitive to junction tempera-ture.

Aside from providing a qualitative measure of the alleged ineffectiveness of the biasing cell depicted in Figure (3.25a), the foregoing discourse offers a clue as to how we might improve the biasing design. In particular, we need to allow Vbe to decrease appropriately with tempera-ture. As we shall see in the next section of material, this decrease can be achieved by employing feedback that senses the undesirable temperature-induced increase in quiescent collector current. Once sensed, this increased collector current can be transformed to a voltage, probably through use of nothing more complicated than a resistor. The transformed voltage (voltage across the deployed resistance) can then be used to subtract from the voltage used to drive the base-emitter terminals of the transistor. In the process, collector current IcQ is forced to decrease in response to its original thermally induced increase. We can even propose that the quality of our compen-sated bias network can be meaningfully quantified by comparing the original current increase to its feedback-controlled decrease. Obviously, we achieve nirvana if the decreased collector cur-rent matches the original, temperature-induced, increased current.

EXAMPLE #3.5:

The silicon transistor in the biasing circuit of Figure (3.25a) has a minimum hFE of 100. Using a 3 volt power supply, design the circuit so that it dissipates no more than 8 mW of power, while delivering a quiescent collector current of 2 mA


- 245 -

at a collector-emitter voltage of 1 volt at room temperature. Assume that the transistor delivers hFE = 100 and that the required quiescent base-emitter vol-tage, Vbe, is 720 mV. For this design, estimate the resultant change in quiescent collector current when the emitter-base junction temperature rises by 30 C. To the latter end, take Sbe = 1.8 mV/C.

SOLUTION #3.5:

(1). The simplest calculation pertains to the collector load resistance, Rl. From either Figure (3.25a) or (3-100), IcQ = 2 mA, Vcc = 3 volts, and VceQ = 1 volt requires

cc ceQl

cQ

V VR 1 KΩ .

I

(E5-1)

(2). The current, say IR1, conducted by resistance R1 in Figure (3.25a) is

beQ cQR1

2 FE

V II .

R h (E5-2)

The subject figure also confirms that the power supply must deliver a current of IcQ + IR1 to the biasing circuit. It follows that the power delivered to the circuit by voltage source Vcc, which is the power, Pdis, dissipated by the biasing circuit, is

beQFEdis cc cQ R1 cc cQ

FE 2

Vh 1P V I I V I .

h R

(E5-3)

Note that the bracketed quantity on the right hand side of this expression is the net current flowing to ground, since the first term in the bracketed quantity is the transistor emitter cur-rent, while the second term is the current flowing through resistance R2. For Vcc = 3 volts, hFE = 100, IcQ = 2 mA, and VbeQ = 720 mV, Pdis = 8 mW stipulates R2 = 1.11 K.

(3). Equation (3-99) can now be exploited to determine the value of resistance R2. For Vcc = 3 volts, hFE = 100, R1 = 1.11 k, IcQ = 2 mA, and VbeQ = 720 mV, R2 = 355.1 . This required value of resistance R2 means that the 8 mW power dissipation specification cannot be met in light of all other stipulated operating requirements.

(4). With Sbe = 1.8 mV/C, hFE = 100, R1 = 1.11K, and R2 = 355.1 , the temperature coeffi-cient, i, of the Q-point collector current is found, using (3-102), to be i = 668.6 μA/C. Given Tj = 30 C, the computed change in collector current is IcQ = iTj = 20.1 mA. In truth, the collector current cannot be perturbed by this amount for at best, the transistor satu-rates as the collector circuit in Figure (3.25a) rises toward its maximum possible value of Vcc/Rl = 3 mA. Even this maximum cannot be precisely achieved in that the collector-emitter voltage can be reduced to only its small, but certainly nonzero, saturation value.


This simple, if not impractical, example teaches two lessons. The first is that all calculations executed on an active network must be carefully scrutinized in light of the assumptions on which these analyses are premised. In the case at hand, it is presumed at the outset that the transistor operates in its linear domain. For linear operation of the circuit at hand, the collec-tor current must remain smaller than about 3 mA, which is the collector current that theoreti-cally flows if the collector-emitter voltage can be reduced to zero. Accordingly, the calculated, temperature-induced change in quiescent collector current of better than 20 mA is a meaningless computation, except to suggest that the transistor in question indeed saturates merely because of an increase in the operating temperature of the emitter-base junction. And mind you, this increased temperature most likely derives as a self-heating phenomena in-curred by the very collector current we are attempting to stabilize in our biasing cell.


- 246 -

The second lesson articulated by this example, is that the circuit in Figure (3.25a) is terrible. Aside from the unpredictability of collector current due to the inherent uncertainty in the gain parameter, hFE, it is difficult to sustain linear domain operation over routinely encountered temperature excursions. For example, routine self-heating of a junction readily results in a 10 C increase in junction operating temperature. But even for this modest 10 C increment, the calculated change in quiescent collector current is almost 6.7 mA, which is more than suffi-ciently large to incur device saturation.

3.4.1.2. Current Controlled Voltage Feedback Biasing

The shortfalls of the simple biasing circuit in Figure (3.25a) are circumvented if an emitter degeneration resistance, Ree, is inserted into the emitter lead, as we show in Figure (3.26a). As we suggested in the preceding section of material, this resistance inserts voltage feedback, which takes the form of the indicated voltage, Vre, developed across resistance Ree, into the base-emitter loop. This voltage is clearly proportional the quiescent collector current, the-reby allowing is to adjust automatically the static base-emitter voltage when the quiescent collec-tor current, IcQ, deviates from its design target. We note that this automatic adjustment capability of base-emitter voltage VbeQ contrasts sharply with the previously considered biasing configura-tion, which effectively and deleteriously maintains constant base-emitter voltage.

Figure (3.26). (a). BJT biasing circuit incorporating emitter degeneration as a feedback vehicle for the

stabilization of the quiescent collector current. (b). Equivalent circuit of the network of (a).

We can glean a qualitative appreciation of the effectiveness of resistance Ree in Figure (3.26a) by assuming at the outset that the quiescent collector current meets its design goal. Subsequent to establishing the correct collector current in the steady state, let IcQ increase, per-haps because of self-heating. The increase in IcQ is sensed directly as an increase in the aforementioned voltage, Vre. A study of the equivalent circuit in Figure (3.26b) allows us to surmise that voltage Vbx at the base node of the transistor is approximately constant. In particu-lar, a constant, current invariant Vbx materializes if the Thévenin resistance, (R1||R2), is small and/or the minimum anticipated value of hFE is large. The latter parametric condition minimizes

I /hcQ FE

R1

Ree Ree

Rl

R2

IcQ

IcQ IcQ

Vcc

+Vcc

VceQ

h +1FE h +1FE

R2

hFE hFE

R +R1 2( ) ( )( )

VbeQ

(a).

I /hcQ FE

Rl

R ||R1 2

IcQ

+Vcc

VceQ

VbeQ

(b).

Vre Vre

Vbx

Vbx

Zx Zx


- 247 -

the quiescent base current conducted by the transistor, thereby ensuring a small voltage drop across the aforementioned Thévenin resistance. Since Vbe = Vbx − Vre, an increase in voltage Vre, is therefore met by a decrease in the base-emitter voltage, Vbe. In turn, diminished Vbe serves to reduce the collector current, thereby offsetting, albeit partially, the parasitic increase in quiescent collector current. Of course, this self-correction mechanism also functions for a decreasing IcQ in that diminished IcQ produces a reduced Vre, which manifests an increased Vbe that mitigates the original current reduction.

By inspection of the equivalent circuit in Figure (3.26b),

cQ2 FEcc 1 2 beQ ee cQ

1 2 FE FE

IR h 1V R R V R I ,

R R h h

(3-103)

whence

1cc beQ

22cQ FE

1 2 1 2 FE ee

RV 1 V

RRI h .

R R R R h 1 R

(3-104)

The dependence of IcQ on the poorly controlled gain parameter, hFE, is substantively reduced if we choose resistances that ensure (R1||R2) << (hFE + 1)Ree. It is interesting that this inequality conflates with our previous requirement that voltage Vbx, which energizes the base terminal of our network, be a constant, independent of the transistor base current. The quantification of the extent to which the parallel combination of resistances R1 and R2 is smaller than the net resis-tance, (hFE + 1)Ree depends on the desired degree of accuracy ascribed to setting the actual collector current. For example, if IcQ is to be controlled to within ±10% of its design target, (R1||R2) ≤ (hFE + 1)Ree/10 constitutes an appropriate design tack. If, on the other hand, ±1% con-trol is required, (R1||R2) should be of the order of 100-times smaller than (hFE + 1)Ree. Degree of accuracy notwithstanding, (R1||R2) << (hFE + 1)Ree collapses (3-104) to the approximate result,

FE 2 1cQ cc beQ

ee 1 2 2

α R RI V 1 V ,

R R R R

(3-105)

where αFE is given by (3-48). Observe that as long as the minimum anticipated value of hFE is much larger than one, as it inevitably is, αFE approaches unity, and IcQ in (3-105) is rendered vir-tually independent of hFE. Accordingly, the inclusion of an emitter degeneration resistance (Ree) serves to mitigate the undesirably pronounced sensitivity of quiescent collector current on hFE. Recall that this undesirable sensitivity is an implicit signature of the awful biasing circuit in Fig-ure (3.25a).

Apart from virtually eliminating the problem of IcQ sensitivity to hFE, emitter degenera-tion proves effectual from the standpoint of relative temperature insensitivity. Using (3-101),

cQ FE bei

j ee

ΔI α Sσ ,

ΔT R (3-106)

which demonstrates that unlike the collector current temperature sensitivity in the circuit of Fig-ure (3.25a), the emitter-base junction temperature sensitivity coefficient, Sbe, is not amplified by the large current gain parameter, hFE. To be sure, (3-100) offers an arguably best case sensitivity measure because of numerous approximations invoked in the course of its development. To wit, (3-106) presumes that the temperature coefficient of resistance Ree is small and can be ignored, the dependence of Vcc on temperature is negligibly small, and the small temperature sensitivity of


- 248 -

parameter αFE is inconsequential. Note that the temperature coefficients of resistances R1 and R2 are likely to prove immaterial in that these resistances appear only as resistive ratios in the quies-cent collector current expression. In particular, let R1 and R2 be laid out proximately on the inte-grated circuit chip so that they experience essentially the same operating temperature. If, in addition, these resistors comparably sized diffused or implanted geometric structures, and if their individual values are within an order of magnitude or so of one another, the temperature depen-dence of either R1/R2 or R2/R1 is unlikely to prove significant to the observed performance of the circuit. For a given sensitivity target, (3-106) establishes a convenient basis for selecting appropriate emitter degeneration.

The degree to which current IcQ modulates in response to signals appearing at the collector port of the network in Figure (3.26a) can be discerned through quantifying the indicated output impedance, Zx, established at the collector terminal. To this end, the subject transistor can be replaced by the transistor small signal model of Figure (3.15). At very high frequencies, impedance Zx is invariably dominated by the shunting substrate capacitance, Cs, which is a rela-tively large parasitic capacitance in conventional monolithic processes. Accepting this conten-tion without proof, attention presently focuses on uncovering only the low frequency component, say Rx, of impedance Zx. Accordingly, all capacitances in the transistor model at hand are set to zero. The ohmic resistances, re, and rc, are also ignored without fear of significant accuracy impairment, so that the resultant low frequency, small signal equivalent circuit is the topology delineated in Figure (3.27). In this representation, voltage Vcc is supplanted by a short circuit since the small signal value of this ideally constant voltage is zero. An additional noteworthy point is that output resistance Rx does not include the collector load resistance, Rl. Such neglect does not reflect engineering oversight since the analytical objective here is to discern the sensitivity of quiescent collector current to signal changes at the collector terminal for any load resistance that sustains transistor operation in its forward active domain.

Figure (3.27). Approximate low frequency model used to evaluate

the small signal resistance, Rout, presented at the collector port of the biasing network shown in Fig-ure (3.26a).

The desired resistance, Rx, is the voltage to current ratio, Vx/Ix, of mathematical ohmme-ter variables, Ix and Vx. For convenience, we have delineated the branch current responses to the imposed ohmmeter excitation in Figure (3.27). By KVL,

1 2 bb π ee ee x

x o ee x ac o ee

0 R R r r R I R I.

V r R I β r R I

(3-107)

rbb

r ro

ReeR ||R1 2

ac I

I

Rx

Ix

Vx

I Ix ac

I I x


- 249 -

Solving the first of these two equations for current I, thence inserting this solution into the second expression, leads to

x ac eex ee 1 2 bb π o

x ee 1 2 bb π

ac eeo

ee 1 2 bb π

V β RR R R R r r 1 r .

I R R R r r

β R1 r .

R R R r r

(3-108)

The indicated approximation is reflective of the fact that the Early resistance, ro, and the AC beta, βac, are typically large numbers. While Rx, is assuredly finite, (3-108) confirms that an emitter degeneration resistance can render resistance Rx significantly larger than the Early resis-tance. Because of a potentially very large Rx, the biasing network in question supplies a quies-cent collector current that is relatively unaffected by signal voltage swings at the collector node. In other words in the limit as Rx approaches infinity, the collector port functions as an ideal cur-rent that sinks to ground. We recall from our good old basic circuit days that an ideal current source (or sink) establishes a current that is independent of the voltage appearing across the source. Thus, with resistance Rx very large, any voltage appearing with respect to ground at the transistor collector terminal has almost no stamina to perturb the collector current.

EXAMPLE #3.6:

The silicon NPN transistor in the biasing circuit of Figure (3.26a) has a mini-mum hFE of 100 and a nominal base-emitter voltage of 720 mV at room tempera-ture. Using a 6-volt power supply, design the circuit to provide a quiescent collector current of 2 mA at a collector-emitter voltage of 1.5 volts at room temperature. The desired quiescent collector current is to be maintained to within ±5% for junction temperature increases as large as 50 °C. An emitter-base junction temperature coefficient of Sbe = 2.0 mV/°C can be presumed Us-ing the HSPICE NPN BJT model parameters given in Table (3.1), simulate the design at 27°C, 50 °C, and 75 °C. Assuming rbb = 250 Ω, r = 1.4 KΩ, ro = 28 KΩ, and βac = 95 amps/amp at the quoted quiescent operating point, estimate the change in the collector Q-point current for a 500 mV signal swing at the collector terminal.

SOLUTION #3.6:

(1). Since the maximum allowable increase in quiescent collector current is 5% of its room temperature, 2 mA value, IcQ ≤ (0.05) (2 mA) = 100 A. Given Tj = 50 C, i = IcQ /Tj ≤ 2 A/C. Using (3-106), in which Sbe = 2 mV/C and FE = hFE /(hFE + 1) = 100/101 = 0.9901,

FE bei

ee

α Sσ 2 μA / C ,

R (E6-1)

which results in Ree ≥ 990.1 Ω. Rounding this resistance upward to Ree = 1 KΩ is prudent engineering action in that a larger than minimally required emitter degeneration resistance provides for a small amount of proverbial breathing room with regard to the target tempera-ture sensitivity of the biasing network.

(2). The circuit in Figure (3.26a) yields


- 250 -

SPICE

SYMBOL

TEXT

SYMBOL

DESCRIPTION

OF PARAMETER

VALUE UNITS

BF f Forward Short Circuit Gain 120 amps/amp

BR r Reverse Short Circuit Gain 1.2 amps/amp

CJC Cjco Zero Bias B-C Depletion Capacitance 1.1 fF

CJE Cjeo Zero Bias B-E Depletion Capacitance 3.8 fF

CJS Cso Zero Bias Substrate Depletion Capacitance 10.2 fF

IKF Ikf Forward Knee Current 11.5 mA

IRB Irb Base Resistance Corner Current 4.5 mA

IS Is Saturation Current 3.2 fA

MJC mc B-C Junction Grading Coefficient 0.333 –

MJE mje B-E Junction Grading Coefficient 0.5 –

MJS ms Substrate Junction Grading Coefficient 0.5 –

NF nf B-E Junction Injection Coefficient 1.05 –

NR nr B-C Junction Injection Coefficient 1.0 –

RB rbb Zero Bias Base Resistance 270 RBM Rbm Minimum Base Resistance 35 RC rc Series Collector Resistance 20 RE re Series Emitter Resistance 1.5 TF fo Zero Bias Minority Carrier Transit Time 4.2 pSEC

TNOM Tj Junction Reference Temperature 27 C

VAF Vaf Forward Early Voltage 30 volts

VJC Vjc B-C Junction Built-In Potential 780 mvolts

VJE Vje B-E Junction Built-In Potential 920 mvolts

VJS Vjs Substrate-Collector Built-In Potential 690 mvolts

XTI Temperature Exponent For IS 3 −

XTF Temperature Exponent For TF 0.025 −

XTB Temperature Exponent For BF 0.02 − Table (3.1). HSPICE model parameters for a representative NPN bipolar junction transistor having a maxi-

mum unity gain frequency of approximately 35 GHz. Although the transistor characterized here-with is fictitious, the parameters are typical of a moderately high speed BJT.

FEcc l cQ ceQ ee cQ

FE

h 1V R I V R I .

h

(E6-2)

With Vcc = 5 volts, VceQ = 1.5 volts, hFE = 100, IcQ = 2 mA, and Ree = 1 KΩ, the collector load resistance, Rl, computes as Rl = 1.24 KΩ.

(3). The parallel resistance combination, (R1||R2) must be selected so that it is substantially smaller than the effective resistance, (hFE + 1)Ree. Since the target quiescent collector current is to be sustained to within ±5% over the quoted temperature excursion, (R1||R2) must be at most (hFE + 1)Ree/20, or 5.05 KΩ. It is therefore reasonable to stipulate (R1||R2) = 4 KΩ, the-


- 251 -

reby ensuring, with ostensibly adequate safety margin, the validity of tacitly neglecting the parallel resistance, (R1||R2), in (3-104).

(4). Equation (3-105) can be recast as

1 2FE 1

cQ cc beQ1 1 21 2 FE ee

R Rh RI V V ,

R R RR R h 1 R

(E6-3)

in which the only unknown quantity is the resistance ratio, (R1||R2)/R1. Solving for this ratio results in the arguably sloppy, but nonetheless tractable, relationship,

1 2 FE eecQ beQ

FE1 2

1 cc

R R h 1 RI V

hR R0.470 .

R V

(E6-4)

Since (R1||R2) = 4 KΩ, R1 = 8.51 KΩ, whence

1 2 12

1 1 2

R R RR 7.55 KΩ .

R R R

(E6-5)

(5). For the computed biasing resistances and the quoted small signal transistor parameters, (3-108) gives Rx = 428.8 KΩ. This means that for a collector terminal signal of 500 mV, the sig-nal-induced change, IcQ, in the quiescent collector current is IcQ = 500 mV/428.8 KΩ = 1.17 A, which is only 0.058% of the target quiescent current.

Figure (3.28). Biasing circuit designed in Example #3.6.

The voltages shown in the boxes correspond to the estimated respective node voltages for a properly functioning circuit.

The completed design is shown in Figure (3.28). To facilitate circuit debugging with meas-ured or simulated results, we have explicitly indicated target node voltages in the diagram.


The simulated results track very favorably with design predictions. In particular, the simu-lated quiescent collector current at 27 C is 1.98 mA, which is only 1% lower than the 2 mA design target. At 50 °C, the simulated Q-point collector current is 2.01 mA, while at 75 °C, the simulated value of IcQ is 2.05 mA, which is larger than the 27 °C value of 1.98 mA by only 3.54%. Moreover, at 27 °C, the simulated collector, base, and emitter voltages, measured with respect to ground, are 3.55 volts, 2.75 volts, and 2.00 volts, respectively.

The circuit at hand is an excellent biasing circuit from the admittedly limited perspective that

8.51 K

1 K

1.24 K

+6 V

7.55 K

3.52 V

2.02 V

2.74 V


- 252 -

both manual and computer-aided analyses confirm the predictability of the quiescent collector current. It also offers adequate desensitization of this collector current with respect to temperature changes, uncertainties in parameter hFE, and collector signal change, which at 500 mV is actually reasonably large by conventional small signal standards. However, it does exude at least a few shortcomings, whose respective significance is better appreciated in a subsequent chapter that addresses the gain characteristics of the amplifier that derives from the considered biasing topology. In particular, it turns out that the maximum voltage gain af-forded by the circuit at hand is the ratio of the collector load to emitter degeneration resis-tances. In the present case, this ratio is barely above one, but mitigation procedures are fortu-nately available. Moreover, the relatively large emitter degeneration resistance required for suitable temperature compensation increases the equivalent input noise voltage, which is the minimum signal strength that the amplifier can detect and process reliably. In most applica-tions, this dilemma can likewise be addressed satisfactorily.

3.4.2. ACTIVE BIASING NETWORKS

Although passive biasing structures can stabilize the quiescent operating points of bipo-lar junction transistors over temperature, their ultimate effectiveness in monolithic circuit realiza-tions is limited. One commonly encountered problem is that the ratios of requisite resistance val-ues in these compensation schemes are large. Three problems prevail with respect to resistance pairs whose values are divergent. The first is that controlling the accuracy of a resistance ratio is progressively more difficult with increasing ratio value. The second is non-uniformity of temperature coefficients between diverse resistance values. Yet another quandary is that the resistance values required for acceptable temperature stabilization are often not synergistic with the desired small signal performance that the network undergoing biasing must ultimately de-liver. To this end, for example, we have noted that the large emitter degeneration resistance in the design example of Figure (3.28) limits the achievable voltage gain of the cell without addi-tional design heroics or modifications.

The foregoing shortfalls can be circumvented in integrated circuits by using companion transistors to control the operating point stability of a given transistor. The basic approach is to develop topological structures for which the quiescent variable of interest in a particular transis-tor is constrained to be directly proportional to the corresponding, and presumably easily stabi-lized, variable of a second, subsidiary transistor. This design tack can prove effective if the second transistor offers volt-ampere characteristics that match those of the transistor for which the quiescent collector current is to be stabilized. One advantage of this active stabilization ap-proach is that judiciously laid out transistor pairs in monolithic embodiments can be matched remarkably well so that their thermal properties track accurately with one another over broad temperature ranges. As a result, design attention can focus on the relatively simple subsidiary subcircuit, with the confidence that the monolithic process is capable of delivering transistor res-ponses that track exceptionally well with the variables proscribed in these ancillary cells. Interestingly enough, the methods documented in the following subsections are far less effective with discrete, off the shelf component, circuit realizations since the relevant electrical characteristics of even ostensibly identical transistor types from the same device manufacturer are rarely matched well.

3.4.2.1. Diode-Resistor Current Mirror

A popular of active biasing compensation structure is the circuit offered in Figure (3.29). A comparison of this circuit with the network in Figure (3.26a) shows that a diode-con-


- 253 -

nected transistor, Q2, (base and collector terminals are electrically tied together) is inserted in series with the resistance R2 in the hope of incurring excellent stabilization of the quiescent collector current, IcQ, conducted by transistor Q1. It is extremely important that, save possibly for differences in emitter-base junction areas, the two BJTs be matched devices that are imple-mented in a manner that ensures that they conduct nearly identical current densities. If Q1 and Q2 are indeed matched and conduct identical densities of static current, their base-emitter vol-tages, VbeQ, are necessarily equal. An equality of these two terminal voltages over all reasonable temperature excursions additionally requires that the subject two transistors be laid out closely to one another so that both experience essentially the same temperatures. Accordingly, if the emit-ter current of transistor Q2 is designated as IdQ,

FEbeQ 2 dQ beQ ee cQ

FE

h 1V R I V R I .

h

(3-109)

Figure (3.29). Active biasing compensation through the addi-

tion of diode-connected transistor Q2 to the basic passive structure of Figure (3.26a).

Since hFE >> 1 (if hFE is not much larger than one, it is time to contract with an alternate processing foundry),

FE 2 2cQ dQ dQ

FE ee ee

h R RI I I ,

h 1 R R

(3-110)

which contends that IcQ mirrors current IdQ through the scale factor, R2/Ree. The fact that the sub-ject constant of proportionality is a simple resistance ratio is symphonic. In particular, if R2 and Ree are of the same order of magnitude, ratio R2/Ree can be controlled precisely (to within a couple of percent or less) over broad ranges of temperature. In a word, stabilizing IdQ automati-cally renders current IcQ stable over temperature, despite the ramifications of other environmental factors.

The most straightforward design circumstance is R2 = Ree, whereupon, IcQ is literally the mirror image of IdQ. But note that if R2 is larger than Ree by a factor of k (k >1), IdQ, is a fac-

I /hcQ FE

I /hcQ FE

R1

Ree

Rl

R2

IcQI +dQ

IdQ IcQ

+Vcc

VceQ

h +1FE

hFE

( )

VbeQ

VbeQ

Q1

Q2

Rx


- 254 -

tor of k smaller than IcQ, which is advantageous from a circuit power dissipation perspective. In other words, the added ancillary branch that is inserted for compensation purposes burns less power than does the branch whose collector current is to be controlled. In this case, the junction injection area of transistor Q1 must be made k-times larger than that of transistor Q2 to ensure that both transistors conduct the identical densities of current that serve to sustain equivalence between their base-emitter terminal voltages. In actual design environments, integer or non-in-teger values of k that do not exceed roughly six to eight prove viable and effective.

KVL applied to the R1-R2-Q2 branch of the circuit in Figure (3.29) gives

cQcc 1 dQ beQ 2 dQ

FE

IV R I V R I .

h

(3-111)

Appealing to (3-109) for the elimination of the current variable, IdQ, in (3-111) results in a quies-cent collector current of

cc beQ2

cQ FE1 2 1 2 FE ee

V VRI h .

R R R R h 1 R

(3-112)

As in the case of the passive compensation topology of Figure (3.26a), ensuring (R1||R2) << (hFE + 1)Ree all but eliminates a collector current dependence on hFE in that (3-112) consequently re-duces to

cc beQ2cQ FE

1 2 ee

V VRI α .

R R R

(3-113)

This result advances a collector current temperature coefficient of

cQ FE be 2i

j ee 1 2

ΔI α S Rσ .

ΔT R R R

(3-114)

Two interesting observations surface from the last expression. The first, and most cla-rion, of the two observations is that the active compensation scheme delivers a collector current temperature coefficient that is smaller than the coefficient associated with the passive compensa-tor by the voltage divider factor, [R2/(R1 + R2]. The second point is that (3-114) combines with (3-113) to yield

cQ cQ beFE be 2i

j ee 1 2 cc beQ

ΔI I Sα S Rσ ;

ΔT R R R V V

(3-115)

that is, the temperature coefficient of interest is actually independent of circuit resistances in that it is set by the desired Q-point collector current, IcQ, the power supply voltage, Vcc, and, of course the transistor properties implied by VbeQ and its voltage sensitivity factor, Sbe. Whereas the pas-sive compensation scheme establishes its current temperature coefficient, σi, via the emitter degeneration resistance, Ree, the active scheme effectively preserves a design degree of freedom by relying on the supply voltage to establish the temperature coefficient of the circuit.

The resistance, Rx, presented to the collector load resistance, Rl, in Figure (3.29) can be evaluated straightforwardly by substituting the low frequency, small signal equivalent circuit of a BJT for both of the devices in the network at hand. In the process of such substitution, care must be exercised to account for the fact that the potentially different junction injection areas of the two transistors foment different values among corresponding small signal parameters. But un-less the reader is exhilarated by detailed circuit analyses, a strongly recommended alternative analytical tack entails a direct exploitation of the resistance result in (3-108), which derives from


- 255 -

a small signal analysis of the biasing configuration in Figure (3.26a). Clearly, the only differ-ence between the two circuits at hand is that a diode-connected transistor (Q2) is inserted in se-ries with resistance R2 in Figure (3.26a). Since the diode-connected BJT is a two terminal ele-ment that is to be replaced by the low frequency version of the small signal model in Figure (3.15), its small signal electrical properties mimic those of a simple two terminal resistance, say Rd. The upshot of the matter is that (3-108) adapts to the circuit in Figure (3.29) merely by replacing resistance R2 by the resistance sum, (R2 + Rd). It follows, essentially by inspection, that Rx in Figure (3.29) is given by

ac1 eex ee 1 2 d bb1 π1 o1

ee 1 2 d bb1 π1

ac1 eeo1

ee 1 2 d bb1 π1

β RR R R R R r r 1 r

R R R R r r

β R1 r .

R R R R r r

(3-116)

There are two outstanding issues about understanding the resistance result, Rx, in (3-116). The first of these issues is to comprehend that under small signal conditions, the manner in which transistor Q2 is connected into the biasing configuration leaves us little choice but to view the Q2 subcircuit as a simple resistance. We can supply two justifications for this allegation. First, with the base and collector terminals connected together, the normally three-terminal transistor collapses to a two-terminal unit. This state of affairs means that Q2 cannot function as an amplifier. Instead, and like any two terminal passive element, the Q2 subcircuit can be con-nected only as an element in series with a network branch or an element in shunt with a branch. Second, upon modeling the two-terminal Q2 subcircuit with our conventional, low frequency small signal transistor equivalent circuit, we are left with a two-terminal, memoryless (meaning no capacitances or inductances prevail as elements in the model) linear subcircuit. This circums-tance is transparent because the small signal transistor model is inherently a linear network. It follows that the current flowing through the Q2 subcircuit is related linearly to the voltage devel-oped across the subcircuit; that is, it behaves as a conventional George Ohm resistance.

The only remaining outstanding issue is the evaluation of resistance Rd in terms of transistor model parameters. To this end, the equivalent circuit of the Q2 interconnection is given in Figure (3.30), where as usual, the internal collector and emitter resistances of the transistor are ignored. The use of our trusty mathematical ohmmeter we depict in the circuit be-fore us delivers

Figure (3.30). Low frequency, small signal equivalent circuit of the diode-connected transistor, Q2, in

the biasing network of Figure (3.29). The model is configured to determine the resistance, Rd, established between the two terminals of the diode unit.

x x

o2 o2

xx ac2 ac2

bb2 π2

V V VI β 1 I β 1 ,

r r r r

whereupon

Q2

rbb2

r ro2ac2 I

I

Ix

( +1)Iac2

Vx

Rd Rd


- 256 -

x bb2 π2 bb2 π2d o2

x ac2 ac2

V r r r rR r .

I β 1 β 1

(3-117)

Owing to a large AC beta, resistance Rd is small and very likely, it is significantly smaller than the biasing resistance, R2, in the network of Figure (3.29). It therefore materializes that from a practical perspective, the base to ground branch in Figure (3.29) is virtually electrically indistinguishable from the base to ground branch in Figure (3.26a).

EXAMPLE #3.7:

The silicon NPN transistors in the active biasing circuit of Figure (3.29) have a minimum hFE of 100 and a nominal base-emitter voltage of 720 mV at room temperature. Design the circuit so that with a collector load resistance to emitter degeneration resistance ratio of 10, a quiescent collector current of 2 mA flows through transistor Q1 when its collector-emitter voltage is 1.5 volts at room temperature. The desired quiescent collector current is to be maintained to within ±5% for junction temperature increases as large as 50 °C. An emitter-base junction temperature coefficient of Sbe = 2.0 mV/°C can be presumed Us-ing the HSPICE BJT model parameters given in Table (3.1), simulate the design at 27 °C, 50 °C, and 75 °C.

SOLUTION #3.7:

(1). Since the maximum allowable increase in quiescent collector current is 5% of its room temperature, 2 mA value, IcQ ≤ (0.05) (2 mA) = 100 A. Given Tj = 50 °C, σi = IcQ /Tj ≤ 2 A/°C. Using (3-115), in which Sbe = 2 mV/°C and VbeQ = 720 mV,

cQ bei

cc beQ

I Sσ 2 μA / C ,

V V

(E7-1)

which offers Vcc ≥ 2.72 volts. A power supply voltage of Vcc = 3 volts is appropriate, particu-larly since 1.5 volt battery cells are readily available commercially.

(2). The circuit in Figure (3.29) shows that

FEcc l cQ ceQ ee cQ

FE

h 1V R I V R I .

h

(E7-2)

With Vcc = 3 volts, VceQ = 1.5 volts, hFE = 100, IcQ = 2 mA, and Rl = 10Ree, we find that the requisite emitter degeneration resistance is Ree = 68.1 Ω and hence, the collector load resis-tance follows as Rl = 10Ree = 681 Ω.

(3). In Figure (3.29) and (3-109), let the emitter current conducted by transistor Q2 be equal to the emitter current flowing in transistor Q1, which means that both are required to have the same emitter-base junction injection areas. Accordingly, R2 = Ree = 68.1 Ω. Moreover, with R2 = Ree, (R1||R2) < Ree. It follows that the requisite inequality, (R1||R2) << (hFE +1)Ree, is satisfied by a factor of better than (hFE +1) = 101, which is more than sufficient in light of the ±5% tolerance constraint imposed on the desired quiescent collector current.

(4). Setting R2 = Ree in (3-112) now leads to R1 = 1,061 Ω. The completed design is shown in Figure (3.31). As in the preceding design example, target node voltages are delineated in the diagram.


- 257 -

Figure (3.31). Biasing circuit designed in Example #3.7. All resis-

tances are in units of ohms. The voltages shown in the boxes correspond to the estimated respective node voltages for a properly functioning circuit.


Once again, the simulated results confirm the propriety of the design methodology. In particular, the simulated quiescent collector current at 27 C is 1.97 mA, which is only 1.5% lower than the 2 mA design target. At 50 °C, the simulated Q-point collector current is 2.00 mA, while at 75 °C, the simulated value of IcQ is 2.03 mA, which is larger than the 27 C value of 1.97 mA by only 3.05%. Moreover, at 27 °C, the simulated collector, base, and emitter voltages of transistor Q1, measured with respect to ground, are 1.66 volts, 884 mV, and 135.3 mV, respectively.

While the active compensator postured herewith is a superb biasing network, it, like virtually all electronic networks, is imperfect. In the case at hand, the desired match between transis-tor base-emitter voltages over temperatures is non-exact because of the finite Early voltages of the transistors and the fact that the collector-emitter voltages of the two transistors are un-likely to equate. In particular, observe that the collector-emitter voltage of transistor Q2 is necessarily constrained to be its base-emitter terminal voltage, while the collector emitter vol-tage of Q1 is designed to be better than twice the base-emitter voltage. Accordingly, the collector current correction for the Early effect differs for each transistor.

3.4.2.2. Diode Current Mirror

Discovering that the temperature coefficient of the collector current in the diode-resis-tor configuration of Figure (3.29) is independent of the emitter degeneration resistance, Ree, hints at the possibility of designing a suitable biasing network that is divorced of emitter degeneration. The advantages of dispelling emitter degeneration include decreased circuit power dissipation, the potential for increased small signal gain, and reduced noise.

To the foregoing end, consider the diode mirror shown in Figure (3.32), which uses, in addition to the collector load resistance, Rl, only one additional resistance, R, to bias the circuit. KVL applied to the R-Q2 branches of the circuit gives

137.6 mV

857.6 mV

1,061

68.1

681

68.1

+3 V

Q1

Q2

137.6 mV

1.64 V


- 258 -

Figure (3.32). Diode current mirror BJT biasing circuit. The

emitter-base junction area of transistor Q1 can be k-times larger than that of transistor Q2, which is otherwise identical to transistor Q1.

cQcc dQ beQ

FE

IV R I V .

h

(3-118)

Let us select transistor Q1 to be identical to transistor Q2, save for the fact that the emitter-base junction area of Q1 is larger than that of Q2 by a factor of k. Assume further that base conductivity modulation (or Early effect) in both transistors is insignificant and/or the collector to emitter Q-point voltages of the two transistors are not widely divergent. Then, the fact that the indicated circuit connections force an identity between the base-emitter terminal voltages of both active devices means that the emitter current, IdQ, flowing through Q2 is k-times smaller than the emitter current of Q1; that is,

cQFEdQ

FE

Ih 1I .

h k

(3-119)

In accordance with the fundamental premise of an actively compensated biasing network, the de-sired Q-point collector current is merely proportional (by a factor of essentially k) to the current, IdQ, conducted by the ancillary network, which in this case is comprised of resistance R and di-ode-connected transistor Q2. The substitution of (3-119) into (3-118) resultantly accrues

FE cc beQcQ

FE

h V VI .

h 1R 1

k

(3-120)

The virtual elimination of a collector current dependence on parameter hFE mandates satisfaction of the inequality, (hFE + 1) >> k, which is easy enough to achieve. Thus,

FE cc beQcQ

α k V VI ,

R

(3-121)

which infers a Q1 quiescent collector current that is about k-times the current conducted by the R-Q2 subcircuit. It is a simple matter to confirm a collector current temperature coefficient of

I /hcQ FE

I /hcQ FE

R Rl

IcQI +dQ

IdQ IcQ

+Vcc

VceQ

h +1FE

hFE

( )

VbeQ

VbeQ

Q1

Q2

Rx


- 259 -

cQ cQ beFE bei

j cc beQ

ΔI I Sα kSσ ,

ΔT R V V

(3-122)

whose final form is identical to the temperature factor associated with the diode-resistor mirror. It is worthwhile repeating that the circuit at hand boasts numerous advantages over its resistor-diode counterpart. However, one disadvantage is that the resistance, Rx, seen looking into the collector node of transistor Q1 is simply the Early resistance, ro1. We see then that the lack of emitter degeneration in transistor Q1 results in an output resistance that is significantly smaller than the output resistances observed in the degenerated biasing cells.

3.4.2.3. Vbe Multiplier Biasing

In the bipolar biasing circuits considered to this point, the quiescent collector current is consistently couched as a function of two transistor variables; namely, the DC beta, hFE, and the quiescent base-emitter terminal voltage, VbeQ. The dependence of collector current on the numerically unreliable metric, hFE, is reduced to insignificant levels through having sufficiently large hFE. On the other hand, the current dependence on Vbe, which is tantamount to a quantifica-tion of the collector current sensitivity to junction operating temperature, is mitigated with pru-dently selected emitter degeneration resistance and/or the use of a large enough power line vol-tage, Vcc. If it were possible to eliminate, as opposed to merely reducing, the collector current dependence on base-emitter voltage, practical circuits offering the engineer enhanced degrees of design freedom and possessed of impressively small temperature sensitivities become reality.

Figure (3.33). BJT biasing circuit using active compensation in the form of the Vbe

multiplier comprised of transistor Q2 and resistances R3 and R4.

I /hcQ FE

I /hcQ FE

R1

R2

Ry

Rx

Rl

IcQI +m

Im

IcQ

+Vcc

VceQ

Vm

h +1FE

hFE

( )

VbeQ

Vbe2

Q1

Q2

Ree

Ic

Rx


- 260 -

To the foregoing end, we shall find that the circuit appearing in Figure (3.33) is theoretically capable of realizing the ideal goal of a quiescent collector current, IcQ, which is independent of base-emitter voltage VbeQ. The core subcircuit underpinning this alluring perfor-mance attribute is the so-called Vbe multiplier, which consists of transistor Q2 and the two resistances, R3 and R4. An analytical inspection of the Vbe multiplier cell itself, which is redrawn for convenience in Figure (3.34a), facilitates the task of evaluating the volt-ampere properties of the biasing network in Figure (3.33). In Figure (3.34a), KCL relates the current, Im, conducted by the voltage multiplier cell to the static collector current, Ic2, flowing in transistor Q2 as

Figure (3.34). (a). The Vbe multiplier used in the biasing scheme depicted in Figure

(3.31). (b). The Thévenin equivalent static circuit of the cell in (a).

be2 c2 be2FE2m c2 c2

4 FE2 FE2 4

V I Vh 1I I I .

R h h R

(3-123)

Moreover, the voltage, Vm, established across the cell in response to the flow of current, Im, is

be2 c2m 3 be2

4 FE2

V IV R V .

R h

(3-124)

If we solve (3-123) for the transistor current, Ic2, and substitute the result into the last expression, we find that voltage Vm relates to base-emitter voltage Vbe2 and cell current Im as

FE2 3 3m be2 m m be2 m m

4 FE2

α R RV 1 V I k V R I .

R h 1

(3-125)

This result fosters the multiplier equivalent circuit in Figure (3.34b), where model parameters km and Rm are given by

FE2 3m

4

3m

FE2

α Rk 1

R.

RR

h 1

(3-126)

The model in Figure (3.34b) suggests that the multiplier cell emulates a Thévenin vol-tage source whose voltage is Vbe2, multiplied by the larger than unity factor, km. The subject fig-ure also suggests that the Thévenin resistance, Rm, associated with the foregoing voltage is rela-tively small. Note that if R3 = 0, km = 1 and Rm = 0, which renders voltage Vm identical to the base-emitter voltage, Vbe2, of transistor Q2. This result reflects our expectations since R3 = 0 short circuits the base terminal of transistor Q2 to its collector terminal. In turn, this short circuit

R3

R4

Im Im

Vm

Vbe2

Q2

Ic2

I /hc2 FE2

I /hc2 FE2

V /Rbe2 4

V /Rbe2 4

k Vm be2

(a).

Rm

(b).

Vm


- 261 -

reduces the Q2-R3-R4 subcircuit to a simple diode-connected transistor whose terminal voltage is Vbe2. For large hFE2, the multiplier approximates an ideal voltage source whose voltage value is

FE2 3 3 be2m be2 be2 be2 3 4

4 4 4

α R R Vk V 1 V 1 V R R .

R R R

(3-127)

The final form relationship in this expression is rendered transparent by mere inspection of the network in Figure (3.34a). In particular, Vbe/R4 is clearly the current conducted by resistance R4. If gain metric hFE is large, the base current conducted by transistor Q2 is nil. It therefore follows that current Vbe/R4 also flows through resistance R3, which effectively places resistances R3 and R4 in series with one another. Clearly, the last form of the expression in (3-127) represents the product of this net series resistance and the current conducted by it.

Figure (3.35). Equivalent electrical representation of the biasing network in Figure (3.33), wherein the Vbe

multiplier comprised of Q2-R3-R4 is supplanted by its equivalent circuit, which we depict in of Figure (3.34b). Transistors Q1 and Q2 are presumed to be identical devices that are biased to con-duct the same collector current densities, thereby implying that Vbe2 = VbeQ and hFE2 = hFE.

Armed with the subcircuit model of Figure (3.34b), the biasing network in Figure (3.33) can be represented electrically as the structure given in Figure (3.35). The latter configuration exploits the presumption that transistors Q1 and Q2 are identical devices that con-duct identical collector current densities. Accordingly, the voltages developed across both base-emitter terminals are identical, as are the DC beta values of the two transistors. It is instructive to observe that the structure in Figure (3.35) collapses to the diode-resistor biasing scheme of-fered in Figure (3.29) for the special case of km = 1 (or R3 = 0). In Figure (3.35),

I /hcQ FE

I /hcQ FE

R1

R2

R3

R4

Rl

IcQI +m

Im

IcQ

+Vcc

VceQ

Vm

h +1FE

hFE

( )

VbeQ

Vbe2

Q1

Q2

Ree

Ic

k Vm beQ

Rm

I /hcQ FE

I /hcQ FE

R1

R2

Rl

IcQI +m

Im

IcQ

+Vcc

VceQ

h +1FE

hFE

( )

VbeQ

Q1

Ree


- 262 -

cQcc 1 m 2 m m m beQ

FE

IV R I R R I k V

h

(3-128)

and

FE2 m m m beQ ee cQ beQ

FE

h 1R R I k V R I V .

h

(3-129)

Upon inserting the solution for current Im in (3-128) into (3-127), we find the solution for the quiescent collector current, IcQ, conducted by transistor Q1 to be the somewhat involved expres-sion,

m 1cc beQ

2 m2 mcQ FE

1 2 m 1 2 m FE ee

k 1 RV 1 V

R RR RI h .

R R R R R R h 1 R

(3-130)

Our confidence in the accuracy of this messy disclosure is bolstered by the observation that for km = 1 (thereby constraining resistance Rm to zero), (3-130) reduces to (3-112), which defines the Q-point collector current appropriate to the diode-resistor compensation scheme of Figure (3.29). Moreover, if km and resistance Rm are artificially set to zero, the network in Figure (3.35) col-lapses to the passive compensation scheme in Figure (3.26a) and reassuringly, (3-130) reduces to (3-104), which is the applicable collector current expression.

In order to desensitize the Q-point collector current in (3-129) to uncertainties in the DC beta, hFE, it is necessary to enforce R1||(R2 + Rm) << (hFE + 1)Ree. As such, (3-129) can be approximated as

m 1cc beQ

2 m2 mcQ FE

1 2 m ee

k 1 RV 1 V

R RR RI α .

R R R R

(3-131)

But in addition, if the constant, km, is selected such that

2 mm

1

R Rk 1 ,

R

(3-132)

the resultant quiescent collector current, which becomes,

2 m FE cccQ

1 2 m ee

R R α VI ,

R R R R

(3-133)

is rendered independent of voltage VbeQ. Recall, however, that this conclusion rests on three assumptions. First, transistors Q1 and Q2 must be physically identical BJTs, save possibly for emitter injection area differences. Second, the two matched transistors must conduct identical collector current densities. Third, either the collector-emitter voltages of the two matched BJTs must be nominally the same or, as is seemingly more pragmatic, both devices must exude negligible Early effect. At a minimum and despite the foregoing presumptions, (3-132) removes the dominant source of collector current sensitivity with respect to operating temperature. We observe further that for large hFE, which delivers αFE ≈ 1 and encourages R2 >> Rm = R3/(hFE + 1), (3-132), becomes, with the aid of (3-126),


- 263 -

3 2

4 1

R R.

R R (3-134)

Two interesting sidebars accompany this simple design requirement. First, if R3/R4 < R2/R1, (km − 1) < R2/R1, and the coefficient of voltage VbeQ in the numerator on the right hand side of (3-130) is resultantly a positive number. Accordingly, IcQ displays its stereotypically positive temperature coefficient in view of the fact that VbeQ must decrease with temperature to preserve constant collector current. But if R3/R4 > R2/R1, (km − 1) > R2/R1, and the VbeQ coefficient in question is a negative number, thereby implying that IcQ decreases with operating temperature; that is, the circuit projects an atypical negative temperature coefficient. In effect, the nature of the relationship of resistance ratio R3/R4 to ratio R2/R1 provides an additional design degree of freedom that may prove fruitful with respect to the problem of minimizing the temperature sensitivity of either the I/O gain or the I/O driving point impedances of the overall network.

As in the case of the diode-connected transistor, Q2, in the active biasing scheme of Figure (3.29), the Vbe multiplier cell in the network of Figure (3.33) functions as a two terminal linear resistance under small signal circumstances. As such, its net small signal terminal resis-tance, say Rv, as highlighted in the diagram of Figure (3.36a), derives as the voltage to current ratio, Vx/Ix, in the low frequency equivalent circuit we provide in Figure (3.36b). The equivalent circuit ignores the internal collector and emitter resistances of transistor Q2 and additionally, it simplifies the analysis through the tacit neglect of the routinely large Early resistance, ro, of transistor Q2. In an attempt to appease the analytical purists, the latter resistance appears in shunt with the current controlled current source, βacI, which implies that the effective resistance across the collector and emitter terminals of the Vbe multiplier cell is actually (ro||Rv). For the indicated branch currents in Figure (3.36b),

Figure (3.36). (a). The Vbe multiplier cell embedded in the biasing network of Figure (3.33). (b). The

small signal equivalent circuit pertinent to the evaluation of resistance Rv across the collec-tor-emitter terminals of transistor Q2 in (a). As usual, the model ignores the series resis-tances in the collector and the emitter leads of transistor Q2. Also ignored is the relatively large Q2 Early resistance, which appears as a simple shunting branch element across the terminals at which resistance Rv is established.

bb2 π2 4 x ac2

x 3 x ac2 bb2 π2

r r I R I β 1 I.

V R I β I r r I

(3-135)

Substituting current I from the first of the foregoing equations into the second leads to

R3

R4

Q2

rbb2

rR4

R3

ac2 I

I

RV

Ix

RV

Vx

I Ix ac2

I ( +1)Ix ac2

(a). (b).


- 264 -

x ac2 4v 3 4 d2

x 4 d2

V α RR 1 R R R ,

I R R

(3-136)

where

ac2ac2

ac2

βα

β 1 (3-137)

is known as the small signal, short circuit, common base current gain (more about this definition later in the text), and Rd2 is the diode-connected transistor resistance introduced in (3-117). In particular, observe in Figure (3.36a) that R3 = 0 and infinitely large R4 combine to reduce the Vbe multiplier cell to a conventional diode-connected transistor. Reassuringly, Rv in (3-136) col-lapses to Rd2 for this special case. Since βac2 >> 1, αac2 in (3-137) approaches one, thereby simplifying the expression for resistance Rv to

d2 3v 3 4 d2 m d2

d2 4 4

R RR R R 1 R k R .

R R R

(3-138)

which is only modestly larger than Rd2.

Like the diode-connected transistor in the active biasing scheme of Figure (3.29), the Vbe multiplier subcircuit in Figure (3.33) appears in series with biasing resistance R2. Otherwise, the two subject circuits are identical. It follows by inspection (don’t you just love when profes-sors say that) that the resistance, Rx, presented to the collector load in Figure (3.33) derives di-rectly from (3-116), subject to the caveat that Rd in (3-116) is replaced by Rv; that is

ac eex ee 1 2 v bb π o

ee 1 2 v bb π

ac eeo

ee 1 2 v bb π

β RR R R R R r r 1 r

R R R R r r

β R1 r .

R R R R r r

(3-139)

EXAMPLE #3.8:

The silicon NPN transistors in the active biasing circuit of Figure (3.33) have a mini-mum hFE of 100 and a nominal base-emitter voltage of 720 mV at room temperature. Design the circuit so that with a power supply voltage of Vcc = 6 volts, transistor Q1 conducts a quiescent collector current of IcQ = 2 mA when the collector-emitter voltage, VceQ, of Q1 is 1.5 volts. The circuit is to be designed so that IcQ is nominally invariant with temperature and is maintained at its design target to within ±3%. Use the HSPICE BJT model parameters itemized in Table (3.1) to simulate the finalized design at 27 °C, 50 °C, 75 °C, and 100 °C.

SOLUTION #3.8:

(1). In order to optimize thermal tracking between the identical transistors, Q1 and Q2, the collec-tor current densities of these two transistors must be the same. Additionally, implementing nominally identical collector-emitter voltages between the two devices is recommended to mitigate the effects of base conductivity modulation. Thus, voltage Vm in Figure (3.33) should equate to voltage VceQ, which is stipulated to be 1.5 volts. Ignoring current Ic2/hFE2 in comparison with current Vbe2/R4 in the companion subcircuit diagram of Figure (3.34a) results in


- 265 -

3m be2 ceQ

4

RV 1 V V 1.5 volts .

R

(E8-1)

Given identical collector current densities in the two transistors, Vbe2 = VbeQ ≈ 720 mV, whence R3/R4 = 1.083. Recalling (3-133), which is the condition underpinning the nominal thermal independence of current IcQ, R2/R1 = R3/R4 = 1.083.

(2). In an attempt to conserve standby power, let Q2 conduct one-half the current of transistor Q1, which is to say that the emitter-base junction area of Q1 must be twice that of Q2. Thus, Ic2 in Figure (3.34a) is 1 mA. Moreover, arbitrarily allow resistance R4 to conduct 1 mA of cur-rent, which makes current Im = IcQ ≈ 2 mA. It follows that Vbe2/R4 = VbeQ/R4 = 1 mA, or Rx = 720 Ω. Since R3/R4 = 1.083, R3 = 780 Ω. Note that Ic2/hFE2 = 1 mA/100 = 10 μA, which is 100-times smaller than the current, Vbe2/Rx, thereby supporting (E8-1) to within an error of roughly 1%. We note that this error is safely within the 3% error tolerance assigned to cur-rent IcQ.

(3). If IcQ/hFE << Im, which has been set to 2 mA, Figure (3.33) confirms

cc 1 2 m mV R R I V . (E8-2)

With Vcc = 6 volts, Im = 2 mA, and Vm = 1.5 volts, (R1 + R2) is 2,250 Ω. Recalling that R2/R1 = 1.083, this computation produces R1 = 1,080 Ω and R2 = 1,170 Ω. It is important to check the propriety of the invoked approximations. In the present case, IcQ/hFE << Im has been pre-sumed. Since IcQ/hFE = 2 mA/100 = 20 A and Im = 2 mA, Im exceeds IcQ/hFE by a factor of 100, which amounts to a computational error of around only 1%.

(4). Equation (3-133) can now be used to determine the resistance, Ree. Although resistance Rm, as defined by (3-126) can be ignored because of its inverse dependence on (hFE + 1), it is a trivial matter to include Rm in the calculations. To this end Rm = 7.72 Ω in that R3 = 780 and hFE = 100. Then, with R1 = 1,080 Ω, R2 = 1,170 Ω, αFE = 100/101, and Vcc = 6 volts, Ree = 1,549 Ω. Since (3-133) presumes (R1||R2) = 561.6 << (hFE + 1)Ree = 156.5 KΩ, the approximation is satisfied by a factor of 156.5 K/561.6 = 278.7, which is tantamount to a computational error of 1/278.7 = 0.36%. This small error means that the computed value of Ree is high by nominally (0.0036)(1,549 ) = 5.6 . Given the other approximations in-voked in the course of this design procedure, it may be prudent to reduce Ree by very slightly more than 5.6 . To this end, allow Ree = 1,540 Ω.

(5). The only remaining resistance to be computed is the collector load resistance, Rl. From Fig-ure (3.33),

FEcc l cQ ceQ ee cQ

FE

h 1V R I V R I ,

h

(E8-3)

which straightforwardly y Rl = 694.6 Ω. Figure (3.37) delineates the completed design. As in the preceding design examples, the estimated static node voltages are underscored in the schematic diagram.


The simulated results confirm the propriety of the design methodology. In particular, the simulated quiescent collector current of transistor Q1 at 27 °C is 2.00 mA, while at 50 °C, 75 °C, and 100 °C the simulated Q-point collector current is 2.01 mA. Moreover, at 27 °C, the simulated collector, base, and emitter voltages of transistor Q1, measured with respect to ground, are 4.61 volts, 3.84 V, and 3.11 V, respectively. For Q2, the corresponding voltages are 3.84 V, 3.05 V, and 2.32 V.

Design solutions are rarely unique. In the present example, different design results accrue if a current other than 1 mA is arbitrarily chosen to flow through resistance R4. From a thermal sensitivity perspective, the circuit at hand is clearly excellent. Nonetheless, it is assuredly not


- 266 -

the panacea for BJT biasing for at least two reasons. First, a large number of resistances are required. It is extremely important that the resistance pairs, R1-R2 and R3-R4, respectively track one another well over temperature extremes. Second, we note as we did in the first biasing example, that resistance Ree exceeds the value of the collector load resistance, thereby limiting the available voltage gain in the absence of additional, design heroics.

Figure (3.37). Biasing circuit designed in Example #3.8. All resistances are in units

of ohms. The voltages shown in the boxes correspond to the estimated node voltages for a properly functioning circuit. Transistor Q2 has twice the emitter-base junction area of transistor Q1.

3.4.2.4. N-Stage Current Mirror

The satisfactory performance of many analog networks depends on the reliable and accurate implementation of current sources (or sinks) that act as high impedance active loads for amplifier cells or provide static paths to ground for currents used in the biasing of other subcir-cuits used in these networks. Rather than implement a required multiplicity of current sinks individually, expedience motivates us to derive these sources or sinks from a single reference cell. To this end, a common embodiment is the network in Figure (3.38). The reference current, Io, for the network derives from a subcircuit comprised of branch resistance R and diode-con-nected transistor Q0. The collectors of identical transistors Q1, Q2, · · · QN establish current sinking paths. In these transistors, the emitter-base junction injection area of the nth transistor is a factor of kn larger than the junction area of Q0. Assuming that the transistors are otherwise identical, the obvious identity among the base-emitter terminal voltages of the (N+1) cascaded transistors in Figure (3.38) produces, in general, an emitter current flowing in the nth transistor of knIo. This current supports corresponding collector and base currents of αFEknIo and knIo/(hFE+1) = (1−αFE)knIo, where parameter αFE is related to the DC beta, hFE, by (3-48). The validity of the last statement rests on each transistor operating in its forward active regime. In turn, this require-ment constrains the nth collector-emitter voltage, Vn, to be at least as large as the base-emitter ter-minal potential, Vbe, applied to all transistors. The tacit assumption of equal hFE among all transistors stems from the presumption that either all forward Early voltages are large and/or that no significant differences prevail among the individual collector-emitter voltages for all (N+1)

1080

720

+6 V

Q1

x 2

Q2

1540

3.11 V

1170

780

694.6

4.61 V

2.34 V

3.06 V

3.83 V


- 267 -

transistors.

Figure (3.38). An N-stage current mirror. All (N +1) transistors are fundamentally identical, save

for the fact that the nth transistor has an emitter-base junction injection area that is kn-times larger than that of the diode-connected transistor, Q0.

The reference current, Ir, conducted by resistance R in the circuit of Figure (3.38) must accommodate the Q0 emitter current, Io, and each of the base currents conducted by transistors Q1 through QN. Thus,

N

r o FE o ii 1

I I 1 α I k .

(3-140)

It follows that the current, Icn, conducted by the collector of the nth device is

FE n cc beFE n rcn N N

FE i FE ii 1 i 1

α k V Vα k II .

1 1 α k 1 1 α k R

(3-141)

Clearly, the relative insensitivity to the DC beta, hFE, of any collector current flowing in Q1 through QN demands that

N

i FEFEi 1

1k h 1 .

1 α

(3-142)

The satisfaction of this design requirement is progressively more challenging if one or more of the area scaling factors is large and/or the number of current sinking stages is large. One caveat to this stipulation is that (3-142) is easily satisfied when SiGe HBTs, which have very large hFE, are deployed in the current sinking configuration.

In addition to potentially compromising collector current sensitivity to hFE, large area scaling factors also limit the small signal output resistance, Rxn, achievable in the nth current sink. It is clear that if the nth transistor in Figure (3.38) is replaced by its low frequency, small signal BJT equivalent circuit, Rxn, as indicated in the circuit diagram, is merely the Early resistance, ron, of the nth device. Ignoring internal collector and emitter series resistances, a reference to (3-56) spawns, in terms of the forward Early voltage, Vaf,

n af n af

xn oncn FE n cc be

V V V VR r R ,

I α k V V

(3-143)

Q1 Q2

QNQ0

R

Ir FE 1 ok I FE 2 ok I FE N ok I

Io k I1 o k I2 o k IN o

V1 V2 VN

Vcc

x k1 x k2 x kN

Rx1 Rx2 RxN


- 268 -

where the validity of (3-142) is presumed. We note in this last expression that the current sink output resistance is inversely dependent on the area factor for the nth emitter-base junction. Thus, too large of a scaling factor compromises the desired relative independence of the nth collector current on the voltage impressed with respect to ground at the nth collector node.

An improved version to the N-stage current mirror, offered in Figure (3.39), addresses the potential area scaling shortfall to which the circuit in Figure (3-48) may succumb. Transistor Q0 in this revised circuit diagram no longer functions as a diode. Nonetheless, its emitter still supports a static current of Io, as in the original diagram of Figure (3.38). The insertion of transistor QP, as shown in Figure (3.39), forces its emitter to conduct the sum of the base cur-rents flowing in transistors Q0 through QN, as well as the current, Ip, conducted by the resis-tance, Rp. In principle, resistance Rp, is not required. But without Rp, the emitter of transistor QP conducts only the superposition of the small base currents in transistors Q0 through QN. This small current risks a debilitating reduction in the DC beta of QP, as well as other undesirable ef-fects. In contrast, if Rp is selected to conduct a current that is nominally equal to the emitter cur-rent of transistor Q0, hFE for transistor QP approximates the DC beta of transistor Q0 and hence, the DC beta values of all other transistors.

Figure (3.39). An improved version of the N-stage current mirror in Figure (3.38). The insertion

of transistor QP diminishes the dependence of the nth collector current on both the number of stages deployed and the area scaling factors of these individual stages.

At the risk of analytical prematurity, we offer an additional point −one whose signific-ance will be clarified later when we talk about regulated cascode networks− before proceeding with the analysis of the compensated topology in Figure (3.39). The foundational essence of this point is that transistor Q0 implements active, global, shunt-shunt feedback around transistor QP, which in turn functions as a voltage buffer. The important effect of this active feedback is that it substantially reduces the net Thévenin resistance seen at the node, NP, to which the emitter of transistor QP is incident. This is an important trademark of the modified current sink topology. Its importance stems from the fact that the feedback compensation forces the impedance wit-nessed at node NP to converge toward zero. To be sure, the subject impedance is never going to be zero, but it is indeed small, as we shall demonstrate in a subsequent chapter. If the impedance at node NP is nearly zero, the corresponding NP node voltage, Vbe0, which is the quiescent base-emitter potential of transistor Q0, functions as virtually an ideal voltage source driving the base-emitter terminals of the other N transistors. Thus, the mirroring of voltage Vbe0 at the base-emit-ter terminals of Q1 through QN nears perfection in that Vbeo is rendered almost independent of the net base current drained from node NP.

Q1QP

Q2

QNQ0

R

Ir FE 1 ok I FE 2 ok I FE N ok I

Io

Ip

k I1 o k I2 o k IN o

V1 V2 VN

Vcc

x k1 x k2 x kN

Rx1 Rx2 RxN

Rp

NP


- 269 -

An inspection of the circuit in Figure (3.39) reveals

N

r FE o FE p FE o FE o ii 1

I α I 1 α I 1 α I 1 α I k .

(3-144)

In addition to ensuring nominally identical hFE among all devices, it is convenient to set Ip = Io. In this case,

N

2r o FE o i

i 1

I I 1 α I 1 k ,

(3-145)

which implies that the current flowing through resistance R in Figure (3.39) is essentially invulnerable to the number of current sink stages and the area scaling factors invoked in the net-work. This observation conflates with our feedback argument above. Equally important is that it contrasts sharply with (3-140), which depicts current Ir in the diagram of Figure (3.38) as poten-tially sensitive to loading effects. We note with additional interest that the subject current is nominally equivalent to the emitter current conducted by transistor Q0. Since Ir ≈ Io, the collec-tor current of the nth transistor becomes

FE n cc becn FE n o

α k V 2VI α k I .

R

(3-146)

The result at hand suggests that the price paid for the incorporation of transistor QP into the cas-caded current mirror is a doubling of the temperature sensitivity in that current Io is now depen-dent on twice the emitter-base junction potential, as opposed to the single Vbe dependence pro-jected by (3-141). However, we can somewhat compensate for this doubling through a prudent increase in the value of circuit resistance R.

3.4.2.5. Wilson Current Mirror

The Wilson current mirror mitigates the port resistance limitations pervasive of the N-stage mirror considered in the preceding subsection by exploiting shunt-series feedback to boost output resistance Rx above the Early resistance of the output port transistor[10]. Its basic sche-matic diagram is shown in Figure (3.40). In this diagram, the grounded emitter transistor, Q2, and the diode-connected device, Q3, implement feedback that is in shunt with the base terminal of output transistor Q1 and in series with the emitter lead of Q1. The three transistors are simi-lar, but transistors Q1 and Q3 have an emitter-base junction injection area that is k-times larger than the corresponding injection area of transistor Q2. We can therefore presume that the DC beta values and applied base-emitter terminal voltages of all active devices are nominally the same, especially if each transistor has large forward Early voltages. All devices operate in their forward active regimes. In the case of transistor Q1, such operation requires that the output port voltage, V1, be at least as large as 2Vbe.

For transistor Q2, the reference current, Ir, flowing into the junction of resistance R with the base of Q1 and the collector of Q2 satisfies

cc ber

V 2VI .

R

(3-147)

If the emitter of transistor Q2 conducts a current of I2, as indicated in Figure (3.40), the emitter of transistor Q3 necessarily conducts kI2 in light of the area stipulations and since the base-emit-ter terminal voltages of these two devices are the same. Accordingly, the collector of Q2 con-


- 270 -

ducts current αFEI2, while a current of (1 −αFE)I2 flows into the base of Q2. In order to keep Kirchhoff happy, the emitter of transistor Q1 necessarily supports a current, Ie1, of

Figure (3.40). Basic schematic diagram of the Wilson current mirror.

e1 2 FE 2I kI 1 α I , (3-148)

whence an output port current, I1, flowing into the collector of transistor Q1 of

FE1 FE 2

1 αI α kI 1 .

k

(3-149)

It follows that the current, Ib1, flowing into the base of transistor Q1 is

1 FEb1 FE 2

FE

I 1 αI 1 α kI 1 .

h k

(3-150)

This current requires a resistance current, Ir, of

FEr b1 FE 2 FE 2

FE

k 1 αI I α I α I 1 1 .

h k

(3-151)

Observe that for large hFE, the output current mirrors, by a factor of k, the current conducted by resistance R, which in turn closely approximates the collector current conducted by transistor Q2. Specifically, (3-149), (3-151), and (3-147) combine to deliver

cc be1 FE 2 r

k V 2VI α kI kI .

R

(3-152)

Recalling that base-emitter terminal voltage Vbe decreases with junction temperature Tj in accordance with the linear empirical expression, Vbe ≈ −SbeTj, the temperature-induced perturbation, I1, in current I1 is seen to be

be 1 be1

j cc be

2kS 2I SΔI,

ΔT R V 2V

(3-153)

which in turn stipulates the temperature-induced per-unit change in current I1 as

Q3

Q2

kI2I2

FE 2I

Vcc

Q1

Ie1

x k

x k

x 1

(1 )IFE 2

I1

Ir Ib1

V1

Rx

R


- 271 -

be j be1

1 cc be cc be

2S ΔT 2ΔVΔI.

I V 2V V 2V

(3-154)

As is generally the prerequisite implicit to a design scenario focused on realizing a high degree of temperature stability, an appropriately large supply voltage (Vcc in this case) is recommended.

Figure (3.41). (a). Low frequency, small signal equivalent circuit of the Wilson current mirror

shown in Figure (3.40). The small signal output resistance, Rx, is the voltage to cur-rent ratio, Vx /Ix. (b). The model of (a) redrawn to account explicitly for the fact that the emitter-base junction injection areas of transistors Q1 and Q3 in Figure (3.40) are a factor of k larger than the junction injection area of transistor Q2.

Figure (3.41a) depicts the approximate low frequency, small signal model for evaluat-ing the output resistance highlighted as Rx. In this equivalent circuit, resistance Rd3 derives from (3-117) in that it represents the small signal terminal resistance of diode-connected transistor Q3. The circuit analysis, which is sufficiently sloppy to warrant the company of a nice pinot noir, can more easily be interpreted if the given junction injection ratios are judiciously exploited. To this

rbb1

r1 ro1ac1 aI

Ia

Rx

Ix

Vx

I Ix ac1 a

I Ia ac2 b I Ix arbb2

r2 Rd3ro2R ac2 bI

IbI Ix a Ib

(a).

rbb

r roac aI

Ia

Rx

Ix

Vx

I Ix ac a

I Ia ac b I Ix akrbb

kr Rd3Rss ac bI

IbI Ix a Ib

(b).


- 272 -

end, assume that all transistors are characterized by large forward knee currents and Early vol-tages. Then, since Q1 and Q3 conduct roughly the same collector current, their base, base-emit-ter diffusion, and Early resistances are nominally the same; that is

bb1 bb3 bb

π1 π3 π

o1 o3 o

r r r

r r r .

r r r

(3-155)

In view of the fact that the small signal beta of each device is the product of forward transconductance gm, which nominally varies directly with quiescent collector current, and base-emitter diffusion resistance rπ, which varies inversely with collector current,

ac1 ac2 ac3 acβ β β β . (3-156)

From (3-117),

bb3 π3 bb π bb πd 3 o3 o

ac3 ac ac

r r r r r rR r r .

β 1 β 1 β 1

(3-157)

Since the emitter-base geometry of transistor Q2 is smaller than that of either Q1 or Q3 by a fac-tor of k and since this device conducts a current that is correspondingly k-times smaller than the current supported by transistors Q1 and Q3,

bb2 bb3 bb

π2 π3 π

o2 o3 o

r kr kr

r kr kr .

r kr kr

(3-158)

The immediate modeling ramification of (3-155) through (3-158) is the equivalent circuit given in Figure (3.41b). In this diagram, resistance Rss is given by

ss oR kr R R , (3-159)

which invariably is adequately approximated by merely the circuit resistance, R.

A conventional analysis of the circuit in Figure (3.41b) generates the following equili-brium equations:

d3 x d3 a bb π d3 b

ss a ac b bb π a bb π b

x o x ac a bb π b

R I R I k r r R I

R I β I r r I k r r I 0 .

V r I β I k r r I

(3-160)

Unfortunately, these equations must be solved simultaneously to arrive at the desired expression for the resistance, Rx = Vx/Ix, of interest. A second glass of the aforementioned pinot noir miti-gates the inclination toward profanity and results in

bb π bb πac ac ss ss bb π

ac acxx o

x bb π bb πss ac ss ac

ac ac

r r r rα β R k k R r r

β 1 β 1VR 1 r ,

I r r r rk 1 R 1 k β 2 k 1 R 1 k β 2

β 1 β 1

(3-161) where (3-156) is used and

acac

ac

βα .

β 1

(3-162)


- 273 -

For large AC beta and the invariably large Early resistance of a bipolar junction transistor, the formidable resistance expression in (3-161) collapses to the simpler relationship,

ac ss

x oss bb π

β RR 1 r ,

k 1 R k r r

(3-163)

which can, for reasonable area factor k, be substantially larger than the Early resistance, ro.

EXAMPLE #3.9:

The SPICE parameters of the silicon technology transistors utilized in the Wilson current mirror of Figure (3.40) are itemized in Table (3.1). Design the circuit so that the current, I1, conducted by transistor Q1 is 4 mA at room temperature. Assuming an emitter-base voltage temperature sensitivity of Sbe = 2 mV/°C, this current is to be sustained to within ±5% up to operating tempera-tures of 75 °C. Use the HSPICE BJT model parameters in Table (3.1) to simu-late the finalized design at 27 °C, 50 °C, and 75 °C. Additionally, simulate the room temperature frequency response of the magnitude of the output impedance presented at the collector of Q1.

SOLUTION #3.9:

(1). Given that conventional silicon transistors are deployed in the subject Wilson mirror, the base-emitter terminal potentials of all active devices are nominally 700 mV. But a slightly more satisfying approach entails deducing these potentials by using the values of saturation current Is, junction injection coefficient nf, and forward knee current Ikf given in Table (3.1). To this end, Ikf = 11.5 mA yields a forward transport current, Icc, in (E3-1) of 1.342 mA for a collector current of 1 mA. Then, with Icc = 1.342 mA, Is = AeJs = 3.2 fA, and nf = 1.05. Additionally, the approximate room temperature value of base-emitter terminal potential, Vbe, derives from (3-5) as Vbe ≈ 727.1 mV. It follows that voltage V1 must satisfy V1 2Vbe = 1.454 V.

(2). In an attempt to conserve standby power, let transistor Q2 conduct one-fourth the current flowing in both transistors Q1 and Q3, which effectively stipulates a requisite junction injec-tion area factor of k = 4.

(3). In (3-154), I1/I1 = 0.05, Tj = (75 °C − 27 °C) = 48 °C, Sbe = 2 mV/°C, and Vbe = 727.1 mV. Then, since

be j1

1 cc be

2S ΔTΔI0.05,

I V 2V

(E9-1)

Vcc Vbe + (2SbeTj /0.05) = 5.294 V. Select Vcc = 6 V to provide at least token design head-room to compensate for parametric uncertainties and analytical approximations.

(4). For a reference current, Ir, of about 1 mA, (3-151) produces R = 4.546 K. Once again, engineering introspection of design-oriented modeling and circuit parameter uncertainties motivates the selection of resistance R as the slightly smaller R = 4.3 K.

(5). Figure (3.42) is the schematic diagram of the completed design, where we have selected vol-tage V1 as 2 V to satisfy the requirement of V1 1.454 V. As usual, estimated static node vol-tages are provided in the diagram.


- 274 -

Figure (3.42). Schematic portrayal of the Wilson circuit designed in

Example #3.9. The voltages shown in the boxes correspond to the estimated respective node voltages for a properly functioning circuit. The indicated 4 mA collector current of transistor Q1 is a design target.


As in previous examples, the simulated results confirm the propriety of the design methodol-ogy. In particular, the simulated quiescent collector current, I1, of transistor Q1 at 27 °C is 4.008 mA, at 50 °C, the simulated Q-point current is 4.075 mA, and at 75 °C, the simulated value of I1 is 4.149 mA. Thus, the largest temperature-induced change in current I1, which unsurprisingly is observed at 75 °C, is only 3.52% larger (well within the target 5% deviation target) than the subject current value at room temperature.

The simulated output impedance magnitude is displayed in Figure (3.43). At the quiescent operating point established by Vcc = 6 volts and V1 = 2 volts, SPICE discloses the operating

Q3

Q2

6 V

Q1

x 4

x 4

x 1

4 mA

2 VZx

4.2 K

727 mV

1.45 V

Q1 Q3 Q2 MODEL NT NT NT

IB 3.5627E-05 3.6239E-05 9.0492E-06IC 4.0080E-03 3.9984E-03 1.0226E-03

VBE 0.7245 0.7250 0.7250 VBC -0.5505 0.0000 -0.7245VCE 1.2750 0.7250 1.4495

BETADC 112.5001 110.3338 113.0081 GM 1.3667E-01 1.3619E-01 3.4835E-02RPI 7.6227E+02 7.4940E+02 3.0011E+03

RX 6.7224E+01 6.7220E+01 2.6888E+02RMU 1.1718E+12 6.0739E+11 1.1946E+12

RO 7.6179E+03 7.4986E+03 3.0027E+04CPI 6.1650E-13 6.1446E-13 1.5701E-13

CMU 3.6996E-15 4.4335E-15 8.8742E-16CBX 0.0000E+00 0.0000E+00 0.0000E+00

CCS 2.0741E-14 2.8694E-14 5.8204E-15BETAAC 1.0418E+02 1.0206E+02 1.0454E+02

FT 3.5071E+10 3.5022E+10 3.5113E+10


- 275 -

point parametric detail itemized above. Several noteworthy observations surface from this itemization and the subject frequency response plot.

Figure (3.43). Simulated frequency response of the magnitude of the output impedance, Zx, for

the Wilson current mirror in Figure (3.42).

(a). The low frequency value of the simulated magnitude of the output impedance is 144.85 KΩ which is almost 19-times larger than the simulated value of the Early resistance (shown above as RO = 7.6179 K) for transistor Q1. Accordingly, our prediction of an output resistance that is substantially larger than the Early resistance is spot on.

(b). Despite the fact that SPICE predicts a unity current gain frequency (FT) of about 35 GHz for all three transistors, the 144.85 KΩ resistance level attenuates by a factor of root two at about 29 MHz.

(c). As presumed in the course of the analysis of the Wilson mirror, the DC beta (BETADC) and the AC beta (BETAAC) are approximately the same for all transistors. Recall that the smallest geometry transistor, which carries a collector current that is 4-times smaller than the other two devices is Q3. Note that the values of rπ (RPI), ro, and rbb (RX) for transis-tor Q3 are nominally 4-times larger than the corresponding parameters for transistors Q1 and Q2. On the other hand, Cπ (CPI) for the higher current transistors is roughly 4-times the Cπ value of Q3, which is as expected owing to the almost direct dependence of emit-ter-base diffusion capacitance on quiescent collector current. In contrast, the base-collec-tor transition capacitances, Cμ (CMU) are relatively independent of current level, as ex-pected, but they do scale with junction area. A similar statement prevails for the substrate capacitances (CCS), which dominantly limit the attainable frequency response of impedance Zx. Recall that substrate capacitances do not factor into the enumeration of the unity gain frequency, fT, of the transistors.

3.5.0. SUPPLY INDEPENDENT BIASING

The last six biasing networks mitigate the deleterious effects of omnipresent junction temperature rises in bipolar junction transistors. Unfortunately, these networks establish quies-

0

40

80

120

160

1 10 100 1000

Mag

nit

ude

Of

Out

put

Impe

dan

ce, Z

, (K

)x

Signal Frequency (MHz)


- 276 -

cent current responses that functionally depend on the supply voltage. A bias current depen-dence on applied power line voltage is hardly surprising. But in the portable electronic age in which we live, such dependence comprises a serious problem. For example, degrading supply voltages incurred by aging batteries is unavoidable. When these voltages decrease to very low levels, quiescent collector currents certainly diminish. In the wake of these line voltage de-creases, there is even the likelihood of disabling the forward active regime operation of certain transistors. A more insidious problem that prevails in both portable and plug-in electronics is the fluctuation in line voltage incurred by the interaction of nonzero Thévenin supply impedances with large transient fluctuations in the currents delivered by these supplies. These fluctuations can influence transient responses and distortion characteristics and in extreme cases, they can even cause network instability. In high performance applications where these power line voltage fluctuations are only minimally intolerable, biasing networks that deliver reduced sensitivity to supply line variations are essential. Networks that function with maximal independence of the power line voltage are said to deliver a high power supply rejection (PSR).

3.5.1. BASE-EMITTER VOLTAGE OFFSET BIASING

One practical example of a network capable of delivering biasing currents that are nominally independent of supply line voltages is the voltage offset configuration appearing in Figure (3.44). The NPN transistors, Q1 and Q2, are identical, save for the fact that the emitter-base junction injection area of Q2 is kn-times larger than that of Q1. If a quiescent current, IQ, is presumed to flow in the emitter of transistor Q2, nominally the same current is conducted by the emitter of the PNP diode-connected transistor, Q3. This statement reflects three assumptions. First, it assumes that all transistors have large DC beta, which allows tacit neglect of all transistor base currents. Second, all transistors have large forward knee currents, and third, they boast large Early voltages. Since transistors Q3 and Q4 have identical junction injection areas and util-ize identical emitter degeneration resistances, Ree, current IQ in Q3 is mirrored in the emitter of transistor Q4 and hence, in the emitter of transistor Q1. From the Ebers-Moll model, it follows that

be1 f T be2 f TV n V V n VQ s n sI I 1 k I 1 .e e

(3-164)

If we neglect the unity terms within the bracketed quantities, this relationship produces be1 be2 f T nV V n V k .ln (3-165)

By using the Q3-Q4-Ree mirror to force equality between the emitter currents of transistors Q1 and Q2, the difference in emitter-base junction injection areas of Q1 and Q2 fosters an offset be-tween the corresponding base-emitter terminal voltages, Vbe1 and Vbe2. This nonzero offset is crucial in that it is the vehicle by which a nominal independence of current IQ on the supply line voltage, Vcc, is established Specifically,

be1 be2 QV V RI , (3-166)

whence, by (3-165), f T nbe1 be2

Qn V kV V

I ,R R

ln (3-167)

which is independent of voltage Vcc.

Before celebrating the supply-independence advanced by (3-167), at least five impor-tant engineering caveats warrant careful engineering scrutiny. First, (3-165) and the current mirroring action between transistors Q3 and Q4 require that transistors Q4 and Q2 function in


- 277 -

their forward active regimes. On the other hand, transistors Q1 and Q3 automatically operate in their linear domains because the diode connection of these transistors forces their base-collector terminal voltages to zero. Such operation for transistor Q4 requires Vec4 ≥ Veb4, where Vec4 and Veb4 respectively denote the emitter to collector and the emitter to base voltages developed on Q4. In turn, Vec4 ≥ Veb4 demands a supply voltage that is large enough to satisfy,

Figure (3.44). Schematic diagram of a biasing network delivering quies-

cent currents IQ and Io that are, to first order, independent of the applied supply voltage, Vcc.

cc ee Q eb4 be1V R I V V . (3-168)

Assuming both Veb4 and Vbe1 are of the order of 700 mV, we see that Vcc in excess of approx-imately (1.4+ReeIQ) volts is commanded if the desired linear operation of the circuit is to be sus-tained. For transistor Q2, linear operation mandates

ce2 cc eb3 ee Q be2V V V R R I V , (3-169)

which in turn commands cc ee Q be2 eb3 f T nV R I V V n V kln (3-170)

You are encouraged to verify that the satisfaction of (3-170) actually guarantees the satisfaction of (3-168). As might we might have expected intuitively, the bias circuit produces quiescent cur-rents that are not precisely independent of supply voltage Vcc. Problems are manifested when, as per (3-170), voltage Vcc drops too low.

The second important point relevant to (3-167) is that while the indicated current is ostensibly independent of Vcc, subject to the constraint imposed by (3-170), it varies with temperature. In fact and to the extent that resistance R boasts a small temperature coefficient, IQ in (3-167) is PTAT in that Boltzmann voltage VT is directly proportional to absolute junction temperature. But the subject temperature dependence is not entirely bad news in that the forward transconductance of transistor Q2 (and also Q1, Q3, and Q4) is rendered relatively insensitive to temperature. In particular, (3-54) confirms that the forward transconductance is inversely depen-dent on the effective Boltzmann voltage, nfVT. To wit, if the effects of knee current and Early

Q2Q1

IQ IoIQ

Vcc

x knx 1 Vo

Rx

R Rl

Q4

Q3

Q5

Ree Ree R /kee p

x 1 x 1 x kp


- 278 -

voltage continue to be ignored, (3-54) gives rise to

Q nm2 m1 m3 m4

f T

I kg g g g .

n V R

ln (3-171)

This disclosure is notable for two reasons. First, if the circuit at hand is operated as an amplifier, wherein the gain and particularly the open loop gain in a feedback configuration, is dependent on forward transconductance, the overall I/O gain can be rendered temperature independent. Second, the forward transconductances of transistors Q1 through Q4 are rendered independent of relatively unpredictable transistor modeling parameters.

The third noteworthy point is that the current conducted by transistor Q5, whose emit-ter-base junction injection area is kp-times that of transistors Q3 and Q4, is, like current IQ, nomi-nally invariant with supply voltage. This contention follows from the fact that the emitter degeneration resistance of transistor Q5 is a factor of kp smaller than that of Q3, which implies

p f T no p Q

k n V kI k I ,

R

ln (3-172)

since

eeee Q eb o eb

p

RR I V I V .

k

(3-173)

If transistor Q5 operates in its linear regime where Vec5 ≥ Veb5, its transconductance is p Q p no

m5f T f T

k I kIg ,

n V n V R

k ln (3-174)

which, like the transconductances of the other transistors in the subject network, is essentially independent of junction operating temperature. In practice, the area ratio, kp, should be kept un-der two or three in that large kp sustains proportionately larger collector current in Q5. In turn, large current levels in Q5 diminish its Early resistance, which reduces the attainable output resis-tance, Rx, of the current source.

The fourth noteworthy point is that resistance Ree can be set to zero without affecting the current solution in (3-167). In fact, it is desirable to set Ree to zero in some low voltage applications, since zero emitter degeneration in the PNP devices in Figure (3.44) lowers the minimum required value of the supply voltage, Vcc. It is included herewith to increase the output resistance, Rx, so that the Q5-Ree/kp subcircuit emulates a current source whose output current is rendered progressively more independent of supply voltage.

The final, and arguably most important, point to be offered is that while (3-167) defines the desired current solution for the biasing network in Figure (3.44), it is unfortunately not the only solution. In particular, Vbe1 = Vbe2 = 0 in (3-166) sets IQ = 0 as a plausible current solution. In other words, it is possible that at power supply turn on, transistors Q1 and Q2, and thus all other transistors in the network, lock to a nonconductive state. Slight parametric differences among the current mirroring devices are likely to preclude this annoying null state, but given the luck of the traditional circuit design engineer, gambling that the desired solution projected by (3-167) is realized is imprudent. Accordingly, a startup circuit −preferably a subcircuit that con-sumes no, or at least negligible, steady state power− is a worthwhile investment in design time and chip area.

To the foregoing end, a relatively simple startup addendum to the network of Figure (3.44) is submitted in Figure (3.45). The startup cell comprised of capacitance C and transistors


- 279 -

Figure (3.45). The supply-independent biasing network of Figure (3.44) with a startup cell incorpo-

rated to preclude a null current solution at network startup.

Q6 and Q7 conduct current only at circuit startup. Startup in the present sense corresponds to closing switch SW. If switch closure occurs at time t = 0, the indicated line voltage, Vp(t), approximates an ideal voltage step; that is, Vp(t) = Vccu(t). Assuming capacitance C is initially uncharged, the idealized instantaneous jump in the power line voltage, Vp(t), is transmitted in-stantly to the base-emitter terminals of transistor Q7. With the emitter-base junction of Q7 strongly forward biased, a potentially large collector current is allowed to flow through Q7. Clearly, this current can derive only from transistor Q3. The current conducted by Q3 is mir-rored to transistor Q4. In response to this mirroring action, the current forced through transistor Q1 by Q4 is accompanied by an increase in base-emitter terminal voltage Vbe1 from its zero value that prevails prior to switch closure. Note, however, that voltage Vbe2 remains nominally zero as Vbe1 commences its increase. We state this with confidence because the large forward bias im-posed across the emitter-base junction of Q7 immediately after switch closure forces the current conducted by Q3 to flow through Q7. In effect, Q7 bypasses the Q2-R subcircuit immediately after time t = 0. But as voltage Vbe1 ultimately increases, transistor Q6 starts to conduct. Its collector current can be supplied only by the capacitive branch of the startup cell. This branch continues to supply current until capacitor C is fully charged, which occurs when the indicated capacitor voltage, Vcap, is Vcc. As Vcap approaches Vcc to within an emitter-base junction thre-shold voltage, the base-emitter voltage of transistor Q7 drops below threshold potential, whereu-pon transistor Q7 enters cutoff. With C almost fully charged, Q6, like Q7, is starved of current, and the startup cell is effectively disconnected from the rest of the circuit. As such, the biasing network eventually achieves steady state in that the current induced to flow in Q3 necessarily flows through Q2, as presumed in the analysis leading to (3-166). We should note that the re-

Q2

Q7

Q6

IQ Io

x kn

x kc

x kc

Vo

Rx

R Rl

Q4

Q3

Q5

Ree Ree R /kee p

x 1 x 1 x kp

Q1

IQ

x 1

CVcap

+

Sta

rtu

p C

ell

t = 0

Vcc

SW

V (t)p


- 280 -

sponse time of the startup cell is effectively defined by the time required for capacitance C to charge to within an emitter-base junction threshold potential of Vcc.

Figure (3.45). The supply-independent biasing network of Figure (3.44) with a startup cell incorpo-

rated to preclude a null current solution at network startup.

EXAMPLE #3.10:

Design the supply-independent biasing network of Figure (3.45) so that at room temperature operating conditions, current IQ is nominally 1 mA and current Io is nominally 2 mA for supply voltages, Vcc, in the range of 1.8 volts to 6 volts. Ve-rify the design through SPICE simulation. Specifically, simulate the static describing functions from Vcc to both IQ and Io at operating temperatures of 27 °C, 50 °C, and 75 °C. Additionally, simulate the time domain responses of cur-rents IQ and Io to a 6 volt battery switched into the circuit at time t = 0 with a 500 nSEC rise time. The HSPICE parameters for the NPN devices appear in Table (3.1), while Table (3.2) lists the parameters for PNP transistors that are nomi-nally complementary to the NPN units.

Q2

Q7

Q6

IQ Io

x kn

x kc

x kc

Vo

Rx

R Rl

Q4

Q3

Q5

Ree Ree R /kee p

x 1 x 1 x kp

Q1

IQ

x 1

CVcap

+

Sta

rtu

p C

ell

t = 0

Vcc

SW

V (t)p


- 281 -

SPICE

SYMBOL

TEXT

SYMBOL

DESCRIPTION

OF PARAMETER

VALUE UNITS

FBF f Forward Short Circuit Gain 100 amps/amp

BR r Reverse Short Circuit Gain 1.3 amps/amp

CJC Cjco Zero Bias B-C Depletion Capacitance 2.4 fF

CJE Cjeo Zero Bias B-E Depletion Capacitance 4.7 fF

CJS Cso Zero Bias Substrate Depletion Capacitance 12.2 fF

IKF Ikf Forward Knee Current 9.4 mA

IRB Irb Base Resistance Corner Current 3.3 mA

IS Is Saturation Current 4.3 fA

MJC mc B-C Junction Grading Coefficient 0.333 –

MJE mje B-E Junction Grading Coefficient 0.5 –

MJS ms Substrate Junction Grading Coefficient 0.5 –

NF nf B-E Junction Injection Coefficient 1.02 –

NR nr B-C Junction Injection Coefficient 1.0 –

RB rbb Zero Bias Base Resistance 310 RBM Rbm Minimum Base Resistance 43 RC rc Series Collector Resistance 22 RE re Series Emitter Resistance 1.7 TF fo Zero Bias Minority Carrier Transit Time 6.2 pSEC

TNOM Tj Junction Reference Temperature 27 C

VAF Vaf Forward Early Voltage 24 volts

VJC Vjc B-C Junction Built-In Potential 780 mvolts

VJE Vje B-E Junction Built-In Potential 920 mvolts

VJS Vjs Substrate-Collector Built-In Potential 690 mvolts

XTI Temperature Exponent For IS 3 −

XTF Temperature Exponent For TF 0.025 −

XTB Temperature Exponent For BF 0.03 − Table (3.2). HSPICE model parameters for a PNP bipolar junction transistor. Although the transistor characte-

rized herewith is fictitious, the parameters are typical of a moderately high speed BJT.

SOLUTION #3.10:

(1). Current IQ is nonzero if and only if transistors Q1 and Q2 possess different emitter-base junc-tion injection areas. Arbitrarily choose kn = 10, meaning that the emitter-base junction area of transistor Q2 is ten-fold that of Q1. There is little point in making kn much larger than ten or so since IQ in (3-166) is seen as dependent, not on kn, but on the natural logarithm of kn. From Table (3.1) the junction injection coefficient, nf, of all NPN devices is nf = 1.05. Thus, with a junction temperature of Tj = 27 °C = 300.16 °K, nf = 1.05, kn =10, and IQ = 1 mA, resistance R in the network of Figure (3.45) derives from (3-167) as


- 282 -

f T n

Q

n V kR 62.6 Ω .

I

ln (E10-1)

In view of the empirical nature of parameter nf, the unavoidable uncertainties associated with the internal junction temperature, and the relatively small size of the requisite circuit resis-tance, we should allow for laser trimming resistance R to the precise value that yields the tar-get IQ = 1 mA current.

(2). The next step in the design process entails determining the appropriate emitter degeneration resistance, Ree, which is commensurate with satisfactory circuit operation at the worst case power line voltage of Vcc =1.8 volts. Equation (3-169) is the applicable relationship, but prior to its use, the emitter-base voltage, Veb3, for transistor Q3 and the base-emitter voltage, Vbe2, for transistor Q2 must be estimated. To this end, precise calculations are not required and therefore, knee currents and Early voltages are ignored. These simplifications enable the use of the simple Ebers-Moll relationship for the forward transport current in (3-5) for both NPN and PNP transistors. In particular,

be f T be f Ts

V n V V n Vc cc sI I I 1 I ,e e (E10-2)

which applies to the NPN devices with minimal junction injection areas. In the case of PNP transistors, the only required change entails the replacement of base-emitter terminal voltage Vbe by emitter-base voltage Veb. For transistor Q2, Table (3.1) gives Is = 3.2 fA and, of course, nf = 1.05. Since Q2 has a ten-fold increase in emitter-base junction area, Is in (E10-2) must be multiplied by 10. Then with Ic ≈ IQ = 1 mA, Is = (10)(3.2 fA), nf = 1.05, and Tj = 300.16 °K, Vbe2 = 656.5 mV. On the other hand, the PNP transistor, Q3, which has minimal junction area, offers from Table (3.2), Is = 4.3 fA and nf = 1.02. Accordingly, Ic = IQ = 1 mA in (E10-2) produces Veb3 = 690.8 mV. Recalling (3-169), Vcc ≥ 1.8 volts leads to a resistance Ree, that satisfies

be2 eb3 f T nee

Q

1.8 V V n V kR 390.1 Ω .

I

ln (E10-3)

Design conservatism is almost always judicious and thus, we select Ree = 300 Ω in an attempt to win the praise of our boss.

(3). If current Io is to be 2 mA, which is twice the value of current IQ, transistor Q5 in Figure (3.45) should boast twice the emitter-base junction injection area of transistor Q3. Moreover, the desired current mirroring between transistors Q3 and Q5 requires that the emitter degeneration resistance for Q5 be one-half that of transistor Q3. Note in Figure (3.45) that the emitter degeneration resistance of Q5 is delineated as Ree/kp, where kp, the junction area factor of Q5, is kp = 2.

(4). When the supply line battery switch is closed at time t = 0, capacitor C begins to charge, such that the indicated capacitor voltage, Vcap, ultimately rises to 6 volts. To crude first order, the rate of capacitor voltage charging matches the slew rate of the supply line, which is 6 volts/500 nSEC = 12 volts/μSEC. The current conducted by capacitance C in the circuit of Figure (3.45) closely approximates the collector current, say Ic6(t) flowing in transistor Q6. Accordingly,

c cc6

dV (t) ΔVI (t) C C C 12 volts/μSEC .

dt Δt (E10-4)

Most transistors in the subject network conduct steady state currents in the range of 1 mA. In order to forestall excessive junction heating in the startup cell devices, it is prudent to limit the maximum current in transistor Q6 to approximately 1 mA, especially if the indicated area factor, kc, is set to one. With Ic6(t) =1 mA, (E10-4) delivers C = 83.3 pF. Set C = 85 pF, which requires that this capacitance be realized as an off chip realization element.


- 283 -

In addition to concerns about junction heating, care must be exercised to preclude voltage overstress in transistors Q6 and Q7. Specifically, note that if switch SW in Figure (3.45) were ideal, the entire 6 volts of supply line energy is developed across the base-emitter terminals of transistor Q7 immediately after switch closure. Depending on the process actually adopted for the monolithic realization of the network we are addressing, high voltage options may need to be exploited for transistors Q6 and Q7.

(5). The variable awaiting computation is the resistance, Rl, in Figure (3.45). The current, Io, flowing through resistance Rl is 2IQ, and this same current approximates the emitter current of transistor Q5. Thus, the emitter-collector voltage, Vec5, supported by transistor Q5 is

ec5 cc ee l QV V R 2R I . (E10-5)

In order for Q5 to sustain operation in its forward active domain, Vec5 must be at least as large as Veb5 even when Vcc lies at its minimum, 1.8-volt level. The Q5 emitter-base voltage, Veb5, effectively matches Veb3, which has been calculated to be 690.8 mV. It follows that

cc ee Q eb5l

Q

V R I VR 404.6 Ω .

2I

(E10-6)

Therefore, we choose Rl = 400 Ω.

Figure (3.46). The supply-independent biasing network, complete with startup

compensation, designed in Example #3.10. All resistances are in units of ohms, the capacitor is in picofarads, and the voltage supply is in units of volts. The indicated node voltage estimates apply in the steady state subsequent to closure of switch SW.

(6). A schematic diagram of the completed design is shown in Figure (3.46). A first simulation of the network reveals a simulated current, IQ, which is about 4.8% larger than its target factor. Accordingly, resistance R in Figure (3.45) is increased from its originally computed 62.6 Ω to (1.048)(62.6 Ω) = 65.6 Ω. Subsequent to running a few static simulations to confirm the pro-

Q2

Q7

Q6

IQ Io

x 10

x 1

x 1

Vo

65 400

Q4Q3

Q5

300 300 150

x 1 x 1 x 2

Q1

IQ

x 1

85

t = 0

6

SW

719 mV

65.0 mV

0 V

5.70 V

5.01 V

5.01 V

5.70 V 5.70 V

800 mV

6 V


- 284 -

priety of relevant design modifications, we resultantly converge to R = 65 Ω.

Several SPICE simulations were executed to confirm the propriety of the design submitted as the schematic diagram in Figure (3.46)

(a). Figure (3.47) displays room temperature, simulated static sweeps of currents IQ and Io versus the supply line voltage, Vcc. At Vcc = 6 volts, IQ = 1.01 mA, which is a scant 1% larger than the target design value. Even if Vcc drops from its steady state 6-volt value by 75% to 1.5 volts, IQ is maintained at 924.9 A, which represents a degradation of only 8.04%. On the other hand, the output current, Io, is 1.97 mA at Vcc = 6 volts and 1.77 mA at Vcc = 1.5 volts, which computes as a 10.12% decrease with respect to the current value at Vcc = 6 volts. The diminished rejection of the power supply voltage at higher quiescent currents can be attributed to the fact that the Early resistances, and particularly the Early resistances in the PNP devices are inversely proportional to bias currents.

Figure (3.47). Simulated static describing functions for the room temperature currents, IQ

and Io, in the circuit of Figure (3.46).

The observed nonzero slopes in the current curves can also be attributed to Early vol-tages that are always finite. Said slope is more pronounced in the output current characteristic because the Early voltage of the PNP transistor, Q5, is smaller than those of any of the NPN devices. Below nominally 1.5 volts, transistors that are not con-nected as diode elements operate in saturation to produce current characteristics that are strongly sensitive to supply line voltage variations.

(b). Figure (3.48) offers the foregoing static sweeps at 50 °C and 75 C, as well as at 27 °C. Temperature sensitivity is apparent, which is as expected because of the current solu-tions in (3-167) and (3-172). In particular, if the junction injection coefficient, nf, and circuit resistance, R, are temperature invariant, (3-167) and (3-7) deliver

Q f n

j

ΔI n k k3.21 μA / C .

ΔT qR

ln (E10-7)

Equation (3-172) demonstrates that the temperature sensitivity of the output current, Io, is larger than the foregoing sensitivity by a factor of kp. Thus,

Cu

rren

t (m

A)

Power Supply Voltage, (volts)Vcc

Io

IQ

0

0.5

1.0

1.5

2.0

2.5

0 2 4 6 8 10


- 285 -

Figure (3.48). Simulated static describing functions at 27 °C, 50 °C, and 75 °C for the cur-

rents, IQ and Io, in the circuit of Figure (3.46).

Q p f nop

j j

ΔI k n k kΔIk 6.42 μA / C .

ΔT ΔT qR

ln (E10-8)

The increase in the temperature sensitivity of current Io by a factor of kp over the sensitivity of current IQ rebukes the use of high junction injection area factors in the PNP units deployed in the circuit at hand. An examination of the data from which Fig-ure (3.48) derive indicates that IQ = 1.006 mA at T = 27 °C, while at 50 °C and 75 °C, the subject current is 1.086 mA and 1.173 mA, respectively. Comparing the 75 °C simulated result to its 27 °C counterpart,

-3Q

j

1.173 1.006 10ΔI3.48 μA / C ,

ΔT 75 27

(E10-9)

which is 8.4% higher than the computed sensitivity in (E10-7). This error can be attri-buted to the temperature dependence of other transistor parameters (such as the Early voltage). These second order temperature sensitivities are tacitly ignored in (3-167). For output current Io, Io = 1.969 mA, 2.125 mA, and 2.295 mA at 27 °C, 50 °C, and 75 °C, respectively. It follows that

-3o

j

2.295 1.969 10ΔI6.79 μA / C ,

ΔT 75 27

(E10-10)

which is only 5.8% larger than the calculated temperature sensitivity in (E10-8).

(c). Finally, Figure (3.49) offers the transient responses of currents IQ and Io to sudden switch closure at time t = 0, subject to the condition that the switch in question induces a supply line voltage rise time of 500 nSEC. Superimposed on this plot are the currents conducted by the startup transistors, Q6 and Q7. The latter curves confirm that the startup devices are effectively disconnected from the biasing network, well within 1 μSEC of switch closure. The currents, IQ and Io, are seen to settle to their respective steady state values at 584.75 nSEC. Since the supply line does not reach 6 volts until 500 nSEC, the circuit can be said to settle within 84.75 nSEC after the time at which the supply line is fully activated. Observe a significant amount of peaking in the cur-

0

0.5

1.0

1.5

2.0

2.5

0 2 4 6 8 10

Power Supply Voltage, (volts)Vcc

Io

IQ

T = 27 °CjT = 50 °CjT = 75 °Cj

Cu

rre

nt

(mA

)


- 286 -

rent outputs, IQ and Io, while the currents conducted by the startup devices always re-main below IQ and Io.

Figure (3.49). Transient current responses to switch closure in the circuit of Figure (3.46).

The current, Ic6, is the collector current conducted by transistor Q6, while Ic7 denotes the collector current of transistor Q7.


As suggested earlier, the circuit addressed in this example is one of several whose operation is premised on formulating a subcircuit that establishes an offset between base-emitter ter-minal voltages of key transistors. All are capable of delivering static current responses that, while not strictly independent of power supply voltage, are significantly desensitized with re-spect to supply line voltage variations. Most of these networks are able to limit current varia-tions about nominal design targets to 5%-10%, despite upwards of 50% degradation in line voltage. The prices paid for these supply-independent topologies are potentially significant temperature sensitivities, a recurring need for resistor trimming, and the inevitable require-ment of startup cells that preclude null current states. Three additional biasing circuits are re-served for your own edification in Problems #3.28 through #3.30.

3.5.2. BANDGAP REFERENCE CIRCUIT

Among the best of the supply-independent biasing schemes is the bandgap reference circuit[11]. Aside from offering excellent output voltage desensitization to power line voltage variations, the bandgap reference also delivers an outstandingly low temperature coefficient for its reference output voltage over wide temperature ranges. This temperature insensitivity is a critically important performance attribute in high performance analog integrated circuits, and especially in circuits earmarked for high-speed data acquisition, data conversion, and informa-tion processing. Circuit performance vulnerability to temperature looms especially severe in deep submicron technologies for which even modest current levels generate the high current densities that can result in intrinsic temperature increases of as much as 50 °C or more. In the subsections that follow, we shall see that the bandgap reference circuit produces a nominally temperature invariant static output voltage by coalescing the electrical properties of two circuit

0

2

4

6

0

1

2

3

0 0.2 0.4 0.6 0.8 1.0 1.2

Cu

rren

t (m

A)

Lin

e V

olt

ag

e,

(vo

lts)

V(t

)p

Time (microseconds)

Io

IQ

Ic7 Ic6


- 287 -

cells that we have already encountered; namely, the emitter-base junction voltage of a diode con-nected transistor and a PTAT voltage generator.

Conceptually, the bandgap reference cell is the system abstraction pictured in Figure (3.50)[12]. An emitter-base junction forward bias is extracted as the base-emitter voltage, Vbe, which is developed in response to a constant current, Ik, applied as shown, to a diode connected BJT. The PTAT generator is formed as a conventional Boltzmann voltage that is scaled by a constant amplifier gain of K. In turn, the output reference voltage, Vref, derives as the superposi-tion of voltage Vbe and the amplified Boltzmann voltage, KVT; that is,

Figure (3.50). System level abstraction of a bandgap reference circuit.

ref be TV V KV . (3-175)

To the extent that current source Ik emulates an ideal (infinite impedance) current source, voltage Vbe is independent of the biasing voltage, Vcc. And if the amplifier shown in the diagram boasts high power supply rejection, gain K is nominally independent of the amplifier biasing voltage, Vaa. It follows that output voltage Vref is all but independent of applied biasing.

Equation (3-101) teaches that to first order, junction voltage Vbe decreases linearly with increasing temperature. Obviously, the Boltzmann voltage, VT, increases linearly with tempera-ture. It is therefore intuitively evident that in addition to achieving a reference response boasting supply voltage independence, constant K, which we presume to be temperature invariant, can be selected to achieve a reference voltage having zero temperature coefficient. In particular,

ref be Tobe

o

dV dV VkK S K ,

dT dT q T

(3-176)

where VTo is the Boltzmann voltage evaluated at a reference temperature of To. Generally, the reference temperature is taken as 27 °C, or 300.16 °K. We see that the temperature coefficient, dVref /dT, of reference output Vref is null if

be o

To

S TK ,

V (3-176)

which produces a corresponding, and somewhat idealized, reference output of

BoltzmannVoltage

GeneratorK

Ik

VT

KVT

Vbe Vref

V + KVbe T

Vcc

Vaa


- 288 -

Tref be T be be o be be

To

VV V KV V S T V S T .

V

(3-177)

This basic result confirms that voltage Vref indeed boasts zero temperature coefficient if junction voltage Vbe decreases linearly with junction temperature at a constant rate of Sbe. Note that if Sbe is indeed constant, the amplifier gain, K, in (3-176) is necessarily temperature invariant.

3.5.2.1. Temperature Coefficient of Forward Biased Junction Voltage

At this point, we have taken the temperature sensitivities of a forward biased PN junc-tion diode and the analogous forward biased emitter-base junction of a BJT to be the temperature invariant constant, Sbe. We even suggested that in the absence of definitive other information, Sbe ≈ −2 mV/°C is an excellent approximation for the pre-CAD, mathematical analysis of a circuit or system. For the vast majority of BJT circuits, these first order presumptions are acceptable and even appropriate. But in bandgap reference cells, which can deliver temperature sensitivities as small as a few tens to a few hundreds of parts per million/°C (ppm/°C), representing Sbe as a mere constant is not sufficiently accurate even for first order investigations. We shall learn that the forward biased, emitter-base junction voltage of a BJT does not decrease linearly with temperature. In fact, it does decrease with increasing temperature, but we shall find that the functional dependence, Vbe(T), on absolute junction temperature T embraces both linear and natural logarithmic terms. It follows that Sbe, which we shall now more astutely designate as the temperature function, Sbe(T), is at least weakly dependent absolute operating temperature.

The archival literature testifies that the functional dependence of the emitter-base vol-tage on junction temperature is expressible as[13],

c obe go beo f T

o o co

J TT TV (T) V 1 V n V m .

T T J Tln ln

(3-178)

In this expression To is the previously introduced junction reference temperature, Vgo is the refer-ence temperature value of the bandgap potential (1.206 volts in silicon operated at To = 300.16 °K), and Vbeo is the reference temperature value of the emitter-base junction voltage; that is, Vbeo ≡ Vbe(To). Parameter m is an empirical constant that for silicon semiconductor lies in the range, 2.0 ≤ m ≤ 2.8. Unless explicitly stated otherwise, m is typically assigned a value of m = 2.3. Parameter Jc symbolizes the density of collector current (collector current Ic divided by the emit-ter-base junction cross section area, Ae) at an absolute junction temperature of T. Finally, Jco is the T = To value of collector current density Jc.

The temperature dependence of the current density ratio, Jc /Jco, is usually fixed by the topology of the subcircuit in which the transistor undergoing scrutiny is embedded. In most of the commonly utilized bandgap reference cells, this ratio is made proportional to absolute temperature in accordance with the simple, linear relationship,

c

co o

J T,

J T (3-179)

assuming that any resistors utilized in the reference cell have negligibly small temperature coefficients and assuming further that no significant temperature gradients prevail across the bandgap reference chip. Accordingly, (3-178) becomes

be go beo f To o o

T T TV (T) V 1 V n m 1 V .

T T Tln

(3-180)


- 289 -

Consequently, the temperature sensitivity, Sbe(T), is

go beo fbebe

o o

V V n k m 1dV (T) TS (T) 1 .

dT T q Tln

(3-181)

Since Vgo > Vbeo and m > 1, both terms on the right hand side of this relationship are negative, thereby confirming a negative temperature coefficient for the emitter-base junction potential. Figure (3.51) displays a plot of Sbe(T) versus temperature T for the case of Vbeo =730 mV, nf = 1.0, a reference temperature of To = 27 °C = 300.16 °K and three values of empirical parameter m. The logarithmic temperature term is invariably inconsequential for practical operating temperatures. Accordingly, and as is subliminally inferred by the curves in Figure (3.51), the temperature sensitivity function, Sbe(T), is almost constant. For m = 2.4, we see that Sbe(T) varies from −1.695 mV/°C at T = 0 °C to −1.733 mV/°C at T = 100 °C, which reflects a change of only about 2.2% over this 100 °C interval. Note further that the slopes of these sensitivity plots change modestly as a function of parameter m.

Figure (3.51). The temperature sensitivity of the forward biased emitter-base junction

voltage of a BJT, depicted as a function of junction temperature. Note that the sensitivity function, Sbe(T), is plotted in units of mV/°C.

The fundamental emitter-base potential relationships of (3-5) and (3-11) are interesting from the standpoint of their implications for two identical transistors (save for different emitter-base junction areas) operated at different collector current densities. Denote these two collector current densities as Jc2 and Jc1, which respectively correspond to base-emitter voltages of Vbe2(T) and Vbe1(T). If the two transistors operate at the same junction temperatures, a simple algebraic manipulation of the basic Ebers-Moll equations confirms that

c2 c2 e1be2 be1 f T f T

c1 c1 e2

J I AV (T) V (T) n V n V .

J I Aln ln

(3-182)

If the circuit in which the two transistors are embedded is designed to ensure that the two collec-tor currents, Ic1 and Ic2, are identical, we have

-1.80

-1.75

-1.70

-1.65

-1.60-25 0 25 50 75 100 125

Te

mp

era

ture

Co

eff

icie

nt,

Sb

e(T

), (m

V/d

eg

C)

Junction Temperature (deg C)


- 290 -

fe1 e1be2 be1 f T

e2 e2

n kTA AV (T) V (T) n V ,

A q Aln ln

(3-183)

which is directly proportional to absolute temperature. Equation (3-183) serves as a foundational platform for constructing a PTAT generator. A slight shortfall of this contention is that identical transistors carrying non-identical collector current densities are likely to be operating at slightly different junction temperatures. Thus, care must be exercised to preclude widely divergent cur-rent densities or equivalently, significant temperature gradients between the two transistors.

3.5.2.2. Circuit Realization of the Bandgap Reference Cell

The topological foundation of most of the currently used bandgap reference cells is the Brokaw circuit shown in Figure (3.52)[11]. The circuit at hand utilizes two monolithic, and there-fore physically similar, BJTs, Q1 and Q2, whose emitter-base junction areas are Ae1 and Ae2, respectively. If the operational amplifier (op-amp) in the schematic diagram3 is characterized by a low frequency open loop voltage gain of Ao, the indicated differential input voltage, Vi, of the op-amp is

Figure (3.52). The basic schematic diagram of a bandgap reference circuit that

uses two bipolar junction transistors and a low bandwidth opera-tional amplifier. The indicated currents flowing through resis-tances R1 and R2 and the emitter of transistor Q2 ignore the base currents conducted by Q1 and Q2.

3 The op-amp need not be realized in bipolar junction transistor amplifier. In fact, since high response speed in the op-amp is not an issue, but static power dissipation is an important design consideration, the op-amp is commonly realized in metal-oxide-semiconductor field-effect transistor (MOSFET) technology.

Q2

R

Q1

R

R1

R2

I2I1

I1

Op-Amp

I +I1 2

Vcc

Vbe1 Vbe2

Vref

Vi

[Open Loop

Gain = A]

o

I2


- 291 -

refi

o

VV .

A (3-184)

From the schematic diagram, we then see that

refi 1 2

o

VV R I I .

A (3-185)

The last equation shows that for a finite reference output voltage, Vref, Vi ≈ 0 if gain Ao is very large. Thus, a sufficiently large open loop gain in the utilized op-amp manifests identical cur-rents, I1 and I2. This large open loop gain is but one of three preeminent requirements we shall invoke on the bandgap reference cell. The second directive is very large input impedances at both of the op-amp input ports. Large input impedances ensure that the op-amp draws negligible input current, which means that current I1 approximates the collector current flowing in transistor Q1. Similarly, current I2 is essentially the collector current conducted by transistor Q2. The fi-nal mandate is that transistors Q1 and Q2 be characterized by large static current gains, hFE. This stipulation means that currents I1 and I2 respectively approximate the Q1 and Q2 emitter cur-rents, as we depict in Figure (3.52). In light of the foregoing approximations, the reference out-put voltage, Vref, is given by

ref be2 1 2 1 be2 1 1V V I I R V 2I R , (3-186)

while

be2 be11

2

V VI ,

R

(3-187)

where it is understood that the base-emitter voltages, Vbe1 and Vbe2, are functions of junction absolute temperature T. Recalling (3-183), (3-186) becomes

e11 1ref be2 be2 be1 be2 f T

2 2 e2

A2R 2RV V V V V n V ,

R R Aln

(3-188)

This result mirrors the generalized reference output response delineated in our system level sche-matic of Figure (3.50). In particular, the first term on the far right hand side of (3-188) is a base-emitter voltage that decreases with temperature at a near constant rate. On the other hand, the second term on the right hand side of (3-188) is proportional to Boltzmann voltage VT. To the extent that the resistance ratio, (R1/R2), projects negligibly small temperature coefficient, which it does if both resistances have roughly the same temperature coefficient, this second term is PTAT. In a word, the first term on the right hand side of (3-188) decreases with temperature, while its superimposed second term companion increases with temperature. The irrefutable conclusion is that the resistance ratio (R1/R2) can be selected to incur a zero temperature coeffi-cient associated with the reference output voltage. Actually, a bit of thought serves to convince that (R1/R2) can be selected to deliver a reference output voltage that has positive, zero, or nega-tive temperature coefficient. As a relevant and important sidebar, we note that voltage Vref in (3-188) is ostensibly independent of the supply voltage, Vcc. It is indeed, as long as Vcc is large enough to ensure the linear operation of the op-amp, which is required to sustain equality be-tween the two currents, I1 and I2.

Using (3-188), the temperature sensitivity, Sref(T), of the reference voltage is


- 292 -

ref f Tobe2 e11ref

2 o e2

dV n VdV A2RS (T) ,

dT dT R T Aln

(3-189)

where we recall VTo as the T = To value of Boltzmann voltage VT. Using (3-181), the last result becomes

ref go beo2 f Too o

f To e11

2 o e2

1 TS (T) V V n m 1 V 1

T T

n V A2R.

R T A

ln

ln

(3-190)

This temperature coefficient is not constant because the temperature coefficient of the base-emit-ter terminal voltage of a BJT is slightly temperature variant, as is portrayed by Figure (3.51). At the reference temperature To, (3-190) becomes

f To e11ref o go beo2 f To

o 2 o e2

n V A2R1S (T ) V V n m 1 V .

T R T Aln

(3-191)

A straightforward algebraic consideration of this expression leads to the conclusion that the reference temperature value, Sref(To), of the temperature coefficient of the reference output vol-tage is zero if resistance ratio (R1/R2) is chosen in accordance with

go beo2f

To1o

2 e1f

e2

V Vn m 1

VRρ .

R A2n

Aln

(3-192)

If we combine this relationship with (3-191), we get

f To e1 1ref o o

o e2 2

n V A RS (T ) 2 .

T A Rln

(3-193)

The last result is interesting because it clearly conveys general design guidelines for particular applications. Specifically, zero reference output temperature coefficient, Sref(To), at T = To re-quires (R1/R2) = ρo. On the other hand, Sref(To) > 0 (positive temperature coefficient) demands (R1/R2) > ρo, while Sref(To) < 0 (negative temperature coefficient)commands (R1/R2) < ρo.

Upon substituting (3-192) and (3-180) into (3-188), we arrive at the reference output voltage for the specific circumstance of Sref(To) = 0. We shall term this specific reference output the optimized output response, Vropt. Then,

ref o

ropt ref go f TS (T )=0 o

TV V V m 1 n V 1 ,

Tln

(3-194)

for which the corresponding optimal temperature coefficient, Sropt(T), is ropt f o

ropt

dV (T) m 1 n k TS (T)

dT q Tln

(3-195)


- 293 -

Figure (3.53) plots this optimal coefficient as a function of temperature. We note that the temperature coefficient varies from +23 μV/°C at T = −25 °C to −34 μV/°C at T = 125 °C.

Figure (3.53). The optimized temperature coefficient of the reference output voltage generated

by the bandgap reference cell. The cell, which exploits BJTs having m = 2.4, is designed to deliver zero temperature coefficient at 27 °C.

Uncertainties plague junction injection coefficient nf, parameter m, and the temperature coefficient of resistance ratio (R1/R2). Additionally, inaccuracies materialize from the facts that the op-amp open loop gain is not infinitely large, voltage Vbeo2 is not known precisely, and the DC gain, hFE, of the BJTs, while doubtlessly large, is not infinitely large. Because of these uncertainties and analytical approximations, laser trimming of at least one of the two circuit resistances, R1 and R2, is essential to ensure the accurate satisfaction of the resistance ratio con-straint in (3-192). When properly trimmed, reference output voltages boasting excellent power line rejection and phenomenally small temperature coefficients are achieved.

Aside from displaying the temperature domain plot of the optimal temperature coeffi-cient, as we have done in Figure (3.53), the impressive performance of the bandgap reference generator is best examined numerically. To wit, in (3-194), take Vgo = 1.206 volts, m = 2.4, nf = 1, and To = 27 °C = 300.16 °K. Then, the optimum reference output voltage at T = 0 °C is, by (3-194), 1.242093 volts, at T = 27 °C, Vropt = 1.242244 volts, and at T = 100 °C, Vropt = 1.241250 volts. Thus, the change, say Vropt, in reference voltage output for a temperature rise of 100 °C from 0 °C is only 843.0 μV or 0.0679% of the reference temperature value of the opti-mum reference output voltage. This voltage change over a 100 °C increase in operating tempera-ture amounts to a voltage perturbation of only 679 ppm/°C!

3.5.2.3. Large Bandgap Reference Output Voltage

As we noted in the preceding section, the bandgap reference in Figure (3.52) is capable of a static response that is limited to the neighborhood of the bandgap potential of the semiconductor technology exploited for transistors Q1 and Q2. For silicon devices, for example, we witnessed a reference output voltage of the order of only 1.24 volts. Larger reference out-puts, which are often required in analog applications, require a topological modification to the

-35

-30

-25

-20

-15

-10

-5

0

5

10

15

20

25

-25 0 25 50 75 100 125

Te

mp

. Co

eff

icie

nt,

Sro

pt(

T)

(mic

rov

olt

/de

g C

)

Temperature (deg C)


- 294 -

reference cell along the lines of the network that appears in Figure (3.54). We observe that the modification entails appending resistances R3, R4, and R5 to the basic cell of Figure (3.52). The indicated interconnection of resistances R4 and R5 enables an increase in the original reference output voltage, Vref, to a voltage, VA, that is larger than Vref by a factor of (1 + R4/R5). On the other hand, we shall demonstrate that resistance R3 cancels the effects of base currents conducted by transistors Q1 and Q2. If transistors Q1 and Q2 conduct the small base currents that material-ize from given collector currents and large hFE, which is assured in SiGe technology, resistance R3 can be supplanted by a short circuit.

In order to demonstrate the operation of the modified cell and how the effects of transistor base currents can be cancelled through proper selection of resistance R3, the circuit in Figure (3.54) is analyzed under the depicted condition of equal collector currents (I) flowing in transistors Q1 and Q2. Clearly, we continue to assume that the op-amp has very large input impedances at both of its input ports and essentially infinitely large open loop gain. To this end, the loop comprised of the base-emitter junctions of Q1 and Q2 and resistances R2 and R3 yields

Figure (3.54). The bandgap reference supply of Figure (3.52), modified to enable a

larger than bandgap potential reference output voltage, VA. Resis-tance R3 is inserted to mitigate for the effects of base currents (Ib) flowing into transistors Q1 and Q2.

be2 be1 2 2 3 bV V R I R R I . (3-196)

In addition, the reference voltage, Vref, is given by

ref be2 1 bV V 2R I I . (3-197)

If the solution for current I in (3-196) is substituted into (3-197), we learn that

1 1ref be2 be2 be1 3 b

2 2

2R 2RV V V V R I .

R R (3-198)

It is vital to recognize that by virtue of (3-188), the sum of the first two terms on the right hand

Q2

R

Q1

R

R1

R3

R2

R4

R5

II

Op-Amp

Vcc

Vbe1 Vbe2

Vref

VA

[Open Loop

Gain = A ]o

I + Ib V /Rref 5

I + Ib

2(I + I )b

Vi

V /R +2Iref 5 b2Ib


- 295 -

side of (3-198) is literally the approximate value of the reference voltage response of our original bandgap cell. Indeed, we arrived at (3-188) by tacitly neglecting all bipolar transistor base cur-rents. To this end, we are reassured that (3-198) is correct in that if we neglect base current Ib in that expression, (3-198) collapses precisely to (3-188).

The enhanced reference voltage, VA, derives from

4A 4 b ref

5

RV 2R I 1 V .

R

(3-199)

Substituting for Vref from (3-198), we find that

4 41 1A be2 be2 be1 4 3 b

5 2 5 2

R R2R RV 1 V V V 2 R 1 R I .

R R R R

(3-200)

The first product of terms on the right hand side of this relationship is the enhanced reference voltage that materializes if the transistor base currents, Ib, are zero, which is approximated if the static short circuit current gains of the two bipolar devices are large. It follows that the last term in the subject equation is a voltage error precipitated by nonzero base currents. Fortuitously, this error, which is proportional to Ib, vanishes if we select resistance R3 carefully. An inspection of (3-200) reveals that the error contributed to VA by the transistor base currents is forced to zero if

23 4 5

1

RR R R .

R

(3-201)

Resultantly, (3-200) reduces to

4 41A be2 be2 be1 ref

5 2 5

R R2RV 1 V V V 1 V ,

R R R

(3-202)

which is to say the embellished reference output voltage, VA, approximates (because of the origi-nal tacit neglect of base currents) the original reference output, Vref, multiplied by the resistive ratio factor, (1 + R4/R5).

Two design-oriented issues surface as an engineering consequence to (3-202). First, if output voltage VA is to preserve the laudable thermal properties ascribed to voltage Vref, resis-tances R4 and R5 must possess identical temperature coefficients. This design requirement impli-citly requires that the values of R4 and R5 must not be excessively divergent. In other words, the modified bandgap reference cell works very well if VA is of the order of two to four times Vref, but not as well if VA/Vref equals ten to twenty. Moreover, the two subject resistances must be laid on chip out closely to ensure that both resistances experience the same operating temperature. The second, and somewhat more subtle issue is that resistance R5 (and hence R4, as well), cannot be too small. Two reasons underpin this directive. First, a small value of R5 yields a relatively large current, Vref /R5, which must be supplied by the output port of the op-amp in Figure (3.54). As it turns out, large output port currents make the task of achieving excellent power supply rejection in the op-amp progressively more difficult. The second reason is that large Vref /R5, which is conducted by both resistances R4 and R5, manifest potentially excessive power dissipa-tion in these resistances. Because of this large dissipation, the thermal characteristics of the resistances may differ markedly from those of the other passive and active circuit components, thereby rendering the thermal compensation measures discussed in the preceding section proble-matic.


- 296 -

3.6.0. REFERENCES

[1]. J. J. Ebers and J. L. Moll, “Large-Signal Behavior of Junction Transistors,” Proceedings of the IRE, vol. 42, pp. 1761-1772, Dec. 1954.

[2]. B. S. Meyerson, “High Speed Silicon Germanium Electronics,” Scientific American, vol. 270, pp. 42-47, March 1994.

[3]. P. Ashburn, SiGe Heterojunction Bipolar Transistors. John Wiley & Sons, 2003, chap. 10. [4]. H. K. Gummel and H. C. Poon, “An Integral Charge-Control Model of Bipolar Transistors,”

Bell System Technical Journal, vol. 49, pp. 115-120, May-June 1970. [5]. C. T. Kirk, “A Theory of Transistor Cutoff Frequency (fT) at High Current Densities,” IEEE

Transactions on Electron Devices, vol. ED-9, pp. 164-174, Mar. 1962. [6]. S. Dimitrijev, Understanding Semiconductor Devices. New York: Oxford University Press,

2000, pp. 334-341. [7]. J. M. Early, “Effects of Space-Charge Layer Widening in Junction Transistors,” Proceedings of

the IRE, vol. 46, pp. 1141-1152, Nov. 1958. [8]. H. N. Ghosh, “A Distributed Model of the Junction Transistor and its Application in the Predic-

tion of the Emitter-Base Diode Characteristic, Base Impedance, and Pulse Response of the De-vice,” IEEE Transactions on Electron Devices, vol. ED-12, pp. 513-531, Oct. 1965.

[9]. J. R. Hauser, “The Effects of Distributed Base Potential on Emitter Current Injection Density and Effective Base Resistance for Stripe Transistor Geometries,” IEEE Transactions on Elec-tron Devices, vol. ED-11, pp. 238-242, May 1965.

[10]. G. R. Wilson, “A Monolithic Junction FET-NPN Operational Amplifier,” IEEE Journal of Solid-State Circuits, vol. SC-3, pp. 341-348, Dec. 1968.

[11]. P. Brokaw, “A Simple Three-Terminal IC Bandgap Reference,” IEEE Journal of Solid-State Circuits, vol. SC-9, pp. 388-393, Dec. 1974.

[12]. P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design (2nd Edition). New York: Oxford University Press, 2002, pp. 153-158.

[13]. Y. Tsividis, “Accurate Analysis of Temperature Effects in Ic-Vbe Characteristics with Applica-tion to Bandgap Reference Sources,” IEEE Journal of Solid-State Circuits, vol. SC-14, pp. 655-657, June 1979.

E X E R C I S E S

PROBLEM #3.1 Each of three bipolar junction transistor interconnections depicted in Figure (P3.1) can function as an effective PN junction diode. For each of these connections, use the Ebers-Moll equations to de-rive an expression for the volt-ampere characteristic, Id -versus- Vd. Stipulate the effective saturation current, say Io, associated with each diode emulation.

Figure (P3.1)

Vd Vd

IdId

Vd

Id

(a). (b). (c).


- 297 -

PROBLEM #3.2 In the composite transistor structure of Figure (P3.2), both transistors are identical, and the indicated supply voltage, Vcc, is large enough to reverse bias the base-collector junctions of both devices. Moreover, the battery voltage, Vbb, is sufficiently large to forward bias the emitter-base junctions of both transistors. Use the Ebers-Moll model to derive expressions for the current ratios, I2/I1, I3/I1, and I4/I1.

Figure (P3.2)

PROBLEM #3.3 Consider a bipolar junction transistor that is operated in a manner as to ensure a strongly reverse bi-ased base-collector junction. Using the Ebers-Moll model, show that the emitter-base junction vol-tage, Ve, commensurate with zero emitter current, is negative and given by

e f T fV n V β 1 .ln

PROBLEM #3.4 A bipolar junction transistor is operated with forward bias applied to its emitter-base junc-tion. Use the Ebers-Moll model to show that the resultant collector current -to- base current transfer ratio, Ic /Ib, is smaller than the gain parameter, f, whenever the base-collector junc-tion of the subject transistor is forward biased.

PROBLEM #3.5 Repeat Example #3.3 for the diode interconnections of Figures (3.6b) and (3.6c).

PROBLEM #3.6 Use the Ebers-Moll model of a bipolar junction transistor to show that the ratio, Ibe /Ibc, of forward to reverse base current components can be cast in terms of the BJT emitter and collector currents, Ie and Ic, respectively, in accordance with

f rbe e r c

bc f e c r f

1 1 α βI I α I.

I α I I 1 1 α β

(a). Explain the engineering significance of a zero value to this ratio when Ie = rIc. (b). Explain the engineering significance of an infinite value to this ratio when Ic = fIe.

PROBLEM #3.7 Repeat Example #3.4 for the case in which the collector-emitter biasing voltage is only one volt.

PROBLEM #3.8 Repeat Example #3.4 for the stipulated biasing point, but for a transistor having three-times the emitter-base junction area.

Vbb

+Vcc

I3

I2

I4

I1


- 298 -

(a). Plot the unity gain frequency, fT, as a function of the quiescent collector current, IcQ. (b). Determine an approximate collector current commensurate with maximum achievable fT. (c). What is the maximum fT corresponding to the collector current found in Part (b)?

PROBLEM #3.9 An occasionally invoked metric for high frequency transistor performance is the transverse cutoff frequency, say fb. This metric is the 3-dB frequency of the small signal, short circuit forward transadmittance, yfe(jω), evidenced in a grounded emitter topology. The “short circuit” refers to a collector-emitter port that supports zero signal. Use the model in Figure (3.14) to derive analytical expressions for both yfe(jω) and fb. For simplicity, take rc = re = 0 in the BJT model.

PROBLEM #3.10 The BJT in the grounded base amplifier of Figure (P3.10) operates in its forward active regime be-cause of the constant voltage supply, Vcc, and the static current sink, IQ. The input signal, whose Thévenin resistance is Rs, is applied as the current, Is. The response to this input current is extracted as the signal component, Ios, of the net current, Io, which flows through the collector load resistance, Rl. Use the model of Figure (3.14), with resistances rc and re ignored, to respond to the following directives.

Figure (P3.10)

(a). Evaluate the current transfer function, Ai = Ios /Is, at low signal frequencies. Give an upper limit to this current gain.

(b). For a sinusoidal input signal, Is, infinitely large Rs and a short circuit load resistance, Rl, eva-luate the current transfer function, Ai = Ios /Is, as a function of frequency ω.

(c). Derive an expression for the 3-dB bandwidth of the current gain determined in Part (b). Suita-ble approximations can be invoked as long as these approximations are clearly rationalized.

(d). Compare the gain-bandwidth product of the grounded base amplifier with the short circuit, un-ity gain frequency, fT, of the grounded emitter configuration.

PROBLEM #3.11 The BJT in the grounded collector amplifier of Figure (P3.11) operates in its forward active regime because of the constant voltage supplies, Vcc and Vbb. The input signal, whose Thévenin resistance is Rs, is applied as voltage Vs,. The response to this input signal voltage is extracted as the signal component, Vos, of the net voltage, Vo, which is established across the indicated load resistance, Rl. Use the model of Figure (3.14), with resistances rc and re ignored, to respond to the following direc-tives.

(a). Explain why the configuration in Figure (P3.11) is commonly referenced as a grounded collector amplifier, despite the fact that the collector is not actually grounded and instead is incident with the positive terminal of a constant voltage source.

Rs

Rl

Is IQ

Io

+Vcc


- 299 -

Figure (P3.11)

(b). Evaluate the voltage transfer function, Av = Vos /Vs, at low signal frequencies. Give an upper limit to this voltage gain.

(c). For a sinusoidal input signal, Vs, zero Rs, and an infinitely large load resistance, Rl, evaluate the voltage transfer function, Av = Vos /Vs, as a function of frequency ω.

(d). Derive an expression for the 3-dB bandwidth of the voltage gain determined in Part (c). Suita-ble approximations can be invoked as long as these approximations are clearly rationalized.

(e). Compare the gain-bandwidth product of the grounded collector amplifier with the short cir-cuit, unity gain frequency, fT, of the grounded emitter configuration.

PROBLEM #3.12 Develop a design-oriented expression for the quiescent collector current, IcQ, in the PNP transistor cell of Figure (P3.12). Assess the shortfalls of the biasing configuration.

Figure (P3.12)

PROBLEM #3.13 The silicon transistor in the biasing configuration of Figure (P3.13) operates in its linear regime where it has a static beta of hFE, an emitter-base junction temperature coefficient of −Sbe, and a no-minal base-emitter turn on voltage of Vbe.

(a). Derive a general expression for the quiescent collector current, IcQ. (b). Stipulate the inequality that the circuit must satisfy if current IcQ is to be rendered relatively

insensitive to gain parameter hFE.

Rl

Rs

Vs

Vo

+Vcc

Vbb

R2

RlR1

IcQ

+Vee

VecQ

VebQ


- 300 -

Figure (P3.13)

(c). For the condition deduced in Part (b), what is the temperature sensitivity, IcQ/Tj, of the cir-cuit?

(d). What small signal resistance, say Rx, is presented to load resistance Rl at the collector node of the subject biasing network? Use reasonable approximations to simplify the expression for this resistance. Comment on the ability of the circuit to sustain nominally constant Q-point collector current in the face of signal changes presented at the collector node.

PROBLEM #3.14 Using a 6 volt power supply, design the circuit in Figure (P3.13) for IcQ = 1 mA and VceQ = 1 volt at room temperature. The collector current is to be held constant to within ±2% over a temperature range extending to 75 °C. Assume that the transistor is identical to that exploited in Example #3.6 and parameterized in Table (3.1). Use HSPICE or similar circuit simulation software to determine the quiescent collector current at 27 °C, 50 °C, and 75 °C.

PROBLEM #3.15 The silicon transistor in the circuit of Figure (P3.15) operates in its linear regime where it has a static beta of hFE, an emitter-base junction temperature coefficient of −Seb, and a nominal base-emit-ter turn on voltage of Veb. The inductors in this circuit are ideal; that is, they have infinitely large quality factors or equivalently, zero series resistances.

Figure (P3.15)

(a). Derive a general expression for the quiescent collector current, IcQ. (b). Stipulate the inequality that the circuit must satisfy if current IcQ is to be rendered nominally

R1

Ree

Rl

R2

IcQ

+Vcc

Rx

IcQ

Vee

Ree

R2R1


- 301 -

insensitive to current transfer parameter hFE. (c). Under the condition deduced in Part (b), what is the temperature sensitivity, IcQ/Tj, of the

circuit?

PROBLEM #3.16 The two identical silicon transistors in the low noise biasing circuit of Figure (P3.16) operate in their linear regimes where they display a static beta of hFE, an emitter-base junction temperature coeffi-cient of −Sbe, and a nominal base-emitter turn on voltage of Vbe. The inductor in this circuit is ideal; that is, it has infinitely large quality factors or equivalently, zero series resistance.

Figure (P3.16)

(a). Derive general expressions for the quiescent collector currents, IcQ1 and IcQ2, conducted by transistors Q1 and Q2, respectively.

(b). Stipulate the inequalities that the circuit must satisfy if the two quiescent collector currents are to be nominally insensitive to gain parameter hFE.

(c). Under the condition deduced in Part (b), what are the temperature sensitivity coefficients, i1 and i2, of the two quiescent collector currents?

(d). The circuit exploits feedback, which is implemented by resistance R3 and the inductive coil. Explain qualitatively the operation of this feedback loop.

PROBLEM #3.17

Figure (P3.17)

The power supply voltage, Vcc, in the biasing network of Figure (P3.17) is 9 volts, and the two transistors are identical to the devices addressed by Example #3.6 and Table (3.1). Design the cir-cuit so that each bipolar junction transistor conducts a quiescent collector current of 2 mA ±5% at a collector-emitter voltage of 1.5 volts over a temperature range extending from 27 °C to 75 °C. Use

R1

R2

R5

R4

R3

Q1

Q2Vcc

Q1 Q2

RlR

Rk

RRl

Vcc


- 302 -

HSPICE or equivalent computer-aided analysis software to confirm the propriety of the finalized de-sign at 27 °C, 50 °C, and 75 °C.

PROBLEM #3.18 Table (3.2) itemizes the HSPICE parameters for a representative, high-speed PNP bipolar junction transistor. Use this device to address the following directives. Unless specified otherwise, assume a junction operating temperature of 27 °C.

(a). Set up a computer-aided simulation that sweeps, for an emitter-collector voltage, Vec, of 1.5 volts, the static collector current as a function of the applied emitter-base voltage, Veb, for 0 ≤ Veb ≤ 800 mV. Plot these curves.

(b). Set up a computer-aided simulation that sweeps, for an emitter-collector voltage, Vec, of 1.5 volts, the static base current as a function of the applied emitter-base voltage, Veb, for 0 ≤ Veb ≤ 800 mV. Plot these curves.

(c). Use the plots garnered from the execution of the preceding two parts of this problem to gener-ate a plot of the DC beta, hFE, as a function of collector current for Vec = 1.5 volts.

(d). Use the foregoing simulated results to deduce the value of emitter-base junction voltage, Veb, commensurate with a collector current of 2 mA. What is the DC beta of the transistor at this collector current?

(e). Repeat Part (a) for a junction temperature of 75 C. Recall that the temperature induced change, Veb, in static emitter-base terminal voltage can be represented as Veb ≈ −SebTj, where Veb is the voltage change required to preserve constant collector current over the temperature excursion, Tj. This temperature excursion can be taken as the temperature difference between 27°C and 75 °C. Deduce the value of coefficient Seb, using the simulations already executed.

PROBLEM #3.19 The power supply voltage, Vcc, in the biasing network of Figure (P3.19) is 3 volts, and the two transistors are identical to the device parameterized in Table (3.2). Use the simulation results gar-nered in the preceding problem to design the circuit so that transistor Q1 conducts a quiescent collector current of 2 mA ±5% at an emitter-collector voltage of 1.5 volts over a temperature range extending from 27 °C to 75 °C. Use HSPICE or appropriate other computer-aided analysis software to confirm the propriety of the finalized design at 27 °C, 50 °C, and 75 °C.

Figure (P3.19)

PROLEM #3.20 Redesign the circuit addressed in Example #3.8 under the constraint that the current conducted by resistance R4 is to be nominally one-fourth of the collector current conducted by transistor Q2. Sub-mit a finalized schematic diagram, and simulate the design at 27 °C, 50 °C, 75 °C, and 100 °C.

PROBLEM #3.21 Redesign the circuit addressed in Example #3.8 under the constraint that the collector load resistance imposed on transistor Q1 is at least 5-times larger than the emitter degeneration resistance, Ree. In this approach, it is likely impossible to achieve equal collector-emitter voltages between transistors

Q2

Q1

RlR

Vcc

IcQ


- 303 -

Q1 and Q2. Submit a finalized schematic diagram, and simulate the design at 27 °C, 50 °C, 75 °C, and 100 °C. The SPICE parameters for the BJTs are itemized in Table (3.1)

PROBLEM #3.22 Derive a general expression for the static collector current, Ic, conducted by transistor Q2 in the net-work of Figure (3.33). Deduce the resultant temperature coefficient of this collector current.

PROBLEM #3.23 Using (3-116), use engineering rationale to develop an expression for the resistance, Rx, indicated as the resistance presented at the collector terminal of transistor Q1. Compared to the biasing configuration shown in Figure (3.29), what is the relative effectiveness of this circuit in the sense of coping with signal fluctuations at the collector port?

PROBLEM #3.24 All four transistors in the cascode current mirror of Figure (P3.24) are identical, save for the fact that transistors Q3 and Q4 each have emitter-base junction injection areas that are k-times larger than those of transistors Q1 or Q2. All transistors operate in their forward active regimes where they support identical base-emitter terminal potentials and identical values of the DC beta, hFE. Do not tacitly ignore transistor base currents.

Figure (P3.24)

(a). What is the static collector-base operating voltage of transistor Q4? (b). What is the minimum allowable collector to ground potential, V, of transistor Q3? (c). Derive the equation that relates current IQ to the current, Ir, conducted by resistance R. (d). Derive the equation that relates current IQ to the supply voltage, Vcc, the circuit resistance, R,

and the base-emitter terminal potential, Vbe, of all transistors. (e). What condition must be satisfied to render current IQ nominally independent of hFE? (f). Derive an expression for the temperature sensitivity, IQ/Tj, of current IQ. Assume Vbe =

−SbeTj, where Sbe is an empirical constant and Tj represents the junction operating tempera-ture of all devices.

(g). Derive an expression for the indicated small signal resistance, Rx, established at the collector of transistor Q3. As usual, assume low frequency conditions and ignore the internal series resistances implicit to the collectors and emitters of all devices. Make sure to account for the model parameter implications of the fact that while the current densities of transistors are likely to be identical, the actual collector currents flowing in all devices are not necessarily the same.

PROBLEM #3.25 In the two stage Wilson current sink of Figure (P3.25), the four transistors are identical except for

Q1

Q2

R

Ir IQ

V

Vcc

x k

x k

Rx

Q3

Q4

x 1

x 1


- 304 -

the fact that transistors Q1 and Q2 have twice the emitter-base junction injection area of transistors Q3 and Q4.

Figure (P3.25)

(a). What are the minimum allowable collector to ground potentials, V3 and V4, which are applied to the collectors of transistors Q3 and Q4, respectively?

(b). Derive the equations that relate currents I3 and I4 to the reference current, Ir, which flows through resistance R.

(c). Derive the equations that relate currents I3 and I4 to the supply voltage, Vcc, the circuit resis-tance, R, and the base-emitter terminal potential, Vbe, of all transistors.

(d). What condition renders currents I3 and I4 almost independent of hFE? (e). Derive an expression for the temperature sensitivities, I3 /Tj and I4 /Tj, of currents I3 and

I4. Assume Vbe = −SbeTj, where Sbe is an empirical constant and Tj represents junction operating temperature of all devices.

(f). Derive expressions for the indicated small signal resistances, Rx3 and Rx4, established at the collectors of transistors Q3 and Q4. As usual, assume low frequency conditions and ignore the internal series resistances in the collector and emitter leads of all devices. Make sure to account for the model parameter implications of the fact that while the current densities of all transistors are likely to be nearly identical, the actual collector currents flowing in all devices are not necessarily the same.

PROBLEM #3.26 In the Wilson current mirror of Figure (P3.26), the transistors are identical except for the indicated differences in emitter-base junction injection ratios.

(a). Derive an expression for the low frequency, small signal resistance, Ry, presented to the junc-tion formed of resistance R, the base terminal of transistor Q1, and the collector terminal of Q2. Ignore internal series resistances in the collectors and emitters of all transistors and additionally, ignore all forward Early resistances. Provide an engineering justification for the somewhat cavalier neglect of the Early resistance in each transistor.

(b). Reduce the expression gleaned in (a) for the case of very large βac. Discuss the size of the resultant resistance in terms of the injection area ratio, k.

Q2

Q1

Vcc

Q3

x 1

x 2

x 2

I3

Ir

V3

Rx3

R

Q4

x 1

I4

V4

Rx4


- 305 -

Figure (P3.26)

PROBLEM #3.27 Using the low frequency, small signal model of a bipolar junction transistor, develop an analytical expression for the small signal resistance, Rx, in the supply-independent biasing configuration of Figure (3.45). Ignore the internal collector and emitter resistances of all transistors. Furthermore, assume that the two startup transistors, Q6 and Q7, are large geometry devices so that the substrate capacitance of transistor Q6 emulates a short circuit for the signal frequencies of interest.

PROBLEM #3.28 An advantage of the startup cell in the supply-independent biasing scheme of Figure (3.45) is that it consumes no steady state power. A disadvantage is that it utilizes a capacitor whose value is generally sufficiently large to cast aspersions on its practical on chip circuit implementation. The circuit in Figure (P3.28) supplants the subject startup cell with a resistance, Rk, which is chosen large enough to ensure that it minimally affects the overall standby power dissipation of the network. Prove that a small current flowing through resistance Rk thwarts an initial null lockup state. What engineering logic underpins deploying resistance Rk?

Figure (P3.28)

Q3

Q2

Vcc

Q1

x k

x k

x 1

I1

Ir

V1

Rx

Ry

R

Q2Q1

IQ IoIQ

Vcc

x knx 1 Vo

R Rl

Q4

Q3

Q5

Ree Ree R /kee p

x 1 x 1 x kp

Rk


- 306 -

PROBLEM #3.29 The circuit in Figure (P3.29) provides an output current, Io, which is dependent on the supply voltage, Vcc. Indeed, current Io is a natural logarithmic function of Vcc. It therefore shows a voltage sensitivity that is smaller than the current sensitivities of biasing networks whose currents of interest are linearly related to the supply line voltage. All three transistors in the circuit are identical and are characterized by the parameters in Table (3.1).

Figure (P3.29)

(a). Assuming large static beta, hFE, in transistor Q1, show that the output current, Io, is given by

cc beTo

2 1 s

V 2VVI ,

R R Iln

where VT is the familiar Boltzmann voltage, and Is is the saturation current of the NPN transis-tors. It is to be understood that while Vbe is the base-emitter terminal voltage of each of the transistors, it can be supplanted by the junction threshold voltage for most design purposes.

(b). Is current Io PTAT? Explain briefly. (c). Using a nominal 5-volt supply, design the circuit so that Io = 5 mA at room temperature. Se-

lect resistance Rl so that the collector-emitter potential supported by transistor Q1 is 2Vbe, even if the supply voltage degrades to 2.5 volts.

(d). Use SPICE to simulate the room temperature, static describing function, Io versus Vcc, for the design effected in the preceding part of this problem. The simulation should span a Vcc range of 0 ≤ Vcc ≤ 10 volts. Does the simulated current sensitivity to supply voltage corroborate with theoretical expectations.

(e). Repeat Part (d) for junction operating temperatures of 50 °C and 75 °C. Does the simulated current dependence on temperature track with analytical expectations? Explain briefly.

PROBLEM #3.30 Figure (P3.30) proposes a supply-independent biasing scheme that can function as either a current source (via the current, Io1, conducted by PNP transistor Q6) or a current sink (via the current, Io2, flowing in the collector of NPN transistor Q3) or both, simultaneously. Current Io1 derives from cur-rent IQ because of the current mirror formed of transistors Q5 and Q4, while current Io2 is likewise directly dependent on IQ because of the effective mirror established by transistors Q1 and Q3. To the extent that the Early voltages of all active devices are large, currents Io1 and Io2 show a first order independence of the supply voltage, Vcc. All NPN transistors are identical, save for the indicated junction area factors, and have the parameters itemized in Table (3.1). Similarly, all PNP devices are identical, except for the delineated area factors, and have the parameters listed in Table (3.2).

Q1

Q2

Q3

Io

Vcc

x 1

x 1

x 1

Vo

R2

RlR1


- 307 -

Figure (P3.30)

(a). Assuming all transistor base currents can be ignored and all transistor Early voltages and knee currents are large, derive expressions for the output currents, Io1 and Io2.

(b). What is the minimum value, say Vmin, of supply voltage Vcc that is commensurate with linear active operation of transistors Q1, Q2, Q4, and Q5?

(c). Are null current states at startup an issue? If they are, mitigate the problem with a suitably connected resistance. Show the modified circuit schematic diagram.

(d). Using a 6-volt supply, design the circuit so that IQ = 1 mA, Io1 = 2 mA, and Io2 = 3 mA at room temperature. Select voltage Vo1 as the maximum voltage permissible with linear active mode operation of transistor Q6 when Vcc = Vmin. Additionally, select voltage Vo as the minimum voltage that ensures linear active regime operation of transistor Q3 when Vcc = Vmin.

(e). Use SPICE to simulate the room temperature, static describing functions, Io1 versus Vcc and Io2 versus Vcc, for the design executed in the preceding part of this problem, over a Vcc range spanning 0 ≤ Vcc ≤ 10 volts. What perturbations in currents Io1 and Io2 are observed when Vcc degrades by 50%?

(f). Repeat Part (d) for junction operating temperatures of 50 °C and 75 °C. Do the simulated cur-rent dependencies on temperature track with analytical expectations? Explain briefly.

(g). Assuming a startup resistance is required, select its value such that the increased power dissipation of the entire circuit is less than 2% of the dissipation observed for the circuit with no startup provision. Simulate the transient responses of currents Io1 and Io2 when Vcc is a 6-volt pulse waveform characterized by 500 nSEC rise and fall times. What is the simulated set-tling time of the entire circuit? To the latter end, define the settling time as that time subse-quent to step input excitation at which currents Io1 and Io2 are maintained at 90% of their respective steady state values.

PROBLEM #3.31 In this problem, we should like to investigate, albeit semi-quantitatively, the input to output (I/O) nonlinearity that pervades the emitter-base junction voltage (Ve) to collector current (Ic) response. To this end, recall that for Ve > Veon, where Veon represents the emitter-base junction threshold vol-tage, and Vc ≤ 0, the collector current is given approximately by the Ebers-Moll relationship,

e f TV n Vc f b sI β I I 1 .e

Let Ve = VeQ + Vm cos(ωt), where VeQ is the quiescent emitter-base junction forward bias that corres-ponds to a quiescent current of IcQ. Plot the approximate current ratio, Ic /IcQ, as a function of the

Q2

Q1

IQIQ

Vcc

x 1

x 1

Vo1

Vo2

R

Q4

Q5

Q6

x 1 x 1 x kp

Io1

Io2

Q3

x kn


- 308 -

normalized time, (ωt), for normalized signal amplitudes, Xm = Vm /nfVT, of Xm = 0.005, 0.05, 0.5, 5, and 50. Your plots should embrace at least four periods of the applied sinusoid. Comment on the nonlinearities postured by your plots.

PROBLEM #3.32 The current mirror offered in Figure (P3.32) is driven by the off chip current source, Ii. The three transistors are identical except that the emitter-base junction areas of transistors Q1 and Q2 are each k-times larger than the emitter-base junction area of transistor Q3. Voltages Vcc and Vpp are suffi-ciently large to ensure that all three active devices operate in their saturation domains.

(a). Derive an analytical relationship that links output current Io to static input current Ii.

Figure (P3.32)

(b). What purpose is served by resistance R in the mirror. (c). Does accurately predictable and reproducible current mirroring between Io and Ii require that

the quiescent collector-emitter voltages of all three transistors be nominally the same? What is the effect of Early voltage on this mirroring?

(d). If voltage Vpp changes by the small (positive or negative) amount, Vpp, estimate the resul-tantly small change, Io, in static current Io. Note that this estimate requires that you deter-mine an expression for the indicated output resistance, Rout. In the course of determining Rout, series collector and emitter resistances can be ignored. If you make other approximations, be sure to justify them.

PROBLEM #3.33 In the cascode current mirror of Figure (P3.33), all transistors are identical (inclusive of emitter-base junction areas), all transistors are biased identically, and all devices operate in their linear regimes.

Figure (P3.33)

Q2

Q3

ReeR

Q1

Ree

Ii

Vcc Vpp

Io

Rout

Q3

Q4

Ii

Vcc Vpp

Io

Rout

Q2

Q1


- 309 -

(a). Deduce relationship that links output current Io to the constant static input current Ii. (b). Determine an expression for the indicated small signal output resistance, Rout. The internal se-

ries collector and emitter resistances can be tacitly ignored, as can the Early resistances of transistors Q1 and Q2. However, do not ignore the Early resistances of transistors Q3 and Q4.

(c). Why is it sensible to ignore the Early resistances of transistors Q1 and Q2, but unreasonable to ignore the Early resistances in the other two transistors? Submit concise, but clear, engineer-ing rationale for your answers.

(d). If voltage Vpp changes by the small (positive or negative) amount, Vpp, estimate the resul-tantly small change, Io, in static current Io.

PROBLEM #3.34 In the current source shown in Figure (P3.34), the two PNP transistors are similar, as are the two NPN devices. However and in general, the ith transistor has an emitter-base junction injection area of Ai. All devices operate in their saturation domains, and care is taken to ensure that the two NPN collector-emitter voltages are the about the same; ditto for the two static emitter-collector voltages of the two PNP transistors.

Figure (P3.34)

(a). Determine an expression for the static current transfer ratio, Iout /Ii. (b). How critical are the NPN and PNP DC betas, hFEn and hFEp, respectively, to a reasonably accu-

rate determination of this current ratio?

PROBLEM #3.35 In the controlled current source of Figure (P3.35), the two transistors operate in their linear active, forward regimes, have negligible base conductivity modulation, and offer very large DC beta. Cur-rent Ii is a constant current sink.

Figure (P3.35)

Q4

Q3

Vcc

IoutII

Q2Q1

R1 R2

Q1

Vcc

Io

Ii

Q2

R1

R2

Vcntr


- 310 -

(a). Derive an expression for the indicated output current, Io, in terms of the supply line voltage, Vcc, the applied control voltage Vcntr, and pertinent circuit resistances.

(b). If voltages Vcc and Vcntr are reasonably insensitive to circuit operating temperatures, and if the temperature coefficients of both circuit resistances are very small, comment on the tempera-ture sensitivity of current Io. In particular, is current Io independent of operating temperature, a strong function of temperature, or a weak function of temperature? Provide clear, but con-cise engineering rationale for your position on this matter.

PROBLEM #3.36 In the current sink reference depicted in Figure (P3.36), the current response is the indicated current, Iref. All transistors operate in their forward active domains. Transistors Q1 and Q2 have identically sized emitter-base junction areas, while NPN transistor Q3 has an emitter-base junction area that is kn-times that of Q2. The PNP BJT, Q5, has an emitter-base junction area that is larger than that of transistor Q4 by a factor of kp.

Figure (P3.36)

(a). Derive an analytical expression for the reference output current, Iref. (b). What must the collector-emitter voltages of transistors Q1, Q2, and Q5 satisfy to ensure that

these devices operate in their linear regimes? What must the emitter-collector voltages of transistors Q4 and Q5 satisfy so that these transistors similarly operate in their forward active regimes. Attempt, as best as possible, to express your engineering disclosures in terms of cur-rent Iref power line voltage, Vcc, and area ratios, kn and kp.

PROBLEM #3.37 Return to the current reference topology of Figure (P3.36).

(a). Derive an expression for the small signal output resistance, Rx. Make reasonable assumptions to simplify this result.

(b). If voltage Vcc changes by the small amount, Vcc, what is the resultant change Iref, in the reference current?

PROBLEM #3.38 The op-amp in the bandgap reference cell of Figure (P3.38) can be presumed to have infinitely large open loop gain and infinitely large input impedances at both of its input ports. All transistors are bi-ased to ensure that they operate in their forward active regimes. Transistors Q1 through Q5 and transistors Q6, Q8, and Q10 have the same emitter-base junction injection areas. On the other hand, the emitter-base junction areas of transistors Q7 and Q9 are a factor of k larger than the areas of transistors Q6 and Q8.

Q5Q4

Q2

Q1

x 1 x 1

x kpx 1

R

Rl

Q3

x kn

+Vcc

Iref

Rx


- 311 -

Figure (P3.38)

(a). Determine a general expression for the reference output voltage, Vref. (b). What design condition must be satisfied if Vref is to offer zero temperature coefficient at the

room temperature reference of To? Take To = 27 °C. (c). In view of the design condition developed in Part (b), what is the corresponding optimized

value, say Vropt, of output voltage Vref?

Q1 Q5

Q6

Q7

x 1 x 1

x 1

x k

Q2

x 1

Q3

Q8

x 1

x 1

x k

Q4

x 1

op-amp

I1 I2

Q10

x 1

R

Vref

Vcc

Q9

chapter 3 - analog integrated circuit design by john choma

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