chapter 6 -- introduction to sequential devices. the sequential circuit model figure 6.1
TRANSCRIPT
Chapter 6 -- Introduction to Sequential Devices
The Sequential Circuit Model
x 1 z 1
x n zm
(a )
y 1 Y ry r Y 1
M em o ry
C o m b in a tio n a llo g ic
C o m b in a tio n a llo g ic
(b )
x 1 z 1
x n zm
Figure 6.1
State Tables and State Diagrams
P resen t sta te
In p u t
(a ) (b )
In p u t/o u tp u t
P resen t sta te
N ex t sta te
y
x
Y /z
x /z
N ex tsta te /o u tp u t
y
Y
Figure 6.2
Sequential Circuit Example
1 /1
P resen tsta te
A C
B D
(a )
(b )
0 1
0 /1
0 /0
1 /1
x /z
In p u t x
0 /0
1 /0 1 /0
D /0B /1C /1A /0
C /1A /0D /0B /1
ABCD
0 /1
Figure 6.3
Latch and Flip-flop Timing
S e t
R ese t
(a )
(b )
C lo ck
Q
S e t
R ese t
Q
Figure 6.4
TTL Memory Elements
Set Latch
(a ) (b ) (c ) (d )
00
0
SQ
00
0
1
SQ1
1
1
SQ0
1
Figure 6.5
Reset Latch
(d ) (e )
10
QR
R = 0 Q
Q1
(c )
10
Q
R = 1
1
(b )
01
Q
R = 0
0
(a )
0
1Q
0
0
0
1
0S
Figure 6.6
Set-Reset Latch (SR latch)
(a )
(c ) (d )
S
QN 1
N 2 Q
(b )
S
QN 1
N 2 Q
R
S
RQ
QN 1
N 2
Q
Q
S
R
Figure 6.7
NAND SR Latch
(b )
(d )
QR = 0 R = 1
S = 1S = 0
Q
(a )
QR
R
SS
QN 1
N 2
(c )
QR
SQ
Q
Q
R
S
(e )
Q
Q
R
S
Figure 6.8
Set-Reset Latch Timing Diagram
(a )
S
R
Q
S e t R ese t I lleg a lin p u ts
U n k n o w n v a lu es
Q
S e t
(b )
S
R
Q
S e t R ese t I lleg a lin p u ts
U n k n o w n v a lu es
Q
S e t
Figure 6.9
SR Latch Propagation Delays
S
R
Q
tPLH(S to Q )
tPLH(N 2 )
tPHL(N 1 )
tPHL(R to Q )
tPHL(N 2 ) tPLH
(N 1 )
Q
SR Latch Characteristics
S R Q Q *
(a )
E x c ita tio nin p u ts
P resen tsta te
N ex tsta te
00001111
00110011
01010101
010011
N o ch a n g e
R ese t
S e t
N o t a llo w ed
Q
S R
0
0 0 0 1 1 1 1 0
R
Q
0 Ð 1
1 0 Ð 1
S
0
1
1 0
0 1
0 d d 0
(b )
S R
0 1
(c )
Figure 6.11
Q* = S + RQ
SN74279 Latch with Two Set Inputs
(b )(a )
Q
Q
RQ
R
S 1S 2
S 1S 2
Figure 6.12
Gated SR Latch
(a )C * R
S
C
R
S
R
Q
Q
(b )(c )
Q
Q
C * S
S
C
R
S
R
Q
Q
S
C
R
S
C
R
Q
Q
(d )
Figure 6.13
Gated SR Latch Characteristics
E x cita tio nin p u ts
S R
N ex tsta te
Q *
0011111111
´00001111
E n a b lein p u ts
C
´00110011
0101010101
01010011
H o ld
N o ch a n g e
R ese t
S e t
N o t a llo w ed
P resen tsta te
Q
1 1 0
1 0 1
0 d d , 1 0 d 0 d d , 1 d 0
(a ) (b )
C S R
0 1
Figure 6.14
Q* = SC + RQ + C Q
Delay Latch (D latch)
(b )
Q
Q
D
C
S
R S R la tc h
(c )
Q
Q
D
C
S
R S R la tc h
D
C
Q
Q
(a )
Figure 6.15
D Latch Characteristics
E x cita tio nin p u t
D
N ex tsta te
Q *
001111
E n a b lein p u t
C
´0011
010101
010011
H o ld
S to re 0
S to re 1
P resen tsta te
Q
1 1
1 0
0 d , 1 0 0 d , 1 1
(a ) (b )
C D
0 1
Figure 6.16
Q* = DC + CQ
D Latch Timing Diagram
Q
D
C
E n a b led
H o ld
E n a b led
H o ld
E n a b led
Figure 6.17
D Latch Timing Constraints
twM in im u m en a b le
p u lse w id th
Q
D
C
D m a y n o tch a n g e S e tu p tim e
v io la tio nH o ld tim ev io la tio n
t s u(se tu p )
t s u
U n k n o w n sta te
th(h o ld ) th
Figure 6.18
The SN74LS75 D Latch
C D
C Q
Q Q *
(a )
D
C Q
Q
D
C Q
Q
(b )
(c )
D
C Q
Q
D
C
(d )
00
1
0
1
0
D t
Figure 6.19
Propagation Delays and Time Constraints for the SN74LS75
Hazard-Free D Latch, the SN74116
D
C
Q
D
C
Q
C 1
C 2
P R E (o r S )
C L R (o r R )
Q
(c )
D
Q
Q
(d )
1
1 1 1
(a )
Q
D
C
1
1 1 1
(b )
Figure 6.20
Q* = DC + CQ + DC
Master-Slave SR Flip-flop
S
C
R
S
C
R
S
C
R
Q M
M a ste r S la v e
(c )
(d )
M a ste r
S la v e
Q M
F lip -flo p o u tp u t ca n ch a n g e
tsu(se tu p )
S a n d R m a yn o t ch a n g e
twC lo w p u lse w id th(m a ste r en a b led )
twC h ig h p u lse w id th
(sla v e en a b led )
Q
g a te d h o ld g a te d h o ld g a te d h o ld g a te d h o ld
h o ld g a te d h o ld g a te d h o ld g a te d h o ld g a te d
th(h o ld )
S
C
R
Q
Q
Q
Q
S
C
R
Q
Q
S
C
R
Q
Q
(a ) (b )(c lo ck )
Figure 6.20
SR Master-Slave Flip-Flop Characteristics
R CQ Q *
00
11
01
01
01
00
N o ch a n g e
R ese t 1 0
0 1
0 d 0 d
(b )
S R
0 1
S
00
00
00
11
01
01
11
S e t
(a )
11
11
N o t a llo w ed
Figure 6.22
Q* = S + RQ
Master-Slave D Flip-Flop
D
C
M a ste r S la v e
Q MD
C
Q
Q
Q
Q
D
C
Q
Q
D
C
Q
Q
(a ) (b )(c lo ck )
Figure 6.23
Master-Slave D Flip-Flop Characteristics
M S
D CQ Q *
00
11
01
01
00
11
S to re 0
S to re 1
(a )(b )
(c )
D
Q M
E n a b led : M S M S M S M
Q = Q S
C
10 D
1
0
Figure 6.24
Q* = D
Pulse-Triggered JK Flip-Flop Characteristics
K CQ Q *
00
11
01
01
01
00
H o ld
R ese t
1 d
d 1
0 d d 0
(b )
J R
0 1J
00
00
00
11
01
01
11
10
S e t
(a )
11
11
T o g g le
Q
J K
0
0 0 0 1 1 1 1 0
0
1
K
0 1 1
1 0 0 1
J
Q
(c )
Figure 6.25
Q* = KQ + JQ
Pulse-Triggered JK Flip Realization
D
C
Q
Q
J
C
K
Q
Q
K
J
C
Q *Q
Q
K Q
J Q
(a )
(b )
Figure 6.26
The SN7476 Dual Pulse-Triggered JK Flip-Flop
J
C
K
(a )
Q
Q
(b )
P R E
C L R
1 P R E
2 P R E
1 C L K
1 C L R
2 C L K
2 C L R
1 K
1 J
2 J
1 K
1 J
S
R
C 1
1 Q
1 Q
2 Q
2 Q
(2 )
(4 )
(1 )
(1 6 )
(3 )
(7 )
(9 )
(6 )
(1 2 )
(8 )
(1 5 )
(1 4 )
(1 1 )
(1 0 )2 K
Q
Q
'7 6
Figure 6.27
SN7474 Dual Positive-Edge-Triggered D Flip-Flop
(b )
(c )
P R E
C L R
1 P R E
2 P R E
1 D
1 C L R
2 C L K
2 C L R
1 C L K
1 D
S
R
C 1 1 Q
1 Q
2 Q
2 Q
(4 )
(3 )
(2 )
(1 )
(1 0 )
(1 1 )
(1 2 )
(1 3 )
(5 )
(6 )
(9 )
(8 )2 D
Q
Q
Q
Q
(a )
Q
Q
P R E
D
C L R
C L K
'7 4
Figure 6.28
SN7474 Excitation Table
In p u ts O u tp u ts
M o d eP R E C L R D C L K Q Q
LHLHHH
HLLHHH
HL
L
HLHHL
Q 0
LHHLHQ 0
S e tC lea r
N o t a llo w edC lo ck ed o p era tio nC lo ck ed o p era tio n
H o ld
Figure 6.29
SN7474 Flip-Flop Timing Specifications
D
C
Q
D sh o u ld b e sta b le
tsu
th
tsu
th
tPHLtPLH
T o O u tp u t Qfro m : D ela y P a ra m ete r V a lu e (n s)
(a )
tPLHtPHL
tPLHtPHL
tPLHtPHL
2 54 0
2 54 0
2 54 0
C lo ck
P R E
C L R
In p u tP in C o n stra in t
M in im u mV a lu e (n s)
tsuth
tw lo wtw h ig htw lo wtw lo w
2 05
3 03 73 03 0
DDC lo ckC lo ckC L RP R E
(b )
(c )
Figure 6.30
SN74175 Positive-Edge-Triggered D Flip-Flop
C L E A R
C K1 D D 1 Q
(2 )Q
Q(3 )
(4 )
1 Q
C L E A R
C K2 D D 2 Q
(7 )Q
Q(6 )
(5 )
2 Q
C L E A R
C K3 D D 3 Q
(1 0 )Q
Q(1 1 )
(1 2 )
3 Q
C L E A R
C K4 D D 4 Q
(1 5 )Q
Q(1 4 )
(1 3 )
4 QC L O C K
C L E A R
(9 )
(1 )
(a )
Figure 6.31 (a)
SN74273 Positive-Edge-Triggered D Flip-Flop
C L O C K
C L E A R
R
C 1
1 D(3 )
1 D
(1 1 )
1 Q(2 )
R
C 1
2 D(4 )
1 D
2 Q(5 )
R
C 1
3 D(7 )
1 D
3 Q(6 )
R
C 1
4 D(8 )
1 D
4 Q(9 )
R
C 1
5 D(1 3 )
1 D
5 Q(1 2 )
R
C 1
6 D(1 4 )
1 D
6 Q(1 5 )
R
C 1
7 D(1 7 )
1 D
7 Q(1 6 )
R
C 1
8 D(1 8 )
1 D
8 Q(1 9 )
(1 )
(b )
Figure 6.31 (b)
SN74LS73A Edge-Triggered JK Flip-Flop Logic Diagram
Q
K J
Q
C L R
C L K
Figure 6.32 (a)
SN74LS73A Logic Symbols
J
C
K
Q
Q
(b )
C LR
(c )
1 J
2 J
1K
1 C LR
2 C LK
2 C LR
1 C LK
1K
1 J
R
C1 1 Q
1 Q
2 Q
2 Q
(1 4 )
(1 )
(3 )
(2 )
(7 )
(5 )
(1 0 )
(6 )
(1 2 )
(1 3 )
(9 )
(8 )2K
'L S 7 3 A
Figure 6.32 (b) and (c)
SN74276 and SN74111 Edge-Triggered JK Flip-Flops
'1 1 1
(d )
1 J
2 J
1 K
1 C L R
2 C L K
2 C L R
1 C L K1K
1 J
R
C1
1 Q
1 Q
2 Q
2 Q
(7 )
(6 )
(9 )
(1 0 )
2 K
P R E
1 K
1 J1 C L K
2 J
2 K
C L K
2 C L K
3 K
3 J3 C L K
4 J
4 K4 C L K
(11 )(1 )
(2 )(3 )(4 )(9 )(8 )(7 )
(1 2 )(1 3 )(1 4 )(1 9 )(1 8 )(1 7 )
1 Q
2 Q
3 Q
4 Q
(5 )
(6 )
(1 5 )
(1 6 )
SR
1 J C11
K
S1 P R E(2 )
(4 )
(5 )
(1 )
(3 )
(1 4 )
(1 2 )
(11 )
(1 5 )
(1 3 )
2 P R E
(e )
'2 7 6
Figure 6.32 (d) and (e)
Negative-Edge-Triggered T Flip-Flop
P R E
C L R
Q
QT
(a ) (b )
V C
C
P R E
C L R
Q
QC
J
K
Figure 6.33
Edge-Triggered T Flip-Flop Characteristics
01
10
T o g g leT o g g le
1
1
0 0
(a ) (b )
T
0 1
Q Q *T
Figure 6.34
Q* = Q
Clocked T Flip-Flop
P R E
C L R
Q
QC
(a ) (b )
P R E
C L R
Q
QC
JT
T
K
Figure 6.35
Excitation Table for Clocked T Flip-Flops
T Q C Q *
00
11
01
01
01
10
H o ld
T o g g le
Figure 6.36
Q* = TQ + TQ
The Clocked T Flip-Flop Timing Diagram
C lo ck
C lo ck
(a )
(b )Q
Q
D tT c
T c T
Q
Q
Q
Q
T
Figure 6.37
Summary of Latch and Flip-Flop Characteristics
SE555 Precision Timing Module
V C C
R ese t
C o n tro l
C o m p a ra to r
QR 1
R
R
T h resh o ld
T r ig g e r
G ro u n d
Q 1
O u tp u t
D isch a rg e
C 1
S E 5 5 5
R
S
R
C 2
1
Figure 6.38
Astable Operation of The SE555
R A
R B
C
S E 5 5 5
2
6
7
4
5 8
3
V C C
R L
0 .0 1 m F
1
C o n t
O u t
R E S E T
D IS C H
T H R E S S q u a re w a v e
T R IG
G N D
V C C
Figure 6.39
Monostable (One shot) Device Realization
R A
CS E 5 5 5
2
6
7
4
5 8
3
V C CR L
0 .0 1 m F
1
C o n t
O u t
R E S E T
D IS C H
T H R E S
T R IG
G N D
V C C
T rig g e r
O u tp u t
3 .3 -m s p u lse ifR A = 3 k O h m a n d C = 1 m F
Figure 6.40
PROM-based Sequential Circuits
y
P R O M 1
N ex tsta te
In p u tx
R eg iste rO u tp u t
z
(b ) (c )
P resen t sta te
Y/z
P R O Mx
A d d ressy
P R O M 1Y
P R O M 2z
C o n ten ts
N ex t sta te /o u tp u t
P R O M 2
(a )
C lo ck
P resen tsta te
In p u tx
y
Y
Figure 6.41
PROM-based Sequential Circuit Example
1
1
0
0
0
1
0
1
00001111
D
C lo ck
0 00 11 01 1
0 1
x
Y 2Y 1/z
x y 2 y 1 Y 2 Y 1 z
1 0 /11 1 /00 1 /10 0 /0
0 0 /11 1 /10 0 /01 1 /0
00110011
01010101
11000101
01100101
10101100
(c )
x
z
y 2y 1
Q
0
1
2
3
4
5
6
7
0
1
1
0
0
1
0
1
1
0
1
0
1
1
0
0
(b )
(a )
Y 2 Y 1
Q
C CD
y 2
y 1
Figure 6.41
Prime Number Sequencer
S N 7 4 2 7 3(8 D flip -flo p s)
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
2 5 1
2 5 2
2 5 3
2 5 4
2 5 5
1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D
1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q 8 QC lo ck
C lo ck
2 5 6 x 8 P R O M
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
1
0
1
0
0
1
0
1
1
0
0
1
1
1
1
1
1
1
0
Figure 6.43