sequential circuit ii
DESCRIPTION
Sequential Circuit II. Latch & Flip-flop. Sequential Logic. Block Diagram of Sequential Logic. SR NOR Latch. Logical Diagram. Functional Table. Simplified Functional Table. SR NOR Latch. Logical simulation for SR Latch. SR NAND Latch with Control Input. Logical Diagram. - PowerPoint PPT PresentationTRANSCRIPT
![Page 1: Sequential Circuit II](https://reader036.vdocuments.mx/reader036/viewer/2022062521/568167dd550346895ddd3baa/html5/thumbnails/1.jpg)
MOHD. YAMANI IDRIS/ NOORZAILY MOHAMED NOOR
1
Sequential Circuit II
Latch & Flip-flop
![Page 2: Sequential Circuit II](https://reader036.vdocuments.mx/reader036/viewer/2022062521/568167dd550346895ddd3baa/html5/thumbnails/2.jpg)
MOHD. YAMANI IDRIS/ NOORZAILY MOHAMED NOOR
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Sequential Logic
Block Diagram of Sequential Logic
![Page 3: Sequential Circuit II](https://reader036.vdocuments.mx/reader036/viewer/2022062521/568167dd550346895ddd3baa/html5/thumbnails/3.jpg)
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SR NOR Latch
Logical Diagram Functional Table
Simplified Functional Table
![Page 4: Sequential Circuit II](https://reader036.vdocuments.mx/reader036/viewer/2022062521/568167dd550346895ddd3baa/html5/thumbnails/4.jpg)
MOHD. YAMANI IDRIS/ NOORZAILY MOHAMED NOOR
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SR NOR Latch
Logical simulation for SR Latch
![Page 5: Sequential Circuit II](https://reader036.vdocuments.mx/reader036/viewer/2022062521/568167dd550346895ddd3baa/html5/thumbnails/5.jpg)
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SR NAND Latch with Control Input
Logical Diagram Functional Table
![Page 6: Sequential Circuit II](https://reader036.vdocuments.mx/reader036/viewer/2022062521/568167dd550346895ddd3baa/html5/thumbnails/6.jpg)
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D Type Latch
Logical Diagram Functional Table
![Page 7: Sequential Circuit II](https://reader036.vdocuments.mx/reader036/viewer/2022062521/568167dd550346895ddd3baa/html5/thumbnails/7.jpg)
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Master Slave Flip-flop
![Page 8: Sequential Circuit II](https://reader036.vdocuments.mx/reader036/viewer/2022062521/568167dd550346895ddd3baa/html5/thumbnails/8.jpg)
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Master Slave Flip-flop
![Page 9: Sequential Circuit II](https://reader036.vdocuments.mx/reader036/viewer/2022062521/568167dd550346895ddd3baa/html5/thumbnails/9.jpg)
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Master Slave JK Flip-flop
![Page 10: Sequential Circuit II](https://reader036.vdocuments.mx/reader036/viewer/2022062521/568167dd550346895ddd3baa/html5/thumbnails/10.jpg)
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D Type Positive Edge Triggered Flip-flop
![Page 11: Sequential Circuit II](https://reader036.vdocuments.mx/reader036/viewer/2022062521/568167dd550346895ddd3baa/html5/thumbnails/11.jpg)
MOHD. YAMANI IDRIS/ NOORZAILY MOHAMED NOOR
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D Type (Flip-flop & Latch)
Positive edge triggered D Type flip-flop simulation
D Latch simulation
D Latch with control input simulation
Comparison
![Page 12: Sequential Circuit II](https://reader036.vdocuments.mx/reader036/viewer/2022062521/568167dd550346895ddd3baa/html5/thumbnails/12.jpg)
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D Type (Flip-flop & Latch)
Negative edge triggered D Type flip-flop simulation
![Page 13: Sequential Circuit II](https://reader036.vdocuments.mx/reader036/viewer/2022062521/568167dd550346895ddd3baa/html5/thumbnails/13.jpg)
MOHD. YAMANI IDRIS/ NOORZAILY MOHAMED NOOR
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D Type (Flip-flop & Latch)
Negative edge triggered D Type flip-flop with Clear and Preset input simulation
![Page 14: Sequential Circuit II](https://reader036.vdocuments.mx/reader036/viewer/2022062521/568167dd550346895ddd3baa/html5/thumbnails/14.jpg)
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Positive Edge Triggered JK Flip-flop
![Page 15: Sequential Circuit II](https://reader036.vdocuments.mx/reader036/viewer/2022062521/568167dd550346895ddd3baa/html5/thumbnails/15.jpg)
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Positive Edge Triggered JK Flip-flop
![Page 16: Sequential Circuit II](https://reader036.vdocuments.mx/reader036/viewer/2022062521/568167dd550346895ddd3baa/html5/thumbnails/16.jpg)
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JK Flip-flop
Negative edge JK flip-flop with input Clear simulation
![Page 17: Sequential Circuit II](https://reader036.vdocuments.mx/reader036/viewer/2022062521/568167dd550346895ddd3baa/html5/thumbnails/17.jpg)
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SR Type
Negative edge SR flip-flop with input Clear simulation
![Page 18: Sequential Circuit II](https://reader036.vdocuments.mx/reader036/viewer/2022062521/568167dd550346895ddd3baa/html5/thumbnails/18.jpg)
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T Type
Negative edge T flip-flop with input Clear simulation
![Page 19: Sequential Circuit II](https://reader036.vdocuments.mx/reader036/viewer/2022062521/568167dd550346895ddd3baa/html5/thumbnails/19.jpg)
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Standard Graphical Symbol Circle on block shows complement
positive pulsenegative pulsepositive edgenegative edge
Arrow like symbol shows a dynamic input where flip-flop responded towards edge transition for clock pulse input
![Page 20: Sequential Circuit II](https://reader036.vdocuments.mx/reader036/viewer/2022062521/568167dd550346895ddd3baa/html5/thumbnails/20.jpg)
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Standard Graphical Symbol