chapter 10 boundary scan and core-based testing

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VLSI Test Principles and Architectures Ch. 10 - Boundary Scan and Core-Based Testing - P. 1

Chapter 10 Chapter 10

Boundary Scan and Boundary Scan and Core-Based TestingCore-Based Testing

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OutlineOutline

Introduction Digital Boundary Scan (1149.1) Boundary Scan for Advanced Networks

(1149.6) Embedded Core Test Standard (1500) Comparison between 1149.1 and 1500

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Boundary ScanBoundary Scan Original objective: board-level digital testing Now also apply to:

MCM and FPGA Analog circuits and high-speed networks Verification, debugging, clock control, power

management, chip reconfiguration, etc. History:

Mid-1980: JETAG 1988: JTAG 1990: First boundary scan standard – 1149.1

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Boundary Scan FamilyBoundary Scan FamilyNo. Main target Status

1149.1 Digital chips and interconnects among chips

Std. 1149.1-2001

1149.2 Extended digital serial interface Discontinue

1149.3 Direct access testability interface Discontinue

1149.4 Mixed-signal test bus Std. 1149.4-1999

1149.5 Standard module test and maintenance (MTM) bus

Std. 1149.5-1995 (not endorsed by IEEE since 2003)

1149.6 High-speed network interface Std. 1149.6-2003

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Core-Based SOC DesignCore-Based SOC Design

ADC

DAC

PLL

RAM RAM ROM

DSP

BUS &INTERCONNECT

CPU

ASIC 1

ASIC 2

GLUE LOGIC

IP 1

IP 2

RAM

ROMASIC

ASIC

ALUDSP

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Digital Boundary Scan – 1149.1Digital Boundary Scan – 1149.1

Basic concepts Overall test architecture & operations Hardware components Instruction register & instruction set Boundary scan description language On-chip test support Board/system-level control architectures

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Basic Idea of Boundary Scan Basic Idea of Boundary Scan

I n t e r n a l

L o g i c

Boundary-scan cell

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A Board Containing 4 IC’s with A Board Containing 4 IC’s with Boundary Scan Boundary Scan

I n t e r n a l

L o g i c

I n t e r n a l

L o g i c

I n t e r n a l

L o g i c

I n t e r n a l

L o g i c

Boundary-scan cell Boundary-scan chain

System interconnect

SerialData in

SerialData out

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1149.1 Boundary-Scan Architecture 1149.1 Boundary-Scan Architecture

InternalLogic

Internal Registers

Bypass Register

Miscellaneous Register

Instruction Register

TAPController

1

1

1

Boundary-Scan Register (consists of boundary

Scan cells)

Test Data In (TDI)

Test Mode Select (TMS)Test Clock (TCK)

Test Reset (TRST*) (optional)

Test Data Out (TDO)

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Hardware Components of 1149.1Hardware Components of 1149.1 A test access port (TAP) consisting of :

4 mandatory pins: Test data in (TDI), Test data out (TDO), Test mode select (TMS), Test clock (TCK), and

1 optional pin: Test reset (TRST) A test access port controller (TAPC) An instruction register (IR) Several test data registers

A boundary scan register (BSR) consisting of boundary scan cells (BSCs)

A bypass register (BR) Some optional registers (Device-ID register, design-specifie

d registers such as scan registers, LFSRs for BIST, etc.)

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Basic OperationsBasic Operations1. Instruction sent (serially) through TDI into instruction

register.

2. Selected test circuitry configured to respond to the instruction.

3. Test pattern shifted into selected data register and applied to logic to be tested

4. Test response captured into some data register

5. Captured response shifted out; new test pattern shifted in simultaneously

6. Steps 3-5 repeated until all test patterns are applied.

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Boundary-Scan Circuitry in A Chip Boundary-Scan Circuitry in A Chip

TDOTDI

TRST*TMSTCK

Design-Spec. Reg.

Device-ID Reg.

Boundary Scan Reg.

Bypass Reg. (1-bit)


IR decode

Data Register

MUX

M U X

0

11D

ENTAP

ClockDR, ShiftDR, UpdateDR3

Reset*

ClockIR, ShiftIR, UpdateIR

3

TAPC

SelectTCK Enable

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Data registersData registers Boundary scan register: consists of boundary

scan cells Bypass register: a one-bit register used to pass

test signal from a chip when it is not involved in current test operation

Device-ID register: for the loading of product information (manufacturer, part number, version number, etc.)

Other user-specified data registers (scan chains, LFSR for BIST, etc.)

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A Typical Boundary-Scan Cell (BSC)A Typical Boundary-Scan Cell (BSC)

D D

ClockDR UpdateDR

MUX

SI

IN

ShiftDR

MUX

OUT

SO

Mode

R1 R2

Q Q

0

1

0

1

Operation modes Normal: IN OUT (Mode = 0) Shift: TDI ... IN OUT ... TDO (ShiftDR = 1, ClockDR) Capture: IN R1, OUT driven by IN or R2 (ShiftDR = 0, ClcokDR) Update: R1 OUT (Mode_Control = 1, UpdateDR)

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TAP ControllerTAP Controller

A finite state machine with 16 states Input: TCK, TMS Output: 9 or 10 signals included ClockDR,

UpdateDR, ShiftDR, ClockIR, UpdateIR, ShiftIR, Select, Enable, TCK and TRST* (optional).

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State Diagram of TAP ControllerState Diagram of TAP Controller

Test-Logic-Reset1

Run-Test/Idle

00

Select-DR-Scan1

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

0

0

1

0

1

10

1

1

0

1

0

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

0

0

1

0

1

10

1

1

0

1

0

11 0 0

Control of instruction registerControl of data registers

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Main functions of TAP controllerMain functions of TAP controller

Providing control signals to Reset BS circuitry Load instructions into instruction register Perform test capture operation Perform test update operation Shift test data in and out

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States of TAP ControllerStates of TAP Controller Test-Logic-Reset: normal mode Run-Test/Idle: wait for internal test such as BIST Select-DR-Scan: initiate a data-scan sequence Capture-DR: load test data in parallel Shift-DR: load test data in series Exit1-DR: finish phase-1 shifting of data Pause-DR: temporarily hold the scan operation (e.g., allow the bus

master to reload data) Exit2-DR: finish phase-2 shifting of data Update-DR: parallel load from associated shift registers

Note: Controls for IR are similar to those for DR.

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Instruction SetInstruction Set BYPASS

Bypass data through a chip

SAMPLE Sample (capture) test data into BSR

PRELOAD Shift-in test data and update BSR

EXTEST Test interconnection between chips of board

Optional INTEST, RUNBIST, CLAMP, IDCODE, USERCODE, HIGH-Z, etc.

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Execution of BYPASS InstructionExecution of BYPASS Instruction

InternalLogic

BypassRegister(1 bit)


TAP Controller

TDI TDO

TMSTCK

TRST

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Execution of SAMPLE InstructionExecution of SAMPLE Instruction

R1 R2R1 R2

Internal Logic

TDI TDO

Output

Input

SAMPLEMUX

MUX

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Execution of PRELOAD InstructionExecution of PRELOAD Instruction

R1 R2R1 R2

Internal Logic

TDI TDO

Output

Input

PRELOADMUX

MUX

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Execution of EXTEST Instruction (1/3)Execution of EXTEST Instruction (1/3)

Shift-DR (Chip1)

Internal Logic

Registers

TAP controller

TDI TDO

Internal Logic

Registers

TAP controller

TDI TDO

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Update-DR (Chip1) Capture-DR (Chip2)

Internal Logic

Registers

TAP controller

TDI TDO

Internal Logic

Registers

TAP controller

TDI TDO

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Shift-DR (Chip2)

Internal Logic

Registers

TAP controller

TDI TDO

Internal Logic

Registers

TAP controller

TDI TDO


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Shift-DR

Internal Logic

Registers

TAP controller

TDI TDO

Execution of INTEST Instruction (1/4)Execution of INTEST Instruction (1/4)

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Update-DR

Internal Logic

Registers

TAP controller

TDI TDO


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Capture-DR

Internal Logic

Registers

TAP controller

TDI TDO


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Shift-DR

Internal Logic

Registers

TAP controller

TDI TDO


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Boundary Scan Description Boundary Scan Description Language (BSDL)Language (BSDL)

Now a part of IEEE 1149.1-2001 Purposes:

Provide standard description language for BS devices. Simplify design work for BS – automated synthesis is possible. Promote consistency throughout ASIC designers, device

manufacturers, foundries, test developers and ATE manufacturers.

Make it easy to incorporation BS into software tools for test generation, analysis and failure diagnosis.

Reduce possibility of human error when employing boundary scan in a design.

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Features of BSDLFeatures of BSDL Describes the testability features of BS

devices that are compatible with 1149.1. S subset of VHDL. System-logic and the 1149.1 elements that

are absolutely mandatory need not be specified. Examples: BYPASS register, TAP controller, etc.

Commercial tools to synthesize BSDL exist.

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Scan and BIST Support with Scan and BIST Support with Boundary ScanBoundary Scan

Scan path

logic

BISTController

Memory /Register file

Compressor

BISTDecoder

ScanDecoder Decoder

IR

TAP Controller

MUX TDObist_so

…

…

TDI

TCK

TMS

…

bist_si

bist_sel

mbistint_scan

scan_input

scan_en

scan_output

rst

clk

holdbist_en

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Ring architecture with shared TMS

TDI TCK TMS TDO

#1

TDI TCK TMS TDO

#2

TDI TCK TMS TDO

#N

TDI TDO TMS TCK

Bus master

Application chips

Bus Master for Chips with Bus Master for Chips with Boundary Scan (1/5)Boundary Scan (1/5)

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Ring architecture with separate TMS

TDI TCK TMS TDO

#1

TDI TCK TMS TDO

#2

TDI TCK TMS TDO

#N

Bus master

Application chips

TDI TDO

TMS1TMS2

TMSN TCK


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Star architecture

Bus master

TDI1TMS1

TCKTDO1

TDI2TMS2

TCKTDO2

TDI3TMS3

TCKTDO3

Ring1

Ring2

Ring3


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Multi-drop architecture

Bus master

TDITMSTCKTDO

Test Bus

Multi-DropDevice

Multi-DropDevice

Multi-DropDevice


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Hierarchical architecture

1149.1


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Boundary scan for advanced networks – Boundary scan for advanced networks – 1149.61149.6 Rationale Analog test receiver Digital driver logic Digital receiver logic Test access port for 1149.6

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RationaleRationale

Advanced signaling techniques are required for multiple-mega-per-second I/O. Differential or AC-coupling networks

Coupling capacitor in AC-coupled networks blocks DC signals.

DC-level applied during EXTEST may decay to undefined logic level.

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Capturing AC-Coupled Signal with 1149.1Capturing AC-Coupled Signal with 1149.1

TX

R X

U pda te -D R

C ap tu re -D R

C U

TX R X

C U

V T

V H

V L

V H

V L

TX

R X

U pda te -D R

C aptu re -D R

C U

TX R X

C U

V T

V H

V L

V H

V L

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1149.1 Configuration for Differential 1149.1 Configuration for Differential Signaling Signaling

C U

TX RX

C U

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Analog Test Receiver Response to AC Analog Test Receiver Response to AC and DC-Coupled Signalsand DC-Coupled Signals

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Digital Driver Logic Digital Driver Logic

0

1

0

1 C U

S h iftD RS h ift in

C lockD R

U pda teD R

M ode

S h ift ou t

D a ta

M iss ion

0

1

A C M ode

TC K

R TI S ta teA C Tes t S igna l

(d is tribu ted to a ll A Cdrive rs )

T ra in /P u lse

M ode A C M ode Tra in /P u lse

1149 .1 B ypass

1149 .1 E xtes t

E xtes t_P u lse

E xtes t_Tra in

0 X X

1 0 X

1 1 0

1 1 1

A C Test S igna l G ene ra to r(nea r TA P C on tro lle r)

A C Tes t S igna lInse rtion , pe r d rive r

D Q

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Digital Receiver LogicDigital Receiver Logic

VHyst

VHyst

Pad RF

CF

VT

DC

AC

EXTEST_PULSE or

EXTEST_TRAIN Selected

HystMemClear

Set

Shift In

Init_Memory (common to all test receivers)

CaptureFF

UpdateFF

ClockDR

0

1

ShiftDR

Shift Out

UpdateDR

0

1

Optional, Required for Observe-and-Control Capabilty on Single-Ended Inputs Only

Boundary Register

Cell

TestReceiver

D

EXTEST_PULSE, EXTEST_TRAIN:

Init_Memory Latch Q

NOTE: The generated clock (Init_Memory) shown is suitable for rising edge-sensitive behavior only.

TCK

Capture-DR Shift_DR

TAP State

TMS

TCK

EXTEST:

Init_Memory

TAP State

Clock_DR

Exit*-DR Update_DR

May be located near TAP controller

TCK

Capture-DREXTEST

EXTEST_TRAINEXTEST_PULSE

Exit1-DRExit2-DRQ

Q SET

CLR

D

L

DQ

G

TMS

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Example of Modification on 1149.1 TAP – Example of Modification on 1149.1 TAP – Driver Behavior During EXTEST_PULSEDriver Behavior During EXTEST_PULSE

TC K

C ap tu re P o in tU pda te P o in t

(TA P S ta te )

Tes t-Log ic R ese t S e lec t-D R C ap tu re -D R

A C Tes t S igna l

D a ta Inve rted D a ta D a ta

P u lse W id th

U pda te -xR R un-Tes t/Id le

A C P in D rive r

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Embedded Core Test Standard - 1500Embedded Core Test Standard - 1500

SOC test problems Overall architecture Wrapper components and functions Instruction set Core test language Core test supporting and system test

configurations Hierarchical test control and plug & play

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Mixing technologies: logic, processor, memory, analog

Need various DFT/BIST/other techniques Deeply embedded cores

Need Test Access Mechanism

Hierarchical core reuse Need hierarchical test management

Different core providers and SOC test developers Need standard for test integration

IP protection/test reuse Need core test standard/documentation

SOC Test Problems/Requirements (1/2)SOC Test Problems/Requirements (1/2)

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Higher-performance core pins than SOC pins

Need on-chip, at-speed testing External ATE inefficiency

Need “on-chip ATE” Long test application time

Need parallel testing or test scheduling

Test power must be considered Need lower power design or test scheduling

Testable design automation Need new testable design tools and flow

SOC Test Problems/Requirements (2/2)SOC Test Problems/Requirements (2/2)

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A System Overview of IEEE 1500 A System Overview of IEEE 1500 Standard Standard

Core N

1500 Wrapper

WIR

Core 1

1500 Wrapper

WIR

Chip I/O

TAM-out

WSI WSO WSI WSO

Wrapper Serial Port (WSP)

User-Defined Parallel TAM

TAMsource

TAMsink

System Chip

TAM-in TAM-out

Chip I/O

Wrapper Serial Controls (WSC)

1 1 N N

TAM-in

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Test Interface of A Core Wrapper Test Interface of A Core Wrapper

Core

WSC

WPI WPO

WPC

WSI WSOWrapper

Wrapper Serial Control

Wrapper Serial Input

Wrapper Serial Output

Wrapper Parallel Control

Wrapper Parallel Input

Wrapper Parallel Output

Required WrapperSerial Port (WSP)

Optional WrapperParallel Port (WPP)

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Serial Test Circuitry of 1500 for a Core Serial Test Circuitry of 1500 for a Core

Core

WBR

WBY

WBR

WIR

FI

FO

FO

FI

WRCK

WSI

WSO

1 1

TestEnable

WFO

WFI

WFI

WFO

WBCCFO

CTO

CTI

CFIWBC

CFO

CTI

CTO

CFI

WBR

WBR

FI

FIFO

FO

User-defined WPP = WPI +WPO + WPC

WRSTNSelectWIR

CaptureWRShiftWR

UpdateWR

TransferDR...

{

AUXCKn

WSC

Note: WSP = WSI+WSO+WSC

{ {

CTI: Cell Test InputCTO: Cell Test outputCFI: Cell Functional InputCFO: Cell Functional OutputFI: Functional InputFO: Functional Output

WPP: Wrapper Parallel PortWSC: Wrapper Serial ControlWSI: Wrapper Serial InputWSO: Wrapper Serial OutputWSP: Wrapper Series Port

WFI: Wrapper Functional InputWFO: Wrapper Functional OutputWBC: Wrapper Boundary Cell WBR: Wrapper Boundary RegisterWBY: Wrapper Bypass RegisterWIR: Wrapper Instruction Register

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Wrapper ComponentsWrapper Components Wrapper series port (WSP)

Wrapper series input (WSI), Wrapper series output (WSO), Wrapper series control (WSC)

Wrapper parallel port (WPP) (optional) Wrapper parallel input (WPI), Wrapper parallel output

(WPO), wrapper parallel control (WPC)

Wrapper instruction register (WIR) Wrapper bypass regiester (WBY) Wrapper data register (WBR)

Consists of wrapper boundary cells (WBC’s)

Core data register (CDR) (optional)

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Wrapper Series Control (WSC) signals Wrapper Series Control (WSC) signals WRCK: wrapper clock terminal AUXCKn: Optional auxiliary clocks, where n is t

he number of the clocks. WRSTN: wrapper reset SelectWIR: determine whether WIR is selected CaptureWR: enable Capture operation ShiftWR: enable Shift operation UpdateWR: enable Update operation TransferDR: enable Transfer operation

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Wrapper Instruction RegisterWrapper Instruction Register

Decode & Update

FFn-1FF1FF0

(Optional) Parallel Capture Data

ShiftWR

WSI

CaptureWR

SelectWIR

UpdateWR

WRSTN

WRCK

Serial Shiftpath

DR_Select[n:0]

WBY_Cntrl

WBR_Cntrl

WDR_Cntrl

CDR_Cntrl

Core_Cntrl

WSO

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Wrapper Boundary Register (WBR)Wrapper Boundary Register (WBR)

Consists of Wrapper boundary cells (WBC’s) WBC

Terminals: Cell functional input (CFI), cell functional output (CFO), cell test input (CTI), cell test output (CTO)

Functional modes: Normal, inward facing, outward facing, nonhazardous (safe).

Operation events: Shift, capture, update, transfer, apply.

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Events of WBR (WBC)Events of WBR (WBC) Shift: data advance one-bit forward on WBR’s shif

t path Capture: data on CFI or CFO are captured and st

ored in WBC Update: data stored in WBC’s shift path storage a

re loaded into an off-shift-path storage of the WBC

Transfer: move data to the storage closest to CTI or one bit closer to CTO

Apply: a derivative event inferred from other events to apply data to functional inputs of cores or functional outputs of WBR

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Four Symbols Used in Bubble Diagrams for Four Symbols Used in Bubble Diagrams for WBC’sWBC’s

Storageelement

Datapath

Decisionpoint

Data pathsfrom a source

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Some Typical WBC’s Represented by BuSome Typical WBC’s Represented by Bubble Diagramsbble Diagrams

CFI

SC

CTI

CFO

CTO

(a) WC_SD1_CII (b) WC_SD2_CIO

SCT

ST

CFOCFI

CTI

CTO

SC

U

CFO

CTO

CTI

(c) WC_SD2_CII (d) WC_SD1_CII_UD

ST

SC

CFOCFI

CTI

CTO

ST

ST

CTI

UCF

CFI CFO

CTO

SC

ST

U

N number of shift storage

elements

CTO

CTI

CFICFO

(e) WC_SD2_CIU_UF (f) WC_SDn_CII_UD

S

CTI

CFICFO

CTO

(g) WC_SD1_CN (h) WC_SD1_CBI_UD

SC

U

CFO

CFICTO

CTI

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Example 10.1 - WIR Interface of WBY, WExample 10.1 - WIR Interface of WBY, WBR WDR(s) and CDR(s)BR WDR(s) and CDR(s)

WIR Circuitry

WBY_CntrlWBR_CntrlDR_Select[n:0]

CDR_CntrlWDR_CntrlCore_Cntrl

WSI

{SelectWIR,WRCK,

WRSTN,CaptureWR,

ShiftWR,UpdateWR}

WBR

CDR k

WBY

WDR k

DR_WSO

DR_Select[n:0]

SelectWIR

WIR_WSO

WSO

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Example 10.2 - Schematic Diagram of Example 10.2 - Schematic Diagram of WBC WC_SD2_CIOWBC WC_SD2_CIO

CFO

MODE

D2

D1

WRCKIO_FACE

CAPT

CFI

XFER

CTISHIFT WRCK

CTO

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WSI WSO

Enabled

Core

FO

FI

WSC

FO

FI

WBR

WBR

Normal Mode

Normal Mode

Normal Mode

Normal Mode

WIR

Bypass

WS_BYPASS InstructionWS_BYPASS Instruction

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WS_EXTEST InstructionWS_EXTEST Instruction

WSO

Disabled

Core

WSC

WBR

WBR

UDL

UDL

UDL

UDL

WIR

BypassWSI

FO

FI FO

FI

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WP_EXTEXT InstructionWP_EXTEXT Instruction

WSI WSO

Disabled

Core

WSC

WPC

WBR

UDL

UDL

WBR

WBR

WBR

UDL

UDL

WIR

Bypass

FO

FI FO

FI

WPI

WPI

WPI

WPI

WPO

WPO

WPO

WPO

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WS_SAFE InstructionWS_SAFE Instruction

WSO

Disabled

Core

FO

FI

WSC

FO

FI

WBR

WBR

Safe States

Safe States

WSIWIR

Bypass

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WS_PRELOAD InstructionWS_PRELOAD Instruction

WSI WSO

Enabled

Core

FO

FI

WSC

WPC

FO

FI

Normal Mode

Normal Mode

WBR

Normal Mode

Normal Mode

WBR

WBR

WBR

WIR

Bypass

WPI

WPI

WPI

WPI

WPO

WPO

WPO

WPO

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WP_PRELOAD InstructionWP_PRELOAD Instruction

WSI WSO

Disabled

Core

FO

FI

WSC

FO

FI

WBR

WBR

Preloaded States

Preloaded States

WIR

Bypass

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WS_CLAMP InstructionWS_CLAMP Instruction

WSC

Core

FO

FI FI

FO

WSI WSO

WBR

WBR

WIR

Bypass

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WS_INTEST InstructionWS_INTEST Instruction

WSC

Core

FO

FI FI

FO

WSI WSO

WBR

Internal Scan

WBR

WIR

Bypass

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WS_INTEST_SCAN InstructionWS_INTEST_SCAN Instruction

WSO

Enabled

Core

FO

FI

WSC

FO

FI

WBR

Normal Mode

Normal Mode

Normal Mode

Normal Mode

WIR

BypassWSI

WBR

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General Parallel TAM StructureGeneral Parallel TAM Structure

Core Core Core

WPP WPP WPP

WSP WSP WSP

Wrapper Wrapper Wrapper

User Defined Test Access Mechanisms (TAM)

WPI WPC WPO WPI WPC WPO WPI WPC WPO

ENA ENA ENA

WSC

WSI WSO

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Multiplexed TAM Architectures Multiplexed TAM Architectures

Core Core Core

WPP WPP WPP

WSP WSP WSP


Multiplexed TAM

WPIWPC

WPO

WSC

WSI WSO

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Core Core Core

WPP WPP WPP

WSP WSP WSP


Daisychained TAM

WPI

WPC

WPO

WSC

WSI WSO

Daisy chained TAM ArchitectureDaisy chained TAM Architecture

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Core Core Core

WPP WPP WPP

WSP WSP WSP


Direct Access TAM

WPIWPC WPO

WSC

WSI WSO

WPO

WPI

WPC

WPO

WPI

WPC

Direct Access TAM ArchitecturesDirect Access TAM Architectures

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Core Core Core

WPP WPP WPP

WSP WSP WSP


Local TAM Controllers

WSC

WSI WSO

Controller Controller Controller

Local Controller TAM ArchitecturesLocal Controller TAM Architectures

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Core Access Switch (CAS) ArchitectureCore Access Switch (CAS) Architecture

CORE 1 CORE 2 CORE 3 CORE 4 CORE 5

CAS 1 CAS 2 CAS 3 CAS 4 CAS 5

TestController

N

P

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Different Functional Modes of CASDifferent Functional Modes of CAS

Configuration mode

Instructionconfig config

Bypass modeTest mode

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Various Types of Test Supporting Various Types of Test Supporting Using CAS StructureUsing CAS Structure

CAS 1( N/P )

SCAN

BIST

CORE CAS

core

core

core

core

CAS

CASCASso

urce

SCAN

SCAN

SCAN

Test Controller

CAS 2( N/1 )

CAS 3( N/1 )

CAS 4( N/P )

sink

NP 1

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A Hierarchical Test Architecture A Hierarchical Test Architecture Supporting Plug & Play FeatureSupporting Plug & Play Feature

1500Cores

(CTAG)

1149.1Cores

(JTAG)

Hierarchicalcores

(H-Cores)

CTC

TAM

TCS HCS

TDI TDO

CHIP

TAM-BUS

Glue logic Glue logic

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Detailed I/O and CTC of The Detailed I/O and CTC of The Hierarchical Test ArchitectureHierarchical Test Architecture

Programble Switch

Hierarchical Test ControllerTAP

CTC(Central Test Controller)

TMS

TRST

TCK

H-TDI

H-TMS

H-UPD

H-SFT

H-ENA

H-TDO

TCS (TAP Control Signals) HCS (Hierarchical Control Signals)

TDI

TDO

TAM(Test Access Mechanism)TAM input TAM output

JTAGCore

TAP

functionaloutput

functionalinputHierarchical

Core

TAM-I

CTC

functionaloutput

functionalinputCTAG

Core

TAM-I

WIR

functionaloutput

functionalinput

TDI TDO TDI TDO TDI TDO

TCS

HCSWCS TCS

I CWSR

I CWSR

TDI TDO

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Core 1(CTAG) Core 2

(BISTed RAM)

Core 5(JTAG)

TAM 1

HTM 1

MBI

WCI WCI HTM 2

TAM 2

TAP

TAM input TAM output

Core 3(CTAG)

Core 4(CTAG)

WCI WCI

TDI_UP TMS_UP TRST_UP TCK_UP TDO_UP

TDI_C PCS TDI_H TCS_DN TDO_H TDO_C

TDO_CTDO_HTDI_HTDI_C

PCS

TDI_UP TCS_UP TDO_UP

A Hierarchical Test Architecture with I/Os A Hierarchical Test Architecture with I/Os Compatible to 1149.1Compatible to 1149.1

EE14181


Comparison between 1149.1 and 1500Comparison between 1149.1 and 1500 1149.1 1500

Purpose Board-level Core-basedParallel Mode No Yes

Extra Data/Control I/Os

Mandatory: TDI, TDO, TMS, TCK

Optional: TRST

Mandatory: WSI, WSO, 6 WSC Optional: TransferDR, WPP, AU

XCKn(s)FSM Yes No

Transfer Mode No YesLatency between

operationsYes No

Mandatory Instructions

EXTEST, BYPASS, SAMPLE, PRELOAD

WS_EXTEST, WS_BYPASS, one Wx_INTEST, WS_PRELOAD (cond. required)

chapter 10 boundary scan and core-based testing

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