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Boundary Scan Testing

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Page 1: [Kenneth P. Parker] the Boundary-Scan Handbook
Page 2: [Kenneth P. Parker] the Boundary-Scan Handbook

THE BOUNDARY-SCAN HANDBOOKSECOND EDITION

Analog and Digital

Page 3: [Kenneth P. Parker] the Boundary-Scan Handbook

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Page 4: [Kenneth P. Parker] the Boundary-Scan Handbook

THE BOUNDARY-SCAN HANDBOOKSECOND EDITION

Analog and Digital

by

Kenneth P. ParkerHewlett-Packard Company

KLUWER ACADEMIC PUBLISHERSNEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

Page 5: [Kenneth P. Parker] the Boundary-Scan Handbook

eBook ISBN: 0-306-47656-8Print ISBN: 0-7923-8277-3

©2002 Kluwer Academic PublishersNew York, Boston, Dordrecht, London, Moscow

Print ©1998 Kluwer Academic Publishers

All rights reserved

No part of this eBook may be reproduced or transmitted in any form or by any means, electronic,mechanical, recording, or otherwise, without written consent from the Publisher

Created in the United States of America

Visit Kluwer Online at: http://kluweronline.comand Kluwer's eBookstore at: http://ebooks.kluweronline.com

Dordrecht

Page 6: [Kenneth P. Parker] the Boundary-Scan Handbook

Dedication

This book is dedicated to the memory of an Uncle for whom I was namesake.

Kenneth Fredric Parker, 1912-1998

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TABLE OF CONTENTSList of Figures xiiiList of Tables xviiiList of Design-for-Test Rules xixPreface to the First Edition xxiPreface to the Second Edition xxiiiAcknowledgement xxv1 Boundary-Scan Basics and Vocabulary 1

22478

10162021272930313233333435353636373839393940414242434546

1.1 Digital Test Before Boundary-Scan1.1.11.1.2

Edge-Connector Functional TestingIn-Circuit Testing

1.21.3

The Philosophy of 1149.1-1990Basic Architecture

1.3.11.3.21.3.31.3.41.3.51.3.61.3.71.3.8

The TAP ControllerThe Instruction RegisterData RegistersThe Boundary RegisterOptimizing a Boundary Register Cell DesignArchitecture SummaryField-Programmable IC DevicesBoundary-Scan Chains

1.4 Non-Invasive Operational Modes1.4.11.4.21.4.31.4.41.4.5

BYPASSIDCODEUSERCODESAMPLEPRELOAD

1.5 Pin-Permission Operational Modes1.5.11.5.21.5.31.5.41.5.51.5.6

EXTESTINTESTRUNBISTHIGHZCLAMPExceptions Due to Clocking

1.61.71.8

ExtensibilitySubordination of IEEE 1149.1Costs and Benefits

1.8.11.8.21.8.3

CostsBenefitsTrends

1.9 Other Testability Standards

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2 Boundary-Scan Description Language (BSDL) 492.1 The Scope of BSDL 52

2.1.12.1.22.1.3

Testing 52Compliance Assurance 53Synthesis 55

2.22.3

Structure of BSDL 57Entity Descriptions 61

2.3.12.3.22.3.32.3.42.3.52.3.62.3.72.3.82.3.92.3.102.3.112.3.122.3.132.3.142.3.152.3.162.3.17

Generic Parameter 62Logical Port Description 62Standard USE Statement 63Use Statements 64Component Conformance Statement 64

656667686970717275767777

Device Package Pin MappingsGrouped Port IdentificationTAP Port IdentificationCompliance Enable DescriptionInstruction Register DescriptionOptional Register DescriptionRegister Access DescriptionBoundary-Scan Register DescriptionRUNBIST Execution DescriptionINTEST Execution DescriptionUser Extensions to BSDLDesign Warnings

2.4 Some advanced BSDL Topics 782.4.12.4.2

Merged Cells 7880Asymmetrical Drivers

2.52.6

BSDL Description of 74BCT8374 8084Packages and Package Bodies

2.6.12.6.22.6.32.6.42.6.5

STD_1149_1_1999 85899199

Cell Description ConstantsBasic Cell Definitions BC_0 to BC_7User-Defined Boundary CellsDefinition of BSDL Extensions 100

101103

2.72.8

Writing BSDLSummary

3 Boundary-Scan Testing 1053.1 Basic Boundary-Scan Testing 106

3.1.13.1.23.1.33.1.43.1.53.1.6

The 1149.1 Scanning Sequence 106112113114116118

Basic Test AlgorithmThe “Personal Tester” Versus ATEIn-Circuit Boundary-ScanIC TestIC BIST

viii

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3.2 Testing with Boundary-Scan Chains 1193.2.13.2.23.2.33.2.43.2.5

1149.1 Chain Integrity 119122136138141142144

Interconnect TestConnection TestsInteraction TestsBIST and Custom Tests

3.33.4

Porting Boundary-Scan TestsSummary

4 Advanced Boundary-Scan Topics 1454.14.24.34.44.54.64.74.84.94.10

DC Parametric IC Tests 146147150151154155157159160163

Sample Mode TestsConcurrent MonitoringNon-Scan IC TestingNon-Digital Device TestingMixed Digital/Analog TestingMulti-Chip Module TestingFirmware Development SupportIn-System ConfigurationHardware Fault Insertion

5 Design for Boundary-Scan Test 1675.1 Integrated Circuit Level DFT 169

5.1.15.1.25.1.35.1.45.1.55.1.65.1.75.1.85.1.95.1.10

TAP Pin Placement 169170174175176177178178179180

Power and Ground DistributionInstruction Capture PatternDamage Resistant DriversOutput PinsBidirectional PinsPost-Lobotomy BehaviorIDCODEsUser-Defined InstructionsCreation and Verification of BSDL

5.2 Board-Level DFT 1825.2.15.2.25.2.35.2.45.2.55.2.65.2.75.2.8

Chain Configurations 182185186187188190190192

TCK/TMS DistributionMixed Logic FamiliesBoard Level ConflictsControl of Critical NodesPower DistributionBoundary-Scan MastersPost-Lobotomy Board Behavior

5.3 System-Level DFT 1935.3.15.3.2

The MultiDrop Problem 194195Coordination with Other Standards

5.4 Summary 195

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6 Analog Measurement Basics 1976.1 Analog In-Circuit Testing 197

6.1.16.1.26.1.36.1.4

Analog Failures 198200204206

Measuring an ImpedanceErrors and CorrectionsMeasurement Hardware

6.2 Limited Access Testing 2116.2.16.2.26.2.3

Node Voltage Analysis 212Testing With Node Voltages 213Limited Access Node Voltage Testing 215

6.3 The Mixed-Signal Test Environment 2176.4 Summary 220

7 IEEE 1149.4 Analog Boundary-Scan 2217.1 1149.4 Vocabulary and Basics 222

7.1.17.1.27.1.37.1.4

The Target Fault Spectrum 223Extended Interconnect 223Digital Pins 225Analog Pins 226

7.2 General Architecture of an 1149.4 IC 2277.2.17.2.27.2.37.2.47.2.5

Silicon “Switches” 229The Analog Test Access Port (ATAP) 230The Test Bus Interface Circuit (TBIC) 231The Analog Boundary Module (ABM) 236The Digital Boundary Module (DBM) 242

7.3 The 1149.4 Instruction Set 2437.3.17.3.27.3.37.3.47.3.57.3.6

The EXTEST Instruction 244The CLAMP Instruction 247The HIGHZ Instruction 247The PROBE Instruction 247The RUNBIST Instruction 248The INTEST Instruction 248

7.4 Other Provisions of 1149.4 2507.4.17.4.27.4.37.4.4

Differential ATAP Port 250Differential I/O 251Partitioned Internal Test Buses 253Specifications and Limits 256

7.5 Design for 1149.4 Testability 2577.5.17.5.27.5.3

Integrated Circuit Level 257Board Level 259System Level 260

7.67.7

Summary 261262Epilog: What Next for 1149.1/1149.4?

x

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APPENDIX A: BSDL Syntax Specifications 263A.1A.2A.3A.4A.5

Conventions 263264267269273

Lexical elements of BSDLNotes on syntax definitionBSDL SyntaxUser Package Syntax

Bibliography 275

281Index

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List of FiguresFigure 1-1: In-Circuit test setup with full nodal access. The component under test

may be embedded within a board and connected to other components. 5Figure 1-2: Cutaway drawing of a board resting on top of an In-Circuit, vacuum-

actuated test fixture: the “bed of nails.” The module interface pins are themechanical interface to the ATE pin electronics, which are placed very close toreduce path lengths. 6

Figure 1-3: General, simplified architecture of an 1149.1 compliant IntegratedCircuit. 9

Figure 1-4: State transition diagram of the sixteen-state TAP controller. 11Figure 1-5: Architecture detail of a typical Boundary-Scan register with shift and

parallel hold ranks. 17Figure 1-6: Example of an instruction register cell design. The expanded cell shows

several control signals generated by the TAP state machine. 19Figure 1-7: A Typical Boundary Register Cell. 22Figure 1-8: A Bidirectional pin with separate input and output Boundary Register

cells. 23Figure 1-9: A Bidirectional pin served by a reversible Boundary Register cell. 25Figure 1-10: Compensating inversions in an input Boundary Register cell that

monitors an inverting input buffer. 26Figure 1-11: Compensating inversion in an output Boundary Register cell connected

to an inverting output buffer. 26Figure 1-12: Two logical symbols for typical boundary cells, one with an Update

(UPD) flip-flop (A) and one without (B). 27Figure 1-13: An example (adapted from [Whet95]) of an output cell design that

eliminates both a discrete register stage and a multiplexer delay. 28Figure 1-14: Block Diagram of a Boundary-Scan IC. 29Figure 1-15: A field-programmable component with Boundary-Scan hard-wired into

its I/O Blocks (IOBs). Each IOB starts out with bidirectional support for acomponent pin, but subsequent programming may reduce each to supportinginput or output only. 31

Figure 1-16: A simple chain of Boundary-Scan ICs. 32Figure 1-17: Code bit allocation in a Device Identification Register accessed by

IDCODE. 34Figure 1-18: Observe-Only Boundary Register cell for inputs. 40Figure 1-19: Product introductions by Companies X and Y, and their relative

performance. 44Figure 2-1: BSDL use model within or outside of a VHDL environment. 51Figure 2-2: BSDL used as a test driver. 53Figure 2-3: A process for checking the compliance of an IC with the Standard. 54Figure 2-4: An 1149.1 synthesis system that both creates and uses BSDL. 56Figure 2-5: The relationship of a BSDL entity to the standard package and package

body. 59Figure 2-6: Candidate for merged cell design. 78Figure 2-7: Design with input and control cells merged. 79Figure 2-8: A design illustrating several merged cell situations. 81Figure 2-9: Texas Instruments 74BCT8374 Octal D Flip-Flop with Boundary-Scan. 82

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Figure 2-10: An abstraction of a Boundary Register cell showing capture data sources.90

Figure 2-11: Cell architecture BC_1, a basic but very flexible design. 92Figure 2-12: Cell architecture BC_2. This cell can capture its own Update latch

content. 93Figure 2-13: Cell architecture BC_3, an input cell with no Update latch. 94Figure 2-14: Cell architecture BC_4, a cell with no Update latch and no series

multiplexer. 95Figure 2-15: Cell architecture BC_5, a control cell that can support HIGHZ-type

behavior. 95Figure 2-16: Cell architecture BC_7 (see the circuitry in the dotted line box) which

supports bidirectional data flow. 97Figure 2-17: A cell that captures a constant 1 during EXTEST. 99Figure 3-1: Side view of a Surface-Mount IC soldered to a board. An open and a short

are pictured. The poor quality joint will be invisible to electrical test methods,including Boundary-Scan. 106

Figure 3-2: TAP Controller state diagram showing path taken to shift an N-bitinstruction into the Instruction Register. 108

Figure 3-3: The newly loaded instruction is activated when UPDATE-IR is passed,selecting a new data register targeted between TDI and TDO when we enter theData Column of the state diagram. 109

Figure 3-4: Sequence of states traversed to capture data and shift it out while at thesame time entering new data. 110

Figure 3-5: Completing a data shifting operation and updating the parallel hold portionof a data register. 111

Figure 3-6: An IC undergoing an INTEST function while loaded on a board. 117Figure 3-7: A chain that has just passed CAPTURE-IR, loading all Instruction

Registers with “01”. 120Figure 3-8: A Boundary-Scan chain of ICs with four interconnect nodes. 123Figure 3-9: Interconnect test drives unique patterns assigned to each node from drivers

to receivers. A short is shown that creates a Wired-OR result. 124Figure 3-10: An interconnect open that prevents driven data from reaching one of two

receivers on a node. This fact can help a diagnostic isolate the location of theopen. 125

Figure 3-11: Simple interconnect test showing STVs (horizontal patterns) for 4 nodes.The columns are PTVs and represent the data as transmitted at each UPDATE-DRstate. Note two nodes are bussed. 126

Figure 3-12: Three examples of bus wire driver opens not detected by interconnectshorts test. 132

Figure 3-13: Control cell fanout combined with board topology that results inundetected opens. 133

Figure 3-14: Parallel testing of two bussed nodes. 134Figure 3-15: A case where four buses containing different numbers of drivers are

tested in parallel. 135Figure 3-16: A circuit where not all Boundary-Scan pins can be tested via interconnect

test. 137Figure 3-17: Example of potential interactions between a Boundary-Scan node and

two non-scanned nodes. 138

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Figure 3-18: Boundary-Scan nodes B and C that can interact (by shorting) withnodes A, D or F. 139

Figure 3-19: Two cooperating components provide stimulus vectors and capture asignature response for data path logic. 141

Figure 3-20: Developing and porting a manually generated test for similarapplications. 142

Figure 3-21: Developing a Boundary-Scan test for similar applications. 143Figure 4-1: The analog testing subsystem of an IC tester is used to switch load and

test resources to measure analog parametric properties of an IC. 147Figure 4-2: A simple circuit and its timing diagram showing setup and hold times, and

the effects of system clock skew. 148Figure 4-3: Simple circuit showing the relationships between the system clock and

TCK during SAMPLE operation. 149Figure 4-4: Concurrent sampling of component I/Os during system diagnostics, with

sampled data compressed in a multiple-input signature analysis register (MISR).151

Figure 4-5: Testing a non-scan IC U7 with a combination of physical nails andBoundary-Scan pins. 152

Figure 4-6: A timing diagram that shows how Boundary-Scan resources must becoordinated with the resources of a host ATE system. 153

Figure 4-7: Shorted inputs on a NAND gate that may not be detectable when tested byordinary Boundary-Scan drivers. 154

Figure 4-8: A Boundary-Scan testable node that has a termination resistor to eliminatenoise. 154

Figure 4-9: A mixed digital/analog IC with the Boundary Register partitioning thedigital from the analog. 155

Figure 4-10: Two digital ICs that communicate by differential signaling, an analogtechnique. 156

Figure 4-11: Three examples of “unusual” differential signaling applications. 157Figure 4-12: Multi-Chip Module shown in cross section. This example shows a multi-

layer ceramic PGA made of multiple dielectric and metalization layers. Bare ICdie and other discrete components are mounted on the top surface. 158

Figure 4-13: Four macro states an FPGA/CPLD can be in and the transitionsbetween them. 162

Figure 4-14: A BC_1 Boundary Register cell modified to support fault insertion. 164Figure 5-1: Three pin layouts for TDI and TDO. 169Figure 5-2: An oscillograph of a Ground-Bounce induced clock cycle on TCK during

UPDATE-DR, measured at the package TCK pin referenced to componentground. 170

Figure 5-3: A high pincount IC with two 32-bit buses. 172Figure 5-4: The transition timing for activities on the two buses in Figure 5-3. 172Figure 5-5: Deliberately inserted delays in the Boundary Register control signal

paths can be used to distribute driver edge placements in time. 173Figure 5-6: A Boundary Register output cell design with the capability of monitoring

its driver output pad during EXTEST. 176Figure 5-7: A Siamese chain pair with common TCK and TMS signals, but

independent data paths. Any number of chains could be linked in parallel thisway. 183

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Figure 5-8: A Siamese chain pair with separate TMS lines, common TCK, and sharedboard-level TDI and TDO signals. 184

Figure 5-9: A simple chain with buffered TCK and TMS signals needed to avoidoverloading. 185

Figure 5-10: A low-skew clock buffer with 50% duty cycle preserved by utilizinginversion. 186

Figure 5-11: A simple Boundary-Scan chain containing ICs from different logicfamilies. Logic level conversion must be made between them. 186

Figure 5-12: A simple Boundary-Scan chain with a scanned level conversion interfacefor the parallel signals. Note the TCK and TMS lines must not have a scannedconversion. 187

Figure 5-13: A Boundary-Scan IC during test can set two normally complementaryoutputs to the same state, exciting conflicts in conventional ICs downstream. 188

Figure 5-14: Two Boundary-Scan nodes A and B need additional support from testerresources to enable proper testing. 189

Figure 5-15: A Boundary-Scan master interfaces between a microprocessor on oneside and 1149.1 on the other. (The directions of TDI and TDO are reversed,reflecting mastership.) 190

Figure 5-16: The 74ACT8997 Scan-Path linker IC linking simple chains A, B and C.Extra shift stages (marked with “*”) are inserted in the linked chain. These stagesare actually resident in the ‘8997, which itself appears in a normal 1149.1 form atthe end of the chain. 192

Figure 5-17: A system of several boards where each slot may accept several boardtypes, or not contain a board at all. A simple 1149.1 chain through these boardswould be broken at an empty slot. 194

Figure 6-1: A simple filter circuit and the actual circuit when parasitic capacitance isincluded. 198

Figure 6-2: Distribution of resistance values for a 4.7 Kohm resistors with atolerance of ±5%. 199

Figure 6-3: Measuring impedance with current source stimulus (A) and with voltagesource stimulus (B). 201

Figure 6-4: Measuring the impedance of a device on a board, connected to a silicondevice (A), and as seen by an ATE system (B). 202

Figure 6-5: Devices may be connected into networks providing parallel pathways forcurrents. 203

Figure 6-6: Some sources of error in an ATE setup for measuring a simpleimpedance. 205

Figure 6-7: Error impedances for a delta measurement (A) and a 6-wiremeasurement configuration (B). 206

Figure 6-8: An operational amplifier with feedback resistor used as a current meter.207

Figure 6-9: An operational amplifier setup to integrate a DC voltage V over time.207Figure 6-10: An operational amplifier setup for DC Dual Slope Integration. 208Figure 6-11: A dual slope integrator modified for AC measurements. 209Figure 6-12: A dual slope integrator used to measure a reactive component. 210Figure 6-13: Imaginary voltage waveform seen when measuring a capacitor. 211Figure 6-14: A simple network containing four resistors with full nodal access. 212Figure 6-15: Three-dimensional coordinates for graphing voltage differences. 213

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Figure 6-16: Three-dimensional plots where only some components are potentiallyfaulty at any one time. 214

Figure 6-17: Example circuit with access to node B removed. 215Figure 6-18: Projecting the shadow of a three-dimensional object onto a plane. 215Figure 6-19: Projections of failure spaces for R2 and R3 onto two of the voltage

planes. 216Figure 6-20: A mixed-signal printed circuit board. 217Figure 6-21: Key to the color photograph appearing on the cover of this book. 219Figure 6-22: Comparison of relative sizes of various features. 220Figure 7-1: A mixed-signal circuit with some possible defects. 223Figure 7-2: Examples of interconnections seen in mixed-signal circuits. 224Figure 7-3: General (minimal) architecture of an 1149.4 compliant IC. 227Figure 7-4: Detail of 1149.4 data register structure. 228Figure 7-5: Symbols used for opened and closed switches. 230Figure 7-6: Two or more 1149.4 ICs chained together. Note AT1 and AT2 are not

required to be connected in parallel as shown here. 231Figure 7-7: A TBIC switching structure inserted between AT1/AT2 and AB1/AB2.

Note one-bit digitized values of the AT1/AT2 signals are generated. 232Figure 7-8: Control structure for the switches shown in Figure 7-7. 234Figure 7-9: ABM design detail for a generalized analog function pin. 237Figure 7-10: Control structure for the switches shown in Figure 7-9. 239Figure 7-11: ESD protection circuit for a typical pin (A) and an 1149.4 pin (B). 242Figure 7-12: Alternative forms for the Boundary Register depending on whether

INTEST and/or RUNBIST are supported. 243Figure 7-13: An ATE system set up to utilize 1149.4 resources in an IC to measure

an externally connected impedance. 244Figure 7-14: Two measurements (A) and (B) used to find the voltage across Z for a

known current. 245Figure 7-15: Testing the digital core using INTEST. The analog core is not directly

tested. 249Figure 7-16: The analog core can be tested by patterns supplied at the D/A interface

and by signals supplied or controlled by the ABMs. 250Figure 7-17: An example implementation for differential inputs and outputs. 252Figure 7-18: Example of a TBIC structure with one extension (k=2). 253Figure 7-19: Control structure for the extended TBIC switches in Figure 7-18. 254Figure 7-20: A conventional transmission gate switch and a shunting “T” switch

structure that reduces coupling when the switch is off. 258Figure 7-21: Degrees of guarding between two ATn signals. 260

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List of TablesTable 1-1:Table 2-1:Table 2-2:Table 2-3:Table 2-4:Table 2-5:Table 2-6:Table 2-7:

Instruction Register operation during each TAP Controller state. 18637475899092

Pin types in a BSDL logical port description.Function symbols and their meanings.Definition of Disable Result field symbols.Definitions of allowable CELL_TYPE symbols.Definitions of CAP_DATA symbols.Mode signal assignment for cell BC_1 used in any context.Mode signal assignments for cell BC_2 in the context of use. See text for

an exception regarding INTEST. 93949698

Table 2-8:Table 2-9:Table 2-10:Table 3-1:

Mode signal assignment for cell BC_3.Mode signal assignments for cell BC_5.Mode signal assignments for BC_7 and its related BC_5 control cell.

Example data bits for chains shown in Figure 3-7. The bits for IC7 are thefirst to appear at TDO. 120

Table 3-2: Data streams from chains shown in Figure 3-7 with IC4 TDI and TDOshorted together, producing a Wired-AND. 122

Table 3-3: Sequential Test Vectors for a set of nodes. The rows are STVs and thecolumns are PTVs. 129

Table 3-4: A set of test PTVs (the columns) for interconnect test. (The Notes areexplained in the text.) 131

Table 3-5:Table 3-6:

Parallel test data for two bussed nodes. 134136Test data required for bus wires with different numbers of drivers.

Table 6-1: Node voltages for the circuit in Figure 6-14 when the component valuesvary from nominal. 212

Table 7-1: Comparison of parameters of various switches. 229Table 7-2: TBIC switching patterns (P0 through P9) for the switches shown in

Figure 7-7. 233234Table 7-3:

Table 7-4:Assignment of TAP instructions to mode signal values for the TBIC.Selection of TBIC switch patterns versus Boundary Register cell content.

235236Table 7-5: Logic equations for TBIC switch control.

Table 7-6: ABM switching patterns (P0 through P19) for the switches shown inFigure 7-9. 238

Table 7-7: Selection of ABM switch patterns versus Boundary Register cell content.240241Table 7-8: Logic equations for ABM switch control.

Table 7-9: TBIC extension switching patterns for the switches in Figure 7-18 forextension k. 254

Table 7-10: Selection of TBIC extension switch patterns versus Boundary Registercell content. 255

256Table 7-11: Logic equations for TBIC extension switch control.

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List of Design-for-Test RulesDFT-l: Place TDI and TDO pins on the end or the corner of a package to reduce

their likelihood of being bridged by solder. 170DFT-2: When possible, place power pins between TDI and TDO pins and other

signal pins. 170DFT-3: Ensure that worst-case switching of all IC drivers will not cause

power/ground transients that disrupt the operation of the TAP controller. 174DFT-4: Use higher-order bits of the Instruction Register capture pattern to

implement an informal ID code. The bits captured must be predictable “0”s and“l”s. 174

DFT-5: If design-dependent bits are captured in the Instruction Register, then anycombination of these bits should decode to the same operation. 175

DFT-6: Specify a tolerance period that drivers can withstand shorts to each other orto Power/Ground voltages. 176

DFT-7: Use self-monitoring output cells in the Boundary Register to improveBoundary-Scan diagnosis of shorts and opens. 177

DFT-8: For bidirectional pins, utilize a single-cell bidirectional design with a self-monitoring capability (such as cell BC_7). 178

DFT-9: When the 1149.1 logic executes a pin-permission instruction, the systemlogic should be forced into a state that prevents internal conflicts. 178

DFT-10: When the 1149.1 logic returns to non-invasive mode, the system logicshould stay in a state that will not conflict with board level signals. 178

DFT-l1: Use formal or informal ID codes to differentiate similar components orrevisions of components. 179

DFT-l2: Consider board-level testing problems that will require user-definedinstructions for their solutions, before final implementation of the 1149.1 logic.

180DFT-13: Verify that a BSDL description matches the silicon implementation of

1149.1 on every component. 181DFT-14: Before designing a board-level chain configuration, be sure that the

software that will be used during testing will support it. 184DFT-15: If there are field-programmable components in a chain of 1149.1 devices,

group them together in the chain order and place the group at either end of thechain. 184

DFT-l6: Utilize simple buffering (where possible) of the broadcast TCK/TMSsignals. Document the enabling and initialization requirements needed topreserve the 1149.1 protocol through TCK/TMS distribution. 185

DFT-17: Do not allow logical inversion in the TCK or TMS pathways. 186DFT-l8: When mixed logic families are used on a board, use scanned level

converters for the parallel signals and a non-scanned level conversion forTCK/TMS distribution. 187

DFT-l9: Check conventional portions of board circuitry that may be affected byBoundary-Scan test data for damaging conflicts that may be induced. Designdisable methods into these portions that will make them insensitive to thistesting activity. 188

DFT-20: Provide for the ability of a tester to disable conventional ICs whose outputswould otherwise conflict with nodes involved in Boundary-Scan tests. 189

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DFT-21: Provide for the ability of a tester to create strong drive values on weaknodes. 189

DFT-22: Make sure you locate and condition all Test Reset (TRST*) pins and allcompliance enable pins before executing any Boundary-Scan tests. 189

DFT-23: Design analog and digital subsystems such that the analog power can beshut off while Boundary-Scan testing is being done. 190

DFT-24: If a Boundary-Scan master is used in a board design, provide for testequipment access and control of the 1149.1 side of the master’s interface. 191

DFT-25: Ensure that a board, after any 1149.1 operation completes, will have safestates on all components and nodes. 193

DFT-26: Restrict 1149.1 implementations for system tests to simple systemarchitectures not containing a multidrop scheme. 195

DFT-27: Eliminate all common conductive paths between a system pin pad and theATn switches (SB1 and SB2). 258

DFT-28: Partition internal analog test buses (per section 7.4.3) to control on-chipcross talk, leakage, and capacitance. 258

DFT-29: Examine the location of switches for places where the circuit may besensitive to parasitic coupling and leakage. Use enhanced switch designs inthese areas to reduce these effects. 258

DFT-30: Analyse the layout of the ATn pins with respect to leakage and parasiticeffects between them and other signals. 259

DFT-31: Group compatible ATAPs together on common ATn buses. Be prepared toaccommodate more ATAP buses than there are TAP chains. 259

DFT-32: For ATn ports expected to be used in measurements of very highimpedances, place a board-level guard wire between the ATn signals. 260

DFT-33: Consider which of all ATn ports in a system will be needed for system testand provide access to them. 260

DFT-34: Consider if noise-immunity testing of differential signaling is required inthe system. 261

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Preface to the First EditionIn February of 1990, the balloting process for the IEEE proposed standard P1149.1was completed creating IEEE Std 1149.1-1990. Later that summer, in record time,the standard won ratification as an ANSI standard as well. This completed over sixyears of intensive cooperative effort by a diverse group of people who share a visionon solving some of the severe testing problems that exist now and are steadilygetting worse.

Early in this process, someone asked me if I thought that the P1149.1 effortwould ever bear fruit. I responded somewhat glibly that “it was anyone’s guess”.Well, it wasn’t anyone’s guess, but rather the faith of a few individuals in theproposition that many testing problems could be solved if a multifaceted industrycould agree on a standard for all to follow. Four of these individuals stand out; theyare Harry Bleeker, Colin Maunder, Rodham Tulloss, and Lee Whetsel. In that I amconvinced that the 1149.1 standard is the most significant testing development in thelast 20 years, I personally feel a debt of gratitude to them and all the people wholabored on the various Working Groups in its creation.

Why do I feel that 1149.1 is more significant than, say, In-Circuit testing (mid1970’s) or the various scan design approaches (mid 70’s again) such as LSSD?Surely these were very significant. However, the In-Circuit test technique, while thebasis of several trillion dollars worth of electronics production, is basically anAd-Hoc technique where the creation of a board test is only partially automatable andsubject to potentially severe debugging problems. In short, every new board is anadventure. The various scan approaches were very significant in their ability to lead tothe automation of test development. However, they were most successful when carriedout within large, vertically integrated electronics companies. As such, they did notcontribute to testing problem solutions of the electronics industry at large.

A major contribution of 1149.1 is that it provides a standard mechanism fordissimilar segments of the electronics industry to provide support for testingproblems without requiring them to understand all those various problems. As anexample, members of the IC Merchant community have virtually no concept of theproblems of board level testing; nor should they have to if they will provide the1149.1 capability in their devices.

Another major contribution of 1149.1 is revealed in the first half of its formalname, “Standard Test Access Port”. This “Port” is an I/O and control protocol assurely as RS-232 and Ethernet are. Combined with the open-ended extensibility ofthe standard, the 1149.1 standard is a gateway to new testing approaches.Built-In-Self-Test (BIST) immediately comes to mind. It is this particular focus thatsuddenly makes the standard attractive to IC designers. They say, “well, I am beingforced to add these four pins and some overhead, but, look at the neat things I couldthen do with it.” These “things” are not limited to the field of testing.

This book is aimed at professionals in the electronics industry who are concernedwith the practical problems of competing successfully in the face of rapid-firetechnological change. Since many of these changes affect our ability to do testing andhence cost-effective production, the advent of the 1149.1 standard is rightly lookedupon as a major breakthrough. However, there is a great deal of misunderstanding about

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what to expect of 1149.1 and how to use it. Because of this, this book is not a re-hash ofthe 1149.1 standard nor does it intend to be a tutorial on the basics of its workings. Thestandard itself should always be consulted for this, being careful to follow supplementsissued by the IEEE that clarify and correct it. Rather, this book attempts to motivateproper expectations and explain how to use the standard successfully.

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Preface to the Second EditionI was delighted when Carl Harris of Kluwer asked me to consider producing thissecond edition. This indicated that he believed 1149.1 and the newly emerging1149.4 standards are of continuing interest to the engineering profession.

IEEE standards, when embraced by practicing engineers, are living entities thatgrow and change quickly. That justifies this edition, but also should serve as awarning that the material in this book may be superceded by upcoming changes inthe standards. Always consult the most recent editions of the standards themselvesfor information needed for implementation. This book is intended to describe thesestandards in simple English rather than the strict and pedantic legalese encounteredin the standards. After reading this book, it is my hope the reader will find it easier tofollow the course of the standards themselves.

Since the first edition of this book became available, the IEEE has formalized theBoundary-Scan Description Language (BSDL) and made it a part of the standard.Indeed, to be compliant, devices must now be documented in BSDL so thatcomputer applications can use their features.

The 1149.1 standard is now over eight years old and has a large infrastructure ofsupport in the electronics industry. Today, the majority of custom ICs andprogrammable devices contain 1149.1. New applications for the 1149.1 protocolhave been introduced, most notably the “In-System Configuration” (ISC) capabilityfor Field Programmable Gate Arrays (FPGAs).

This book also introduces the very recently balloted standard, IEEE 1149.4“Mixed-Signal Test Bus”. This standard builds upon the base created by 1149.1. In1990, it was not at all clear how analog pins in mixed-signal devices should betreated by a testability standard. Now that 1149.4 exists, the two Working Groupshave begun the process of reconciling the two, with the possibility that the twodocuments will be merged together. Be alert for this event since it will mean morechange in the future.

Finally, the cover of this book shows a picture of what is driving our industrytoday. (See Figure 6-21 on page 219 for a key and discussion of this photograph.)Miniaturization is rampant in many sectors of our industry. Two examples arecellular telephones and handheld video cameras. A trend in our industry is thatminiaturized components are becoming the low-cost alternative because of thevolumes that consumer applications demand. Thus, those portions of industry thatdon’t need these components for reasons of density will still find it attractive toadopt them. This portends an increase in testing problems that 1149.1 and 1149.4 aremeant to solve. It is my sincere hope that this book will be of some use in solvingthese problems.

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AcknowledgmentI’d like to acknowledge those who contributed to this effort. Significant technicalcontributions have been made over several years by Stig Oresjo, Ken Posse, JohnMcDermid and Rod Browen. Beth Eikenbary made management support happen.Others who influenced this work were Colin Maunder, Rod Tulloss, Chi Yau, NajmiJarwala, Lee Whetsel, Gordon Robinson, Peter Hansen, Tom Williams, Luke Girard,Dick Chiles, Larry Saunders, David Simpson, Grady Giles, Tom Langford, MarkusRobinson, C. J. Clark, Carl Thatcher, Adam Cron, Steve Sunter, Mani Soma, KeithLofstrom, Steve Dolens, Brian Wilkins and Ramaswami Dandapani.

Special mention goes to my friends at Matsushita Electric Industries in Osaka,Japan who worked incredibly quickly to produce working silicon containing 1149.4structures. They are Kozo Nuriya, Katsuhiro Hirayama, Akira Matsuzawa, AtsushiKukutsu and Ren Franse.

Reviews of various manuscripts were conducted by Anne Dudfield and JohnMcDermid of Hewlett-Packard, Ben Bennetts of Bennetts Associates, ColinMaunder of British Telecom and Keith Lofstrom of KLIC Incorporated, directed byCarl Harris of Kluwer Academic Publishers. All errors and omissions that survivedtheir careful efforts are my own.

I am indebted to my wife Jana, and my eight and six-year-old daughtersKatherine and Lisa who missed paternal contact while their father spent all thosehours in the basement. Without their support, I could not have completed this work. Ithank them. Now that this is finished, I look forward to making it up to them.

Fort Collins, Colorado

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CHAPTER 1

Boundary-Scan Basics and Vocabulary

Boundary-Scan, formally known1 as IEEE/ANSI Standard 1149.1-1990 [IEEE90,Maun90], is a collection of design rules applied principally at the Integrated Circuit(IC) level that allow software to alleviate the growing cost of designing, producingand testing digital systems. A fundamental benefit of the standard is its ability totransform extremely difficult printed circuit board testing problems that could onlybe attacked with Ad-Hoc testing methods [Will83] into well-structured problems thatsoftware can easily and swiftly deal with.

Note I have twice stated that software would be utilizing the standard. Incomplex designs where testing problems are most difficult, Boundary-Scan is quitetedious for a human to program manually. The attendant serialization of test datamakes the purpose of a test quite incomprehensible. Thus, it is extremely importantthat the rules of this standard be strictly obeyed, and, that the details of how a givenIC has Boundary-Scan implemented be described with complete accuracy. If thiswarning is not heeded, then software may well obey a fundamental law ofcomputing: Garbage In, Garbage Out. The net result will be difficulty or even

1Informally, the Standard is often referred to as the “JTAG” proposal, due to its history of

development. JTAG was the Joint Test Action Group made up of companies primarily inEurope and North America. This group created the foundation for the IEEE work.

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failure. However, if you have a robust and well-described implementation of theStandard [Ores92], you can expect many improvements in efficiency in several areasas will be outlined later in this book. Some startling improvements have beenobserved, such as in [Kaji92] where a complex board test was created at least tentimes more quickly than anticipated, without need of debugging.

The suffix that you see on the name of the Standard indicates the year theStandard was issued or last reissued. The IEEE requires that every five years, astandard be updated if necessary and balloted again. When it passes ballot, it gets anew suffix. During the five-year cycle, up to two Supplements may be issued asseparate documents that give clarifications and/or corrections to the standard. Theoriginal Standard [IEEE90] was issued in 1990. Supplement A appeared in 1993[IEEE93] and contained a thorough rewrite of the fundamental chapter describingthe Boundary Register. Then in 1994, Supplement B issued. This supplementcontained the formal description of the Boundary-Scan Description Language (seeChapter 2) known as BSDL. At this writing, the next reissue of the Standard is beingbrought to ballot. This should end up with a 1999 suffix. The remainder of thischapter gives an overview of the Standard2 upon which subsequent chapters of thebook rely. The IEEE requires the following disclaimer, so please note:

The information presented in this book represents the interpretation of theIEEE 1149.1 and 1149.4 Standards by the author. If you intend to usethese Standards, you should always refer to the official documentsprovided by the IEEE, taking care to obtain the latest issue and anySupplements.

First, we give a brief preview of digital test technology before the advent ofBoundary-Scan.

1.1 DIGITAL TEST BEFORE BOUNDARY-SCAN

Digital logic testing is nearly as old as the digital system, because it was quicklyrealized that volume production of digital boards and systems could not beeconomical without some type of formalized testing. Furthermore, this testing shouldbe accomplished with relatively unskilled labor to free designers for new projects.This led to the birth, in the 1960s, of the Automatic Test Equipment (ATE) industry.3

1.1.1 Edge-Connector Functional TestingThe first digital testers were often not ATE systems at all, but rather, “hot mock-ups.” These consisted of testbeds cobbled together on a designer's workbench alongwith a few instruments such as signal sources, digital word generators, and otherrigging that attempted to approximate the operating environment of the board orsystem to be tested. Sometimes, a known-good system was used as a mock-up to test

In this portion of this book, the term “Standard” shall refer to 1149.1. Later we will switchour attention to 1149.4.

There were many examples of proprietary test systems in existence well before this time,typically at the larger, vertically integrated electronics manufacturers.

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newly manufactured boards and indeed, this is still widely in use today for finalassurance

4 that a board meets its specifications. The main problem with the hot

mock-ups is that it generally takes a skilled person, very familiar with the design ofboth the board and the mock-up, to construct tests and evaluate the results of afailing test.

The commercial ATE industry got started by attempting to provide a universalenvironment for testing digital boards or systems. This amounted to providing powersupplies for the device or unit under test (DUT or UUT) and a collection ofprogrammable digital drivers and receivers operating in parallel under the control ofa test sequencer. These resources were usually fixed in some physical format (a box)that had to be connected to the DUT via some adaptation scheme. The obviousmethod was to provide an interface from the tester to the edge-connector(s) of theDUT via a “test adapter.” This became known as edge-connector functional test.Thus, a universal hot mock-up was approximated.

Of course, this approach had problems: it was not really universal and it was nota good approximation of the ultimate environment of the DUT. For example, edge-connector functional testers were inevitably slower than the environment of theDUT, because testers were built from existing components and expected to last along time to justify their (high) capital expense. Thus, the circuits they were testingwere often newer generations of higher speed and denser logic. This taxed theirabilities. But, the biggest problem of all was the difficulty in programming the tester.This spawned the research field of digital test generation, which has kept legions ofinvestigators busy for decades. (See [Agra88] for a tutorial, history, and manyreferences.)

In attempting to create stimulus and response patterns for assemblies of complexdigital components, whole industries have been created. The most popular tool is thelogic simulator. A logic simulator allows a designer to create an abstract model of acircuit, then apply stimulus “vectors” to it and let the model produce the output orresponse “vectors”. By adding the capability of injecting failure mechanisms (faults)into the model, it was then possible for a simulator5 to track differences in how thecircuit responds to stimulus; if the differences were visible at an observation point(like an edge-connector pin), the fault was said to be “detected.”

Clever circuit designers with intimate knowledge of how a circuit behaves stillhave some difficulty in deriving stimulus vectors that will detect all the faultspossible6 within a circuit.7 Worse, it is often the case that the original designer was

4The quality of this “assurance” varies wildly from place to place. In some instances, the

effectiveness is good. In other cases, this last test step may be nearly useless, serving mainlyas a psychological comfort, or the fulfillment of some contractual agreement.

In the early days of simulation (late 1960s) simple gate level models or systems of Booleanlogic equations were used to describe circuits. Now there is a range of technology spanningtransistor level models to high level behavioral models.6 “Faults” are an abstraction. The most popular fault model is the Single Stuck-at fault model.Considering multiple Stuck-at faults is explosively combinatorial and quickly becomeintractable. Thus, “all faults” means “all faults that are practical to consider.”

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not available (or motivated) to create tests. Thus a harried, overburdened testengineer was expected to receive a complex design and create tests with little or noinformation on how the design worked.

By the mid 1970s, the severe blow was delivered to simulator-based functionaltesting (although it survived in certain niches) in the form of the (LSI) of integratedcircuits. At this time, the sizes of ICs exploded beyond these capacities:

the capacity of existing simulators to process the size of models,

the capacity for creating accurate models for LSI circuits.

While today, the Intel 8008 microprocessor seems like a trivial relic, it was at thetime a revolution that stymied simulator-based functional testing.

Simulator-based functional testing is enjoying resurgence today. There are twocontributing factors: first, today’s simulation tools have made significant strides incatching up with IC technology; second, the successor to functional testing (In-Circuit testing) is running into obstacles that are threatening its effectiveness.

1.1.2 In-Circuit TestingThe successor to simulator-based functional testing became pre-eminent in the

latter 1970s; In-Circuit testing. The key concept (shown in Figure 1-1) was thataccessing the circuit via the edge-connector was too limiting. What if we couldaccess internal nodes as well? What if we could observe these nodes AND we couldalso stimulate8 these nodes?

With In-Circuit testing, we could now divide and conquer formidable digitalcircuits by testing individual components as if they were standing alone. Thisreduced the test preparation problem to that of a (significant) one-time investment ofa test per IC, which could then be recalled from a test library for each applicationinstance of the IC.

If the In-Circuit test for a IC failed, then more relevant diagnosis was possible;the problem had to be in the vicinity of the IC or its interconnect. A weakness of In-Circuit IC testing was that opens on IC inputs could not be accurately diagnosed andcould indict the IC itself. This could cause us to replace the (expensive) IC ratherthan touching up a faulty solder connection. However, the overall efficiency ofpreparing and interpreting tests was overwhelmingly popular. In-Circuit testingbecame King. (See [Park87], [Coom95] for more detail on the In-Circuit technique.)

Automatic Test Generation software has had marginal success in supplanting humans in thistask. In cases where strict design rules are obeyed, automation can be achieved. For manyelectronics manufacturers, this has not been practical.

Stimulating embedded nodes requires the ability to overdrive the states that upstream ICsmay be driving. This "backdrive" capability requires tester drivers that can source/sink inexcess of 700 milliamperes of current (at speed) for many of today’s logic families.

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But, as technology marched on, problems grew for In-Circuit testing as well. TheIn-Circuit approach depends on a bed-of-nails test fixture, such as the one shown inFigure 1-2, to gain access to the internal nodes of the DUT. In the 1970s and into the1980s, IC packaging technology was dominated by dual-inline, through-hole-mounted packages. This meant that every board signal was visible on the bottom of aboard where they were soldered to through-hole package pins and the majority ofthese pins were spaced on tenth-inch (100-mil) centers. It was common to arrangeIn-Circuit fixture nails to target the IC pins9 themselves.

With the switch to Surface-Mount Technology (SMT) and much finer packaginggeometries, new problems arose. First, there were no through-hole pin targets for In-Circuit nails. Second, some board-level signals may never appear on the bottom sideof the board if In-Circuit test access was not a design criterion. Third, for further

When targeting IC pins, the test probes often do not look like sharpened nails, but insteadhave a variety of machined surfaces that are circular and contain a “waffle” pattern of small,sharpened points that will not slip off the targeted pin/solder surface. This surface, in time willcollect solder flux and other debris leading to contact problems. Today’s nails are usuallytargeted at specific test pads and have a single (very) sharp point.

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packing density, ICs might be mounted on both sides of the board. This all led toaccess problems; some board nodes may be inaccessible to In-Circuit nails.

Notice I did not list fine-pitch package leads as a problem. One of the fallacies ofSMT testing is that fine-pitch packages are automatically inaccessible to nails. Thisis a carryover from the days when In-Circuit nails were targeted at package pins.With fine pitch packages, this is not feasible. What must be done is to target inter-

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layer vias10 or deliberately placed test pads. (See [Bull87] for a practical analysis ofSMT probing.) This necessitates having precise X-Y coordinate location data for alltest points and vias, not just the package pins.

Nevertheless, the trend is clear; board-level probing will become increasinglydifficult and costly so that alternatives are needed. Boundary-Scan clearly makes acontribution to solving this problem. As we shall soon see, Boundary-Scan actuallyhelps one prolong the life of the In-Circuit approach, because it allows the reductionof the number of nails needed to test a board while maintaining fault coverage. Thisreduction in nail count tracks the increasing difficulty in placing nails.

1.2 THE PHILOSOPHY OF 1149.1-1990

IEEE Standard 1149.1-1990 [IEEE90] is a testing standard. However, upon readingit, you mostly find that it is a collection of design rules, and that these are applied atthe Integrated Circuit (IC) level. Yet, the Standard is intended to have impact atseveral points in the life cycle of a product. These are:

At the Integrated Circuit level. The Standard facilitates IC testing and hasdirect support for Built-In Self-Test [Bruc91].At the Printed Circuit Board level. The Standard facilitates Board testing. Itcan be used for bench testing of prototype boards [Hall89], for productiontesting [Hans89a], [Hans89b], [Park89], [Park90a], [Robi90], [Coom95] andcan be used to support Emulation functions [AMD91].At the module or system level. The Standard can be used to support the testingof higher-level assemblies from modules [Poss91] and “boxes” [Fasa89],[Swee88] to full systems [Lefe90]. Here, the Standard may also cooperatewith other standards such as 1149.5 [IEEE95].

Next, you will notice that the Standard has two major modes of operation. Thesemodes are defined by setting up the 1149.1 portion of the ICs with specificinstructions. The major modes are:

Non-Invasive. The Standard specifies a set of resources guaranteed to beindependent of the rest of the logic (called the System Logic11) within an IC. InNon-Invasive mode these resources are used to communicate asynchronouslywith the outside world to set up tests or read out results. These activities areinvisible to the normal behavior of the IC.Pin-Permission. The Standard specifies instruction modes of operation that canusurp control of the input/output (I/O) pins of the IC, effectively disconnecting

A "via" is a cylindrical conductor that makes a physical connection between segments of anode on different layers of a printed circuit board. Most vias traverse the entire thickness ofthe board and are thus visible to In-Circuit nails. These are referred to as "natural" test points[Bull87]. Those that do not pierce the entire thickness and are not visible from the outside arecalled “blind” vias.11 In the literature, the term "System Logic" has a number of synonyms. Some are "corelogic", "internal logic", and "mission logic". Currently, with the attention attracted by the1149.4 Analog Test Bus Standard, there is a move to replace “logic” with “circuitry”.

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the ICs System Logic from the outside world. These modes allow the testingof the ICs System Logic or its isolation from testing activities taking place atits pins.

The implications of these major modes are extensive. When a circuit assembly,such as a board or system, is first “brought to life” by applying power, it must betaken to an initial state from which all future behavior progresses in an orderlyfashion. All 1149.1 ICs must “wake up” in non-invasive mode. While 1149.1 ICs areoperating in non-invasive mode, the assembly will initialize to a proper starting state,at least to the extent that any faults that may exist will allow. However, when anyone of the 1149.1 ICs switches to a pin-permission mode, this disconnects its SystemLogic from the rest of the circuit. For circuit assemblies of non-trivial complexity,this constitutes radical surgery. As with any surgery, great care might be needed inpost-operative recovery. (I will refer to a number of problems through the course ofthis book; this one will be called the Lobotomy problem and will be revisited later.)

The Standard tends to view itself as a test vehicle that when put to use (that is,when pin-permission modes are invoked) will do useful test functions. After theseuseful things are done, the Standard offers little guidance on what may be necessarynext. It behooves the user of the Standard to study what after-effects may occurwhen the circuit assembly has completed an 1149.1-based operation. It might benecessary to immediately perform a hard reset or remove the power because busdriver conflicts could be the result when leaving the pin-permission mode.

Finally, the Standard is highly extensible, allowing designers to add modes ofoperation (either non-invasive or pin-permission) in support of functions useful atany level(s) of assembly. This flexibility is a fundamental contribution. It allows avariety of testing schemes to be accessed in a standardized manner. Further, as willbe seen in Chapter 4, it allows for other activities not necessarily recognized as“test.”

1.3 BASIC ARCHITECTURE

The basic architecture of 1149.1 Boundary-Scan is incorporated at the IntegratedCircuit level. See the illustration in Figure 1-3. First, four (optionally, five) newpackage pins are dedicated to Boundary-Scan. These pins form the Test Access Port(TAP) and must be dedicated to Boundary-Scan; they may not be shared with anyother function. These pins are used with a simple protocol to communicate with on-chip Boundary-Scan logic.

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The protocol is driven by two of the pins (three if the optional Test ResetTRST*12 input pin is included13). These two input pins are a Test Clock (TCK) and aTest Mode Select (TMS). The remaining two pins are for serially shifting data intoand out of the IC, labeled Test Data In (TDI) and Test Data Out (TDO). TheStandard requires that TMS, TDI and TRST* float high14 if they are unconnected(intentionally or due to a fault). This requirement enhances system reliability (as willbe seen) since these values on these pins permit fail-safe operation. Second, on theIC die itself, a simple finite state machine is added called the TAP controller. Itrecognizes the communication protocol and generates internal control signals usedby the remainder of the Boundary-Scan logic. The TAP controller is driven by TCKand TMS (and optionally, TRST*, if it exists) only; no other signals affect the TAPcontroller.

Third, on the die again, is a Boundary-Scan Instruction Register and decodelogic. This register is controlled by the TAP and can be placed between TDI andTDO for loading (and unloading) serially shifted instruction data. The InstructionRegister is used to set the mode of operation for one or more data registers. Severalinstruction modes are mandated by the Standard. Others are described, but areoptional. Rules are also given that allow the addition of user-defined instructions andmodes.

Last, also on the die, is a collection of Boundary-Scan data registers. Two arealways required to be present on an 1149.1 component: the Bypass Register and theBoundary Register. Several others are described by the Standard such as a DeviceIdentification Register, but are optional. Finally, rules are given for adding user-defined data registers.

1.3.1 The TAP ControllerThe TAP controller is a finite state machine with a state diagram containing

sixteen (16) states. A transition between states only occurs on a rising edge of theTest Clock (TCK) or asynchronously with the assertion of Test Reset (TRST*) if itexists. An assertion of TRST* will always send the machine to the reset state. Asynchronizing sequence for the state machine also exists: five cycles of TCK withTMS held high will set the machine to the reset state, regardless of its currentposition in the diagram.

As in the Standard itself, signals that are asserted or active in the low state will have anasterisk suffix. All others are asserted in the high state.

Making TRST* optional allows the tradeoff of having an asynchronous reset for the TAPversus the cost of adding a fifth pin.

This requirement implies the use of internal pull-ups on these pins, which drain current.There are two negatives to this that sometimes tempt designers to ignore the float-high rule;first, in ultra-low power systems (for example, battery-powered), the extra power drain is aconcern. Second, the quiescent current consumption in CMOS ICs (IDDQ) is significantlyhigher which frustrates IDDQ testing [Hawk85], an example of two testing methodologies inconflict. These negatives can be mitigated with clever design. For example, as an extension ofthe standard, a designer could provide a mode that turns off the pull-ups for IDDQ testing.

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The state transition diagram is shown in Figure 1-4. It is the fundamental“roadmap” that all 1149.1 applications must follow. Each state contains a label. Eacharc between states is labeled with a 0 or 1 indicating the logic value of TMS thatmust be set up before the rising edge of TCK to cause the transition. Falling edges ofTCK do not cause state transitions, but cause other actions within the architecture.The asynchronous transitions due to TRST* are not shown, but all lead to the TEST-LOGIC-RESET state.

Looking at Figure 1-4 you will notice that there are two vertical columns ofseven states each and that they are identical except for the labels they carry.Furthermore, notice that the labels are quite similar. Indeed, the left vertical columnis the data column and the right vertical column is the instruction column. These twocolumns reference data registers (DR) or the Instruction Register (IR) respectively.

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They behave in an otherwise identical fashion that greatly simplifies understandingthem. The purpose of each state follows.

TEST-LOGIC-RESETThis is the reset state. In this controller state, the test logic is disabled so that normaloperation of the IC’s system circuitry can proceed unhindered. The InstructionRegister is initialized to contain the IDCODE instruction (described in 1.4.2) if thecomponent contains a Device Identification Register or the BYPASS instruction (see1.4.1) if the component does not contain a Device Identification Register. Regardlessof the controller's original state, it will enter TEST-LOGIC-RESET when TMS isheld high for at least five rising edges of TCK15(or when an asynchronous TRST* isasserted). The controller remains in this state while TMS is high. Power-up shouldalso force the TAP Controller to this state.

RUN-TEST/IDLEOnce entered, the controller will remain in the RUN-TEST/IDLE state as long asTMS is held low. When TMS is high, the controller moves to the SELECT-DR-SCAN state.

In the RUN-TEST/IDLE state, activity in selected test logic occurs only whencertain instructions are present. For example, the RUNBIST instruction (described in1.5.3) causes a self-test on the IC’s system circuitry to execute. Self-tests selected byother instructions can also be designed to execute in this state. For instructions thatdo not cause functions to execute in this state, all test data registers selected by thecurrent instruction retain their previous states.

SELECT-DR-SCANThe Standard calls this a “temporary controller state”, meaning that it will be exitedon the next rising edge of TCK. Here, a decision is made whether to enter to DataRegister (DR) column, or to continue on to the Instruction Register (IR) column. IfTMS is held low when the controller is in this state, the controller moves into theCAPTURE-DR state and a scan sequence is initiated for the selected test dataregister. If TMS is held high, the controller moves on to the SELECT-IR-SCAN state.

SELECT-IR-SCANThis is a temporary controller state. Here, a decision is made whether to enter theInstruction Register (IR) column, or to reset the TAP Controller by returning to theTEST-LOGIC-RESET state. If TMS is held low when the controller is in this state,then the controller moves into the CAPTURE-IR state and a scan sequence isinitiated for the Instruction Register. If TMS is held high, the controller returns to theTEST-LOGIC-RESET state.

15 Upon entering TEST-LOGIC-RESET by means of clocking TCK, it is necessary to returnTCK to 0 (a falling edge) to completely reset certain portions of the 1149.1 logic that aresensitive to falling edges of TCK. TRST* on the other hand completely resets all 1149.1circuitry immediately.

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CAPTURE-IRIn this controller state, the shift-register16 contained in the Instruction Registerparallel loads a pattern of fixed logic values on the rising edge of TCK. The twoleast significant bits17 are assigned the values “01”. Any higher-order bits of theInstruction Register, if they exist, may receive fixed bit values or design specificvalues. This bit pattern is not necessarily an instruction; it has significance as a testpattern for the integrity of the 1149.1 circuitry as will be seen in Chapters 3 and 5.

When the TAP Controller is in CAPTURE-IR, the controller enters either theEXIT1-IR state if TMS is high or the SHIFT-IR state if TMS is low.

SHIFT-IRIn this controller state the Instruction Register is connected between TDI and TDOand shifts, on each rising edge of TCK, the captured pattern one stage towards itsserial output. It also shifts the new instruction bits into the Instruction Register fromTDI. When the TAP Controller is in this state, the controller enters either the EXIT1-IR state if TMS is high or remains in the SHIFT-IR state if TMS is low. By stayingin SHIFT-IR, a long sequence of instruction bits can be shifted into the instructionregister.

As can be seen by examining Figure 1-4, it is possible to return to SHIFT-IR bypassing to the EXIT1-IR, PAUSE-IR and EXIT2-IR states. This is important if anexternal controller (called a Boundary-Scan master, see section 5.2.7) is loadinginstruction bits but does not have enough memory depth to complete the entire shiftsequence in one burst. The shift sequence can be broken into manageable pieces bypassing to PAUSE-IR18 while the next portion of shift data is prepared.

EXIT1-IRThis is a temporary controller state. At this point, a decision must be made whetherto enter the PAUSE-IR state, or the UPDATE-IR state. If TMS is held high while inthis state, the controller enters the UPDATE-IR state, which terminates the scanningprocess. If TMS is held low, the controller enters the PAUSE-IR state.

PAUSE-IRThis controller state allows shifting of the Instruction Register to be temporarilyhalted. It is used, for example, when Automatic Test Equipment (ATE) reloads tester

Registers are constructed with dual ranks, a shiftable part and a hold part to preventrippling, due to shifting, from being visible to downstream logic. When we say a register isselected or shifted, we mean the shift portion of it which is connected between TDI and TDO.

Throughout this book, any pattern of bits will be displayed with the most significant bit onthe left, through to the least significant on the right. The least significant bit would be the firstbit shifted into TDI or out from TDO.

Another approach to solving this problem is to simply stop the TCK signal (in the low state)while in SHIFT-IR while overhead activities are processed. However, some Boundary-Scanmasters may not be capable of halting TCK.

16

17

18

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14 Boundary-Scan Basics and Vocabulary

memory. The controller remains in this state while TMS is low. When TMS goeshigh, the controller moves on to the EXIT2-IR state.

EXIT2-IRThis is a temporary controller state. Once again a decision must be made whether tomove on to the UPDATE-IR state, or return to the SHIFT-IR state. If TMS is heldhigh while in this state, the scanning process terminates and the TAP Controllerenters the UPDATE-IR state. If TMS is held low, the controller enters the SHIFT-IRstate.

UPDATE-IRIn UPDATE-IR, the instruction previously shifted into the Instruction Register islatched, on the falling edge of TCK, by the hold portion of the Instruction Register.Once the new instruction has been latched, it becomes the current instruction settinga new operational mode. When the TAP Controller is in this state, the controllerenters either the SELECT-DR-SCAN state if TMS is high or the RUN-TEST/IDLEstate if TMS is low.

CAPTURE-DRIn this controller state, data can be parallel-loaded into the shift portion of the testdata register selected by the current instruction on the rising edge of TCK. When theTAP Controller is in this state, the controller enters either the EXIT1-DR state ifTMS is held high or the SHIFT-DR state if TMS is held low.

SHIFT-DRIn this controller state the test data register connected between TDI and TDO, asselected by the current instruction, shifts data one stage towards its serial output oneach rising edge of TCK. At the same time, it shifts data into data registers fromTDI. When the TAP Controller is in this state, the controller enters either the EXIT1 -DR state if TMS is held high or remains in the SHIFT-DR state if TMS is held low.

As can be seen by examining Figure 1-4, it is possible to return to SHIFT-DR bypassing to the EXIT1-DR, PAUSE-DR and EXIT-DR states. This is important if anexternal controller (called a Boundary-Scan master, see section 5.2.7) is loadinginstruction bits but does not have enough memory depth to complete the entire shiftsequence in one burst. The shift sequence can be broken into manageable pieces bypassing to PAUSE-DR19 while the next portion of shift data is prepared.

EXIT1-DRThis is a temporary controller state. At this point, a decision must be made whetherto enter the PAUSE-DR state, or the UPDATE-DR state. If TMS is held high whilein this state, the controller enters the UPDATE-DR state, which terminates thescanning process. If TMS is held low, the controller enters the PAUSE-DR state.

19As before with instruction shifting, we could simply stop the TCK signal (in the low state)

while in SHIFT-DR while overhead activities are processed if stopping TCK is supported.

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PAUSE-DRThis controller state allows shifting of the test data register in the serial path betweenTDI and TDO to be temporarily halted. It is used, for example, when ATE systemsreload tester memory. The controller remains in this state while TMS is low. WhenTMS goes high, the controller moves on to the EXIT2-DR state.

EXIT2-DRThis is a temporary controller state. Once again a decision must be made whether tomove on to the UPDATE-DR state, or return to the SHIFT-DR state. If TMS is heldhigh while in this state, the scanning process terminates and the TAP Controllerenters the UPDATE-DR controller state. If TMS is held low, the controller enters theSHIFT-DR state.

UPDATE-DRSome test data registers might be provided with a latched parallel output to preventchanges at the parallel output while data is shifted in the associated shift-registerpath in response to certain instructions. In UPDATE-DR, data is latched, on thefalling edge of TCK, onto the parallel outputs of these test data registers from theshift-register path. The data held at the latched parallel output changes only in thisstate. When the TAP Controller is in this state, the controller enters either theSELECT-DR-SCAN state if TMS is high or the RUN-TEST/IDLE state if TMS islow.

A few additional remarks about the actions of the Boundary-Scan test logic are inorder.

The two shift states SHIFT-IR and SHIFT-DR both activate the output driverfor the TDO pin. This driver remains active until the falling edge of TCK inEXIT1-IR or EXIT1-DR respectively. At all other times the TDO driver isturned off, that is, in a high impedance state.

In either update state (UPDATE-IR or UPDATE-DR), the update process oftransferring data from the shift portion of the shift register to the hold rankoccurs on the falling edge of TCK. Thus, a write operation20 occurs on thefalling edge.

In either capture state (CAPTURE-IR or CAPTURE-DR), the data is capturedby the shift portion of the target register between TDI and TDO on the risingedge of TCK. Because this edge causes the TAP controller to leave the capturestate, the data is captured on either arc leaving the capture state. We call this aread operation. Paired with the write operation of updating, these twooperations allow a Boundary-Scan circuit to write data, and later read it in nofewer than 2.5 cycles of TCK.

Data is shifted out on TDO on the falling edge of TCK when in either of thetwo shift states. Note however that data is shifted in from TDI on the risingedge. This yields two effects:

The meaning of "write" operation will become clearer in the description of the BoundaryRegister.

20

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16 Boundary-Scan Basics and Vocabulary

Data is shifted out when taking either arc that leaves a shift state. Acommon mistake is to associate shifting with the state and not the arc.When you want to shift one last bit into a register, you must take the arcthat goes to EXIT1-IR or EXIT1-DR. No data is shifted by the rising edge ofTCK that first brings the TAP controller into a shift state from eitherCAPTURE-DR or CAPTURE-IR.

The data that might be present on TDO when first entering a shift state willnot be valid until after the first falling edge of TCK. Data is set up on TDOa half TCK cycle before TDI is read for the first time.

1.3.2 The Instruction Register

The Instruction Register defines the mode in which Boundary-Scan data registerswill operate. As with most other registers in an 1149.1 design, it is composed of ashift rank and a parallel hold rank as shown in Figure 1-5. The shift rank can beloaded in parallel at CAPTURE-IR, shifted between TDI and TDO at SHIFT-IR, andthe contents of the shift rank are transferred to the hold rank at UPDATE-IR.

Each Instruction Register cell comprises a shift register flip-flop and a paralleloutput latch

21. The shift registers hold new instruction bits moving through the

Instruction Register. The latches hold the current instruction in place while anyshifting is done. This prevents “shift ripple” from being observed at the registerparallel hold outputs during shifting. (This ripple-free behavior is important to manyBoundary-Scan applications.)

Many mandatory and optional instructions are defined by IEEE Standard 1149.1;the instructions will be discussed later in this chapter. Design-specific instructionscan also be added to a component by a designer. The minimum size of theInstruction Register is two cells. The size of the register dictates the size of theinstruction codes that can be used: code size must match the length of the register.

21 The parallel output stage can be implemented with a simpler latch. The shift register

element must be a full edge-triggered design.

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The two least significant register cells must capture a fixed binary “01” patternduring controller state CAPTURE-IR. (These bits will be used later for testing theintegrity of the 1149.1 logic. See section 3.2.1 on page 119.) Higher-order bits ofthis register, if they exist, may capture fixed bits or variable, design-dependent bits.The instruction shifted into the shift register flip-flops is latched into the parallelhold latch outputs at the completion of the shifting process; this must occur duringthe UPDATE-IR state only. This requirement ensures that the instruction changesonly at the end of the Instruction Register (IR) scanning sequence. The valueslatched into the Instruction Register parallel hold output latches define the test modeto be entered and the test data register to be accessed.

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It is not possible to directly observe the TAP Controller state for the purpose oftesting the TAP itself during IC test. Some designers have elected to have the higher-order bits of the Instruction Register capture internal states of the TAP Controller, orto capture instruction decode states of the previously loaded instruction. These arethen shifted out where they can be observed. However, there are good reasons to fixat least some of the higher-order bits. (See section 3.2.1 on Integrity Testing inChapter 3.) Also, if this technique is used, it is possible for the 1149.1implementation to exhibit strange behavior. Consider what happens when the paththrough the state diagram is CAPTURE-IR to EXIT1-IR to UPDATE-IR. In thisinstance, design-dependent bits are captured in the Instruction Register, then latchedas the next effective instruction. While this may be nonsensical to do, it is possible todo.

When a reset is applied to TRST*, or after the controller enters the TEST-LOGIC-RESET state, one of two instructions must be latched onto the InstructionRegister outputs. If the IC has a Device Identification Register, then the IDCODEinstruction bit pattern must be loaded onto the parallel hold rank. Otherwise, theBYPASS instruction is loaded. Table 1-1 summarizes the behavior of the InstructionRegister during each TAP Controller state.

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A Sample Instruction Register CellFigure 1-6 shows an example of a single Instruction Register cell. The signalslabeled “Capture Data” and “Instruction Bit” are the parallel input and output. Thepins labeled “From Previous Cell or TDI” and “To Next Cell or TDO” are the serial

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20 Boundary-Scan Basics and Vocabulary

input and output of the Instruction Register’s shift-register flip-flops. The pin labeled“ClockIR” is derived from TCK and clocks the shift-register flip-flop for capturingand shifting data. The pin labeled “UpdateIR” is derived from a negated TCK andclocks the update latch for updating the hold rank of the Instruction Register. The pinlabeled “ShiftIR” is true only when the TAP Controller is in SHIFT-IR. The pinlabeled “Reset*” is true only when the TAP Controller is in TEST-LOGIC-RESET.TAP Pin TRST*, asserted asynchronously, will immediately clear (or preset) thestate of the hold latch. Upon a TRST* or Reset*, all bits in the Instruction Registerparallel hold rank will preset or clear to set up the required initial instruction(BYPASS or IDCODE).

1.3.3 Data RegistersAll Boundary-Scan instructions set operational modes that place a selected dataregister between TDI and TDO.22 This register is referred to as the target register.This preserves a fundamental notion of Boundary-Scan; that TDI and TDO alwaysconstitute the two ends of a shift register. The function of this register is dictated bythe instruction currently loaded (active) in the Instruction Register. The generalarchitecture of most data registers is shown in Figure 1-5 on page 17. Some dataregisters are simpler because they do not require a parallel hold rank. This rank maybe omitted for registers that do not control anything with their content.

Bypass RegisterOne mandatory register is the Bypass Register. The Bypass Register is a simpleregister that doesn’t require a parallel hold rank. This register consists of only onescan cell. When selected by the BYPASS instruction (see 1.4.1), the Bypass Registershortens the shift path within an IC to a single cell. This is useful for reducing shifttime when testing other boundary-scan components on a board. Another importantfeature of the Bypass Register is that when the TAP passes through CAPTURE-DR,it captures a fixed binary “0” which is subsequently shifted out. This will be usefulfor chain integrity testing (see section 3.2.1).

Device Identification RegisterAnother data register, the Device Identification Register (called Device_ID),described by the Standard is optional. When implemented, it must be 32 bits inlength. This register contains component identification information. The registerservices two functions: the IDCODE instruction (see 1.4.2) and USERCODEinstruction (see 1.4.3). This register is also simple, with no parallel hold rankrequired.

The Device Identification Register, when the TAP passes through theCAPTURE-DR state, will parallel load a fixed 32-bit identification code to be shiftedout. The assignment of this code is discussed in sections 1.4.2 and 1.4.3. This codewill be useful for chain integrity testing (see 3.2.1) as well as for simply identifyingthe IC.

22 However, if an instruction is marked private then the size and purpose of a target register

may or may not be documented. (See section 2.3.12.)

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Boundary registerMost important is the Boundary Register, which has a boundary-scan cell adjacent toeach digital system input and digital system output pin (but not the TAP Pins). Thisregister is used to control and observe activities on the IC’s input and output pins.The Boundary Register is a mandatory feature of IEEE 1149.1 and is covered inmore detail in section 1.3.4 that follows.

User-Defined RegistersThe standard also allows designers to implement user-defined registers. Theseregisters are used in conjunction with user-defined TAP instructions for proprietarybuilt-in self-tests, internal scan testing, or other functions. These registers must forma consistent shift path between TDI and TDO so that when selected, the path is notbroken (a detail sometimes overlooked by designers).

1.3.4 The Boundary RegisterFigure 1-7 shows an example of a single data register cell suitable for use in aBoundary Register. The cell design shown is flexible enough to permit the cell to beused as an input or output cell. The “Parallel In” and “Parallel Out” labels in thesignals in Figure 1-7 are connected to the device pin or system circuitry dependingon the role of the cell. For example, if the cell services an input pin, then the ParallelIn signal is connected to the device pin and the Parallel Output signal is connected tothe system circuitry. For a device output these assignments are reversed. Note thecapture (CAP) and update (UPD) flip-flops; these components (members of the shiftand parallel hold ranks) are important to the functionality of the data register cellsduring test functions.

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22 Boundary-Scan Basics and Vocabulary

In Figure 1-7 the signals labeled “Shift In” and “Shift Out” are the serial inputsand outputs of the Boundary Register forming the shift path. All other signals routecontrol signals from the TAP Controller into the cell.

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For Boundary Register support of bidirectional pins, you can use one of twoapproaches. First, you can use two data register cells: one as an input and one as anoutput as shown in Figure 1-8. Second, you can use a single, somewhat morecomplex cell to perform both functions as shown in the lower half of Figure 1-9.Both figures show an additional control cell (in their upper halves) that gives theBoundary Register control over the output enables of the driver. The Standard allows

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24 Boundary-Scan Basics and Vocabulary

a single control cell to fan out to multiple driver enables, though when this is done,all drivers must behave identically

23 to the value stored in the control cell.

Ignoring the control cell, the reversible cell shown in Figure 1-9 has theadvantage of creating only one position in the Boundary Register scan chain ratherthan two required by the double-cell structure of Figure 1-8. This reduction in cellcount can be substantial for larger ICs. While the actual reduction in siliconconsumption is likely to be negligible, the reduction in shift length is beneficial.Shorter registers take less time (and disc space!) to load and unload.

Inherent in the double-cell structure is the ability for the input cell to capture thestate of the package pin regardless of what the driver is attempting to do. This allowstest software, by noting a discrepancy between what the output cell is programmedto drive and what the input cells observes, to determine if the output driver isdamaged or is attempting to drive into a short.

On examination of Figure 1-9 you will notice that it too can monitor the outputpin while the driver is enabled. This allows the state of the pin to be sensed while thedriver is driving it. The original version of the standard [IEEE90] showed abidirectional cell design now considered flawed

24because it lacked this important

capability. Supplement A [IEEE93] introduced this improved design that does allowdriver monitoring.

It is sometimes the case that signal inversion is an inherent feature of an input oroutput buffer. However, the Standard is firm in requiring the data captured in (say)an input Boundary Register cell to have the same polarity as the data that entered thepin. The cell design in Figure 1-10 for an inverting input buffer shows twocompensating inversions that assure this requirement is met. Similarly, data shiftedinto an output Boundary Register cell, upon updating, should produce the samepolarity data on the output pin. The cell design in Figure 1-11 will compensate foran inverting output buffer.

23 The initial release of IEEE 1149.1 [IEEE90] did not have this restriction. Then, it wasallowable to have some drivers enabled and others disabled simultaneously by a single controlcell. This caused problems for test algorithms and decreased fault coverage so in 1993, thisrestriction was added [IEEE93].24 The flawed cell is named “BC_6 ” in BSDL. The improved cell is called “BC_7”.

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The Boundary Register may include cells that do nothing, called internal cells.These cells are not associated with I/O pins, or enables. They are most likely to befound in field-programmable ICs, FPGA, (see section 1.3.7) where bidirectionalBoundary Register resources are allocated to all pins because it is not known howthe IC will eventually be programmed. If, for example, each pin is configured withthree cells (input, output, and output enable), but one is programmed as a simpleinput pin, the one cell is used as an input cell and the other two are not used; theyexist but are just place-holders.

When reading Chapter of the Standard titled “The Boundary-Scan Register”, onefinds a number of Boundary Cell designs and rules for designing others as well. Wewill use a logical symbols shown in Figure 1-12 to denote a Boundary Register cell.

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Figure 1-12A shows a common cell symbol containing a capture (CAP) ) flip-flop,an update (UPD) flip-flop or latch, the parallel input (PI) and output (PO) signalsand the shift in (SI) and shift out (SO) signals. Figure 1-12B shows an “observe-only” cell that does not have an update flip-flop.

1.3.5 Optimizing a Boundary Register Cell DesignIt is important to note that the 1149.1 Standard is a collection of rules that govern theimplementation of the facilities of the standard. The written rules tell you what youmust do. The figures published in the Standard are not rules, but examples of waysthat the rules could be interpreted. Thus there are conceivably myriad ways youcould interpret the rules to obtain new Boundary Register cell designs.

Many of the figures of Boundary Register cells shown in the Standard are fullyfeatured. For example, they may support several (or all) optional instructions as wellas those that are mandated. This can lead to additional complexity that could bestripped out if you decide to support less functionality.

A common mistake made by designers who are implementing 1149.1 is to treatthe figures showing cell designs as if they were rules rather than interpretations ofrules. They look at cell design examples such as shown in Figure 1-7 and concludethey must use the circuit elements shown in that figure. A paper by Lee Whetsel[Whet95] is very useful because it shows how designing from the rules rather thanthe figures can lead to some fundamental optimizations. Consider one example from[Whet95] shown in Figure 1-13.

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This design is essentially the same as that in Figure 1-7 for the capture portion(CAP) of the cell, but differs quite a bit in the update (UPD) portion. Whetsel attacksthe inserted delay problem (see 1.8.1) presented by the output multiplexer byreplacing it with two FET switches S1 and S2. These switches are controlled by twonew signals DC and UC from the TAP controller, replacing Update-DR and Mode.He then commandeers the output buffer and adds a weak feedback buffer FB,converting it into a latch that serves as the update latch (UPD).25 The claim is made(arguably) that if you didn’t know this was the actual implementation, you wouldconclude that the structure of Figure 1-7 was in place. Whetsel points out that this istrue when there are no faults present. However you can determine which of thesetwo implementations is present if you short the output (even momentarily) since thiswill have the effect of setting or clearing the update latch in his design, but not in the“standard” design. (The 1149.1 Working Group has not taken a stand on whetherthis behavior is acceptable, but it is not currently forbidden by a rule.) A desirableside effect of this resetting/clearing is that the driver only momentarily fights with ashort that stresses the driver, while the “standard” design will persist with thisstressful endeavor. However, a momentary glitch presented to the Whetsel output(perhaps even a line reflection) could conceivably cause the output to toggle.

26 This

behavior treads into a gray area, again not addressed by any rules in the Standard.

The point to be made is that the Whetsel design is quite different from a“standard” figure in 1149.1, but offers significant new advantages. It was arrived atby deliberately ignoring the figures in 1149.1 and synthesizing a cell from the rulesalone.

25Care must be taken to assure that on transitioning from PRELOAD to EXTEST (at

UPDATE-IR), that the update latch does indeed load the content of the Capture Flip-Flop.26

Without proper design care, this driver structure could interact with external circuitry(passive or active) to form an oscillator. If the output portion of this driver was implementedin stages of successively larger buffers, an internal stage could have the latching property andthe final stage would isolate the latch (feedback) from outside influences. This would removethe “anti-stress” feature of the Whetsel driver however.

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1.3.6 Architecture SummaryBy now we have examined the major pieces of the Boundary-Scan architecture.There is a Test Access Port (TAP) Controller, consisting of a sixteen-state machine.This machine is the first in a cascade of three simple state machines. The nextmachine is the Instruction Register and its decode logic. The last machine is made upof the Data Registers. In particular, the Boundary Register surrounds the SystemLogic that could be looked on as a fourth machine—the one the designer originallycreated. A block diagram of this overall architecture is given in Figure 1-14.

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Notice also in Figure 1-14 that TDO is synchronized by an additional registerstage clocked by the falling edge of TCK. This ensures that all transitions on TDOoccur ½ TCK cycle after TDI bits are read in.

1.3.7 Field-Programmable IC DevicesField-programmable ICs are the Chameleon of the Integrated Circuit world. They are“blank pages” that can have logic written into them while they sit on a board. Thewriting process is not unlike storing data into a volatile, or non-volatile memory. Ifdesired, new logic can be programmed in at any time. (At this writing, there is astandardization working group defining an 1149.1-based protocol for programmingthese devices discussed in section 4.9.)

Field-programmable ICs often cause severe testing problems for board test. Bytheir very nature, their logic is fluid and changeable. Preparation of conventional In-Circuit tests for such components may be delayed by these changes. During theboard design, these ICs may be the last to settle into a “final” configuration.Furthermore, volatile devices must be programmed at the time power is applied(often from an on-board Read-Only Memory) so there is plenty of opportunity forboard faults to cause confusion and diagnostic difficulties.

Field-programmable ICs seem to come in two flavors: the “blank page”containing no pre-defined logic; and components that do have a small amount oflogic in place. In the second case, we are interested in the type of IC exemplified bythe Xilinx 4005 [Xili90] or the Xilinx XC9500 family [Xili98] which contain a hard-wired Boundary-Scan facility.

The “blank page” component can always be programmed to have Boundary-Scanlogic [Xili92]. Indeed, it could have only Boundary-Scan logic rather than itsmission logic if Boundary-Scan testing is a one-time event. The mission logic wouldlater replace the test logic. Of course, before programming, the component is notcompliant with the Standard. The 1149.1 Working Group is also hesitant to declareanything compliant that can have its Boundary-Scan logic “disappear” on subsequentreprogramming. This attitude notwithstanding, a test engineer will certainly see thevalue of adding Boundary-Scan to a field-programmable IC whether or not thisfacility is permanent.

The Xilinx 4005 has a hard-coded 1149.1 “shell” that is always present as shownin Figure 1-15. This is done by placing a TAP, an Instruction Register and a BypassRegister onto the component infrastructure. What is left to be added is the BoundaryRegister itself. This is made part of the Input/Output Blocks (IOBs)27 which aregeneral purpose blocks attached to each IC signal pin. Each IOB makes itsassociated pin fully bidirectional, including a dedicated control cell for the outputbuffer enable.

Now all seems to be settled, except that during programming, each system pincan take on a new personality. A pin can change from bidirectional to simple inputor output. In the case of the Xilinx 4005 this personality change causes certain

27See also the notion of a “Digital Boundary Module” introduced in section 7.2.5 on page 242

by the 1149.4 standard.

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Boundary Register cells to become “internal” cells. For example, if an IOB isprogrammed to become a simple input, then the two cells that provide data andoutput enable control become internal cells, just placeholders. Test engineers dohave to make a basic choice; they can use the full bidirectional resources of thedevice or use the restricted resources defined by the system programming. Using thefull resource set gives more flexibility during test, but it may introduce newproblems by adding additional disabling problems to be solved (see section 5.2.5).

1.3.8 Boundary-Scan ChainsBoundary-Scan ICs are designed to link together into chains. A simple chain on aprinted circuit board is shown in Figure 1-16. Simple chains are a collection ofBoundary-Scan ICs with common TCK and TMS, and with their shift paths linkedtogether by connecting a TDO pin of one IC to the TDI pin of the following IC.

The parallel system pins of the components may be connected together. Whenthis is true, the Boundary Register of one component can be set up to communicatewith the Boundary Register of another. In other cases, IC pins may be connected tothe board edge connector. When connected to an edge connector or bed-of-nails, anexternal ATE system can be used in conjunction with the Boundary Register toimplement tests. In both cases, we can implement tests and at the same time avoidhaving to set up or propagate logic values through the System Logic of thecomponents.

In some cases there might be Boundary Scan ICs connected to conventional ICs.In such a case, it is possible to use the Boundary Register(s) to set up logic valuesnecessary for testing the conventional ICs. This will be covered in Chapter 4.

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An important property of simple chains is that, because of the commonality ofTCK and TMS, every TAP of every IC in the chain is always in the same state.28

This means that a single TAP state diagram is sufficient to keep track of the state ofthe entire chain.

Multiple simple chains could exist on a board (or in a system) where no TAPsignals are shared between them. Any parallel system signals shared between ICs ofseparate chains can be tested, but we now have to coordinate the operation ofmultiple chains.

The Standard issued in 1990 shows some additional chain configurations that wecall Siamese chains because they consist of two (or more) chains that share certainTAP signals. For example, two chains could share TCK and TMS, meaning they arelocked together state-wise, but have independent shift paths. In anotherconfiguration, they could share TCK, have paralleled shift paths, but have separateTMS signals. By clever manipulation of the TMS signals, you can make the chainsco-exist.

More exotic chain configurations can be imagined, but an important questionshould be asked; will the software tools at hand be able to comprehend and utilizethese more complex configurations? The answer could well be NO, so beware.

1.4 NON-INVASIVE OPERATIONAL MODES

The TAP Controller and the four (optionally five) independent TAP Pins may beoperated asynchronously and independently of the System Logic. This allows theBoundary-Scan TAP to be used without disturbing the normal operation of a chip,

28Exceptions could occur when some of the ICs have an optional TRST* pin. We assume all

ICs are synchronized to TEST-LOGIC-RESET and that no assertions are made to TRST*.

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29board or system, as long as we utilize only the Non-Invasive modes of operation.These modes are keyed to TAP instructions.

1.4.1 BYPASSThe BYPASS instruction places the single-bit BYPASS data register between TDIand TDO. Its purpose is to produce a short one-bit shift path through a component,and for this component to be operating normally. This instruction and its targetregister are mandatory features of any 1149.1 component. Further, the bit pattern ofall 1s in the Instruction Register must decode to the BYPASS instruction. Other bit

30patterns may also decode to BYPASS if desired.

When the BYPASS instruction is in effect, the Bypass Register is parallel loadedwith a 0 upon passing through the CAPTURE-DR state. This initializes the registerwith known, predictable data.

1.4.2 IDCODEThe IDCODE instruction places the 32-bit Device Identification Register betweenTDI and TDO that contains an identification code. IDCODE is an optionalinstruction. The Standard makes no requirement on the instruction bit pattern usedfor IDCODE.

The Device ID Register is parallel loaded with a hard-coded value upon passingthrough the CAPTURE-DR state. The least significant bit (bit 0) of any IDCODEmust be a 1. This bit is the first shifted out via TDO. The other bits of the DeviceIdentification Register are assigned as shown in Figure 1-17. Bits 31 to 28 (four bits)are a version number for the IC. The version number should be changed every timethe IC is revised. Bits 27 to 12 (sixteen bits) are a part number assigned by themanufacturer. Bits 11 to 1 (eleven bits) are a manufacturer’s identity number31

derived [IEEE90] from the JEDEC (the Joint Electron Device Engineering Council)code32 [JEDE86]. The IDCODE instruction allows a component to be identified viathe Boundary-Scan port.

29If a Pin-Permission mode has been entered, it may be necessary to perform a reset upon

both the Boundary-Scan logic and the System Logic before the System Logic will operatenormally. In some cases, the surest, safest way of achieving this is by cycling the power.

The Standard also states that all unused instruction codes not declared to be private mustalso decode to BYPASS.

There is a code (00001111111) reserved by 1149.1 and considered an “illegal”manufacturer’s code. This code can be fed into the TDI of a chain of devices of unknowncomposition so that when it finally appears at TDO, you then know you have scanned out allthe devices in the chain.

The actual list of manufacturer’s ID numbers maintained by JEDEC has more bits, so this11-bit field is a compression and allows for only 2048 unique numbers. It could happen thattwo unique devices could appear some day with identical IDCODE values, but the probabilityis low that this will ever cause confusion in testing boards and systems.

30

31

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34 Boundary-Scan Basics and Vocabulary

What about second-source manufacturers? It is expected that a second-sourcedIC will have a different IDCODE value33 (at least different in the manufacturer’sidentification) than the original IC. There is provision in the BSDL language (seesection 2.3.11) to specify all IDCODEs that might exist for devices that areotherwise (supposed to be) identical. Also beware of pin-compatible replacementcomponents such as we see in the microprocessor world. These devices are reverse-engineered to have identical pinouts and system behavior, but are not likely to beidentical with respect to their 1149.1 implementation.

In an earlier discussion of the TEST-LOGIC-RESET state (on page 12) we sawthat the Instruction Register is jammed with either BYPASS or IDCODE, ifIDCODE exists. This would allow a test sequence to proceed directly to data shiftingvia CAPTURE-DR with one of the two instructions in effect by default. Because thefirst bit shifted out is a “0” for BYPASS and a “1” for IDCODE, it is possible tocarry out a blind interrogation of a component or chain of components. Blindinterrogation can be done with no knowledge of any Boundary-Scan device’sinstruction register implementation or opcode assignments. Those possessingIDCODEs indicate so by first shifting out a “1” which indicates that the next 31 bitsto follow are the remainder of the IDCODE. A “0” indicates that there is noIDCODE and that the component is in BYPASS. In principle, blind interrogationcould be used to learn the configuration of a system that comes with a set of options.

1.4.3 USERCODEThe USERCODE instruction places the same 32-bit Device Identification Registerbetween TDI and TDO as IDCODE does, but the value captured upon passingthrough the CAPTURE-DR state is user-defined. USERCODE is an optionalinstruction and the Standard does not specify a bit pattern for it. However, if a devicedoes support USERCODE, it must also contain IDCODE.

The purpose of USERCODE is to expand upon IDCODE in situations such as forprogrammable ICs, where an IDCODE alone is insufficient for identifying the ICand its programming. For example, IDCODE would alert you to the fact that an ICwas programmable, but because the programming will occur after the manufactureof the IC (or board or system), the USERCODE function can be used to identify the

This is much easier to accomplish if a second–source agreement is based upon the exchangeof design data (that can be re-synthesized) rather than based upon exchanging mask data.

33

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version of programming. The user is free to define the 32-bit USERCODE value; ascheme similar to IDCODE, containing several fields of information would allow theencoding of several pertinent types of information.

1.4.4 SAMPLE

The SAMPLE instruction is a mandatory instruction34 , but its bit pattern in theInstruction Register is not specified by the Standard. This is the first instruction totarget the Boundary Register between TDI and TDO. While it does so, it does notdisconnect the System Logic from the IC pins. (See the multiplexer in Figure 1-7(page 22); the Mode signal is “0”.)

SAMPLE functionality occurs upon passing through the CAPTURE-DR TAPstate. All the capture flip-flops (CAP) load the states of the signals they are attachedto; IC inputs, or System Logic signals destined for IC outputs. The BoundaryRegister thus takes a “snap-shot” of the activity of the IC's I/O pins. This datasample can then be shifted out for examination. In principle, one can implement“logic analyzer” functionality in a digital system using SAMPLE. (See thediscussion in section 4.2 for some practical issues regarding the use of SAMPLE.)

1.4.5 PRELOADThe PRELOAD instruction is a mandatory instruction, but its bit pattern in theInstruction Register is not specified by the Standard. This instruction targets theBoundary Register between TDI and TDO. While it does so, it does not disconnectthe System Logic from the IC pins. (See the multiplexer in Figure 1-7 (page 22); theMode signal is “0”.)

The PRELOAD function is used to initialize the capture (CAP) flip-flops of theBoundary Register. The CAP flip-flops receive this data, which is then transferred tothe update (UPD) flip-flops upon passing through the UPDATE-DR TAP state.Because this data is blocked by the multiplexer (see Figure 1-7, page 22) from beingdriven out, it will not affect the IC outputs or System Logic. However, when themultiplexer Mode line is switched by loading a Pin-Permission instruction (seesection 1.5) at UPDATE-IR, the multiplexer will switch to the update flip-flops asdata source. The PRELOAD function allows us to have proper data set up before thisswitching takes place.

The PRELOAD instruction has no requirement for what is captured in the CAPflip-flops when the TAP passes through the CAPTURE-DR state. This allows the

34SAMPLE and PRELOAD, in previous releases of the Standard since the beginning

[IEEE90], were one instruction with one opcode. (They were called “SAMPLE/PRELOAD”.)In a long ranging debate, the 1149.1 Working Group has now divorced the two instructions sothat each can be independently encoded and implemented. This lays the groundwork for apossible future demotion of SAMPLE from mandatory to optional status. (PRELOAD willremain mandatory.) There are subtle implications of this move which are controversial withinthe Working Group and still subject to much debate. It is possible and permissible however tomerge the design of SAMPLE with PRELOAD so that the same opcode does both functions.This is likely to be how these instructions will be treated until SAMPLE is (if ever) demoted.

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functionality of PRELOAD to be merged with the functionality of SAMPLE suchthat the two instructions need only consume one instruction bit pattern. (See thediscussion in footnote 34.)

1.5 PIN-PERMISSION OPERATIONAL MODES

The Pin-Permission instructions provide the next major mode of operation. Theseinstructions are characterized by the switching of the cell output multiplexers suchthat the update flip-flop data bits are selected and passed to the parallel outputs of theBoundary Register cells. This disconnects the component I/O pins from the SystemLogic. It is important that the System Logic not be harmed by this radical change ofconfiguration. Thus, on component inputs, it may be necessary to add logic to forcespecific holding values presented to the System Logic. For example, the componentRESET line might be forced to an asserted state by a Pin-Permission instruction.This would prevent the System Logic from suffering internal conflicts. Notice thatboth BYPASS and IDCODE are not pin-permission modes, so if a pin-permissioninstruction is currently active, passing to the TEST-LOGIC-RESET state will removethis mode and put the IC’s test logic back into non-invasive mode.

What happens to an IC that has been held in a safe RESET state when the Pin-Permission mode is departed; for example, when TEST-LOGIC-RESET is entered?This is a serious problem (the Lobotomy problem) for IC, board and systemdesigners to consider. What should the System Logic do upon “waking up” fromPin-Permission mode? One answer would be to assert, as quickly as possible, somemaster reset to the entire board or system to force a safe sequence of events.However, a fault could frustrate this. Another approach would be to remove or cyclethe power, recognizing that this is not an instantaneous process. Yet anotherapproach is to have the System Logic remember that it was disconnected from its I/Opins and stay in a benign reset state until such time as a formal reset sequence orcycling of power is performed.

1.5.1 EXTESTThe EXTEST instruction is a mandatory instruction, but the choice of instruction bitpattern is left to the designer. In the first edition of the Standard [IEEE90] the all-zero instruction bit pattern was mandated to decode to EXTEST. This led to a safetyconcern; what happens to a system when a stuck-at fault (such as a solder short toground) occurs on the TDI input of one IC? If the next instruction scan sequenceintends to load non-invasive instructions (for example BYPASS or SAMPLE) thestuck TDI signal will instead load all zeros into one (or more) IC’s instructionregister, causing the IC(s) to instead go into EXTEST. This could have devastatingconsequences to a system performing a critical mission. To remove this potentialproblem, the 1149.1 Working Group removed the all-zero requirement for theEXTEST opcode [IEEE99] and further recommends that the all-zero opcode nowmap to a non-invasive instruction, such as BYPASS to improve system safety in theface of this possible failure mechanism.

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The EXTEST instruction targets the Boundary Register between TDI and TDO.At the CAPTURE-DR state, all IC inputs35 are captured in their respective BoundaryRegister cells.36 Looking at Figure 1-7 on page 22, the multiplexer Mode signal is setto “1”. Because the cell output multiplexers are reading the UPD flip-flops, all ICoutputs and output enables are under control of the Boundary Register. Thus, duringEXTEST, we can sample the inputs and control the outputs of the IC pins. Shiftingthe Boundary Register during SHIFT-DR allows us to read out captured input statesand to set up new output and output enable states that will become effective uponpassing through UPDATE-DR. EXTEST is the workhorse of Boundary-Scan testing.

1.5.2 INTESTThe INTEST instruction is an optional instruction and the Standard does not specifyan instruction bit pattern for it. INTEST targets the Boundary Register between TDIand TDO.

INTEST is an inward-looking instruction; it puts the System Logic inputs undercontrol of the update (UPD) flip-flops of the Boundary Register input cells. TheBoundary Register cells connected to System Logic outputs and output enablessample the states produced by the System Logic at CAPTURE-DR. Thus, atUPDATE-DR, a test pattern can be applied to the System Logic inputs, and atCAPTURE-DR, the results of that pattern can be sampled. During shifting, theseresults can be shifted out and a new test pattern can be shifted in. While this ishappening, the states driven to the component output pins are controlled one of twoways: first, they may be under control of the Boundary Register so that they can beheld at deterministic values37 while the System Logic is being tested. The secondchoice is to place all system outputs (including 2-state drivers) in a disabled, non-driving state. Whichever option is chosen, it must be applied uniformly to all ICpins.

INTEST can be used to apply IC tests38 to the System Logic while the IC restsIn-Situ on a board. Board level conflicts can be controlled by assuring that the ICoutputs are held to benign values by the Boundary Register39 if the first output

Also, input cells on bidirectional I/O pins will capture their states.

Note the Standard only requires EXTEST to capture IC inputs (and bidirectionals) but doesnot specify what must be captured by control or output cells. This will allow us to merge thebehavior of EXTEST with INTEST so that the two instructions can be implemented with asingle opcode. Another option is to implement self-monitoring outputs (see section 5.1.5 onpage 176) if INTEST is not implemented.

This option must be chosen if a merger of EXTEST and INTEST behavior is desired.

These tests are not the same as those applied by an IC tester in parallel to the component I/Opins. The tests must be prepared for the System Logic I/O signals. For each bus orbidirectional pin, there may be several System Logic I/O signals.39

Actually, if the outputs are disabled which is an option offered by the Standard, this mightnot be perfectly true. Disabled outputs may seem safe but downstream board logic may beconfused by high impedance values on their inputs.

35

36

37

38

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control option (above) is selected. The second option (disabling all IC outputs) willalso eliminate board level conflicts.

One major problem with INTEST IC testing is that the test is serialized anddelivered via the TAP Port. It is possible for the apparent testing rate to be greatlyreduced, by factors of hundreds. The reduction is proportional to the length of theBoundary Register, plus any other bits contributed by other ICs in a chain. If theSystem Logic is dynamic, it might not be possible to maintain a high enough testingrate to keep the dynamic logic alive.

1.5.3 RUNBISTThe RUNBIST instruction is an optional instruction and the Standard does notspecify an instruction bit pattern for it. RUNBIST has a designer-specified targetregister. The purpose of this instruction is to provide users of an IC access to internalbuilt-in self-tests with a standardized access protocol.

While RUNBIST is in effect, the IC output pins are controlled one of two ways(just as for INTEST); first, under control of the Boundary Register or second, all(including 2-state outputs) placed in a non-driving state. In the first instance, statessupplied by a PRELOAD sequence executed before loading RUNBIST will be usedto control the IC outputs while the self test is being performed. Either method allowsus to eliminate potential conflicts that the IC might have with other board-levelcomponents.

RUNBIST is self-initializing; it does not require any seed data (for example, toinitialize counters or signature accumulators) to be loaded in advance of itsoperation. Loading the Boundary Register with a PRELOAD process to eliminateboard-level conflicts is not considered part of the initialization of the self-test.

RUNBIST targets some register between TDI and TDO as specified by the ICdesigner. It may be a dedicated register or it may be an existing register such as theBypass or Boundary Registers. The purpose of this register is to accumulate theresult of the self-test so it can be shifted out for observation. This result must be:

deterministic. All bits must be defined.

invariant for all versions of the IC.

independent of any activity on (non-clock) component I/O pins.

The actual self-test runs when the TAP is placed in the RUN-TEST-IDLE state.The clocking of the self-test may come from TCK, from the system clock(s), or both.The production of the self-test result may take many clock cycles, but a furtherrequirement states that any clocks received beyond this number will not affect theresult. This freezing of the self-test result allows us to execute RUNBIST in severalcomponents in parallel, applying clocks to all, such that the largest number requiredby any component have occurred. The test result is captured by the target register ineach component upon passing through CAPTURE-DR. Then all results can beshifted out for examination.

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1.5.4 HIGHZThe HIGHZ instruction was introduced with the 1993 supplement to the Standard[IEEE93]. It is an optional instruction and the Standard makes no requirement on itsinstruction bit pattern. Its purpose is to enhance the ability of In-Circuit test ATEsystems to test complex boards by reducing the potential for overdrive damage. Byloading an IC with HIGHZ we make it release control of its output nodes. We canthen safely overdrive them with an In-Circuit tester indefinitely.

HIGHZ targets the Bypass Register between TDI and TDO, to shorten the shiftpath. It also causes all output and bidirectional pins to go into high-impedance states.(In the case of asymmetrical drivers such as TTL Open-Collector or ECL Open-Emitter drivers, the non-driving state is selected.) In this condition, In-Circuitoverdrive is not needed to gain control of the IC’s output pins. This switching to adisabled state occurs when HIGHZ becomes effective, upon passing throughUPDATE-IR.

1.5.5 CLAMPThe CLAMP instruction was introduced with the 1993 supplement of the Standard[IEEE93]. This, too, is an optional instruction and the Standard makes norequirement on its instruction bit pattern.

CLAMP targets the Bypass Register between TDI and TDO, to shorten the shiftpath. It also places all output and bidirectional pins under control of the BoundaryRegister, which should be previously set up beforehand with a PRELOAD sequence.These states become effective at UPDATE-IR. This allows a test to set fixed valueson an IC’s output pins without incurring the overhead of its entire BoundaryRegister. In other words, this function could have been accomplished by putting theIC in EXTEST, but the Boundary Register would then be in the shift path(lengthening it) and it would have to have its clamp values reinstated on every newshifting cycle.

CLAMP is intended for “digital guarding.” When testing a board, it is oftennecessary to force static “0”s or “l”s on selected nodes in order to set up testableconditions or to block interfering signals. With an In-Circuit tester having full nodalaccess, we would simply assign tester drivers to the selected nodes and force therequired values. If the nodes of interest are sourced from Boundary-Scan devices thatpossess the CLAMP function, then this digital guarding activity can be performedwithout nail access or potentially damaging overdrive.

1.5.6 Exceptions Due to ClockingFor extremely performance-sensitive component inputs, the Standard allows a

designer to use “observe-only” Boundary Register cells. Figure 1-18 shows anexample. Notice there is no update (UPD) flip-flop or multiplexer in the path frominput pin to System Logic. The logical symbol for this was shown in Figure l-12(b)on page 27.

Such cell designs do not support INTEST or RUNBIST because they cannotisolate the System Logic from the effects of external signals attached to these pins.

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The Standard does allow an exception; if a component pin is a clock then a observe-only cell may be used and the component may still claim support of INTEST and/orRUNBIST. This complicates the application of test patterns for INTEST because wemust now coordinate the shifted portions of a test with parallel clocking. In theprevious section on RUNBIST, we saw that clocking of self-tests could be a functionof TCK or system clock pins. Designers might be tempted to categorize otherperformance-sensitive pins as “clocks” in order to circumvent the rules, but this willsimply make testing more difficult.

1.6 EXTENSIBILITY

A powerful feature of the 1149.1 Standard is its extensibility. The architecture can beextended two ways; by adding user-defined instructions and user-defined registers.User-defined instructions may be public or private. Public instructions must beproperly documented (see section 2.3.10), but private instructions may beundocumented except for their instruction bit patterns. This much is required sousers will know to avoid these patterns. User-defined instructions could causeunusual or hazardous conditions to occur so they must be used with care or avoidedaltogether.

User-defined instructions may target standard registers (such as the BoundaryRegister or the Bypass register), portions of standard registers, or concatenations ofregisters between TDI and TDO. Alternatively, new user-defined registers may betargeted.

40Consider the Texas Instruments 74BCT8244 [Texa91 ]. This IC has a number of

extensions defined by TI. Several of these reference standard registers such asBoundary or Bypass while others reference a TI-defined Boundary Control Register(BCR). This 2-bit register can be loaded with control bits that configure theBoundary Register for special functions that other TI-defined instructions then

40This IC is one of several in a family (called the SCOPE octals) that all implement the same

extensions. SCOPE is a trademark of Texas Instruments.

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activate. For example, the Boundary Register can be configured as a LinearFeedback Shift Register that can collect a signature of the states seen on the inputpins. Similarly, the outputs can be controlled by the Boundary Register, configuredas a Pseudo-Random Pattern Generator. Both functions can be set up, so that the ICgenerates random patterns on its outputs and performs Signature Analysis [Nadi77]on its inputs. Because octal bus components are often the logical partition points in acircuit, these functions are attractive; these ICs can be used to perform board-levelBuilt-in Self-Tests. All of this can be done using the 1149.1 facility as acommunications protocol for accessing a unique test function.

In general, this view of the Standard as a communication protocol for accessingnew functions within an IC is a powerful contribution. Board-level self-tests, specialIC self-tests, hybrid digital/analog tests, emulation support and many other functionscan be accessed using the same four-wire port already there for 1149.1 testing.Section 4.9 discusses how the 1149.1 port is being used to define a class ofinstructions for programming Field-Programmable ICs.

1.7 SUBORDINATION OF IEEE 1149.1

The 1149.1 Working Group formally recognized, in 1993 [IEEE93], that othertesting technologies might exist within an IC. Notably, internal scan methodologiesmay be used that test all the circuitry within an IC, including the 1149.1 testcircuitry.

For example, a single Integrated Circuit could contain 1149.1 and some othertestability technology such as IBM’s Level Sensitive Scan Design (LSSD) [Will83].Indeed, the first release of the Standard [IEEE90] contains Appendix A, whichshows just such a scenario. Such an intersection of testability approaches can lead toa problem; does one standard have superiority over the other when it comes tointerpreting the rules of both? For example, must the control signals for LSSD begoverned by the 1149.1 Boundary Register? Does the TAP controller use LSSDmemory elements in its construction? Careful study of Appendix A of the Standardwill reveal that LSSD exercises superiority over 1149.1. It would be impossible tomaintain LSSD rules without this superiority, but it has the effect that that several ofthe LSSD controlling pins are not testable by the 1149.1 facility. Further, if thesepins are not held at certain stable levels, then the 1149.1 facility will not work at all.

The solution to this is to recognize certain pins as “compliance enable” pins.These pins must be conditioned with stable logic states before and during all 1149.1activities. If this condition is not met, then the 1149.1 features cannot be used. Suchdevices are considered 1149.1 compliant when the compliance enable conditioning issatisfied.

Compliance enable pins do exist on many devices that have been implemented,many of which do not include a second testing technology. Unfortunately, this wasnot always communicated to users of these devices. Hence they spent a great deal oftime trying to get the 1149.1 features to work reliably but they suffered enormousdifficulties. (Compliance enable pins can now be described in BSDL, see section2.3.9.) Today, compliance enabling is a recognized condition for some ICs and

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software should be able, when notified, to handle many of the implications. Seesection 5.2.5 for more discussion.

1.8 COSTS AND BENEFITS

On first examination of the structure in Figure 1-14 (page 29), it certainly looks likethe System Logic is dwarfed by Boundary-Scan circuit overhead. Indeed, earlycriticism of the Boundary-Scan effort often centered on the apparent impracticalityof the costs. If you look at some actual ICs in existence today that have Boundary-Scan, you can get a feel for what the overhead penalties are.

1.8.1 CostsFirst, consider the Texas Instruments 74BCT8244 Octal Buffer with Boundary-Scan[Texa91]. This IC represents an extreme in that the System circuitry is simply eightbuffers while the Boundary-Scan logic is several hundreds of gates. Note severalthings however. First, the die contains twenty-four bonding pads (four dedicated toBoundary-Scan) for the eight buffers. It is a pad-limited design, meaning there is alot of unused silicon space and most of the die is made up of bonding pads. Second,Texas Instruments has added a number of additional capabilities to the BoundaryRegister and a number of additional instructions to the TAP. Thus, it is a richimplementation. Third, most of this circuitry made use of the unused silicon spaceand was much less expensive as a result. A significant cost was simply the additionalfour pins needed for the TAP signals and the four additional bonding pads on the die.This is pad overhead.

Another problem with adding 1149.1 to the 74BCT8244 is potential yield loss;fewer good die are found per silicon wafer. This is a result of placing active circuitryin formerly “unused” silicon space. Any silicon defects lurking in these spaces cancause the die to fail.

Next consider a VLSI component, the Motorola 68040. This IC contains a basicimplementation of Boundary-Scan. It has a large number of pins (174) of which 102are for System Logic, so five (including TRST*) additional TAP pins is a smallpercentage. Indeed, on many VLSI components, pins are often dedicated for testingpurposes anyway to support proprietary testing functions. The 68040 is area-limitedrather than pad-limited, meaning they packed as many gates onto the largest size ofdie that was commercially feasible. Thus, every gate expended on Boundary-Scansubtracted from those available for System Logic. In [Gall90], the percentage ofgates in the 68040 used for Boundary-Scan was listed as 0.3 percent. For dense ICdesigns such as CMOS VLSI, the gate overhead41 due to Boundary-Scan will besmall.

41Another concern is the routing of global signals such as ClockDR, ShiftDR, UpdateDR and

Mode (see Figure 1-7 on page 22). These signals must be routed to every Boundary Registercell. Note that once a routing channel has been found for one signal, adding more isconsiderably easier.

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Consider the problem of inserted delay. Figure 1-7 (page 22) shows a multiplexerin the system data path between the I/O pin and the System Logic. This will insertsome delay. Now the Standard allows, in selected cases on input pins, for this

42multiplexer to be eliminated. However, the multiplexer function must be present onoutput pins. Again this caused a lot of concern in the early development ofBoundary-Scan, and was often seized upon by reluctant IC designers as a fatal flaw.In reality, merging its function with the output driver can minimize the multiplexerdelay. That is, the multiplexer shown in Figure 1-7 (page 22) is a logicalrepresentation of the cell design and not a preferred implementation. It is interestingto note that when Intel switched to Boundary-Scan design in their microprocessors,the first product containing Boundary-Scan [Inte91] was their fastest processor ofthat time, the 80486DX, not a slower version. Every Intel processor since, includingthe Pentium Pro has contained 1149.1. IC designers committed to implementingBoundary-Scan successfully can greatly reduce the inserted delay penalty by cleverdesign.

Another cost of Boundary-Scan is increased design time. This has beenaggravated by the lack of tools that support Boundary-Scan designs. This problem isbeing solved today, as several EDA design tool vendors such as Cadence, CompassDesign, LogicVision, Mentor Graphics and Synopsys, to name five. The ATEcommunity has been offering test equipment and supporting software for Boundary-Scan since late 1990. Examples of proprietary design tools were reported as early as1991 [Chil91]. When Boundary-Scan reaches maturity, the goal will be for its designand use to be “untouched by human hands”; that is, fully automated.

Yet another problem is lack of discipline in the overall manufacturing process.As stated in the very first sentence in this book, software is a key to success withBoundary-Scan. Software is highly dependent on the quality of data it uses. Amanufacturer must have the discipline to assure that 1149.1 devices are compliant,that the attendant BSDL descriptions are accurate representations, and that boardnetlist data really reflects the construction of the boards (complete with engineeringchanges), to be successful. However, this hasn’t been the case for all of thoseattempting to use 1149.1. To be fair, some attempts have been sabotaged by the lackof discipline amongst vendors of ICs and tools, who have sometimes been sloppywith their degree of compliance with the Standard. This is changing, but you shouldbe wary.43

1.8.2 BenefitsCritics of 1149.1 often cite the various problems listed above. Although most ofthese problems seem individually less significant, they worry about their combinedeffects. However, these worries may be balanced by a systematic view of the

42The price for eliminating these multiplexers may be the inability to implement the optional

INTEST instruction. However, the value of INTEST to anyone beyond the originalmanufacturer is debatable and many original manufacturers use internal scan techniques ratherthan INTEST anyway.43

Indeed, if more people are wary, improvements will come faster!

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economics of producing products. Lab prototypes of a new product may promiseincredible performance for a modest price, but the realities of volume productionmay prove disappointing. Without suitable testability, the product may not beproducible. As product complexities and densities increase, so does the risk ofproduct failure. A maxim in the industry is:

44“Don't be silicon-wise, but system-foolish.”

There are many benefits that will be credited to Boundary-Scan. These are oftenlisted as 1) the automation of test development, 2) the reuse of tests, 3) thestandardization of testability access, and so on. These are all admirable, but it isinteresting to see what affect they may have on the electronics industry while takingtheir costs into account as well.

For this purpose, consider two hypothetical electronics companies X and Y thatcompete with each other. They are using similar technologies, including Surface-Mount Technology (SMT), Application Specific ICs, and they are increasingcomponent densities on boards. They are both examining 1149.1 testability.Company X decides to wait while company Y decides to develop Boundary-Scantechnology. Both companies introduced their last products (1) and (A) in 1996. SeeFigure 1-19 for a possible scenario.

In this scenario, company X introduces its next product (2), without Boundary-Scan, promptly in 1997. These are followed regularly every year by products (3)

44I am told that Vishwani Agrawal originated this phrase. It beautifully sums up the fact that

placing some responsibility for the economic success of a product on the design team cansolve many of our testing problems. This usually requires enlightened management support.

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through (6). Company Y does not get its next product (B) to market until afterproduct (2), and its performance is a slightly less than product (2) as well. This isbecause of the learning curve for Boundary-Scan, the lack of some tools, and someperformance penalties directly ascribed to Boundary-Scan. But, company Y haslearned to use Boundary-Scan, found and developed tools, and is ready to takeadvantage of this on its new product (C). Product (C) is introduced in record timedue to the advantages of Boundary-Scan. Company Y’s engineers did not have tospend much time preparing tests, and were able to react swiftly to last minute designchanges. Thus they beat product (3) from company X to market, although it has alittle less performance than product (3) will eventually have. Now, company Yinvests the savings in engineering due to Boundary-Scan two ways; first, they canget products out faster; second, they can investigate more aggressive technologies.They begin to use very-high density boards and a few Multi-chip Modules.Meanwhile company X is still trying to get its products out the old way, and haslittle time to try new approaches. Company Y introduces products (D) through (F) inrapid succession, which exceed both the performance and the schedule of companyX.

Does this scenario seem far-fetched. I think not. Other revolutions in theelectronics industry showed similar patterns, like the move to Surface Mount. WithSMT there was a significant learning curve and a need for advanced automaticplacement machinery and new test procedures. At first these slowed down theprocess of bringing out new products. But the overall improvement in manufacturingprocesses eventually paid off in better efficiency. Indeed, as time progressed, SMTbecame the more cost-effective process and devices were no longer packaged as bothSMT and through-hole. Thus, even manufacturers who perceived no real need forSMT were forced to use it. As always, there are no guarantees and no substitutes forthe thoughtful application of technology.

1.8.3 TrendsIt has been eight years now since the ratification of the first IEEE 1149.1 Standard[IEEE90]. Some trends are becoming clear.

There is a growing list of vendors for 1149.1 devices and tools.

Most larger devices today contain 1149.1. As one example, there is a move inthe Field-Programmable marketplace to support 1149.1. This reflects two facts; first,these devices, without Boundary-Scan, are inherently difficult to test within theirapplications. Second, the vendors of these devices have begun standardizing on the1149.1 protocol (see section 4.9) as the programming port for these devices, thusgiving (in their view) value to the TAP pins.

As already noted, there is an increasing amount of support from the ElectronicDesign Automation community. This reflects growing demand from designers for1149.1 support. This will increase both the quantities of ICs containing 1149.1, andthe uniformity of their quality.

More people have experience with 1149.1.

While it would be foolish of me to claim that all 1149.1 experiences are good, manymanufacturers have begun to utilize Boundary-Scan. The driver for this trend is lack

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46 Boundary-Scan Basics and Vocabulary

of probing access that is threatening the viability of highly valued In-Circuit testtechnology. Recently, Matsushita Electric Industries Ltd. (MEI) documented theiradoption of Boundary-Scan technology for their products [Milo95]. Theirmarketplace is very cost sensitive, high volume, density driven and fiercelycompetitive,45 yet they see Boundary-Scan as a way to get ahead in the long term.

The silicon costs of 1149.1 are declining.

This is an inevitable result of two facts; the first is that Boundary-Scan siliconoverhead is roughly proportional to the signal pin count of the devices it is placedinto. Signal pin count, while increasing, is not increasing as fast as silicon density.The second is that the density of silicon devices is increasing exponentially, roughlydoubling every 18 months or so (known as Moore’s law). These two facts combinewith the result that Boundary-Scan silicon costs are going down in a roughly linearfashion to the point where they will vanish. Thinking back to 1990, what was thepredominant silicon feature size? It certainly wasn’t we see today. Yet at thislevel, Boundary-Scan technology is quite affordable [Park97]. It can only be gettingcheaper with and geometries coming.

1.9 OTHER TESTABILITY STANDARDS

IEEE/ANSI Standard 1149.1 is part of an overall effort titled IEEE 1149 TestabilityBus Standards. There are five standardization efforts mapped out under 1149.Boundary-Scan (1149.1) was the first to complete its mission. The second was IEEE1149.5, “Standard Module Test and Maintenance (MTM) Bus Protocol” whichcompleted in 1995. The brand new IEEE 1149.4, is covered later in this book (seeChapter 7). The P1149.3 (a system test bus) has long been defunct. In 1997 theP1149.2 [IEEE92] effort decided to end its quest.

P1149.2 (“Extended Digital Serial Subset”) was similar in many respects to1149.1. It was a Boundary-Scan capability in that there was a Boundary Register thatcould observe and control component I/O pins. It had a different control design,called a “stateless” approach. There was no TAP state diagram; to make up for this,more control pins were needed to control the test facility. Offsetting this price wasthe ability to move from one function to another merely by changing the patternapplied to these pins. One goal of this effort was to supply more direct support forhigher testing speeds and to allow the sharing of certain test logic elements withsystem logic. Another goal was for components adhering to both 1149.1 andP1149.2 to be able to perform tests cooperatively. However this compatibility goalturned out to be a fundamental problem. The work done by Lee Whetsel [Whet95](see section 1.3.5) showed how clever design might be able to achieve many of thesegoals within the 1149.1 discipline (though that Working Group still needs toevaluate these ideas). In this light, the P1149.2 Working Group voted to join with theexisting 1149.1 Working Group to find ways to evolve 1149.1 to address theconcerns of the P1149.2 constituency.

45MEI is the world’s second largest electronics manufacturer, participating in many consumer

markets with products like handheld video cameras, VCRs, laptop computers, etc.

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The 1149.5 standard is a bus protocol that focuses on high-level systemstestability. This standard allows the partitioning of a system into subsystems,modules or boards. The lower-level items may utilize 1149.1. This gives moreorganizational flexibility than 1149.1 has by itself (see section 5.3.1).

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CHAPTER 2

Boundary-Scan Description Language(BSDL)

The chapter of IEEE/ANSI Standard 1149.1 titled "Conformance andDocumentation Requirements," [IEEE99] gives a list of items a designer of an1149.1 component must document. This information must be provided to users ofthe component so they may effectively use the Boundary-Scan features. While thislist is necessary, it is not sufficient in the practical sense that in nearly all casessoftware will be utilizing this data. Software cannot read specification documentsgenerated by randomly chosen designers, each with a unique interpretation of thedocumentation requirements, each with a unique style. On top of this, the propensityof humans to overlook an item or two, or to make mistakes, is high.

For 1149.1 to be really successful, it became apparent that some canonical andmachine-readable description was needed to describe the parameters of an 1149.1 IC[Park91]. This is even more important because 1149.1 is intended to bridge betweenindustry segments. Each segment, be it the merchant IC community, the DesignAutomation tool providers or the Automatic Test Equipment (ATE) vendors, and soon, have their own way of describing and using 1149.1 data internally. Each segment(or worse, each entity within each segment) could develop a proprietary way of

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50 Boundary-Scan Description Language (BSDL)

describing Boundary-Scan components. This looked like a Tower of Babel problemin the making, for sooner or later these entities would need to share this data.

In 1989, a group at Hewlett-Packard that produces board test ATE systems wasbusily creating its own proprietary description syntax for 1149.1 ICs. It suddenlybecame clear that there was little incentive for IC vendors, Design Automationvendors, and others to adopt this format, particularly if there was an equivalent effortinside their organizations. Thus, chaos was looming because an ATE system wouldbe presented with ICs to test from numerous sources. Realizing that cooperationwould be necessary, Hewlett-Packard began a process of creating a standarddescription language with the aid of a diverse group of companies. White paperswere written, distributed and commented upon. Next, a more refined proposal (stillin a unique syntax) was presented to the IEEE 1149.1 Working Group at its meetingin March 1990 in Amsterdam. The Working Group recognized the value of astandard language and encouraged more development, but strongly recommendedthat the proposal take on the syntax of an existing language.

Upon looking about for a suitable language, it was clear that no existing languagewas ideal, at least to all observers. However, one language did exist that was alreadyan IEEE standard, dealt with describing, modeling and synthesizing digital logic, andwas gaining a growing following in the commercial marketplace. This was theVHSIC Hardware Description Language, VHDL (IEEE Standard 1076) [IEEE93b].Thus, VHDL became the foundation language specification for BSDL, [Park90b]that after significant additional development was formally balloted and adopted bythe IEEE in 1994 [IEEE94] as IEEE Std 1149.1b-1994.

There are problems with VHDL as indeed there are with other existinglanguages. First, it is a huge language.1 Second, not everyone is using it. Therefore,some applications would be implemented within a VHDL environment and somewould be written to stand alone. Thus, BSDL had to be a subset and standardpractice of VHDL. By keeping the subset small, stand-alone software would not beburdened with supporting a large VHDL parser. By specifying a standard practicewherever VHDL allows a choice in syntactic style, we both simplify software andcreate a canonical form for BSDL. All of this is accomplished without costing theability of a VHDL system to utilize BSDL.

Figure 2-1 shows use models for BSDL within and outside of VHDLenvironments. A BSDL source can be consumed by a VHDL analyzer, whichconverts it into a compiled design library. From here, tools specific to Boundary-Scan can be created that access the compiled design information. Other tools are freeto access this information (as well as any other information present) to performsimulation, logic synthesis, or other tasks. In a non-VHDL environment, tools mustanalyze BSDL directly.

A few more words on the genealogy of BSDL are in order. The first version ofthe language [Park90b] quickly became a de-facto standard near the end of 1990. Aside effect of the development of BSDL was a realization that there were some

Even within the VHDL world, there are full and partial implementations of the VHDLlanguage.

1

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unanswered questions about the 1149.1 Standard itself. Most of these questionscentered on the construction of the Boundary Register and the definition of “SystemLogic”. In response to these questions, the 1993 revision [IEEE93] called IEEE Std1149.1a-1993 concentrated on improving the clarity of the rules for implementingthe Boundary Register. This revision completely re-wrote the chapter on BoundaryRegister construction and ushered in other improvements. Later in 1994, BSDLbecame a formal part of 1149.1 [IEEE94].

There are differences between the initial version of BSDL and the official IEEEversion, but these are relatively minor. These will be pointed out in this chapter, butthis chapter will document only the IEEE version. All important softwareapplications that I am aware of will accept either version of the language, so onedoes not have to write BSDL in both versions. When you create BSDL, it should bein the IEEE version. However, if you have older devices and BSDL files in yourinventory, they should be usable without change.2 IEEE BSDL has an internalmechanism for documenting its revision level that is covered in section 2.3.3.

The older version of BSDL lacks certain capabilities that may be crucial to your success. Forexample, compliance enable pins (see section 2.3.9) cannot be described. If a device hascompliance enable pins, applications using this device will not condition these pins correctly,leading to complex debugging problems. In such cases, you should convert the older BSDL tothe new IEEE form.

2

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52 Boundary-Scan Description Language (BSDL)

2.1 THE SCOPE OF BSDL

BSDL allows the description of the testability features in components that complywith IEEE/ANSI Standard 1149.1. This language can be used by tools that make useof those testability features. Such tools include testability analyzers, test generators,and fault diagnosis routines. With a BSDL description of a component andknowledge of the Standard, software tools can completely understand the datatransport characteristics of the component; that is, how the IC captures, shifts, andupdates data. Note that BSDL itself is not a general-purpose hardware descriptionlanguage. It is not a “model”. BSDL does not provide architectural, structural ordetailed design information about an 1149.1 implementation.

The BSDL description of a compliant component’s parameters has a keycharacteristic: its adherence to the rules of the Standard. As a result, those elementsof a design that are absolutely mandated by the standard are not included in BSDLdescriptions. For example, the Bypass Register is not described in BSDL because itis completely described by the Standard itself, without option. The same is true forthe TAP State Diagram. As another example the content of the Device IdentificationRegister (upon passing CAPTURE-DR) is described, but not the design detail ofhow the register is implemented, because that is completely defined by the Standard.In essence, stating “1149.1” implies a great deal of information common to any suchcomponent. This eliminates both redundancy and the opportunity for error. BSDL isintended to specify those parameters necessarily unique to a given Boundary-Scanimplementation.

2.1.1 TestingBSDL can be used as a test driver. Consider the automatic generation of board testsas shown in Figure 2-2. Here, an ATE program generator is provided with a BSDLdescription of every unique IC adhering to the Standard. Then, as many suchprogram generators do today, it consumes a description of the board topology(consisting of parts list, interconnections, and so on) and writes a test for the ATEsystem.

To support Boundary-Scan, this generator notices that some of the componentshave BSDL descriptions. It can then determine which pins are the TAP pins. Fromthis it can determine the layout of Boundary-Scan chains. Once this layout is known,it can determine which board nodes3 are testable using Boundary-Scan and create theappropriate tests. (Test generation is covered in Chapter 3.)

The term “node” refers to an interconnection of component pins. Frequently used synonymsfor “node” are “net”, “network”, “signal”, “trace”, “track” and “wire”.

3

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2.1.2 Compliance AssuranceWhen one attempts to implement 1149.1 within an IC, one question naturally arises;“Did I do it right?” Answering this quickly becomes a process for ensuringcompliance. One approach for this is shown in Figure 2-3. In this process, the IC isconceived and the 1149.1 facility is then added. The full and perfectedimplementation of the IC’s System Logic may need much further development, butbecause the System I/O assignment, or pinout, of the IC is one of the first items tostabilize, it is often possible to design the 1149.1 circuitry before the IC design isfinalized. When the 1149.1 portion of the IC is designed, a BSDL description maybe written.

The process of writing BSDL can uncover errors in the implementation of the1149.1 circuitry. For example, if System Logic is illegally placed between BoundaryRegister cells and the I/O pins, it will not be possible to describe this configurationwithin BSDL.

After a BSDL description is written, it may be checked by a program that looksfor specific requirements that must be met for the component to be in compliance.For example, it might check that the TAP Instruction Register captures a valid

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54 Boundary-Scan Description Language (BSDL)

pattern at CAPTURE-IR as laid out by the Standard. It may look for more subtleproblems, such as using a Boundary Register cell design that does not supportINTEST when INTEST was listed as one of the instructions the TAP will decode. Ifan error is found, then the design must be corrected. If the program approves of thedesign, then it may proceed to create an IC test program that can then be used to testthe 1149.1 portion of the IC. One important result is that the BSDL will match theimplementation of the 1149.1 circuitry. See section 5.1.10 on page 180 for moreinformation regarding compliance certification of both 1149.1 and BSDL.

In general, the programmatic verification of compliance is very difficult and aguarantee is virtually impossible. This is because:

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the Standard offers no formalized rules or procedures for checkingcompliance.

the Standard is open; it allows the implementation of user defined extensionsof arbitrary complexity.

the IEEE does not bestow a seal of approval upon persons or softwarepurporting to judge compliance.

It is important to note that an IEEE standards effort represents a consensusamong many individuals. In the case of 1149.1 (and many others) this consensusshould be well communicated by the standard document, but supplements andrevisions are planned for clarifications. Questions of interpretation are formallycollected by the IEEE and sent to the standard working group for ruling, again aconsensus process.

For those who are (rightfully) concerned that they may innocently misinterpretthe Standard and generate a non-compliant design, it is highly recommended thatthey take the following course:

implement only the most basic 1149.1 functions.

describe the 1149.1 function in BSDL.

pass this description through a checker and/or test generator from one or moreindependent sources.

physically run any tests created against the real component or simulate themagainst a high-quality model.

When success breeds new confidence, you may want to incorporate advancedfeatures. The next section on synthesis offers hope that much of the risk of acompliance violation can be removed during structured design.

2.1.3 SynthesisIdeally, standardized testability circuitry can be added to an IC automatically duringits synthesis. The goal would be 1149.1-compliant ICs (and BSDL descriptions)untouched by human hands. Good news! The development of such systems ishappening. Let us examine one of the first reported synthesis systems [Chil91],which is diagramed in Figure 2-4.

This synthesis system works in a VHDL environment where IC designers workto describe and simulate the System Logic of their ICs. Typically, they do not havedeep knowledge of the 1149.1 Standard, but they are required to produce 1149.1-compliant components. When the design of the System Logic is relatively mature,they invoke a program that automatically adds an 1149.1 TAP and BoundaryRegister. These come from pre-designed library information (meaning one designerdid have to know the Standard). This software produces a fairly random organizationand layout of the 1149.1 circuitry, adds it into the System Logic description(producing a model for simulation) and creates a BSDL description of the 1149.1implementation.

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56 Boundary-Scan Description Language (BSDL)

Designers are both creative and artistic; therefore, they tend to dislike anythingthat modifies their design. At the same time, they may consider learning theStandard to be an interference with their real job. The interesting feature of thissystem is that it recognizes these characteristics of designers and caters to them.

Designers may do two things. First, they simulate the new design that containsthe 1149.1 circuitry to see if it still meets target specifications. After all, theoverhead due to Boundary-Scan could have made a critical change. Second, theymay decide they want to improve upon the random choices made by the insertionprogram. This is done by editing the BSDL (text), not by editing the 1149.1 circuitryitself. They can then feed the edited BSDL back into the insertion program, whichwill use it as guidance for redesigning the Boundary-Scan implementation. Now the1149.1 circuitry is theirs as well. Typical edits may reorganize the order of theBoundary Register cells, or group driver enables differently among control cells.This process can be iterated until the designer is happy with the result. The end resultis:

the designers did not need intimate knowledge of the 1149.1 Standard.

BSDL is created automatically, exactly matching the silicon.

the designer has control over the effects of the 1149.1 circuitry on the designgoals of the IC.

Is the IC compliant? Most likely, but it depends on the skill of the designer whointerpreted the standard when creating the support library and on the faithfulness ofthe insertion program. It still would be very wise to use the resulting BSDL and an

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independent test generation program to create and execute tests for theimplementation.

A more recent BSDL generator/checker has been documented [Sing97] thatworks from a Hardware Description Language (HDL) input such as Verilog orVHDL. It operates in a succession of phases with just a few clues supplied in thebeginning; the user identifies the TAP signals, the system clocks, and anycompliance enable pins and one compliance enable pattern.

Phase 1 extracts the TAP and verifies the TAP state diagram and timing. Itverifies TAP synchronization and whether the TCK signal can be halted perthe rules. It looks for the required pull-ups on TDI, TRST* and TMS. Finallyit checks TDO generation to assure it is properly handled in each TAP state.

Phase 2 begins the extraction of the shift register portions of the instructionregister and various data registers. It does this by a series of deductions drivenby loading the instruction register with required opcodes,4 and by seeing whatis selected when in the TEST-LOGIC-RESET state. Then it checks the lengthsof these registers and their capture patterns, and performs extensive checks onthe mapping of signal pins to the Boundary Register.

Phase 3 extracts the instruction decode logic and identifies the various targetregisters. SAMPLE and PRELOAD are deduced from this exercise and thenchecked for adherence to the rules.

Phase 4 finds more instructions (INTEST, CLAMP, HIGHZ and so on) andtheir data register interactions. It checks that the Boundary Register cellbehavior is appropriate for these instructions and labels the cells per theStandard.

Phase 5 reads an externally supplied pad-to-pin mapping and then writes outthe BSDL for the IC, provided the rules check out.

As you can see, we’ve come a long way since 1991.

2.2 STRUCTURE OF BSDL

IEEE Std 1149.1b-19945 [IEEE94] describes BSDL in minute detail. (The Appendixof this book contains a syntax summary of the language.) The supplement can beused by a compiler expert to create BSDL-driven software, but may be somewhatdaunting for the more casual reader. This chapter will give an overview of BSDLsufficient for the reader to understand, read and write the language. Please rememberthat BSDL is a subset and standard practice of VHDL [IEEE93b].

4For example, it loads the all-one opcode to force a BYPASS instruction. It then looks to see

what register was accessed and checks it for the rules concerning BYPASS. Note the recentrelaxation of the former rule that associated the all-zero opcode with EXTEST adds a newcomplication here.

This supplement to the Standard is included whenever you order a copy of the 1149.1Standard from the IEEE.

5

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58 Boundary-Scan Description Language (BSDL)

Before jumping in, I’ll try to map some VHDL terms that are probably foreign toengineers accustomed to “normal” programming languages. In VHDL, an entitydescription is similar to a subroutine. It may contain declarations and an executionpart. In BSDL, there is an entity, but it contains only declarations.6 An entity can bepassed formal parameters, again like a subroutine.7 These are called “generic”parameters (literally generic). An entity can incorporate external definitions, like the“include” process in other languages, with use statements. These items that are“used” are called packages and are themselves broken into package and packagebody elements. The package contains global data type declarations and the bodycontains more declarations, enumerating constant data, as will be described later.

BSDL is structured as a VHDL entity supported by VHDL packages and VHDLpackage bodies. All BSDL entities reference a standard package and package bodylabeled STD_1149_1_1994. The standard package contains definitions of theelements of BSDL such that a VHDL system will understand how to recognize them.The standard package also contains logical definitions of Boundary Register celldesigns given by the 1149.1 Standard [IEEE99] and likely to be adopted bydesigners. Figure 2-5 shows this structure.

The following sections describe the elements of the BSDL language. We will usea real IC as an example, the Texas Instruments 74BCT8374 [Texa91b]. Here aresome notes on the lexical structure of the language.

The language is case insensitive and free form, with statements that may covermultiple lines, terminated with semicolons.

Identifiers are made up of alpha, numeric, and underscore “_” characters, withthe first character being alpha. Adjacent or trailing underscores are notallowed in identifiers.

A double dash “--” starts a comment, which continues to the end of the currentline.

BSDL uses VHDL string structures to contain some information. These stringsmay be broken into manageable pieces by concatenation of smaller stringsusing the “&” operator. A single string cannot be split across lines.

This is an important point; BSDL is not an executable language, but rather a description.

Again, BSDL uses a “generic”, but it is used to select among several descriptive options.

6

7

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Here is an example of how BSDL uses strings. (BSDL examples appear inCourier New Font, a non-proportional typeface, to help differentiate them.)

"This is an example of a BSDL string that just fits a line."

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60 Boundary-Scan Description Language (BSDL)

The following string expression using concatenation takes two lines but it isotherwise logically identical to the string above. This example also shows commentsbetween, and following, two concatenated strings. These comments are logicallyinvisible.

"This is an example of a BSDL string " & -- shorter string"that just fits a line." -- remaining string

Strings are used to express certain BSDL structures that are often quite long.Concatenation is used to map these structures into the constraints of common editingsoftware and can be used to produce a visually appealing format. Having just saidthat...

Warning! BSDL is intended for distribution from serving organizations to clientorganizations. It is common practice today to use the Internet or other electronicsystems for this communication. However, BSDL strings and comments can interactwith features of this channel between server and client to produce errors in theinformation as received by clients. Here is an example. Say you create a BSDL filecontaining the following hypothetical text:

A_String := "A text line longer than an Email system likes";

-- A Comment that exceeds an Email system’s line definition

Here is what your client may receive after using electronic mail service to receiveyour BSDL:

A_String := "A text line longer than an Email systemlikes";

-- A Comment that exceeds an Email system’s linedefinition

Your client then compiles the file and sees errors something like this:

A_String := "A text line longer than an Email system*** syntax Error: Missing quote marklikes";*** Syntax Error: Unexpected symbol ‘likes'

-- A Comment that exceeds an Email system’s linedefinition*** Syntax Error: Unexpected symbol ‘definition'

This problem is surprisingly common and puts an unnecessary burden on clients.Further, their impression of “your” BSDL is that it has obvious quality problems andshould not be trusted. The solution is, as a practical measure, to ensure that the linesyou use in a BSDL description are reasonably short, say 55 to 65 characters. Whenyou start getting near 70+ characters, you will find some electronic information

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transfer systems begin to make formatting decisions on their own that potentiallyinject BSDL syntax errors. These errors may be injected at either end of the transfer.

2.3 ENTITY DESCRIPTIONS

The entity description begins with an entity statement and terminates with an endstatement like so:

BSDL for the Texas Instruments 74bct8374 Octal D Flip-Flop

entity ttl74bct8374 is

{BSDL statements to describe the entity}

end ttl74bct8374;

The entity statement names the entity. Typically we place the component name here.(Notice that this entity identifies the “74bct8374” component, but the entity name is“tt174bct8374”, reflecting the VHDL requirement that identifiers must start with analphanumeric character.) Other statements within the entity body will reference thisname.

The entity body contains a set of mandatory and some optional statements. Theoptional statements are shown between “{ }” brace characters. They must occur in aspecific order. Below is a listing of these statements that will serve as a roadmap.

entity <component name> is<generic parameter><logical port description><standard use statement>{<use statements>}<component conformance statement><device package pin mappings>{<grouped port identification>}<scan port identification>{<compliance enable description>}<instruction register description>{<optional register description>}{<register access description>}<boundary-scan register description>{<RUNBIST description>}{<INTEST description>}{<BSDL extensions>}{<design warning>}

end <component name>;

The next few subsections describe these statements.

(see section 2.3.1)(see section 2.3.2)(see section 2.3.3)(see section 2.3.4)(see section 2.3.5)(see section 2.3.6)(see section 2.3.7)(see section 2.3.8)(see section 2.3.9)(see section 2.3.10)(see section 2.3.11)(see section 2.3.12)(see section 2.3.13)(see section 2.3.14)(see section 2.3.15)(see section 2.3.16)(see section 2.3.17)

----

----------------------------------

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2.3.1 Generic ParameterThe generic parameter immediately follows the entity statement. It may look like this:

generic (PHYSICAL_PIN_MAP : string);

or like this, with a default assignment:

generic (PHYSICAL_PIN_MAP : string := "DW");

A generic parameter is a parameter that may be filled by a call from the outside world,or it may be defaulted. In BSDL, the generic is a string with the namePHYSICAL_PIN_MAP. It is either passed in from outside (by an application) or itdefaults to the string value like "DW" in this example. The default string is arbitrary.Ultimately, the value of PHYSICAL_PIN_MAP must be assigned for future reference.

A generic parameter, in BSDL, is used to select an IC packaging option by name.Because the same IC die may be placed in packages with different configurations(pinouts), BSDL allows the specification of all package-to-pin mappings within oneBSDL description. The generic allows an external application to select one. If there isonly one package, then by defaulting the generic to its name, one can implicitly selectthe option from within. Remember that one package option is "no package" in the caseof bare die. The bare die bonding layout could also be documented and selected thisway and could be used by BSDL-driven applications supporting IC wafer test.

The string value assigned to PHYSICAL_PIN_MAP should be a meaningful,descriptive string. For example, if an IC is packaged in an 18x18 pin grid array, thenyou could use “PGA_18x18” as the value, which obeys the requirements of a VHDLidentifier (for the reason see 2.3.6) and conveys the package type to observers.

2.3.2 Logical Port DescriptionThe logical port description gives logical names to the I/O pins (system and TAP pins),and denotes their nature such as input, output, bidirectional, and so on. The portstatement for the example IC is as follows.

port (CLK:in bit;Q:out bit_vector(1 to 8);D:in bit_vector(1 to 8);GND, VCC:linkage bit;OC_NEG:in bit;TDO:out bit;TMS, TDI, TCK:in bit);

In this example we see that CLK is an input (in bit), TDO is an output (out bit), thatthere is an eight-bit input bus labeled D (in bit_vector (1 to 8)), and so on. If this IChad bidirectional pins, they would be of type inout. The bit_vector notation indicates aseries of related signals numbered (here) from 1 to 8, inclusive. (Bit_vectors can usedescending orders by replacing “to” with “downto”.) Non-digital signals such as

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Power, Ground, no-connects or analog are labeled as linkage. The set of labels for pinsis given in Table 2-1.

Port names must be VHDL identifiers. Later (see section 2.3.6) we will see howthese ports are associated with a device’s pins, which may be numeric identifiers.VHDL allows more richness in logical port expression, but BSDL limits the syntaxto that shown here as a standard practice.

2.3.3 Standard USE StatementThe standard use statement refers to external definitions found in packages andpackage bodies, as in our example.

use STD_1149_1_1994.all; -- Get Std 1149.1-1994 definitions

This standard use statement must appear in any BSDL description, and must appearbefore any other use statement (see 2.3.4). It instructs a VHDL analyzer to look into aVHDL package named STD_1149_1_1994 for definitions of statements that willsubsequently be found in the description. The “.all” suffix means to use all of thepackage and is not part of the package name. This package, with its attendant packagebody, also contains frequently used Boundary Register cell definitions as defined bythe Standard. (The content of STD_1149_1_1994 appears in section 2.6.1 starting onpage 85.)

VHDL, and thus BSDL, is a case-insensitive language. However, practicallimitations often arise here with the actual name of the standard package. In a pureVHDL environment, a package is a set of definitions that reside in the workspace ofthe VHDL application. This workspace is isolated from the details of the hostcomputer’s file system. Thus, the fact that the host computer is running underWindows-NT (which is case-insensitive) versus UNIX8 (which does give significanceto case) is not apparent to the VHDL user. However, many BSDL tools are not writtenwithin a VHDL application. These tools often store package data in the native filesystem of the host computer. For this reason, some applications will have case-

8 Windows-NT and UNIX are trademarks of their respective owners.

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64 Boundary-Scan Description Language (BSDL)

sensitivity on the name of the package. Taking care to preserve the casing of packagenames can prevent future errors if you port a BSDL between environments.

There is another important implication to the actual name of the standard package.The name implies the version of the BSDL language being used to describe a device.As BSDL evolves with subsequent issues of the Standard, it is important for softwareto understand which version of the language it may be processing. Today’s versionmay contain new constructs that did not exist in a previous version. In some cases, a

9construct may be obsoleted, as has actually happened. When coding BSDL, it isimportant to use only the syntax defined by current issue of the language.

2.3.4 Use StatementsUse statements are optional and more than one may be added. If a designer were toinvent new cell definitions, these could be placed in a new package and referencedwith a use statement, like so.

use My_New_Cells.all; -- Get new Boundary Register cell info

(See section 2.6.2 on page 89 for details on cell definitions.) User-defined packagescan also be used to define BSDL extensions, covered in section 2.3.16 appearing onpage 77. The package name used in a use statement will have the same sensitivity tocasing just described for the standard use statement in section 2.3.3.

2.3.5 Component Conformance Statement

The component conformance statement10 identifies the release of the Standard thatwas used to design the 1149.1 circuitry within an Integrated Circuit. This allowsusers (and software) to identify what features may be present in the implementation.

attribute COMPONENT_CONFORMANCE of ttl74bct8374 is"STD_1149_1_1990";

This statement, written in the 1994 (IEEE) version of BSDL, tells us that the IC wasdesigned by the rules of the 1990 version of the Standard. Other values this attributemay have are “STD_1149_1_1993” and “STD_1149_1_1999” reflecting the 1993Supplement A and the most current issue of the standard.11 Future releases of BSDLwill most likely be coordinated with any future changes or additions to the Standard

The original version of BSDL (pre-IEEE) had a standard package named STD_1149_1_1990which defined five attributes that were obsoleted with the acceptance of the IEEE version ofthe language. Several new attributes have also been introduced. These are included in thischapter.

Component conformance was first defined by the 1993 Supplement to the Standard itself,with BSDL syntax first appearing in the 1994 Supplement that first defined IEEE BSDL.

The alert reader may ask “why not a ‘-1994’ suffix?” This is because the 1994 revision[IEEE94] made no change to the rules for implementing silicon.

9

10

11

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itself. However, the component conformance attribute allows us to know exactly whatset of rules were used to design an IC in any case.

Certain features in an 1149.1 design may be “grandfathered”, meaning they weredesigned by the rules of a previous issue of the Standard, but are no longerconsidered compliant by a later version. By knowing the issue of the Standard thatgoverned the design of an IC, software that checks for compliance can make theexceptions for these grandfathered features. For example, in the 1990 release of1149.1, it was allowed (because there was no forbidding rule) to have a control cellenable two output drivers with complementary values. This of course means that thetwo drivers cannot both be enabled or disabled simultaneously.12 In the 1993 releaseof the Standard, this type of control structure was expressly forbidden.

2.3.6 Device Package Pin MappingsAs mentioned in the discussion on generic parameters, we can describe the mapping ofpackage pins to logical names from the port description. Further, BSDL can describe amultiplicity of mappings. This is done with a VHDL attribute and one or more VHDLconstants. These constants are the first example of BSDL data encoded within VHDLstrings. Notice that because the mappings are long (they rarely fit in one line) they arebroken up into substrings joined by concatenation “&” operators.

attribute PIN_MAP of ttl74bct8374:entity is PHYSICAL_PIN_MAP;

constant DW:PIN_MAP_STRING: ="CLK:1, Q:(2,3,4,5,7,8,9,10), " &"D:(23,22,21,20,19,17,16,15), " &"GND:6, VCC:18, OC_NEG:24," &"TDO:11, TMS:12, TCK:13, TDI:14";

constant FK:PIN_MAP_STRING:="CLK:9, Q:(10,11,12,13,16,17,18,19)," &"D: (6,5,4,3,2,27,26,25) ," &"GND:14, VCC:28, OC_NEG:7," &"TDO:20, TMS:21, TCK:23, TDI:24";

This example shows mappings for two IC package types, the DW and FKpackages. For example, signal CLK is pin 1 in the DW package, but pin 9 in the FKpackage. The attribute sets up a relationship between the generic string and thePIN_MAP attribute so that an application will know that the generic value is used formapping. See also that bussed signals such as D are associated with a group of pins(eight in this case) because D was declared in the port definition as being abit_vector(1 to 8). In this example, D(l) corresponds to pin 23 of the DW package,D(2) is pin 22 and so on.

If the package uses a matrix scheme to label pins such as those often used on ballgrid array (BGA) packages, then these may be named H13 or B7 so as to be VHDL

12 Fortunately, this “feature” was quite rare. If it had proliferated, it would have seriouslycompromised the ability of 1149.1 to support interconnection tests.

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66 Boundary-Scan Description Language (BSDL)

identifiers. They cannot be named 13H or 7B because these are not legal VHDLidentifiers.

When an application program uses a BSDL description of a component, it passes inthe desired package option via the generic parameter. This in turn selects one of thepackage-to-pin mapping constants that sets the association between the logical portnames and the physical pins of the package. Obviously, this mapping will be crucial toproperly understanding how a component interacts with board topologies.

It sometimes happens that an IC is packaged in two very different packages withdifferent pin counts. The extra pins in the larger package may be no-connects or simplybonded as extra power/ground pins. In this case, the extra pins are mapped in the largerpin map and omitted in the smaller. All pins must correspond to ports in the logicalport statement. Note that only linkage ports may be handled this way; all other pinsmust be accounted for in all pin mappings. It is highly recommended that all linkagepins be documented in BSDL.

2.3.7 Grouped Port Identification

The grouped port identification is optional. It is used to identify system pins13 thathave the special property of using more than one pin to carry a bit of data.Differential signaling is the most common example, with pairs of pins used toconvey each bit of data. Note that differential signaling may be done with voltagesignals, or with directional current flow.

With differential signaling on a pair of pins, one pin is always the logicalcomplement of the other (again, in the assigned voltage or current domain). One pinis the “plus” pin and the other is the “minus” pin. Differential signaling is used toimprove noise immunity by its inherent ability to reject common-mode noise. It isalso used to improve system speed and to reduce signal skew, though at the(considerable) cost of doubling the pin count.

Differential signaling needs special consideration in Boundary-Scanimplementations. In the case where a differential driver or receiver is considered an“analog” port, we can still test its ability to deliver digital data, albeit on a pair ofsignal lines. BSDL’s grouped port identification gives software the mechanism toidentify these situations.

The example IC we have been using has no differential signals, so we will use ahypothetical case for a “Diff_IC” device:

attribute PORT_GROUPING of Diff_IC:entity is"Differential_Voltage((Q_Pos(1), Q_Neg(1)), " &

"(Q_Pos(2), Q_Neg(2)), " &"(Q_Pos(3), Q_Neg(3)), " &"(Q_Pos(4), Q_Neg(4))), " &

"Differential_Current((D_Pos(1), D_Neg(1)), " &"(D_Pos(2), D_Neg(2)), " &"(D_Pos(3), D_Neg(3)), " &"(D_Pos(4), D_Neg(4))) ";

13 The 1149.1 Standard makes no provision for differential TAP pins.

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In this example, we are defining the relationship of two 4-bit differential ports madeup of 4 BSDL ports, each with 4 signals. The first pair are Q_Pos and Q_Neg whichare each defined in the port statement as “bit_vector(1 to 4)”. Similarly, ports D_Posand D_Neg are both “bit_vector(1 to 4)” as well. Ports Q_Pos and Q_Neg arevoltage differential pins while D_Pos and D_Neg are current differential pins. Thestructure above identifies the pairings. For example, pins Q_Pos(1) and Q_Neg(1)are a voltage differential pair. A BSDL convention is that the first pin mentioned in apair is the “plus” pin and the second is the “minus” pin.14 Similarly, pins D_Pos(2)and D_Neg(2) are a current differential pair and so on.

Later in the same BSDL description, we will see ports referenced in theBoundary Register description (described in section 2.3.13 on page 72). Normally allsystem signals are required to appear somewhere in the Boundary Registerdescription. An exception is that the “minus” ports shown in a grouped portdescription are not required, indeed they should not appear. This reflects the fact thatonly one Boundary Register cell is associated with each pair of differential pins. (SeeFigure 4-10 on page 156.) Note that if a pair of system pins do have a full set ofBoundary Register resources, then with respect to 1149.1 these pins are notdifferential and should not be described as such.

2.3.8 TAP Port IdentificationThere are four (optionally five) TAP pins. The TAP port identification sectionassigns special meaning to these signals. It looks like this.

attribute TAP_SCAN_MODE of TMS : signal is true;

attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6, BOTH);

If there is an optional TRST* pin, it is identified by the following statement.

attribute TAP_SCAN_RESET of TRST : signal is true;

The statements in this section may appear in any order, but the first four mustalways appear in any BSDL description. All of them assign a VHDL attribute to asignal that must have appeared in the port definition. In the example above, familiarnames such as “TDI” or “TCK” are shown, but these may have been arbitrary names.For example, binding an attribute like TAP_SCAN_OUT to a signal identifies it asbeing the Test Data Output (TDO). There is no significance to these attributes being“true”; the Boolean value is a requirement of VHDL syntax. Any signal bound with ascan port attribute may not appear later in any other BSDL structure.

The signal identified as TAP_SCAN_CLOCK is bound to a VHDL recordcontaining two fields. The first (a real number) is the maximum TCK clocking

14The choice of port names used here helps a reader maintain the “plus” and “minus”

relationship, but is not required by BSDL.

attribute TAP_SCAN_IN of TDI : signal is true;

attribute TAP_SCAN_OUT of TMS : signal is true;

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68 Boundary-Scan Description Language (BSDL)

frequency15 in Hertz and the second is a field with one of two values, BOTH or LOW,indicating the allowable states the TCK signal may be stopped in. Note that acompliant implementation may not specify HIGH as the only allowable stop state.

2.3.9 Compliance Enable DescriptionCompliance enable pins were described in section 1.7 on page 41. These pins mustbe held at static logic states before any 1149.1 activities are attempted on an IC, andmaintained until the completion of these activities. If such pins exist on an IC, thenan optional compliance enable description must be documented in BSDL .

Annex A of the Standard shows an example of an 1149.1 IC that was designed ina Level-Sensitive Scan Design (LSSD) environment. The 1149.1 facility issubordinate to LSSD, so this means that the LSSD feature must be controlled toallow the Boundary-Scan implementation to work. Here we use the example fromAnnex A to illustrate the syntax:

attribute COMPLIANCE_PATTERNS of Annex_A_Chip : entity is"(LSSD_A, LSSD_B, LSSD_P, LSSD_C1, LSSD_C2) (00011)";

Here we see five signals from the port description, LSSD_A, LSSD_B, LSSD_P,LSSD_C1 and LSSD_C2 must be held to the static logic states “00011”, assignedfrom left to right to the listed signals. When this condition is met, the 1149.1circuitry will perform as mandated by the Standard. The signals listed in acompliance enable attribute cannot be scan port signals (see 2.3.8) nor can theyappear in the subsequent Boundary Register description (see 2.3.13).

In real life we have seen many devices with “compliance enable” pins that arenot subordinating testability pins, but pins used for other purposes. A major exampleis the programming control pins on Field-Programmable devices.16 The complianceenable attribute is very helpful for alerting software algorithms (and users) thatspecial handling is needed to make an IC behave. Unfortunately, the complianceenable feature in BSDL was defined in 1994 by IEEE BSDL and many ICs thatwould benefit were already introduced and described in pre-IEEE BSDL. It isessential to convert these older BSDL files to the IEEE form so that the complianceenable information can be conveyed.

15 The Standard is not very clear on the significance of this maximum TCK frequency. Forexample, is it the maximum frequency we can shift bits through any register? How does thisparameter relate to capture and update behavior? What does it tell us about TDI/TDO setupand hold time? In general, many devices have maximum TCK rates of (say) 20 MHz, but wefind that chains of such devices from multiple vendors should be probably be run somewhatslower, for example, at 10 MHz. Some devices are particularly sensitive to rise and fall timeson TCK itself. One important note, it is not necessary for a device’s 1149.1 circuitry toperform at the same frequency as the mission circuitry.16 Field-Programmable devices are now receiving special attention in 1149.1 circles, seesection 4.9 on page 160.

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2.3.10 Instruction Register DescriptionThe next major piece of information required in a BSDL description covers the TAPinstructions that are implemented by the IC’s 1149.1 facility. These include themandatory, optional and user-defined (both public and private) instructions and theirassociated registers. Hence this description contains five elements; the length of theinstruction register, an enumeration of instructions by name, the instruction codes(called “opcodes”) associated with instructions, the instruction register capture patternand whether any instructions are private. Here is the description for the examplecomponent:

attribute INSTRUCTION_LENGTH of ttl74bct8374 : entity is 8;

attribute INSTRUCTION_OPCODE of ttl74bct8374 : entity is"BYPASS"EXTEST"SAMPLE"PRELOAD"INTEST"TRIBYP"SETBYP"RUNT"READBN"READBT"CELLTST"TOPHIP"SCANCN"SCANCT

(11111111,(00000000,(00000010,(00000010,(00000011,(00000110,(00000111,(00001001,(00001010,(00001011,(00001100,(00001101,(00001110,(00001111,

10001000, 00000101, 00000001)," &10000000)," &10000010), " &10000010), " &10000011) ," &10000110) ," &10000111) ," &10001001), " &10001010) ," &10001011) ," &10001100) ," &10001101), " &10001110) ," &10001111)";

BoundaryBoundaryBoundaryBoundaryBoundaryBoundaryBoundaryBCR ScanBCR Scan

Hi-Z1/0run testread normalread testselftesttoggle testnormaltest

attribute INSTRUCTION_CAPTURE of ttl74bct8374 : entity is"10000001";

attribute INSTRUCTION_PRIVATE of ttl74bct837417 : entity is"CELLTST";

The first attribute (INSTRUCTION_LENGTH) gives the length of the InstructionRegister, which must be two or greater. Next, the instruction mnemonics are identifiedand the bit patterns (opcodes) that decode to them are listed in theINSTRUCTIONJDPCODE attribute. There may be more than one opcode listed forone mnemonic18. Each opcode must have a length equal to that specified byINSTRUCTION_LENGTH.

BYPASS must have an all-one decode. Because BSDL does not requiredocumenting what is mandated by the Standard, BYPASS documentation for the all-one opcode could be left out. The Standard, in its initial release, specified that

17 The 74bct8374 in reality does not have any private instructions. This example is used toillustrate the syntax.18 It may be necessary to use "x" characters to specify don’t care locations in an opcode. Whenthis is done, software that consumes BSDL must check that ambiguous decodes have not beenerroneously specified. In this example, the line defining EXTEST could be written "EXTEST(x0000000),".

------------------

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70 Boundary-Scan Description Language (BSDL)

19EXTEST must have an all-zero opcode but this was relaxed in [IEEE99]. BecauseEXTEST, SAMPLE and PRELOAD20 do not have prescribed opcode bit patterns, theymust be given in a BSDL description. Note in the example above that the 74BCT8374has a number of Texas Instruments defined instructions as well as an optional 1149.1instruction, INTEST.

After the instruction mnemonics and opcodes have been defined, one andoptionally two attributes are given that provide additional information. First we see theattribute INSTRUCTION_CAPTURE which specifies a bit pattern captured by theInstruction Register when passing through the CAPTURE-IR TAP State. The bottomtwo bits (as specified by the Standard) must be "01", but any higher-order bits may beconstants (“0” or “1”) or unknown (“X”).

Next, we see the optional attribute INSTRUCTION_PRIVATE, which is used toidentify any instructions that are private to an implementation. Other users shouldnot access private instructions that the designer of an IC has implemented.Documenting them in BSDL allows software to avoid loading those opcode patterns.Failure to respect private opcodes may result in damage to an IC, circuit board orsystem.

2.3.11 Optional Register DescriptionTwo more optional attributes may now appear. They identify the content of theDevice Identification Register after passing CAPTURE-DR when the IDCODE orUSERCODE instructions are loaded, if they exist for the component. (The exampleIC does not have these instructions.) The mnemonics and all associated opcodesmust have been listed in the table of data given in the INSTRUCTION_OPCODEattribute. The syntax for these attributes looks like this:

19The reason for not assigning the all-zero opcode to EXTEST is for fail-safety; a stuck-at

fault on TDI could cause the all-zero opcode to load into an instruction register rather than anon-invasive instruction opcode.20

In the initial release of 1149.1, SAMPLE and PRELOAD were defined as the sameinstruction, or “merged”, and called SAMPLE/PRELOAD. With the current release [IEEE99]these two instructions have been separated, but still can be merged within an implementation.This is shown (as above) by both have the same instruction opcode(s).

attribute IDCODE_REGISTER of My_IC : entity is"0011" &"1111000011110000" &"00000000111" &"1";

4-bit version number16-bit part number11-bit manufacturer's numbermandatory LSB of 1

attribute USERCODE_REGISTER of My_IC : entity is-- 3A1BOOF3 hex programming ID"0011" & "1010" & "0001" & "1011" &"0000" & "0000" & "1111" & "0011";

--------

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The character “X” may appear in the 32-bit fields indicating don’t care bit positions.This could be used, for example, to null out some of the manufacturer’s bits if youwere using a component that had multiple sources.

With the advent of IEEE BSDL, it was also allowed to specify multipleIDCODEs to handle scenarios where a given IC had multiple IDCODE patterns.Some examples are: second sourcing (otherwise identical ICs have differentmanufacturers) and version updates (different versions of an IC have identical1149.1 logic). This allows a single BSDL to encode all the information for a familyof otherwise identical ICs. The syntax for this addition uses a comma-separated listof bit patterns like this for either instruction:

21 The Standard states that designers may add new data registers, or they may access existingregisters, in whole or in part. Further, they may take a collection of registers (whole or in part)and concatenate them. If an existing register is subsetted or concatenated in any way, theStandard requires that it be given a new name and treated as a unique new register.22 This feature only describes constant (static) bits. Bits that may differ in successive passagesthrough the CAPTURE-DR state are either marked as “x” bits, or the capture description maybe omitted altogether.

"0011" & "1010" & "0001" & "1011" &"0000" & "0000" & "1111" & "1111," &"0011" & "1000" & "0001" & "1011" &"0000" & "0000" & "1111" & "0011";

2.3.12 Register Access DescriptionFinally, to wrap up the discussion of instruction description, we have the optionalattribute REGISTER_ACCESS that is used to show how user-defined instructionsinteract with data registers. These data registers will be placed between TDI and TDOwhen the instructions become effective at UPDATE-IR.

attribute REGISTER_ACCESS of ttl74bct8374 : entity is"BOUNDARY (READBN, READBT, CELLTST)," &"BYPASS (TOPHIP, SETBYP, RUNT, TRIBYP)," &"BCR[2] (SCANCN, SCANCT CAPTURES 0x)";

A user-defined instruction may target an existing data register such as the Bypass,Boundary or Device_ID Registers. It may target a user-defined register.21 In theexample above we see that some instructions such as READBN or SETBYP accessstandard registers (Boundary and Bypass) and that others like SCANCN andSCANCT access a new register called BCR, which is two bits long. It is redundant tospecify standard pairings (for example, Boundary with EXTEST) but if such pairingsare written, they must obey the rules of the Standard. For example, it is an error topair the BYPASS instruction with the Device_ID register.

The development of IEEE BSDL brought a new (optional) capability to theREGISTER_ACCESS attribute; the ability to describe a pattern of static bits22 that aregister captures (when passing the CAPTURE-DR state) for a given instruction.

First code

Second code

--

--

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Looking at the example above, the two-bit BCR register captures a “0x” pattern23

when the SCANCT instruction is active, but no specification is made for SCANCN,which could have been coded somewhat redundantly as capturing “XX” in thisexample. The “captures” modifier allows software to verify that the bits that areshifted out of a register after passing CAPTURE-DR are indeed those expected forthe implementation in response to a given instruction. Note that the standardregister/instruction pairings (for example, Device_ID with IDCODE) cannot havetheir capture patterns documented using the “captures” modifier because they arealready specified by the Standard itself or by other elements of BSDL.

If any previously defined instruction was marked private (see section 2.3.10) bythe INSTRUCTION_PRIVATE attribute, then it does not need to appear in theREGISTER_ACCESS attribute at the option of the designer. All other user-definedinstructions must appear in this attribute description. This allows softwareapplications to predict the static capture behavior and data transport characteristics ofthe IC for any public instruction.

2.3.13 Boundary-Scan Register DescriptionThe description of the Boundary Register contains a large block of data. It gives adescription of every cell in the register.

Two attributes make up this description. The first is the attributeBOUNDARY_LENGTH. The length attribute simply states the length of the register,an integer greater than zero.

The second attribute, BOUNDARY_REGISTER, is an array of data records. Eachrecord has a cell number field 24 followed by a cell description structure withinparentheses. The description structure contains either four or seven fields. The firstfour are always the same. The remaining three fields, when present, give informationfor cells devoted to IC outputs regarding how those outputs are disabled. This is howthese attributes look for the example component.

23 Using the established BSDL convention, the capture pattern has its rightmost bit closest toTDO and the leftmost bit closest to TDI.24 Note the cell number field “tags” the cell description. Thus the cell descriptions can belisted in any order. In this book the order will typically be ascending or descending. Asalways, cell 0 is closest to TDO. All cells must be described, i. e., all numbers between 0 andN-1 must appear.

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attribute BOUNDARY_LENGTH of ttl74bct8374 : entity is 18;

attribute BOUNDARY_REGISTER of ttl74bct8374 : entity is-- num cell port function safe [ccell disval rslt]

"17"16"16"15"14"13"12"11"10"9"8"7"6"5"4"3"2"1"0

(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,

CLK,OC_NEG,*,D(l),D(2),D(3),D(4),D(5),D(6),D(7),D(8),Q(1),Q(2),Q(3),Q(4),Q(5),Q(6),Q(7),Q(8),

input,input,control,input,input,input,input,input,input,input,input,output3,output3,output3,output3,output3,output3,output3,output3,

X),"X),"0),"X),"X),"X),"X),"X),"X),"X),"X),

&&&&&&&&&&&

-- Merged In/Cntrl-- See section 2.4

16,16,16,16,16,16,16,16,

0,0,0,0,0,0,0,0,

Z),"Z),"Z),"Z),"Z),"Z),"Z),"Z)";

&&&&&&&

The fields in Boundary Register description structure are defined in the followingparagraphs.

Field 1: This is the cell identification field where the specific cell design is listed.The definition of this cell design must be provided in a package called out in a “use”statement. (See sections 2.3.3 and 2.3.4 beginning on page 63.) In this example, celldesign BC_1 is referenced from the standard package STD_1149_1_1999.

Field 2: This is the port field where a signal from the port statement25 that is attachedto this cell is identified. In some cases a cell has no attached signal; then an asterisk(“*”) appears in this field.

Field 3: This is the function field where the cell function is identified from anenumeration. This enumeration consists of the symbols input, clock, output2,output3, internal, control, controlr, bidir and observe_only. See Table 2-2 for detailson the meanings of these symbols.Field 4: This is the safe field. It contains a single character “0”, “1” or “x”. This fieldspecifies what an Update (UPD) flip-flop should be loaded with when softwaremight otherwise choose a value at random. This value has the least precedence withrespect to any other choice so it cannot be used to influence a test generationalgorithm. An “x” indicates that it doesn’t matter what value is loaded. In theexample shown above, a “0” was specified in the safe field for the control cell (cell16) so that its associated drivers would be disabled when the safe value is loaded.

25 If the port uses a “bit_vector” to denote a group of signals, then a subscripted port namemust be used here. In the example, see that the D and Q ports are shown in Boundary_Registerattribute as subscripted signals, like D(3) or Q(5).

X,X,X,X,X,X,X,X,

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This ends the first four fields required of every cell description record. Somerecords will have the next three fields as well.

Field 5: This is the control cell (ccell) field. It contains an integer that is the cellnumber of the control cell associated with an output or bidirectional pin. This cellcan be used to disable the driver attached to the output or bidirectional signal. (In thecase of asymmetrical output drivers such as an open-collector driver, this field mustcontain its own cell number, indicating the cell controls itself. See section 2.4 onpage 78 for an example.)

Field 6: This is the disable value (disval) field that contains either a 0 or a 1. Thisvalue is what must be loaded into the associated control cell (of field 5) to disablethe driver.

Field 7: This is a disable result field (rslt) that indicates what happens when thedriver is disabled. It may contain one of an enumeration of six symbols; Z, Pull0,Pull1, Weak0 Weak1 or Keeper. These values correspond to a 3-state disable or to

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asymmetrical drivers (such as TTL Open Collector or ECL Open Emitter) whendisabled. See Table 2-3.

All (non-linkage) IC pins must appear in the port field of cell(s) in the BoundaryRegister description with three exceptions that should never appear;

TAP control signals such as TCK, TDO, etc. (See section 2.3.8).

Compliance enable pins (see section 2.3.9).

Negative (or “Minus”) representatives of grouped port pins. (See section2.3.7.)

Many other rules about the construction of the Boundary Register description aregiven in the Standard. Some are obvious, such as the numbers assigned to cells mustfall in the range of 0 to BOUNDARY_LENGTH-1, and all numbers in this rangemust be assigned to a cell. Some deal with the special requirements of the INTESTinstruction. For “generic” implementations of 1149.1, these rules are mainlycommon sense. For more intricate designs, you should take BSDL guidance directlyfrom the Standard.

2.3.14 RUNBIST Execution DescriptionThe (optional) RUNBIST instruction has a myriad of implementation possibilities,particularly with respect to clocking options. BSDL allows the description of thebasic, logical nature of RUNBIST in an IC. Details, such as multiple clock phasing,may have to be adjusted after a RUNBIST test is generated from a BSDLdescription.

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76 Boundary-Scan Description Language (BSDL)

The RUNBIST_EXECUTION attribute is optional, even if RUNBISTfunctionality is implemented in an IC. It contains three pieces of information asshown in this example:attribute RUNBIST_EXECUTION of BIST_IC : entity is"ait_Duration (1. 0e-4) ,""Observing HIGHZ At_Pins,""Expec t_Data 0011001";

The first piece of information is the duration of test clause. A RUNBIST instructionmust run for some length of time in the RUN-TEST/IDLE state, governed by thepassage of time, or some number of clock cycles, or both. The duration in thisexample was but there are other options. For example, maybe the IC needsto be clocked by the TCK port 1000 times. Then the duration would have been“(TCK 1000)” rather than “(l.0e-4)”. A more complicated device might require boththe system clock and TCK to be running, and for a minimum time to elapse as well.In this case the duration might look like this: “(2.8e-2, TCK 1000, SCLOCK12000)”.

The observing clause tells us how the output and bidirectional pins behave whileRUNBIST is in effect. All of these pins do one of two things; they go into a HIGHZ(high impedance) state, or they take on states defined by the Boundary Register,which should be initialized by a PRELOAD operation before RUNBIST is executed.These two options are selected by “HIGHZ” and “Boundary” keywords.

The expect clause documents what test result will be found in the target registerof RUNBIST, listed in the REGISTER_ACCESS attribute appearing earlier in theBSDL description (see section 2.3.12). A pattern of bits is given here that mustmatch the length of the target register. All of these bits must be deterministic “0” or“1” bits. For a passing test, these bits will be read out from the target register afterthe duration requirements for the test have been met.

2.3.15 INTEST Execution DescriptionThe (optional) INTEST instruction has a myriad of implementation possibilities,particularly with respect to clocking options. BSDL allows the description of thebasic, logical nature of INTEST in an IC. Details, such as multiple clock phasing,may have to be adjusted after a INTEST sequence is derived from a BSDLdescription.

The INTEST_EXECUTION attribute is optional, even if INTEST functionalityis implemented in an IC. It contains two pieces of information as shown in thisexample:

Duration of testCondition of Output pinsResult of passing test

attribute INTEST_EXECUTION of INTEST_IC : entity is"Wait_Duration (1. 0e-4) ,""Observing HIGHZ At_Pins";

Duration of testCondition of Output pins

26 All pins, including those whose system nature is to be 2-state pins.

--------

----

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These two pieces of information are identical to those used by the description ofRUNBIST execution (see 2.3.14).

The actual patterns that one would apply via INTEST must come from anexternal source such as the design verification tests for an IC. BSDL does notprovide a means of describing these patterns. The INTEST_EXECUTION attributedocuments the details on how such patterns should be applied.

2.3.16 User Extensions to BSDLSome people have expressed the desire to “extend” BSDL to include support newsyntax for some options and capabilities important to them. These applications mightnot be relevant to anyone else. BSDL Extensions allow a standardized mechanismfor users to define their own extensions to the BSDL language that will not upsetother applications that are otherwise unaware of their format and content.

BSDL Extensions are named. These names must be declared before they can bedefined. Here is an example for a fictional IC named “My_IC”:

attribute My_First_Extension : BSDL_Extension; -- Declaration

attribute My_First_Extension of My_IC : entity is"A string that provides " & -- Definition of extension"data for my personal, " &"proprietary application " &"in my own personal format.";

You can define multiple extensions, with the declaration for each appearing before itis defined. It is also possible to include the definitions of extensions in User-definedpackages (see section 2.6.5 on page 100) which may be useful if you intend to useone or more extensions in multiple BSDL descriptions. When this is done, you onlyneed to define the value of the desired extensions in a given BSDL file.

Once you have decided on a BSDL extension and its format, you can addprocessing capability to your tools that will recognize the attribute by name. Foreigntools will see the attribute too, but will recognize it as an extension and ignore it.

2.3.17 Design WarningsIt is possible that the IC designer will want to communicate information to users of theIC about dangerous or illegal conditions to be avoided. This may be conveyed with anoptional attribute DESIGN_WARNING. This is a textual attribute with no format; itsimply contains a message from the designer. It must appear just before the end of theentity. It looks like this.

attribute DESIGN_WARNING of My_IC : entity is"The private instruction USER_BIST must be used " &"carefully! It requires a seed register to be " &"initialized (See LOAD_SEED), and the output drivers " &"should be disabled during operation.";

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It is intended for application software to pass this warning text on to the user of thesoftware as appropriate. The attribute is useful for capturing and transmitting theintent of a function from the designer to a user.

2.4 SOME ADVANCED BSDL TOPICS

Certain structures in ICs need special treatment when 1149.1 is added to an IC, andthese are reflected in BSDL as special cases. The reader may have already detected“cell merging” in the foregoing example of the 74bct8374. The treatment ofasymmetrical drivers and bidirectionality can also require special action.

2.4.1 Merged CellsIn the description of the 74BCT8374 (see the example BSDL fragment on page 73)you may have noticed that the BOUNDARY_REGISTER array had two entries forcell 16. The first showed the cell to be associated with an input pin; the second showedthe cell to be a control cell for disabling drivers. This is an example of a cell withmerged behavior.

Figure 2-6 shows a Boundary Register design that contains a candidate case forcell merging. Here, an input pin is attached to an input cell. The output of this celltravels directly to a control cell for an output driver. There is no System Logic in thepath, unless one were to count the wire as “logic”. Because there are two flip-flops(CAP) and (UPD) in a cell, one can capture and shift data while the other holds theoutput to a fixed value. Thus, we could merge two cells into one and still obey the rulesof the standard.

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Figure 2-7 shows the same Boundary Register design of Figure 2-6 after cellmerging has combined two cells into one. Cell merging is reflected in BSDL as adoubled cell entry in the attribute BOUNDARY_REGISTER as we have seen in theexample.

Cell merging has two benefits: it cuts down on the cell count in the BoundaryRegister, which reduces gate overhead due to Boundary-Scan; and, cell merging alsoreduces inserted delay. Cell merging can only be done where the System Logicbetween two cells is a wire .

There are other instances where merged cells can be found. Figure 2-8 showsseveral examples where cell merging has been done between input/control cells andbetween input/output cells. The BSDL fragment below gives the Boundary Registerdescription for this design.

num"0"1"2"3"4"5"5"6"6"7"8"9"9

cell(BC_1,(BC_1,(BC_6,(BC_2,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,

port*,OUT2,BIDIR1,**BIDIR3,BIDIR2,BIDIR2,BIDIR3,*

/

IN2,IN1,OUT1,

functioncontrol,output2,bidir,control,control,input,output3,input,output3,control,input,input,output3,

safe0),"1,X,0),"0),"X),"X,X),"X,1),"X),"X),"X,

&1,3,&&&7,&4,&&&0,

1,0,

1,

0,

0,

Weak1),"&Z)," &

Z)," &

Z)," &

Z)";

attribute BOUNDARY_LENGTH of My_IC : entity is 10;

attribute BOUNDARY REGISTER of My_IC : entity is[ccell disval rslt]

27In section 1.3.4 starting on page 21 we saw cases where System Logic consisting of an

inverter can be subsumed into a Boundary Register cell. Having done this, if the logic left is awire, then cell merging can again be done.

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80 Boundary-Scan Description Language (BSDL)

Cell 0 is simply a control cell between the system logic and the enable for signalOUT1. (Cells 4 and 7 are similar to cell 0.) Notice that the safe bits are assigned tocause the associated drivers to disable. Cell 3 is the control for the bidirectional cell(see figure Figure 1-9 on page 25) used on the bidirectional signal BIDIR1.

Cell 1 is discussed in the next section (2.4.2).

Cell 2 is the bidirectional cell in the lower half of Figure 1-9 on page 25. Thiscell always monitors the state of BIDIR1 regardless of whether its driver is enabled.

Cell 5 (and similarly with cells 6 and 9) has merged behavior: it serves as the inputreceiver for BIDIR3, and as the data source for BIDIR2. As a result, the cell has twolines of description in the Boundary Register definition. The first gives its behavior asan input cell while the second describes its characteristics as an output cell. Note thatcell BC_1 used in this capacity must support both input and output3 functions. This isreflected in the definition of BC_1 (see section 2.6.1) where both functions exist for allinstructions.

Cell 8 is a simple input cell using cell BC_1, but it could be an Observe_Only cellif we do not wish to support INTEST in this implementation.

The example illustrated by Figure 2-8 is deliberately extreme and dwells on oddcases. Most component implementations will be quite simple by comparison.

2.4.2 Asymmetrical DriversReturning to Figure 2-8 for a moment, notice that cell 1 is a 2-state output data cell.It has the three extra fields needed to describe an output driver that can be disabled;so, the cell is marked “Output2” and the output can be disabled. This indicates thedriver is asymmetrical because one state is actively driven and the other must be aninactive drive state. (The external pull-up resistor is another clue.) This design doesnot have a separate cell to enable the 2-state driver. BSDL codes this configurationas a cell that controls its own open-collector, asymmetrical driver. Placing a "1" incell 1 will disable OUT2 by putting it into the "Weak1" state.

2.5 BSDL DESCRIPTION OF 74BCT8374

All BSDL descriptions are similar; some will be longer than others will of course, butthe data content and organization are the same. This is true regardless of the nature ofthe System Logic function. For example, the BSDL descriptions of a simple octaltransceiver will be quite similar to that of a large 32-bit microprocessor.

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The example BSDL description for Texas Instruments 74BCT8374 shown inFigure 2-9 looks like this in its entirety.

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-- BSDL for Texas Instruments 74bct8374 Octal D Flip-Flop

entity ttl74bct8374 isgeneric (PHYSICAL_PIN_MAP : string := "DW");

port (CLK:in bit; Q:out bit_vector(1 to 8);D:in bit_vector(1 to 8);GND, VCC:linkage bit; OC_NEG:in bit;TDO:out bit; TMS, TDI, TCK:in bit);

use STD_1149_1_1999.all; -- Get Std 1149.1-1999 defs

attribute COMPONENT_CONFORMANCE of ttlbct8374 : entity is"STD_1149_1_1990"; -- This is an older IC

attribute PIN_MAP of ttl74bct8374 : entity isPHYSICAL_PIN_MAP;

constant DW:PIN_MAP_STRING:="CLK:1, Q: (2,3,4,5,7,8,9,10), " &"D: (23,22,21,20,19,17,16,15) ," &"GND:6, VCC:18, OC_NEG:24, TDO:11, " &"TMS:12, TCK:13, TDI:14";

constant FK:PIN_MAP_STRING:="CLK:9, Q:(10,11,12,13,16,17,18,19)," &"D:(6,5,4,3,2,27,26,25)," &"GND:14, VCC:28, OC_NEG:7, TDO:20, " &"TMS:21, TCK:23, TDI:24";

-- This is where grouped port identification would appear

attribute TAP_SCAN_IN of TDI : signal is true;attribute TAP_SCAN_MODE of TMS : signal is true;attribute TAP_SCAN_OUT of TOO : signal is true;attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6, BOTH);

-- This is where compliance enable description would appear

attribute INSTRUCTION_LENGTH of ttl74bct8374 : entity is 8;

attribute INSTRUCTION OPCODE of ttl74bct8374 : entity is"BYPASS"EXTEST"PRELOAD"SAMPLE"INTEST"HIGHZ"CLAMP"RUNT"READBN"READBT"CELLTST

(11111111,(00000000,(00000010,(00000010,(00000011,(00000110,(00000111,(00001001,(00001010,(00001011,(00001100,

10001000,10000000),10000010)10000010),10000011),10000110),10000111),10001001),10001010),10001011),10001100),

10000100, 00000001), " &&&&&&&&&&&

SAMPLE are merged

Boundary Hi-ZBoundary 1/0/ZBoundary run testBoundary readBoundary read testBoundary self test

Note PRELOAD and

--

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84 Boundary-Scan Description Language (BSDL)

"TOPHIP (00001101, 10001101)," & -- Boundary toggle out"SCANCN (00001110, 10001110)," & -- BCR Scan normal"SCANCT (00001111, 10001111)"; -- BCR Scan test

attribute INSTRUCTION_CAPTURE of ttl74bct8374 : entity is"10000001";

-- This is where INSTRUCTION_PRIVATE would appear.-- This is where IDCODE_REGISTER would appear.-- This is where USERCODE_REGISTER would appear.

attribute REGISTER_ACCESS of ttl74bct8374 : entity is"BOUNDARY (READBN, READBT, CELLTST)," &"BYPASS (TOPHIP, SETBYP, RUNT, TRIBYP)," &"BCR[2] (SCANCN, SCANCT)",- -- 2-bit Boundary Control Reg

attribute BOUNDARY_LENGTH of ttl74bct8374 : entity is 18;

attribute BOUNDARY_REGISTER of ttl74bct8374 : entity is— num cell port function safe [ccell disval rslt]

"17"16"16"15"14"13"12"11"10"9"8"7"6"5"4

"2"1"0

(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,(BC_1,

CLK,OC_NEG,*

D(1),D(2),D(3),D(4),D(5),D(6),D(7),D(8),Q(1),Q(2),Q(3),Q(4),Q(5),Q(6),Q(7),Q(8),

input,input,control,input,input,input,input,input,input,input,input,outputs,outputs,outputs,outputs,outputs,outputs,outputs,output3,

X),"X),"0),"X),"X),"X),"X),"X),"X),"X),"X),"x,X,x,x,x,x,x,x,

&&&&&&&&&&&

16,16,16,16,16,16,16,16,

-- Merged In/Cntrl-- Merged In/Cntrl

0,0,0,0,0,0,0,0,

Z),"Z),"Z),"Z),"Z), "Z),"Z),"Z)";

&&&&&&&

-- This is where BSDL_EXTENSIONs would appear.-- This is where DESIGN_WARNING would appear.

end ttl74bct8374;

2.6 PACKAGES AND PACKAGE BODIES

Packages and package bodies are VHDL files containing supporting information that isimported into an entity definition. It is analogous to the concept of inclusion orimportation found in other languages. In BSDL, the main information about an IC isconveyed in an entity description described in section 2.3. There, the statement "use

"3

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STD_1149_l_1999.all” (section 2.3.3) is used to set up the definition of the BSDLenvironment. User-defined packages may then be included with additional “use”statements to allow BSDL to mirror the extensibility of the 1149.1 Standard.

A VHDL package can contain definitions of data structures and may also containpre-defined constants constructed from those definitions. If a definition is ever changedthen anything that ever references that package would have to be re-compiled (re-analyzed in VHDL parlance).

A package body, associated with a package, can be used to contain pre-definedconstants. The advantage of this is that if the definition of a constant’s contents ischanged, everything that references the associated package does not have to be re-analyzed. This is how packages and package bodies are used for BSDL.

The basic definition of the BSDL environment (the data structures) is given in astandard BSDL package called STD_1149_1_1999, which has an associated packagebody that contains (to date) seven constant definitions representing 1149.1 BoundaryRegister cell designs. This information is considered the foundation definition ofBSDL and should only change when BSDL itself is revised. This package wouldtypically be write-protected on a BSDL based system to prevent modification.

2.6.1 STD_1149_1_1999The information contained in STD_1149_1_1999 is documented next. This includesboth the package and package body. Following this is a set of figures and discussionabout the cell definitions given in the package.

package STD_1149_1_1999 is

-- Give component conformance declaration

attribute COMPONENT_CONFORMANCE : string;

— Give pin mapping declarations

attribute PIN_MAP : string;subtype PIN_MAP_STRING is string;

— Give TAP control declarations

type CLOCK_LEVEL is (LOW, BOTH);type CLOCK_INFO is recordFREQ : real;LEVEL: CLOCK_LEVEL;

end record;

attributeattributeattributeattributeattribute

TAP_SCAN_IN :TAP_SCAN_OUT :TAP_SCAN_CLOCK :TAP_SCAN_MODE :TAP_SCAN_RESET:

boolean;boolean;CLOCK_INFO;boolean;boolean;

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86 Boundary-Scan Description Language (BSDL)

-- Give instruction register declarations

attribute INSTRUCTION_LENGTH : integer;attribute INSTRUCTION_OPCODE : string;attribute INSTRUCTION_CAPTURE : string;attribute INSTRUCTION_PRIVATE : string;

-- Give ID and USER code declarations

type ID_BITS is ('0', '1', 'x', 'X');type ID_STRING is array (31 downto 0) of ID_BITS;attribute IDCODE_REGISTER : ID_STRING;attribute USERCODE_REGISTER: ID_STRING;

-- Give register declarations

attribute REGISTER_ACCESS : string;

-- Give boundary cell declarations

type BSCAN_INST is (EXTEST, SAMPLE, INTEST);type CELL_TYPE is (INPUT, INTERNAL, CLOCK, OBSERVE_ONLY,CONTROL, CONTROLR, OUTPUT2,OUTPUT3, BIDIR_IN, BIDIR_OUT);type CAP_DATA is (PI, PO, UPD, CAP, X, ZERO, ONE);type CELL_DATA is recordCT : CELL_TYPE;I : BSCAN_INST;CD : CAP_DATA;

end record;type CELL_INFO is array (positive range <>) of CELL_DATA;

-- Boundary cell deferred constants (see package body)

constant BC_0constant BC_1constant BC_2constant BC_3constant BC_4constant BC_5constant BC_6constant BC_7

CELL_INFO;CELL_INFO;CELL_INFO;CELL_INFO;CELL_INFO;CELL_INFO;CELL_INFO;CELL_INFO;

-- Boundary register declarations

attribute BOUNDARY_LENGTH : integer;attribute BOUNDARY_REGISTER : string;

-- Miscellaneous

attribute PORT_GROUPING : string;attribute RUNBIST_EXECUTION : string;attribute INTEST_EXECUTION : string;

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subtype BSDL_EXTENSION is string;attribute COMPLIANCE_PATTERNS : string;attribute DESIGN_WARNING : string;

end STD_1149_1_1999; -- End of 1149.1-1999 Package

package body STD_1149_1_1999 is -- Standard boundary cells

-- Generic cell capturing minimum allowed data

constant BC_0 : CELL_INFO :=((INPUT, EXTEST, PI), (OUTPUT2, EXTEST, X),(INPUT, SAMPLE, PI), (OUTPUT2, SAMPLE, PI),(INPUT, INTEST, X), (OUTPUT2, INTEST, PI),(OUTPUT3, EXTEST, X), (INTERNAL, EXTEST, X),(OUTPUT3, SAMPLE, PI), (INTERNAL, SAMPLE, X),(OUTPUT3, INTEST, PI), (INTERNAL, INTEST, X),(CONTROL, EXTEST, X), (CONTROLR, EXTEST, X),(CONTROL, SAMPLE, PI), (CONTROLR, SAMPLE, PI),(CONTROL, INTEST, PI), (CONTROLR, INTEST, PI),(BIDIR_IN,EXTEST, PI), (BIDIR_OUT, EXTEST, X ),(BIDIR_IN,SAMPLE, PI), (BIDIR_OUT, SAMPLE, PI),(BIDIR_IN,INTEST, X ), (BIDIR_OUT, INTEST, PI),(OBSERVE_ONLY, SAMPLE, PI), (OBSERVE_ONLY, EXTEST, PI) );

-- Description for the cell shown in Figure 2-11 on page 92.

constant BC_1 : CELL_INFO :=((INPUT, EXTEST, PI), (OUTPUT2, EXTEST, PI),(INPUT, SAMPLE, PI), (OUTPUT2, SAMPLE, PI),(INPUT, INTEST, PI), (OUTPUT2, INTEST, PI),(OUTPUT3, EXTEST, PI), (INTERNAL, EXTEST, PI),(OUTPUT3, SAMPLE, PI), (INTERNAL, SAMPLE, PI),(OUTPUT3, INTEST, PI), (INTERNAL, INTEST, PI),(CONTROL, EXTEST, PI), (CONTROLR, EXTEST, PI),(CONTROL, SAMPLE, PI), (CONTROLR, SAMPLE, PI),(CONTROL, INTEST, PI), (CONTROLR, INTEST, PI) );

-- Description for the cell shown in Figure 2-12 on page 93.

constant BC_2 : CELL_INFO :=((INPUT, EXTEST, PI), (OUTPUT2, EXTEST, UPD),(INPUT, SAMPLE, PI), (OUTPUT2, SAMPLE, PI),(INPUT, INTEST, UPD), -- Intest on output2 not supported(OUTPUT3, EXTEST, UPD), (INTERNAL, EXTEST, PI),(OUTPUT3, SAMPLE, PI), (INTERNAL, SAMPLE, PI),(OUTPUT3, INTEST, PI), (INTERNAL, INTEST, UPD),(CONTROL, EXTEST, UPD), (CONTROLR, EXTEST, UPD),(CONTROL, SAMPLE, PI), (CONTROLR, SAMPLE, PI),(CONTROL, INTEST, PI), (CONTROLR, INTEST, PI) );

-- Description for the cell shown in Figure 2-13 on page 94.

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88 Boundary-Scan Description Language (BSDL)

constant BC_3 : CELL_INFO :=((INPUT, EXTEST, PI), (INTERNAL, EXTEST, PI),(INPUT, SAMPLE, PI), (INTERNAL, SAMPLE, PI),(INPUT, INTEST, PI), (INTERNAL, INTEST, PI) );

-- Description for the cell shown in Figure 2-14 on page 95.

constant BC_4 : CELL_INFO :=((INPUT, EXTEST, PI), -- Intest on input not supported(INPUT, SAMPLE, PI),(OBSERVE_ONLY, EXTEST, PI),(OBSERVE_ONLY, SAMPLE, PI), -- Intest on observe_only

-- not supported(CLOCK, EXTEST, PI), (INTERNAL, EXTEST, PI),(CLOCK, SAMPLE, PI), (INTERNAL, SAMPLE, PI),(CLOCK, INTEST, PI), (INTERNAL, INTEST, PI) );

-- Description for the cell shown in Figure 2-15 on page 95.

constant BC_5 : CELL_INFO :=((INPUT, EXTEST, PI), (CONTROL, EXTEST, PI),(INPUT, SAMPLE, PI), (CONTROL, SAMPLE, PI),(INPUT, INTEST, UPD), (CONTROL, INTEST, UPD) );

-- Description for a reversible cell. Used for backward-- compatibility only.

-- !! Not recommended; replaced by BC_7 below!!

constant BC_6 : CELL_INFO :=((BIDIR_IN, EXTEST, PI), (BIDIR_OUT, EXTEST, UPD),(BIDIR_IN, SAMPLE, PI), (BIDIR_OUT, SAMPLE, PI),(BIDIR_IN, INTEST, UPD), (BIDIR_OUT, INTEST, PI) );

-- !! Recommended over cell BC_6!!

-- The BC_7 design will always monitor the driver output,-- as shown in Figure 2-16 on page 97.

constant BC_7 : CELL_INFO :=((BIDIR_IN, EXTEST, PI), (BIDIR_OUT, EXTEST, PO),(BIDIR_IN, SAMPLE, PI), (BIDIR_OUT, SAMPLE, PI),(BIDIR_IN, INTEST, UPD), (BIDIR_OUT, INTEST, PI) );

end STD_1149_1_1999; -- End of IEEE Std 1149.1-1999 Body

In the above set of definitions for Boundary Register cells (in the package body)you will see comments that call out figure drawings in this book to help you recognizethe architecture of cells versus the names given in the package. A description of thesecells and their figures is given in section 2.6.3, and a detailed discussion of howBoundary Register cells are described in BSDL is given in the next section.

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2.6.2 Cell Description ConstantsBoundary-Scan Boundary Register cell designs are documented in packages bodiessuch as STD_1149_1_1999 using constants of type CELL_INFO. In that package onecan find the definition of CELL_INFO. It is an unconstrained array of CELL_DATArecords. "Unconstrained" means the array size is defined at the time the constant isdefined. Each CELL_DATA record contains three fields

28 that define how the cell

behaves upon passing through CAPTURE-DR. Each field is an enumerated type. Thefields are:

the CELL_TYPE field. This field identifies the context that the cell can beused in within a component design. Its values may be INPUT, INTERNAL,CLOCK, CONTROL, CONTROLR, OUTPUT2, OUTPUT3, OBSERVE_ONLY,BIDIR_IN and BIDIR_OUT. (See discussion below.)

the BSCAN_INST field. This field identifies an instruction supported by thiscell. The values allowed in this field are EXTEST, SAMPLE, and INTEST. Allcells are required to support SAMPLE and EXTEST.

the CAP_DATA field. This field identifies the source of the data captured bythe capture (CAP) flip-flop in a given context and for a given instruction. Itsvalues must be PI, PO, UPD, CAP, X, ZERO and ONE. (See discussionbelow.)

A Boundary Register cell design such as shown Figure 2-11 is very versatile andmay be used in a number of contexts; it may serve as an input cell, an output cell, aninternal cell, a control cell, and so on. (This cell is called BC_1 in the standardpackage.) For compactness, eliminating the need for a description for each context, theCELL_TYPE field allows us to state the allowable contexts the cell can be used in.Table 2-4 gives the definitions of the CELL_TYPE field symbols.

28It is a BSDL standard practice that these fields be defined positionally (as shown) rather

than by VHDL field tagging. The order of the fields is significant.

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90 Boundary-Scan Description Language (BSDL)

The CAP_DATA field can be determined by tracing backward from the captureflip-flop through the various multiplexers until the source of the captured data is found.We use an abstraction of a Boundary Register cell to show the various sources ofcapture data, shown in Figure 2-10.

match the capture data sources shown in Figure 2-10. Two of these symbols, PI(parallel input) and PO (parallel output) must be interpreted in the context that the cellis used. For example, if the cell may be used at an IC input, then PI must be interpretedas the IC input pin and PO must be interpreted as the output that drives System Logic.If, on the other hand, the cell is serving an IC output, then PO must be interpreted asthe IC output pin after any driver and PI must be interpreted as a System Logic output.This is important for many software applications because they often will not know howthe system logic behaves. Thus, capturing a System Logic output will be associatedwith the unknown value "X" by these applications.

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For a bidirectional such as shown in Figure 2-16, the context is complicated by thedirection that the cell is currently serving. Such a cell has a collection of multiplexersthat reverse the apparent direction of data. While the cell is operating as bidir_out asgoverned by its attending control cell, then PO is the IC pin and PI is the SystemLogic. While the cell is operating as bidir_in, then PI is the IC pin and PO is theSystem Logic. Note that in the attribute BOUNDARY_REGISTER description, thefunction field (see Table 2-2 on page 74) for a reversible cell is coded as bidir while ina CELL_DATA description, the symbols bidir_in and bidir_out are used to incorporatethe direction information.

2.6.3 Basic Cell Definitions BC_0 to BC_7In the previous section (2.6.1) we saw constants that describe certain “standard” cellscommonly found in 1149.1 implementations, as given in the Standard itself. Theseconstants were labeled BC_0 through BC_7, and new cells designs may beintroduced in the future. Indeed, BSDL has reserved the names BC_0 throughBC_99 to give the capability to define 100 “standard” cell designs, although it isvery unlikely the Working Group will ever define more than a fraction of these.

This section shows some common architectures of cell designs, extracted fromthe Standard itself. If you examine the chapter titled “The Boundary-Scan Register”in the Standard in detail, you will see many examples of cell architectures, but manyof these are based on a common theme. BSDL has extracted these commonarchitectures and labeled them for reference purposes with the result that there areonly seven basic architectures.

Seven cells? Yes. The cell BC_0 is a special case. The Working Group added itto BSDL to serve as a “minimum” cell description that satisfies all the rules for cellarchitecture but has no additional capabilities. It is intended to be used as a “default”cell design when the situation arises where you need to describe an IC’s 1149.1implementation, but do not know the exact details of the Boundary Register cellarchitectures used in the design. A BC_0 cell definition should allow software toolsto provide minimum basic performance. Of course, using BC_0 also means areduction in test diagnostic resolution if a device actually contains more advancedcell designs. If you know (or can find out) the actual cell design information, thenyou should avoid using the BC_0 default.

Cell BC_1This cell architecture is shown in Figure 2-11. It is a very basic design and also veryflexible. It can be used in many contexts; as an input cell, an output cell, a controlcell, an internal cell and as a building block for handling bidirectional pins.Furthermore it will support all 1149.1 instructions that deal with the BoundaryRegister, including INTEST. This cell is typified by the fact that it contains amultiplexer in the system signal path that is placed at the exit of the cell to theParallel Output.

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Cell BC_2This cell architecture differs from BC_1 in that there is a multiplexer in the signalpath placed at the entrance of the cell from the Parallel Input. Examining Figure 2-12you will see that the Capture flip-flop can capture the content of the Update latchwhen the Mode control signal is set to “1”. This feature increases the testability ofthe 1149.1 logic29 itself; if, for example you use BC_2 cells at input pins, then theUpdate latch and the “1” pathway through the series multiplexer are now testable(using the INTEST instruction) without requiring data to be propagated through thesystem circuitry.30 (The BC_1 design does require that the system circuitry beinvolved in testing these same portions of an input Boundary Register cell.)

29It is important to consider how the 1149.1 circuitry will be verified during production of the

IC. This is one reason why some will want to include the 1149.1 circuitry within anothertestability discipline such as internal scan (for example LSSD). If another testability schemesubordinates 1149.1 (see section 1.7 on page 41), then the testability of a given cell design in1149.1 operation may not be an issue.30

This feature may not be utilized by ATPG software however. You should investigate thecapabilities of an ATPG algorithm if this feature will be important to you.

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BC_2 is also very flexible in that it can be used for input cells, output cells,internal cell, control cells and in some composite bidirectional cell structures.However, this cell has a subtle limitation with respect to INTEST support; if the cellis used to support a two-state output pin, where the two-state driver is integrated intothe signal path multiplexer, then this cell does not satisfy a rule for INTEST. Thisrule requires that the cell capture the system output, but because of the placement ofthe multiplexer, a faulty state on the output pin could be captured rather than thesystem output value. Table 2-7 shows mode assignments for cell BC_2 for the casewhere the cell is used to service an input versus being used to service an output ordriver enable control.

Cell BC_3Cell BC_3 shown in Figure 2-13 is a cell, used only for inputs (or internal cells), thatdoes not possess an Update latch but does support INTEST. One of the principlereasons for providing an Update latch is to prevent shift ripple that occurs on theoutput of the Capture flip-flop while shifting data. from being propagated to theparallel output of the cell. This data noise would then be presented to the systemcircuitry where it might have unwanted effects. However, for some system circuitry(notably, combinatorial circuitry) this shift noise would have no harmful effects nor

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94 Boundary-Scan Description Language (BSDL)

would it even be detectable from outside the IC. For applications where this will betrue, a BC_3 design will have the (small) economy of eliminating the Update latchand its clock signal.

Cell BC_4Cell BC_4 shown in Figure 2-14 also has no Update latch and it eliminates the seriesmultiplexer from the system signal path as well. This is attractive because it removessome potential signal delay from the system signal pathway. The price foreliminating delay is that the cell does not support INTEST on general input pins. IfINTEST functionality is desired in an IC, then the BC_4 cell design cannot be usedon any input pin except a system clock

31input.

31Omitting INTEST control (by using cell BC_4) from a clock pin eliminates delay from a

pin that could be extraordinarily sensitive to inserted skew and propagation effects due toBoundary-Scan. However, it creates the complication of coordinating system clocks with anINTEST application.

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Cell BC_4 has no mode signal supplied by the TAP instruction decoder.

Cell BC_5Cell BC_5 is shown in Figure 2-15. This cell is virtually identical to the BC_2architecture, but is only used for controlling output driver enables. The difference isdue to the AND function that inserts another control variable (shown as Mode3) intothe signal used to turn a driver on or off.

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This new mode signal comes from the TAP instruction decoder just as othermode signals do. In this example, when Mode3 is low, the associated driver isdisabled. This is used to implement the HIGHZ instruction and the HIGHZ-typeBoundary Register control feature that INTEST and RUNBIST may exhibit32 aswell.

Cell BC_6Cell BC_6 is used as a data cell at a bidirectional system pin, but it is not shown in afigure in this book because the 1149.1 Working Group is actively discouraging itsfurther use in Boundary-Scan implementations. The cell architecture called BC_7should be used in its place.

Cell BC_6 does conform to the rules of the Standard, but is seriously limited inone respect. It cannot monitor the state of its bidirectional pin when the pin’s driveris enabled to drive data out. Pin monitoring capability is inherently available inmulti-cell bidirectional structures we saw in Figure 1-8 (page 23) and is nowprovided by the BC_7 architecture, also a single-cell implementation. Pin monitoringat all times gives important diagnostic capability that the Working Group wants topromote.

The BC_6 architecture was only promoted with the first edition [IEEE90] of the1149.1 standard. Since the release of Supplement A [IEEE93] it has beendiscouraged. If you have an older design for Boundary Register cells supportingbidirectional pins, you should examine them to see if they are indeed utilizing theBC_6 architecture. If so, you should convert them to the BC_7 architecture.

33

32HIGHZ behavior also controls two-state outputs which implies a special mode signal for

them as well. However there is no explicit cell design showing this in BSDL since the modesignal would be passed directly to the output driver rather than the upstream BoundaryRegister cell.33

It may be true that the ATPG software you plan to use cannot tell the difference between aBC_6 and BC_7 architecture. Such limited software will probably make the assumption thatall bidirectional cells act like BC_6. If you are designing an IC to be used by others outsideyour industry segment, you should assume that they have access to a fully capable ATPGalgorithm that can use the advanced capability offered by BC_7. In any event, it is a goodquestion to put to the provider of your ATPG algorithms.

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Cell BC_7The BC_7 Boundary Register cell architecture shown in Figure 2-16 (in the dottedline box) is a single data cell that supports bidirectional system pins.

BC_7 can provide data to the output driver and also monitor the pin activity evenwhen the output driver is driving the pin. This is an important feature that waslacking in the BC_6 architecture just documented. and is a feature inherent in thedouble-celled implementation for a bidirectional pin shown in Figure 1-8 on page23. Monitoring a pin while it is driving can be used by diagnostic software todiscover that a driver is looking into a short and is thus not capable of delivering the

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98 Boundary-Scan Description Language (BSDL)

requested pin state. This is doubly important when the signal being driven does nottravel to other Boundary-Scan ICs.

The “sea of multiplexers” in Figure 2-16 can be confusing. It may be helpful tomake copies of the figure and mark it with a highlighting pen to trace the data flowunder various conditions. For example, if the cell is acting as an output (the controlcell contains a “1”) with the EXTEST instruction loaded (setting the three Modesignals to 101), you can see how data must move through the cell. Similar tracingswill show how the other instructions route data for the cell behaving as either inputor output.

Contrasting the double-celled implementation with BC_7, it is obvious that thedouble-celled approach is very straightforward and that the BC_7 approach containsmore circuitry in the form of additional multiplexers. So it is probably true that eachapproach contains about the same silicon area. So why would you use a BC_7? Oneimportant advantage is that BC_7 reduces the cell count of an IC, by requiring onlyone data cell per bidirectional pin versus two. Since most ICs these days are heavyusers of bidirectional pins, you could see savings in cell counts

34from 30% to nearly

50%. Since ICs have growing pin counts, this can easily represent saving scores oreven hundreds of cells per IC.

Cell count matters when practical application of 1149.1 is studied. When manyICs are strung together into Boundary-Scan chains, the lengths of the BoundaryRegisters can accumulate into a very long total register length. This directly impactsshift time and since Boundary-Scan tests are often stored for future use, the length ofthese registers dictates storage space35 and the time to move this data around.Another practical problem is that a given 1149.1 master architecture (like an ATEsystem) will ultimately have to break up a shifting process into manageable pieces.These pieces are separated by overhead processing which may significantly delay theoverall shift time and thus reduce throughput.

34The variability in savings is influenced by the number of control cells included to enable

collections of bidirectional pin drivers.35

It also influences the length of the BSDL used to describe the IC, which you may have towrite!

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Note that the control cell circuitry shown above the dotted line box shown inFigure 2-16 is a BC_5 control cell design. The entire structure shown is capable ofsupporting a complete set of instructions. If, for example, INTEST were not ofinterest in your IC, you could eliminate the Mode2 signal and a multiplexer.

36

Further, eliminating HIGHZ and the HIGHZ-type option for RUNBIST eliminatesthe need for Mode3 and the AND gate in the BC_5 structure which reduces it toBC_2.

2.6.4 User-Defined Boundary CellsSuppose a designer wanted to implement a component that could give an informal self-identification rather than suffer the overhead of the IDCODE instruction. The designercould do this by implementing a cell structure such as in Figure 2-17 where a newmultiplexer has been added to route a constant 1 (or 0) into the capture (CAP) flip-flopwhenever EXTEST is in effect. This cell could be used as an output cell, a controlcell

37or an internal cell. Then, by using combinations of these cells that capture 0 or 1

during EXTEST at various locations within the chain, the IC could uniquely identifyitself whenever captured EXTEST data was shifted out.

The next problem is to communicate this capability in a BSDL description. This isdone by creating a user-defined package and package body that describe two new cellsas in the example below. There, the two cells are named USER_0 and USER_1. Thesenames will be used in the component entity description, in field 1 of the BoundaryRegister description (see section 2.3.13 on page 72). BSDL-based software then knowsfrom the package body that during EXTEST, the cells capture their respectiveconstants.

36With appropriate assignment of the “X” values for Mode2, you can make it the complementof Mode3. Then you can remove one of these signals.

37This cell design will not support cell merging of a control cell with an input cell because thecapture flip-flop cannot capture data from two different sources at the same time.

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The example package and package body, titled "USER_PACKAGE" looks likethis:

package USER_PACKAGE is

-- Boundary Cell deferred constants (see package body)

use STD_1149_1_1999.all; -- Get definition of "Cell_Info"

constant USER_0 : CELL_INFO;constant USER_1 : CELL_INFO;

end USER_PACKAGE; -- End of User Package

package body USER_PACKAGE is -- User Boundary Cells

use STD_1149_1_1999.all;

constant USER_0 : CELL_INFO :=((OUTPUT2,(OUTPUT2,(OUTPUT3,(OUTPUT3,(OUTPUT3,(OUTPUT3,(CONTROL,(CONTROL,(CONTROL,(CONTROL,

EXTEST,INTEST,EXTEST,SAMPLE,INTEST,RUNBIST,EXTEST,SAMPLE,INTEST,RUNBIST,

ZERO),PI),ZERO),PI),PI),PI),ZERO),PI),PI),PI),

(OUTPUT2,(OUTPUT2,(INTERNAL,(INTERNAL,(INTERNAL,(INTERNAL,(CONTROLR,(CONTROLR,(CONTROLR,(CONTROLR,

SAMPLE,RUNBIST,EXTEST,SAMPLE,INTEST,RUNBIST,EXTEST,SAMPLE,INTEST,RUNBIST,

PI),PI),ZERO),PI),PI),PI),ZERO),PI),PI),PI) );

constant USER_1 : CELL_INFO :=((OUTPUT2,(OUTPUT2,(OUTPUT3,(OUTPUT3,(OUTPUT3,(OUTPUT3,(CONTROL,(CONTROL,(CONTROL,(CONTROL,

EXTEST,INTEST,EXTEST,SAMPLE,INTEST,RUNBIST,EXTEST,SAMPLE,INTEST,RUNBIST,

ONE),

PI),ONE) ,PI),PI),PI),ONE),PI),PI),PI),

(OUTPUT2,(OUTPUT2,(INTERNAL,(INTERNAL,(INTERNAL,(INTERNAL,(CONTROLR,(CONTROLR,(CONTROLR,(CONTROLR,

SAMPLE,RUNBIST,EXTEST,SAMPLE,INTEST,RUNBIST,EXTEST,SAMPLE,INTEST,RUNBIST,

PI),PI),ONE),PI),PI),PI),ONE),

PI),PI),PI) );

end USER_PACKAGE; -- End of User Package Body

2.6.5 Definition of BSDL ExtensionsA user-defined package can also be used to contain definitions of BSDL extensions.Then, by referencing the package with a “use” statement (see sections 2.3.4 and2.3.16) the declarations of the extensions become available to a BSDL description.Consider this example:

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Package Global_Def is -- An example BSDL extension package-- Does not define boundary cells, just extensions

use STD_1149_1_1999.all;

-- Deferred constant declarations go here, if any

attribute First_extension : BSDL_EXTENSION; -- Declare BSDLattribute Second_extension : BSDL_EXTENSION; -- extensionsattribute Third_extension : BSDL_EXTENSION; -- here.

end Global_Def;

package body Global_Def is

use STD_1149_1_1999.all;

-- Deferred constant definitions go here, if any

end Global_Def;

Any of the three extensions declared in this package are now available for referencein BSDL descriptions that “use” this package.

2.7 WRITING BSDL

How does one go about writing a BSDL description? First, you must gatherinformation about the 1149.1 implementation within the IC to be described. Once youhave this information, it is a fairly simple process to transcribe it into BSDL. Somepeople choose to take an existing BSDL description and edit it into the new one. Asimilar approach taken by some is to create a BSDL template with guiding commentsembedded within it to prompt the writer for the correct style and organization.

The following list will help you gather the needed information and write theBSDL description. Note that in several places, mandatory statements must appearthat are common (for example, the "use" statement) to any BSDL. Editing a templateor existing file will help you remember these statements and their placement.

1.

2.

3.

Identify the component with a name. This will become the entity name that issprinkled throughout a BSDL description. Remember it must begin with analpha character.

Find all packaging configurations for the component. Typically, ASICs orother one-of-a-kind components will have only one packaging option, butmerchant components may have several.

Examine the packaging configurations. Make sure all the pin names are validVHDL identifiers. This will now allow you to write the port statement (see2.3.2) for the entity. You may choose to use the bit_vector shorthand for buses,or give each pin a unique name.

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102 Boundary-Scan Description Language (BSDL)

4.

5.

6.

7.

8.

9.

10.

11.

12.

13.

14.

15.

After the port statement, write the “standard use” statement (see 2.3.3). Youmay need to come back to this spot later to add a user-defined package “use”statement (see 2.3.4) if step 13 below turns up any user-defined cell designs.

Write the component conformance statement (see 2.3.5). Remember that thisidentifies the release of the Standard that governed the design of the IC.

Write the pin mapping constants for all package configurations (see 2.3.6).Name these constants with recognizable names such as "PGA_18xl8" or"PQFP_64." If there is only one constant, consider making the genericparameter default to this value (see 2.3.1).

Does this device have any differential signals? If so, use a grouped portstatement to describe them (see 2.3.7).

Identify the TAP Port pins. Write the TAP pin attributes. Don’t forget TRST*if it exists. (See 2.3.8.)

This step is very important; if this device has any compliance enable pins, besure to document them (see 2.3.9). Lack of this information can cause uglydebugging problems later.

Find the TAP instruction set for the IC; the length of the Instruction Register,the instructions names and opcode bit patterns. Then write theInstruction_Length and Instruction_Opcode attributes. (See 2.3.10.)

Find the Instruction Register capture pattern, the bits it captures at CAPTURE-IR. The least two should be "01" and any higher order bits may be constants ordesign-dependent. Those that are constants can be written so, but variable bitswill have to be coded as "X". Write the Instruction_Capture attribute. (See2.3.11.) If any of the instructions are considered private, then write anInstruction_Private attribute that identifies them.

If any user-defined instructions exist, find out which register(s) they access.Note any public instructions that access user-defined registers. Then write theRegister_Access attribute for these, taking care to define the lengths of user-defined registers. If any of the user-defined registers capture static bits, denotethis with a “captures” clause. (See 2.3.12.) If any instructions were markedprivate in step 10 above, you may choose to omit them from this attribute.

Begin investigating the Boundary Register construction. Note its length andorganization. Find out what cell designs were used. If any are special designsnot covered by cell definitions BC_1 through BC_6 given inSTD_1149_1_1999, then you will need to write a user-defined supportingpackage that gives their behavior (see section 2.6.4 on page 99). This packagemight already exist if the IC reuses cell designs from other ICs. Don’t forget toadd another "use" statement (see step 4 and 2.3.4) to refer to this new package.

Write the two attributes that describe the Boundary Register (see 2.3.13). Theyare Boundary_Length and Boundary_Register.

Does this device support RUNBIST and/or INTEST? Then considerdocumenting their behavior with the associated execution statements (see2.3.14 and 2.3.15).

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16.

17.

18.

Do you wish to document any additional data beyond the current definition ofBSDL? If so, consider using BSDL extensions (see 2.3.16) to place thisinformation within your BSDL file.

Does any design-specific information need to be documented so that otherpeople using this description will be alerted to its existence? If so, consideradding a Design_Warning attribute (see 2.3.17).

End the entity with an end statement.

The main effort in creating a BSDL usually goes into the package-pin mappingsince typographical errors are easy to make, and into describing the Boundary Register.In particular, the cell designs used in the Boundary Register and the sense of thedisabling bits for drivers seems to be difficult to dig up. Sometimes the originaldesigner must be located to supply this data. Remember, after creating a BSDLdescription it is very important to verify its accuracy. This will be covered in Chapter5.

You might ask, “I am not an IC designer so I cannot use these wonderful BSDLgenerator/checkers. Can I avoid writing BSDL?” The answer is “maybe”. Consider the

38work reported in [Raym95]. Here, they used a hardware simulation of a target IC anda minimum of advance knowledge of the IC; like which pins are the TAP pins and soon. Then the hardware simulation painstakingly performs experiments on the IC toslowly deduce its basic structure. It finds the BYPASS instruction, IDCODE (if there),EXTEST and SAMPLE. Once it knows EXTEST it then works to find the length ofthe Boundary Register and then, one-by-one finds the I/O mapping. This process couldpotentially take hours of time, but if overnight you get a workable BSDL from it, thatsounds like a good deal.

The process will only find out the most basic facts about the IC. It will not discoveradvanced cell designs, for example. However, it may well be good enough to doelementary Boundary-Scan testing.

2.8 SUMMARY

BSDL exists in recognition of several problems. First, the 1149.1 Standard, whileconceptually simple, contains a great deal of detail that must be communicatedaccurately. Second, software to support Boundary-Scan will be essential. Third, thissoftware will come from many sources crossing boundaries among industry segments.

A standardized description language serves as a canonical form for 1149.1information. This form helps to ensure that all necessary data is described and iseasily interpreted by software. Without this standardization, much needless workmust be done to send 1149.1 data between industry segments.

38In a hardware simulation, the IC is actually mounted in a socket on a tester, powered up,

and driven with signals while the responses are learned. This requires both a tester and aknown-good copy of the IC in question.

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39At this writing 459 copies of the BSDL Version 0.0 parser have been directly

distributed by Hewlett-Packard to people in countries ranging from Australia toYugoslavia. The desire for effortless interchange of 1149.1 data is real.

39This parser was developed to handle the first (non-IEEE) version of the language. Since the

IEEE version of BSDL is substantially similar to the first version, and since most people wantto augment their existing BSDL parsing software to accept both versions of the language,Hewlett-Packard did not release a second IEEE version of the parser specification.

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CHAPTER 3

Boundary-Scan Testing

Boundary-Scan testing is aimed primarily at digital logic structures, althoughBoundary-Scan assets can provide invaluable resources for assisting with mixeddigital/analog testing as well. This chapter covers various test approaches utilizing1149.1.

Before launching into a discussion of Boundary-Scan testing, it is important toagree on what we are testing for. Boundary-Scan testing is primarily focusedoutward from ICs, since the mandatory features of 1149.1 are set up to supporttesting of the interconnect between Boundary-Scan devices. Other optionalBoundary-Scan features, if present, will allow various degrees of testing within agiven IC. Also, the fact that we are using the internal Boundary-Scan features of aset of ICs will give us identification information about each IC as a side effect.

Boundary-Scan testing is good at detecting solder problems between devices andboards; too much solder will often lead to solder bridges (shorts) between devicepins. Too little solder may lead to open pins. Pins may get bent duringmanufacturing, leading to shorts and opens. If a device has had a pin driver orreceiver damaged by Electrostatic Discharge (ESD), this will be detected byBoundary-Scan testing. If a device is rotated 180 degrees before it is placed on theboard, this will be detected as a device within a chain that does not operate at all.Figure 3-1 shows examples of some manufacturing defects affecting solder.

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106 Boundary-Scan Testing

Boundary-Scan is not a good technology for detecting or diagnosing certainproblems. For example, say ESD damage has occurred in a transistor deep inside adevice, far from the Boundary-Scan logic. Unless a (very thorough) Built-in Self-Test accessible via a TAP instruction is run, this defect will not be discovered byBoundary-Scan testing. Similarly, if a device has a parametric defect (for example,its propagation delay slightly exceeds specifications), it is unlikely that Boundary-Scan testing will find this problem. If a solder joint is marginal but continuity stillexists, Boundary-Scan will not see a problem.

Boundary-Scan testing is primarily aimed at finding and diagnosing majormanufacturing defects; bad devices, rotated devices, bad solder joints, blown drivers,and so on. It is not able (without the addition of optional or user-defined capabilities)to find subtle problems unrelated to manufacturing errors such as parametric defectswithin ICs. Boundary-Scan testing essentially assumes that perfect devices are usedin an imperfect manufacturing process, and we want to find the manufacturingdefects that result.

3.1 BASIC BOUNDARY-SCAN TESTING

Basic testing with Boundary-Scan requires detailed use of the TAP state diagram andthe fundamental TAP instructions BYPASS, PRELOAD, EXTEST, SAMPLE andother optional instructions (if present) such as RUNBIST, IDCODE, CLAMP,HIGHZ or INTEST. The fundamental 1149.1 scanning sequence is described next asa basic building block.

3.1.1 The 1149.1 Scanning SequenceIn this section, we will examine the basic operation of the 1149.1 Standard. Many ofthe operations we need to perform testing will utilize the Boundary-Scan logic and

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the TAP state diagram in the same way. The following discussion will examine asingle IC containing Boundary-Scan. Later, we will look at the implications ofoperating chains of ICs.

In nearly all cases when we want to use the 1149.1 test logic, we must start byinitializing it to the TEST-LOGIC-RESET state. Because it is not a safe assumptionthat the test logic is already in this state, and since not all ICs possess the optionalTRST* pin, a robust test sequence should begin with a Boundary-Scansynchronizing sequence: hold TMS high for five cycles of TCK. This forces the TAPinto TEST-LOGIC-RESET regardless of its starting state. Once the logic is reset, weneed to set up an instruction in the TAP Instruction register.

Figure 3-2 traces the operation of the TAP state machine to accomplish this.Note we proceed to the SHIFT-IR state using only the TMS and TCK signals. Whenwe reach SHIFT-IR the TDO pin becomes active (it was disabled) and data can beshifted in via TDI.

Because we passed through CAPTURE-IR to get to SHIFT-IR, the shift portion ofthe Instruction Register, which is placed between TDI and TDO, now contains theInstruction Capture pattern. This is the data that will appear on TDO while we areshifting the desired instruction bit pattern into TDI. This data can be checked as itcomes out on TDO to see if it matches what we expect; the capture pattern specifiedin the BSDL description using the attribute INSTRUCTION_CAPTURE. If theinstruction register is N bits long, we cycle back to SHIFT-IR N-1 times, each timepresenting a new bit

1of the instruction code to TDI. The bit is shifted while

taking the transition to EXIT1-IR..

1The bits are shifted in via TDI, starting with the least significant bit.

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At this point, we have a new instruction code in the shift portion of theInstruction Register. This new instruction becomes effective upon passing throughUPDATE-IR, when it is transferred to the parallel hold portion of the register. Notethat this is the time that a Pin-Permission mode of operation would be entered if thatis what the loaded instruction calls for.

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Figure 3-3 then shows how we set up to utilize the new instruction and the dataregister that it targets. First, we travel to CAPTURE-DR by way of UPDATE-IR.Passing UPDATE-IR sets up the new instruction and targets the appropriate dataregister between TDI and TDO.

The shift portion of the target data register captures parallel data upon exitingCAPTURE-DR and entering SHIFT-DR. The nature of this parallel data dependsupon the register and the current instruction. For example, if the BYPASS instructionis in effect, then the BYPASS register captures a “0” as the Standard requires. IfEXTEST is in effect, then the Boundary Register captures parallel I/O data. IfIDCODE is in effect, the DEVICE_ID register captures the 32-bit DeviceIdentification code for the component, and so on.

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110 Boundary-Scan Testing

We are then ready to shift this register as shown in Figure 3-4. As we saw beforewith the Instruction Register, we need to loop back upon the SHIFT-DR state untilN-1 bits have been shifted. The last bit is shifted on the transition to the EXIT1-DRstate. Typically, we want to shift N bits where N is the length

2of the target register.

While this shifting is occurring, the captured bits are transmitted out by TOO whilenew bits are entering via TDI. These bits that enter will become the new residents ofthe shift portion of the target register. When shifting is completed, they will be

2 Application software must keep track of N by knowing what register is targeted by thecurrent TAP instruction. A BSDL description contains the length of all registers and theirassociations with TAP instructions.

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transferred to the parallel hold portion of the target register at UPDATE-DR as inFigure 3-5. That is, the contents of the Capture (CAP) flip-flops, which form theshift portion, are transferred to the Update (UPD) flip-flops, which form the parallelhold portion. (Please refer to 1.3.3 on page 20 for the construction of a data register.)

At the point where we are sitting in UPDATE-DR , we have completed an entireoperation consisting of loading an instruction and capturing, shifting and updating adata register. We are at a juncture here; we can proceed to RUN-TEST/IDLE if weare executing an instruction that uses TCK cycles; we may load another instructionby proceeding to SELECT-IR-SCAN; or we may make another pass down the datacolumn for another capture-shift-update operation on the target data register. Thislast option is what is done most often during testing and is shown in Figure 3-5.

Every time we pass down the data column while EXTEST is in effect, we capture(read) data on component inputs (and bidirectional pins configured as inputs). We

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then may shift this data out for examination. The update (write) part of the processplaces newly shifted data on the output pins (and bidirectional pins configured asoutputs). This gives us a basic testing mechanism: we can use component outputs towrite data on board-level nodes

3. We can then read, by means of component inputs,

the data that appears on their associated nodes. Thus, if one Boundary-Scan driver inone IC is connected to another Boundary-Scan receiver in a second IC, theinterconnecting pathway (node) can be checked for opens and shorts. This can becarried out in parallel for all nodes. While this is a straightforward process, youshould readily appreciate the role that software will play in keeping track of thisdata.

3.1.2 Basic Test Algorithm

The following steps describe the basic test process of Boundary-Scan, including:initialization of the TAP, initialization of the Boundary Register, multiple scanningsequences, flushing the last stimulus pattern, and resetting the TAP. Note that thealgorithm is written using EXTEST, but the process is often similar for other testinginstructions as well. In this description, the “stimulus” pattern is applied to thecomponent driver pins and the “response” pattern is received at the component inputpins.

In the literature on Boundary-Scan testing (see [Wagn87], [Yau89] and[Jarw89]), a pattern applied by a collection of drivers is called a Parallel Test Vector(PTV). A PTV applies data by all drivers in parallel. For a given driver, a series ofPTVs applied in sequence creates a Sequential Test Vector (STV) on each associatednode. Thus, an STV is a stream of data applied sequentially by some driver to anindividual node. A Sequential Response Vector is a set of states received (captured)sequentially by a Boundary-Scan receiver listening to a node.

Basic Test AlgorithmStep 1: Initialize the TAP to TEST-LOGIC-RESET.

Step 2: Load the Instruction Register with the PRELOAD instruction. Thisputs the Boundary Register between TDI and TDO, but does not grant pin-permission.

Step 3: Shift the first stimulus pattern into the Boundary Register. This is the“preload” phase of the algorithm.

Step 4: Load the Instruction Register with EXTEST. This puts the BoundaryRegister between TDI and TDO and grants pin-permission upon passingUPDATE-IR. This applies (writes) the first stimulus pattern (PTV).

Step 5: Capture (read) the response pattern into the shift portion of theBoundary Register.

3In practice, we would have preloaded the Boundary Register with the first set of data to be

written by using a capture-shift-update cycle with PRELOAD in effect. This data would thenactually be written to the board-level nodes when passing through UPDATE-IR after loadingthe EXTEST instruction.

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Step 6: Shift the captured response pattern out while shifting in the nextstimulus pattern.

Step 7: Update (write) the next stimulus pattern.

Step 8: Have we written the last stimulus pattern? If so, go to step 9;otherwise go to step 5.

Step 9: Capture (read) the last response pattern.

Step 10: Shift in a “safe” stimulus pattern4

while shifting out the last capturedresponse pattern.

Step 11: Update (write) the safe pattern.

Step 12: Go to TEST-LOGIC-RESET and halt the test.

Analysis of the basic test algorithm shows that steps 1 through 4 initialize and setup the test. Steps 5 through 8 apply tests, and steps 9 through 12 finish the test andclean up. Note that “capturing,” as in steps 5 and 9, is done by all Boundary Registercells, not just the input cells of interest. Thus there is plenty of extraneous datamixed in with the data of interest.

As we shall see in future sections, the data shifted out will need to be analyzed asa whole in order to interpret the results of the test and prepare a diagnosis. It isusually the case that the “stop-on-first-fail” test approach typically used by In-Circuittest systems is inadequate for Boundary-Scan testing. A true diagnostic system mustcapture all the Boundary-Scan test results for a complete set of Parallel Test Vectors.

3.1.3 The “Personal Tester” Versus ATE

In the early days as the 1149.1 Standard was being developed, it was said thatBoundary-Scan would eliminate In-Circuit testing. This would lead us to a worldwhere ATE systems consist of nothing more than a Personal Computer with aspecial (inexpensive) I/O card

5that could drive the four-wire 1149.1 protocol. A

floppy disk full of software would enable us to test any Boundary-Scan board.Indeed some cynics have suggested that this view was excessively promoted in orderto “sell” management on the merits of investing in the IEEE Standard developmentprocess.

To some degree, the concept of a “Personal Tester” is viable and the ASSET®System from Asset Intertech

6is one actual example. This system is positioned as a

useful tool for prototype development as well as a way to learn about 1149.1 designs

4 A typical “safe” pattern would use the data from the BSDL description safe field (see 2.3.13

beginning on page 72) within the attribute BOUNDARY_REGISTER description. This can beaugmented with data needed to create safe board-level conditions as well.5 Indeed, some people have used a standard 16-bit parallel I/O card for this purpose.

6The ASSET system was originally developed by Texas Instruments [Texa90] and later spun

off as a new company devoted to personal Boundary-Scan equipment. Similar productconcepts and services are available from companies such as Corelis, Intellitech and JTAGTechnologies, to name three more. They all can be found on the World Wide Web.

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and verify their operation. It is not intended as a general-purpose production ATEsystem, although for low volume applications it can be used as such.

A major difference between a personal tester and a fully capable ATE system isin the use model. It turns out that you almost always need to control more than 4 (or5) signals to make Boundary-Scan work for practical board testing.

7Further, these

signals may require In-Circuit overdrive to achieve this control and these signalsmay be embedded somewhere inside the board which leads you to the accessquestion. Now you are looking at the need for a test fixture. While you are testing,you also must apply power to the board, so that brings on a little more complexity.Next, consider how much of a board contains Boundary-Scan versus that portion(digital and analog) that does not. The bench top tester offers no solutions here.Thus, for low volume bench-top applications where limited test coverage could beacceptable, the personal tester is a successful approach, but it can quickly becomeimpractical for the general production line with high throughput and defect coveragegoals.

For the verification of prototype boards, the personal tester has good merit. Here,a designer responsible for getting 15 “Rev A” boards ready for evaluation will bethrilled to get Boundary-Scan coverage of at least a portion of a board. If it takes halfa morning to set up some bench top power supplies and rig up a connector for theTAP signals, this is quite acceptable. This disabling and conditioning problem can beaddressed with clip leads or by simply ignoring the affected nodes. Indeed,Boundary-Scan has proven quite useful for “rapid prototyping” as it is called atcompanies that use it.

8

3.1.4 In-Circuit Boundary-ScanWhen people talk today about the difficulties facing In-Circuit testing, they oftenfocus on the anticipated difficulties in gaining nodal access. But actually, anotherproblem has been around longer and has had a much more deleterious effect: theApplication Specific

9 Integrated Circuit (ASIC).

7These additional signals are typically control nodes needed to hold certain states on a board

that will disable or condition other devices (that do not contain Boundary-Scan) so they do notinterfere with the test. The complicated support software behind this capability is not likely tobe available on personal testers even if some control node capability is advertised. Even moretester I/O signals are required to stimulate and receive data from incomplete Boundary-Scannodes as the rest of this section explains.8Interestingly, rapid prototyping is sometimes performed on personal testers, but with tests

developed on fully capable ATE systems. This reflects the desire to use the programdevelopment tools found on the ATE system without building an expensive, throw-awayfixture. It also frees up the more capital-intensive ATE for production test.9The meaning of “Application Specific” has a very narrow definition in the industry. For the

purpose of this discussion on the difficulty of testing, an ASIC could mean any one-of-a-kinddesign, including Field-Programmable Gate Arrays (FPGAs), Complex Programmable LogicDevices (CPLDs) and the like.

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It is extremely difficult, in general, to develop board-level tests for ASICsbecause they are one-of-a-kind designs; you will not find a “canned” test in a libraryfor an ASIC. Also, they rarely are designed with much thought towards testing,particularly board level testing. Because ASICs may rival large VLSI processors insize, yet may contain obscure and relatively unstructured logic, they presentformidable test generation problems

10 [Agra88]. Add to this the fact that an ASIC

might undergo a design change at the last minute that would most likely obsolete apainstakingly developed test. These problems add up to the following unfortunatefact of life: many ASICs are never tested at In-Circuit board test! Thus, a simplesolder problem, such as an open, would have to be discovered at functional/systemtest. As ASICs are becoming a significant fraction of the digital components used intoday’s board designs, there is a serious problem here.

So what does Boundary-Scan do to help out? Imagine for a moment that youhave full nodal access to a board, and it has many ASICs. You have In-Circuit nailssurrounding each Boundary-Scan IC, but no “canned” tests for them in a library.Because we have full nodal access to every pin of the IC, we can use standard, In-Circuit unpowered shorts testing

11to find shorts. This still leaves opens testing

12and

the basic verification that the IC is alive. This will require a powered digital test.

We can use the Boundary-Scan facility within each IC to enable Automatic TestProgram Generation (ATPG) for board-level ASIC testing. All that is needed is aBSDL description of an ASIC’s 1149.1 implementation. With this, it is possible toautomate the creation of an In-Circuit test for that IC that will cover 100% of themanufacturing fault spectrum and do a better job of isolating open solder problemson input pins than is possible with conventional ICs. We call this “In-CircuitBoundary-Scan Testing.”

In-Circuit Boundary-Scan testing makes use of the basic testing algorithm(section 3.1.2.) and the fact that the In-Circuit ATE system can read IC output pinswhen Boundary-Scan writes to them and it can write to IC input pins for theBoundary Register to read. Thus the problem is to coordinate the Boundary-Scanresources with the parallel drive/receive resources connected to In-Circuit test nails.

10Structural problems in the electronics industry also contribute to the difficulty; tools for IC

level testing of ASICs do exist, but are of little use at board test due to board level constraints(nodal wiring) and to the difference in failure mechanisms of interest between the twocontexts. Finally, the ASIC designer may have no motivation to solve board level testproblems.11

“Unpowered shorts testing” is accomplished before power is applied to the board. It uses aseries of very low voltage analog measurements that can isolate shorts between nailed nodes.Note that the power supply nodes would be included in this test, finding Power/Ground shortsas well as (nailed) signal nodes shorted to power nodes.12

There are also unpowered techniques for finding opens on ICs, called Unpowered OpenTest technology. Three such technologies are Capacitive Leadframe test, Radio FrequencyInduction test and Analog Junction test. These have been documented at the International TestConference (see 1996 proceedings) and are available from major ATE vendors. Note allrequire nodal access.

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In steps four and seven of our basic test algorithm (on page 112) we are causingthe Boundary-Scan drivers to write a stimulus pattern, which our ATE system canthen read and compare for valid data. In steps five and nine we are reading thecomponent inputs into the Boundary Register. We must instruct the ATE system todrive the parallel inputs of the component just before this read occurs. Note that wecan disable the ATE drivers after the read occurs, which reduces the time thatupstream drivers are being overdriven. Between read and write operations, we areshifting out captured states that the ATE system placed on the inputs and shifting innew stimuli to be written to the component outputs where ATE receivers may seethem.

A failing bit on TDO indicates that some Boundary Register cell did not capturethe value that the ATE system set up on an IC input. We can correlate the failing bitposition in the scan sequence to a cell in the Boundary Register. From there we map(using the information from the BSDL attribute BOUNDARY_REGISTER) to an ICinput (or bidirectional acting as input) and can give a diagnostic for a failing input.This capability is difficult

13or impossible with In-Circuit testing before 1149.1.

Other capabilities can be enjoyed that were not possible before 1149.1. Forexample, if we have a very large pin count on an ASIC, we can choose to test subsetsof pins in succession, taking advantage of an In-Circuit ATE system’s multiplexedresources. Thus, we can multiply the value of our resources at the expense of testingtime. The concept of testing portions of a IC’s I/O pins would not be possible withconventional ASICs, unless of course they contained trivial logic. If some of the ICinputs are connected to fixed signals (such as logic 0 or 1) we can skip these pins, ordirectly verify the fixed values. With conventional ASICs, fixed values have to beconsidered as a board-level constraint when developing the test, a constraint thateffectively modifies the logic of the IC.

When Boundary-Scan was in its infancy (in the early 1990s) it was common forpeople to say, “I only have one or two ICs with Boundary-Scan, so it will not helpme.” To them I would respond, “If Boundary-Scan can take a two-week In-Circuitprogramming problem and solve it in less than ten seconds, is that of interest?” Itwas.

3.1.5 IC TestThe INTEST function allows us to test the System Logic of an IC even when the ICis mounted on a board such as shown in Figure 3-6. (Here, the IC is shown as part ofa chain, though we could also make use of an In-Circuit nail on the TDI-TDOconnection between the chips to directly access the target IC.) When the TAPInstruction Register is loaded with INTEST and we pass through UPDATE-IR, theIC’s I/O pins are disconnected from the System Circuitry, and the Boundary Registertakes control of it. The IC’s output drivers also can be controlled by the Boundary

13 It is possible to use a “fault dictionary” approach to diagnose opens on inputs, if there is

only one open, because this looks like a single stuck-at failure and matches the assumptionsused to create dictionaries. If multiple failures exist, then the dictionary approach will usuallygive no diagnosis, or a false diagnosis.

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Register14

. This control allows us to set safe values on the IC’s outputs whileINTEST in functioning.

To do an INTEST, we make use of the basic testing algorithm (section 3.1.2)with the following modifications:

The “stimulus” pattern is being written to the System Logic inputs rather thanto the component output pins.Component outputs can be held at safe or disabled states by adding thesevalues to each stimulus pattern.The captured (read) response is that of the of System Logic outputs, includingoutput enable signals.INTEST is loaded in place of EXTEST at step 4.All stimulus and response patterns must be organized with respect to theSystem Logic I/Os rather than the component I/O pins.

In principle, it is possible to use the INTEST function to fully exercise theSystem Logic of an IC loaded on a board, independent of its board wiring. In reality,there are some practical restrictions. First, System Logic tests are often very longbefore 1149.1 serialization. After serialization, they could be far too long from twostandpoints: application time and the requirements placed on tester memory. Second,the tests may have, as part of their goal, a high pattern application rate. This mightnot be achieved after serialization, thus nullifying their intent.

14As noted in Chapter 1, there are two options for output control during INTEST. All outputs

may be under control of the Boundary Register or they may all be set to the high impedancestate.

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One last difficulty is contributed by the notion given in the Standard thatINTEST may be implemented in an IC but that certain “clock” inputs do not have tobe controlled by the Boundary Register. When you have uncontrolled system clockinputs, you must coordinate them with the application of the INTEST patterns andperhaps with TCK as well. In this case, we must ensure that an ATE systemcoordinates these additional requirements along with the basic INTEST concept. Onanalysis, there can be one or several system clocks, as well as TCK, to manage andthe problem can, in principle, become quite complex. When INTEST is to be used inthis environment, additional engineering of the basic test algorithm outlined abovecould be necessary; in short, there is still a need for test engineers, even with theadvent of Boundary-Scan!

3.1.6 IC BIST

The 1149.1 Standard contains direct provisions for IC-level Built-in Self-Test(BIST) of the System Logic. There is the optional RUNBIST capability specified bythe Standard. (Designers can implement their own BIST functions separate fromRUNBIST.) Shown next is a description of a basic RUNBIST test process.RUNBIST is self-initializing, so no steps are shown that initialize internal countersor accumulators.

Basic RUNBIST Test AlgorithmStep 1: Initialize TAP to TEST-LOGIC-RESET.

Step 2: Load the Instruction Register with PRELOAD. This puts the BoundaryRegister between TDI and TDO, but does not grant pin-permission.

Step 3: Shift a “safe” pattern15

into the Boundary Register. This pattern willprevent the IC drivers from conflicting with other board level signals when theBoundary Register takes control of them.

Step 4: Load the Instruction Register with RUNBIST. This puts the BISTresult register between TDI and TDO and grants pin-permission to theBoundary Register upon passing UPDATE-IR. This applies the “safe” patternto all output drivers.

Step 5: Proceed to the RUN-TEST/IDLE state. Issue TCK cycles16 from thisstate fulfilling at least the minimum RUNBIST clocking requirement.

Step 6: Proceed through CAPTURE-DR, capturing the BIST response patternin the BIST result register targeted by RUNBIST.

Step 7: Shift out the BIST result pattern for verification.

Step 8: Go to TEST-LOGIC-RESET and halt the test.

15Steps 2 and 3 can be omitted for ICs that do not use the Boundary Register to control

outputs during RUNBIST. These ICs place all output drivers in a high impedance state duringRUNBIST.16

The same clocking complications noted in section 3.1.5 concerning just what is a “clock”apply here as well.

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The Standard has crafted the RUNBIST function such that it can protect thecomponent outputs from harm due to conflicts during the potentially lengthy BISTtest. Notice in step 5 that a minimum number of clocks must be issued to exercisethe BIST function; however, more may be applied. This facilitates performingRUNBIST on several ICs in a chain in parallel even when they have different (non-conflicting) clocking requirements. When the BIST result register is shifted out (step7), the interpretation of this result is up to the designer of the BIST function; it couldbe a single pass/fail bit or perhaps a longer register with meaningful diagnosticinformation encoded within it.

3.2 TESTING WITH BOUNDARY-SCAN CHAINS

The Boundary-Scan Standard allows for ICs to be linked into chains by linking theTDO pin of one IC with the TDI pin of the next. For example, the 1149.1 ICs on aboard may all be linked together in a simple chain by sharing the TCK and TMSsignals and linking their TDO-TDI pins in succession. Several distinct simple chainsmay exist on a board if they do not share any TAP signals; or “Siamese” chains canbe created by sharing some TAP signals. For a single simple chain, operation of theStandard for testing purposes is straightforward. For multiple simple chains orSiamese chains, operation becomes more difficult (see 5.2.1). Here we will restrictour discussions to individual simple chains.

As mentioned in Chapter 1, a simple chain of Boundary-Scan ICs are always inthe same TAP state

17. This simplifies our view of the TAP states of the ICs; one can

picture the chain itself as following the TAP state diagram. However, each memberof the chain could have a different instruction active at any time, each of whichtargets a different register. On top of this, each IC may have its own uniquedimensions on each register. This all changes as new instructions are loaded. Thus,there is some careful bookkeeping involved with managing a Boundary-Scan chain.(Note if we want to consider multiple simple or Siamese chains, then we must keeptrack of independent TAP states for each chain or even for each IC.)

A fact of Boundary-Scan testing is that we depend upon our chain being inoperational order before we can do useful testing. In essence, we have moved part ofour tester hardware onto the board we are trying to test. Just as no one would expecta malfunctioning tester to reliably test a board, we cannot expect a malfunctioningchain to be of much service either. The problem becomes that of ensuring that achain is basically functional and if it is not, quickly locating the problem so that itcan be repaired.

3.2.1 1149.1 Chain IntegrityChain integrity must be assured before we should trust the results of a test and obtainreliable diagnoses. There are many faults that can damage a chain, for example:

A component in the chain could be dead, missing, or misloaded.

17 Again, assume that no assertion of an optional TRST* signal occurs that would drive some

chain members to TEST-LOGIC-RESET independently.

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A component in the chain could have a broken connection for one of its TAPpins.

A TDO to TDI connection between components could be shorted to anothernode.

Fortunately, the 1149.1 Standard has provided resources that facilitate chainintegrity testing. You should note that a combination of the above problems couldexist in a chain of components. If this is the case, it may be necessary to test andrepair and re-test the chain repeatedly until integrity is restored. Typically, anintegrity test will find only the problem closest to the TDO end

18of the chain. This

will usually prevent us from seeing any problems that might exist further upstream.

The primary characteristic that facilitates integrity testing is the ability of each ICin a chain to set up a deterministic data pattern in its TAP Instruction Register atCAPTURE-IR. We can then shift all the concatenated capture data out on TDO of thelast IC. By examining the BSDL description of each IC in a chain, we know from theattribute INSTRUCTION_CAPTURE what this data will be. Furthermore, becausethe Standard states that the two least significant bits must be “01,” we know thateach IC should cause TDO to toggle to both logic states. In the simplest case whereall instruction registers in a chain have only two bits (see Figure 3-7), we would seethe following concatenated data for a good chain (of seven ICs) and one example ofa failed chain. (Remember the rightmost bits, the least significant, flow out of TDOfirst.)

In the bad data stream, IC 7 first shifts out its “01” (which is correct) followed bythe data for IC 6 (shifted through IC 7), which is also a correct “01.” Then we see acorrect “01” for IC 5. For IC 4, we see an incorrect “11” come out, and all

18However, one can sometimes find multiple chain integrity problems with a single test

execution if tester access is provided to the interior TDI-TDO connections within the chain.

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subsequent bits are “11” for the upstream ICs 1-3. From this we can conclude thatICs 5-7 were basically functional but that something is wrong with one or more ICsstarting with IC 4. This conclusion might not be perfect because a damaged TDIreceiver

19 in IC 5 that always reads a “1” could be the real cause of the problem.

Because solder problems are often a prevalent failure mechanism, we could begin bylooking at the solder workmanship on IC 4; is there an open circuit on TCK, TMS orTDO of IC 4? How about a solder open between TDO of IC 4 and TDI of IC 5? IsIC 4 misloaded? Is IC 4 dead? From this, a diagnosis would have to suspect aproblem first with IC 4, but cannot completely rule out a problem with IC 5. Thus,integrity testing will usually indict one of two ICs, with one having a higherlikelihood of causing the problem.

Because testing algorithms such as we have already seen start by immediatelyprogramming the Instruction Registers of each component in the chain, we have thenucleus of an integrity test built into the beginning of the test itself. If we instruct ourATE system to check the instruction capture bits as they come out during the firstinstruction programming sequence, it is possible to make basic integrity testing anintegral part of any test. This is highly advisable, as it will protect a test from thepotentially false assumption that a chain has integrity.

The above test sequence has one limitation—it does not test the integrity of TDI forIC 1. This is easily solved by shifting two more bits, prepended to (that is, attached tothe beginning of) the sequence we want to load into the Instruction Registers. If thesebits are deliberately made the opposite of the mandatory instruction capture pattern(that is, “10”), they will be the last two bits shifted out and will serve to indicate theend of the chain. These prepended bits are called sentinel bits.

More intricacy may be added to integrity testing; for example, we could programthe IDCODE instruction into those components that have it, while setting the rest toBYPASS

20. We can then proceed to SHIFT-DR and read out the IDCODEs of those

components. This will tell us if any pin-compatible components have been loaded inthe wrong positions. In general, many of the failure mechanisms of interest have fairlycatastrophic effects on chain integrity. Thus, simply programming the InstructionRegisters for the first time will expose most problems.

One fairly insidious problem (see DeJo91]) can cause difficulty in diagnosing chainintegrity. If several identical components are chained in series, then the patterns theycapture in their Instruction Registers are also identical. Now, imagine mat TDI andTDO of IC 4 are shorted together and assume a Wired-AND occurs (see Figure 3-7).This creates the AND of the TDO signals in ICs 3 and 4. Using our improved test

19 We assume that all ICs have been thoroughly tested before placement on a board. Damage

from handling and placement, either physical (bent pins for example) or electrical (fromElectrostatic Discharge—ESD for example) are our main concerns.20

Alert readers may wonder why we would program these instructions when the TEST-LOGIC-RESET state sets these intrinsically; you could proceed directly to SHIFT-DR to readout the IDCODEs. The reason is many ICs do not contain IDCODE and place a single-bitBypass Register with a captured “0” between TDI and TDO. This single bit cannot cause atransition on TDO so that we suffer even more ambiguity in isolating chain problems.

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sequence with a prepended sentinel “10” attached, we see the following datapropagated from TDO.

What we see would indicate there is a problem in the vicinity of IC 1 when it reallyis located at IC 4. This is because the data being wire-ANDed at IC 4 never conflictsuntil the “10” sentinel is finally shifted out of IC 3. Then it ANDs to “00” and this isloaded into both IC 4 and IC 5 at the same time. We do not see this result until the datatraverses ICs 6 and 7. This problem is studied in [DeJo91] and some diagnosticprocesses are offered. However, there are two easier solutions; one is to place In-Circuit probes on all interior TDI-TDO nodes so that all TAP signals used by the chaincan be tested for shorts using unpowered shorts test. The second is to eliminate thechance that TDI can short to TDO on an IC; this can be done by making sure that TDIis physically distant from TDO on the package pins

21(see 5.1.1).

3.2.2 Interconnect TestInterconnect test refers to the testing for shorts and opens within the nodal wiringbetween Boundary-Scan components only (see section 3.2.4 for interactions betweenBoundary-Scan nodes and other nodes

22). Figure 3-8 shows a simple example. Note

that nodal connections between components are considered “interconnect.” The nodesconnected to nails are assumed to be board-edge signals; these will be tested byConnection tests covered in section 3.2.3. In this drawing we use the convention thatI/O pins on the left side of the package are inputs and those on the right are outputs orbidirectional pins.

21 We are taking advantage of the fact that the vast majority of shorts are caused by improper

connections (for example, bad solder) between physically adjacent I/O pins. Board shortsbetween printed node traces are usually eliminated before expensive components are loadedonto a board.22

Boundary-Scan nodes are defined as those possessing at least one driver and receiver undercontrol of the combined Boundary Registers of a chain. (Note that this could be satisfied by asingle, bidirectional I/O pin.) “Other” nodes include analog nodes, conventional digital nodesand power supply or voltage-reference nodes that would not appear to be a logic “0” or “1”value.

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The interconnect testing problem was studied by Kautz long before Boundary-Scanwas invented [Kaut74]. Kautz showed how a binary counting sequence could offer aminimum sized test for wiring interconnects. Wagner [Wagn87] placed the countingsequence technique into the Boundary-Scan lexicon. The definitive papers bycollaborators Yau and Jarwala offer an excellent survey, analysis and theoreticalframework for the problem ([Jarw89] and [Yau89]). To this book, we add somepractical experience to leaven our expectations for Boundary-Scan.

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Interconnect testing usually lumps the testing for shorts and opens into one topic.Here, we will split the two problems apart. Shorts (see Figure 3-9) are a verydestructive problem in that they can confuse diagnostic procedures and hide theoccurrence of other failures.

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Opens, on the other hand (see Figure 3-10) are a relatively simple problem todiagnose. Shorts, by their very nature, may cause driver conflicts on a board thatcould degrade the lifetime or performance of the affected components. Opens willusually not damage components. Since any Boundary-Scan testing necessitatesapplying power

23to a board, shorts that are present immediately begin to act upon

the affected drivers. This gives us concern about component damage that could occurdue to powered shorts. There is a wealth of study [Sobo82], [Robi83], [Bush84],[Hewl85], [Swen86] in the area of abused drivers, study inspired by In-Circuittesting. These studies show us that we need to be concerned with the duration oftime that a short is excited under power. We can do little about the power sequencingand stabilization time, so we need to try to minimize the time spent testing whentesting will excite driver conflicts. We have seen how the 1149.1 protocol can greatlylengthen test times due to serialization; this then forces us to organize our tests suchthat shorts are excited for a minimized duration.

By breaking our interconnect problem into two phases, one that focuses on shortsfirst followed by another that focuses on opens, we can minimize the time that drivers

23The process of applying power is more complex and time consuming than many realize. It

might take several hundred milliseconds to stabilize a power voltage to specification. Theremay be several voltages to be applied in sequence. It also might take hundreds of millisecondsto turn power off!

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are in conflict. Be aware that failures will not allow neat assumptions; when testing forshorts first, we cannot assume that opens do not exist. However, once we havecompleted testing for shorts, then we can perform opens testing under the assumptionthat there are no shorts to complicate matters.

Interconnect Shorts TestInterconnect shorts testing is done by utilizing our basic test algorithm (section 3.1.2).It is used to transmit Sequential Test Vectors (STVs) onto nodes to be received byBoundary-Scan input pins (see Figure 3-11). The data received at Boundary-Scaninput pins are called Sequential Response Vectors (SRVs). If a given node is operatingproperly, then the SRVs seen at all its receivers should match the STV of the driver. Weproceed as follows:

Step 1: Examine the board netlist and BSDL descriptions of the Boundary-Scan components. Enumerate the Boundary-Scan interconnect nodes and allattached component pins.

Step 2: For each node, identify all component pins that can drive the node,including bidirectional pins. Select one and call it the designated driver of thenode. (See discussion.)

Step 3: Assign a unique Sequential Test Vector (STV) to each node. (Seediscussion.)

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Step 4: Transpose the STVs into Parallel Test Vectors (PTVs). Use the basictest algorithm to write an ATE program for the test.

Step 5: Execute the test on an ATE system. Record each captured PTV that isshifted out.

Step 6: Transpose the captured PTVs into SRVs.

Step 7: Analyze the SRVs. Use observed differences from the original STVs todiagnose shorts and opens.

Note that steps 1-4 can be done once in preparation of the interconnect test and, ofcourse, can be completely automated. Step 5 is performed by an ATE system once perboard tested. Steps 6 and 7 may be skipped if the ATE system does not note a failureduring the test. If a failure is detected, the ATE system can immediately remove powerfrom the board before steps 6 and 7 are performed.

DiscussionStep 2 selects a designated driver for a node. This driver is frozen for the entireinterconnect test; no other driver is used. This means that for nodes with multipledrivers (buses), there are opens that might not be detected. Since we are deliberatelyconcentrating on shorts detection, we leave this class of undetected opens for futuretesting as discussed later in this section (see “Interconnect Opens Test” on page131).In that discussion, we will examine several cases where opens are missed byinterconnect shorts testing.

The main reason for selecting and freezing a designated driver is to keepinterconnect shorts tests brief. Testing for opens on bussed drivers can be relativelyexpensive in terms of the number of PTVs needed. Because opens are benign andshorts are dangerous, we defer testing for this class of opens until we are satisfied thatshorts have been eliminated.

Step 3 assigns a unique STV to each node. The work by Yau and Jarwala [Jarw89],[Yau89] goes into great depth on this matter. The simplest and shortest test uses binarynumbers, sequentially assigned, as the STVs for nodes. When transposed into PTVs,this gives us a number of PTVs equal to

where N is the number of nodes being tested.

Logarithmic compression is impressive; we can test 1000 nodes with just 10 PTVsand 4000 with just 12 PTVs. The length of a PTV is loosely related to N. For example,if the average node connects 4 pins, then there are 4*N pins being tested. Each has atleast one Boundary Register cell so there is an order of 4*N bits to shift in the PTV. LetA be the average number of pins per node. Then the number of shift cycles in the test ison the order of

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cycles.24

For 4000 nodes of four pins each this is approximately 192,000 shift cycles.

In contrast to a counting sequence is a walking-bit sequence. (The walking-bitsequence has the advantage that it eliminates a problem called aliasing, discussed inthis section in the topic “Aliasing and Confounding” below.) Here a single “1” (“0”)is imposed on a field of “0”s (“1”s). For N nodes, each PTV is N bits long with onlythe bit set to “1” (“0”) among them. This makes a much longer test, on the order of

cycles. For the same 4000 nodes of four pins each, this is approximately 64,000,000shift cycles.

The counting sequence test and the walking-bit test are two extremes of acontinuum of test patterns, as studied by Yau and Jarwala. They trade length fordiagnostic resolution. This will be discussed in the topic of “Aliasing” found next.

Step 4, our preparation for interconnect test, transposes STVs into PTVs. Here, wetake the least significant bit of each STV and assign it to the Boundary Register cell ofits designated driver, taking care to also turn on any associated driver enable cell aswell. When this has been done for the LSB of every STV, we have the stimulus portionof the first test cycle, a PTV. We then look for every receiving cell connected to eachnode and program our ATE system to expect those same bits in those locations. Thisbecomes the expected SRV that the ATE system can use to note if any failures occurduring the test. We iterate this process for each more significant bit of the STVs untilwe have created all the PTVs.

In step 5, the ATE system executes the test. If a failure is noted, it does not stop-on-first-fail as would be typical in times past. Rather it continues, logging all the shiftedresponse data for processing in steps 6 and 7. If no failure is noted, this subsequentprocessing can be skipped.

In step 6, we transpose the captured PTVs back into a list of SRVs. This is done byexamining each receiving cell location in the captured PTVs and building theassociated SRVs from least to most significant bits. When this is done, we know whateach receiving cell observed (its SRV) during the test. In step 7, we act upon any casewhere a receiving cell’s SRV does not match the designated driver’s STV. Thisindicates an interconnect failure.

Aliasing and ConfoundingWe diagnose failures by examining the SRVs that are incorrect and by trying to decidewhat could have caused the discrepancies. In many logic families, an open will beinterpreted by a receiving pin as a constant “1” or “0”. If an SRV were all “1”s or “0”s,we might suspect an open, but there could also be a short of that node to a fixed signalsuch as Ground or Power. In some logic families, two shorted drivers will perform aWire-AND function. Other logic families may see Wire-ORs. In logic families wheredrivers have varying strengths for “0” and “1” (for example, CMOS) is may not be

24The “order” of a problem’s complexity identifies how that complexity grows with the size

of problem variables. The equations given here are not exact because of various assumptions,but do show you how to estimate the behavior of a problem that is twice as big, for example.

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possible in general to predict the result of a short; we call this a Wire-X function. Nowif two Wire-AND nodes were shorted, then the SRVs of all the related Boundary-Scanreceivers would be identical and would be the bitwise AND of the two STVs of thedesignated drivers. It would seem a straightforward process to write a diagnostic reportfor this short. But, depending on how the STVs were chosen, a precise diagnosis mightbe frustrated by aliasing.

Aliasing occurs when the combined failures of two or more nodes results in anSRV (seen at a receiver) matching the STV (assigned to the designated driver) of yetanother node. For example, if nodes B and C shown in Table 3-3 were shorted (assumeWire-AND), the resulting SRVs captured on these nodes (0001) is the same as the STVfor node A. Does this indicate a short to node A as well? Aliasing leaves us with thisambiguity: two (or more) nodes are known to be shorted, but another correctlyoperating node is also suspect.

Similarly, if nodes D and E were also shorted, the resulting SRVs captured on thesenode receivers (0001) would also indicate a short to node A (0001). This phenomenonis known as confounding; we cannot determine if there is one short or two shorts, andwhether A is part of the short in either case.

Aliasing and confounding do not harm the ability of 1149.1 interconnect testing todetect shorts, but complicate the diagnosis of shorts. This complication can be anirritation during the actual repair of the board. In the example above, nodes B and Care definitely shorted together; we just are not sure if node A is also involved. Sincesolder problems are the main cause of shorts, we would visit each pin destination ofnodes B and C and inspect the solder at each location for a short. One or more of theselocations may also be adjacent to a pin belonging to node A, the aliased node. If asolder defect were found, we would repair it. For the price of inspecting all thedestinations of B and C, we can discover any short to A as well if one should exist.Since repair is a manual process anyway, this bit of extra care is not a bad investment.A key assumption here is that the destination pins of each node are indeed visible forinspection.

25 In the case that some are not, then a simple electrical continuity test from

node A to either of nodes B or C will tell if a short to node A is also present. It is alsopossible to use X-Y coordinate data of all the pins of the three nodes to see if anyadjacencies exist that could be the site of a short.

25 Inspection can be done with the human eye, or with an automated inspection system. With

the increasing use of Ball-Grid Array (BGA) packaging, optical visual inspection is givingway to X-Ray laminographic inspection, a technology that can see through most opticallyopaque objects and make quantitative measurements of solder quality in three dimensions.

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If your goal is to reduce the probability of aliasing and confounding so that therepair process is as straightforward as possible, the price you must pay is that of alonger test. We have seen two extremes of tests: the counting sequence, which willoften exhibit aliasing; and the walking bit test, which is virtually immune. We havealso seen a dramatic difference in the length of the two tests with the walking bitapproach producing tests of breathtaking proportions. Jarwala [Jarw89] and Yau[Yau89] show how to construct tests of varying sizes such that the aliasing probabilitycan be traded for test size.

Another tradeoff must also be considered; that of the probability of damagingcomponents by applying power to shorted drivers versus some convenience during therepair process. This is not a trivial matter. One proposed diagnostic procedure uses anadaptive process. First run a brief (that is, alias-prone) test to produce a relativelycompact list of shorted nodes and their aliases. Then, construct a new test (like awalking-bit test) for the compact list of nodes and run this to produce the finaldiagnosis. The assumption is that since the list of suspect nodes is compact, the newtest will be compact as well. However, the duration of time for this process will not besmall, since the new test must be calculated on-the-fly with data from the first test.

A more frightening problem with the adaptive process comes from an analysis of akey assumption in the Yau-Jarwala work; that shorts always have wired-AND, wired-OR or strong-driver behavior with known and deterministic results. If thisdeterministic assumption is ever violated by a real fault,

26 then we are using adaption in

an unpredictable or unrepeatable environment. Imagine, during test development, thatyou are trying to debug a “flaky” test and that the adaption process behaves differentlyon each application of the test! This will make debug very interesting indeed. If theproblem is not seen during test preparation (very likely since tests are not validatedagainst the myriad possible failure combinations), then it will wait until productiontesting to appear.

If we decide that the problems with an adaptive process are too severe, that leavesus with a preset test that should be as brief as possible and yield good diagnoses withlittle irritation due to aliasing. The “preset” requirement means the test never changes,which is a great help during debugging. The “brief” requirement suggests that acounting sequence test be the basis of the test, while the “good diagnoses” and “littlealiasing” requirements suggest that we augment the counting sequence with additionaltests (PTVs).

Table 3-4 shows such an augmented counting sequence test. Note 1 heads a PTVthat places all nodes at “0”. Note 2 heads a PTV that places all nodes at “1”. Shortednodes will never cause a driver conflict in either of these two PTVs, so both the “0”and the “1” will be conserved in the SRVs for these PTVs for any shorted signal nodes.This means we can differentiate an open (or a Power/Ground short) that causes a

26 Consider a short between three drivers of varying strengths, none overwhelming. Then

consider the eight combinations of data they may have during the test. Next consider that eachreceiver of the combined nodes will interpret voltages as one or zero differently, particularly ifthere is any hysteresis at work. This example, entirely common, should give you concernabout “simplifying” assumptions.

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constant SRV (all 1s or 0s) from any other short. Note 4 heads three columns that are abinary counting sequence, known to be brief, but also prone to aliasing.

Note 3 heads two columns in the table. These two columns are complements of therightmost two columns from the binary counting sequence. These are anti-aliasingPTVs. A full set of anti-aliasing PTVs would consist of adding the complement of thecomplete binary counting sequence, which in this case, is the complement of the lastthree columns [Wagn87] [Jarw89]. Adding less than the full set represents acompromise; fewer PTVs but more chance of aliasing. The advantage of this approachis simplicity; we are not using any knowledge of the circuit topology or any complexanalysis to create anti-aliasing PTVs. We just complement a subset of the countingPTVs, starting with the least significant bits (that change the most). Adding more suchPTVs increases the length of the test, but reduces the chance of aliasing.

Practical testing experience has shown that the test selection approach illustrated byTable 3-4 gives good diagnostic resolution for shorted signals, good resolution ofPower/Ground shorts, rarely produces aliasing, is quite brief, and is deterministic.

Interconnect Opens TestOnce we have tested the Boundary-Scan interconnect, using the counting sequencestyle of approach, we have detected any short between these interconnects and havealso discovered many of the possible opens as well. However, if there are nodes withmultiple drivers, then we know that only the designated driver for each such node hasbeen verified for opens. The others were never activated

27, so we have not tested for

opens on them. We need to do an interconnect opens test that will finish the job.

27 In some cases these other drivers may actually be part of a bidirectional pin structure. In thiscase, the receiving Boundary Cell was tested, so the solder must be good. However, since wehave never turned on the driver, we still do not know if there is any problem with it.

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Figure 3-12A shows the basic configuration used during interconnect shortstesting. There you see three ICs that drive the node and one that receives. U2 wasarbitrarily chosen to be the designated driver during interconnect shorts test, but thatleaves both U1 and U3 untested for driver opens.

Figure 3-12B shows a case where there are two ICs, U1 and U2, both activated todrive the bus during interconnect shorts testing. In other words, we could not designatea single driver for this node. This is necessary because the control cell that turns on thedriver in one IC fans out to other drivers (in the same IC) that must also be turned on toperform interconnect shorts test. Each masks a problem that might exist with the other

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and introduces the requirement that both data cells must be loaded with matching datato prevent drive conflicts.

Figure 3-12C shows an example of two drivers ganged together to increase drivecurrent. Solitary opens on either driver cannot be detected using Boundary-Scan,unless of course the DC loading is such that one driver cannot create proper logiclevels.

The situation in Figure 3-12B is caused by control cell fanout to multiple driverscombined with board-level topology that requires two or more drivers to be turned onat the same time. Figure 3-13 shows a simple case of this; pins 11, 12 and 13 ofcomponent U1 must be turned on to detect shorts between their nodes. Pins 11 and 12are also bussed drivers. Down in U3, pin 10 must be turned on as well or its nodewould not be tested for shorts. When this is done, we also have pins 8 and 9 turned onas well, causing multiple designated drivers to exist for their nodes potentially maskingopens. Thus, when bus wires exist on a board, it is likely that conditions exist wherethe interconnect shorts testing process will not completely test for opens.

If we had a single bussed wire with N drivers we could test it very simply with 2*N28

PTVs, N pairs that turn on just one driver and set it to “0” and “1” successively.

28 All receivers, including those within bidirectional structures that are not driving, should be

checked to ensure the correct driver data is received from the node.

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Figure 3-14 shows an example of a board topology where two bussed wiresmarked A and B exist side by side. These two wires each have two drivers, but we cantest them in parallel as before with N equal to 2. This is shown in Table 3-5.

In this example, nodes A and B are driven simultaneously, first from componentU1, then from component U3. The bit patterns show either “01” for two PTVs drivenby a pin, or “ZZ” for two PTVs where a pin is disabled. The SRVs seen at eachreceiver are “0101”. Nodes C and D are not tested (meaning their SRVs are notexamined) because they were already tested by interconnect shorts test.

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Figure 3-15 shows a case where four bus nodes A, B, C and D exist with twodrivers for nodes A, C, and D and three for node B. These, too, can be tested inparallel, but with N equal to 3, the maximum size of any one bus. Table 3-6 shows thedata for this case. When a node is not driven for a PTV which occurs on nodes A, C,and D, then the SRVs in these cases are “XX” as shown, indicating a “don’t care.”

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In either case just shown in Figure 3-14 and Figure 3-15, the fanned-out, controlcell structure that we saw in Figure 3-13 could be present as well. This influences howwe choose which drivers to turn on at the same time. Obviously, if the same control

29cell enables two drivers, they must be enabled or disabled simultaneously . As shownin Table 3-6 we choose to test all the drivers in an IC in parallel while the other ICs aredisabled. We call this process “choosing a designated IC” rather than just a designateddriver.

3.2.3 Connection TestsConnection tests are similar to In-Circuit Boundary-Scan tests. They test theconnectivity of nailed nodes to Boundary-Scan components. The circuit in Figure 3-16shows an example of several ICs that have nailed connections in need of testing. Thiscircuit has a number of nodes and Boundary-Scan pins that cannot be tested with anyof the typical Boundary-Scan interconnect tests. These nodes may come from edge-connector pins or may be those that cross between the Boundary-Scan portion of thedesign to the conventional portion. A connection test utilizes the tester resourcesavailable on such nodes to test that the Boundary-Scan IC is connected to those nodes.One, several, or all IC pins may be tested this way.

29 Supplement A [IEEE93] to the Standard makes it a firm rule that drivers that are controlled

by the same control cell must respond identically to the value loaded into that cell. Theoriginal standard allowed them to be different, causing obvious problems for test algorithms.

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A connection test is relatively easy to do. It only looks for opens, since shortsbetween the nodes it is testing are already detected by a preceding, unpowered shortstest that should be performed on all tester nails before applying power to the board.Two PTVs that drive all inputs (and bidirectionals acting as inputs) are first run to seethat each can receive a “1” and a “0”. Then two more PTVs are used that cause eachoutput (and each bidirectional acting as an output) to drive a “1” and a “0”. The testercan directly see failing output pins, and can correlate failing TDO bits with faultedinput pins.

It is common for some component inputs to be tied to fixed “0” or “1” signals(often Power or Ground). By noting which pins are fixed, we can also verify that theseinputs are always capturing constant “0”s or “l”s.

It is possible to perform connection tests on several ICs in parallel, but this willrequire more parallel and independent tester resources. By testing the ICs in separatetests, we can multiplex and reuse these resources. Indeed, if one IC were particularlylarge and had many connections to test, we could choose to test portions of theseconnections in separate tests. This allows us to save on tester resources and lower thecost of the tester.

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3.2.4 Interaction TestsMost literature on Boundary-Scan discusses interconnect testing as if all nodes wereconnected to 1149.1 components. In reality, especially in the early days of theStandard, full Boundary-Scan implementations are an exception rather than a rule. Notall digital components have Boundary-Scan. Since shorts do not show a preference, aBoundary-Scan node could be shorted to a non-scan node. These interactions can causesome special testing problems [Robi90].

Figure 3-17 shows a simple example of potential interactions between a Boundary-Scan node B and two non-scanned nodes A and C, which are connected to physicallyadjacent pins and thus, prone to shorting. Here, node B is a simple Boundary-Scannode driven by U1 and received by U2. Node A is driven by conventional componentU3. Node C is a digital node with an intervening analog filter. If we assume that thereare no In-Circuit nails available for these nodes, then it might be difficult to test forshorts between nodes A, B and C. If the driver in U3 is strong enough to interfere withthe operation of node B and it is enabled, we could see a failure on node B duringinterconnect testing. Node C might not have enough current source/sink capability tointerfere with the operation of node B. If so, a short from node C to B might not bevisible during testing.

If we have limited nail access, we should first spend one nail on node C. This30

allows our ATE system to place a strong and deterministic value on node C that willdefinitely interfere with node B in the case of a short. This leaves node A; we couldplace a nail on it, or, perhaps we can more easily gain control of the inputs to U3. Ineither case, the goal is to set up a condition where node A will definitely interfere withnode B if a short is present.

30The ATE driver must be strong enough to overdrive node C and node B simultaneously.

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Once we have ATE resources available31

to set up interference, we can run astandard, interconnect shorts test. We can use our ATE drivers to freeze the values ofthe non-scanned nodes A and C during CAPTURE-DR when any interference will becaptured in the Boundary Register receiver cells. The ATE drivers can be turned off atother times to minimize overdrive stress on upstream IC drivers. We can choose staticvalues to place on the ATE drivers, or, as suggested in [Robi90] we could assign eachATE driver a unique counting sequence number as we have done with the Boundary-Scan nodes. This way, any Boundary Register receiver seeing one of these SRVscorresponding to an STV assigned to an ATE driver will readily identify the non-scanned node involved in a short. The approach chosen will be influenced by ourconcern over how many (expensive) ATE drivers we wish to have running in parallelversus running the test several times with multiplexed resources.

A somewhat different approach to this problem is given in [USP93]. Again the ideais to use ATE resources to create strong values on neighboring non-scan nodes andthen see if these values appear on Boundary-Scan nodes. The drawing in Figure 3-18shows an example board topology.

Here we set up a Boundary-Scan test with only two PTVs, one that drives allBoundary-Scan nodes (in this case nodes B and C) to “0” and a second that drivesthem all to “1”. Thus, while we are performing this interaction test, if there are anyother shorts between Boundary-Scan nodes themselves, they will not be excited andtherefore are unable to cause driver damage or confuse the ultimate diagnosis.

Next, while these two PTVs are being driven, we use our ATE drivers to create theopposite states (“1” and then “0”) on only the adjacent non-scan nodes, in this case

31Note that this could be a large number of expensive resources if there are many locations on

a board where interactions are likely. This introduces the problem of managing theseresources (for example, by multiplexing) so that our tester costs are not driven too high.

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nodes A, D and F. This ATE drive condition need only exist for the length of time thechain of devices is in the CAPTURE-DR state.

Figure 3-18 shows some situations that need further discussion. Node A is beingtested because it is adjacent to node B, a Boundary-Scan node. This adjacencyrelationship can be determined two ways; first, by examining the X-Y board locationdata for every pin (in this case, pins 1 and 2 of U2) we can determine the distancebetween any two pins. If this distance is less than a predetermined shorting radius,then we will include the related nodes in our interaction test. The shorting radius ischosen by our experience with solder shorts such that two pins beyond this radius havelittle probability of ever being spanned by solder short. Second, if we do not haveboard X-Y location data, we can infer adjacency by looking at device pin numbers.Here we assume that pin 1 is adjacent to pin 2, but not adjacent to pins 3 or 4. Thissecond method is certainly less satisfactory since on a pin-grid array device, we maynot know that pins A3 and B5 are adjacent. Numerical adjacency may also cause us totest nodes that X-Y data would have told us are beyond the shorting radius.

Figure 3-18 also shows us that Boundary-Scan node C is adjacent to nailed nodeD. We can test node D, even though it is a TDO-to-TDI connection. This is because weonly overdrive node D with our ATE driver when the chain is in the CAPTURE-DRstate. Because TDO is unused during this time, we are able to do this. This could detecta short from TDO to some other signal that was disabled during other forms ofBoundary-Scan testing including chain integrity testing.

Next note that we can check for a short between nodes B and F which are adjacentat device U4, pins 8 and 9. (Also note that node E will have to be controlled by an ATEdriver so that the output driver in U4 is disabled during testing.) Now ask the question,what if Boundary-Scan node B is shorted to both node A and node F at the same time?The test will fail, but which nodes do we diagnose? This can be solved by noting thatnodes A and F are adjacent to the same Boundary-Scan node and should be tested at bythe same algorithm, but at separate times. This temporal splitting resolves theambiguity.

The circuit in Figure 3-18 can thus be tested with two applications of ourBoundary-Scan test; the ATE drivers drive nodes A and D in the first application andthen drive node F in the second. If a failure

32is observed in the first test application, we

can say without ambiguity which node(s) failed since they will affect independentBoundary-Scan nodes. If the second test application fails, we know that it had to benode F. Multiple applications also allow us to re-use expensive ATE resources insuccessive applications, if they are multiplexed. Finally, it is possible when producingthe diagnostic report, to report the adjacent pins

33 of the shorted nodes. These pins are

32Note, a failure here is defined as the opposite state being observed on the Boundary-Scan

node for both the expected “0” and “1” states. This helps us prevent other problems (forexample, an open solder joint on a receiver) from confusing the diagnosis.33 The use of pin adjacency data, integrated with knowledge of the workings of a testalgorithm, can be used to enhance the diagnosis in other cases, such as standard Boundary-Scan interconnection tests. Again, the assumption is that shorts and opens are likely to becaused by solder defects, so the diagnostic reports should use the words “probably located at”.

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the probable location of the short, so we are now getting a pin-level diagnostic for ashorts test that tests nodes.

3.2.5 BIST and Custom TestsWe can perform other tests with Boundary-Scan component chains. For example, ifseveral components have the RUNBIST capability, we can load all of them withRUNBIST (and the rest with BYPASS) and in principle,

34have them all execute their

self-tests in parallel. We put the chain in RUN-TEST/IDLE and clock it for themaximum number of clocks that any of the components require. All those receivingmore clocks than necessary will retain their self-test result. After clocking is done, weproceed down the data column of the TAP diagram to SHIFT-DR where the self-testresults are shifted out for examination.

User-defined instructions may be accessed to set up tests for internal portions ofcomponents, or to set up tests between cooperating components. For example, theTexas Instruments SCOPE Octal ICs [Texa91] can be made to cooperate for testingcircuitry and interconnect between them as shown in Figure 3-19. One such IC (U1)can have its Boundary Register drivers create pseudo-random patterns while beingclocked in RUN-TEST/IDLE. A cooperating IC (U2) can be set up as a LinearFeedback Shift Register (LFSR) to capture a test signature in its Boundary Registerinput cells. The intervening data path is thus tested with random patterns with theresulting data undergoing signature analysis compaction [Nadi77]. The compactedsignature can then be read out and compared against a known-good signature. (Theknown-good signature could be “learned” by exercising this test on a known-goodboard.) One point to note, if the signature received is not good, that indicates a failureof the data path but gives no diagnostic information.

34This parallel operation may not be possible if the allowable variations in how the ICs are

clocked are not mutually compatible.

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3.3 PORTING BOUNDARY-SCAN TESTS

The question sometimes arises, “Can I port a Boundary-Scan test from oneapplication to another?” This usually happens when someone creates a Boundary-Scan test in one setting (say for example, prototype debug) and now wants to run thistest in another (say, production test). The answer is “yes”, but there is a new andrather exciting opportunity here that many people miss. To see this, consider thehistorical root of this question.

Before Boundary-Scan came about, people had to construct digital tests(typically, for individual ICs) manually

35with a great deal of engineering sweat. It

could take weeks or even months for larger, more complex ICs. Naturally, afterexpending this much talent and time, if the test was to be used in a new context (say,ported from an IC production tester to an In-Circuit board tester) the difficulties inporting this test were usually much less than redeveloping the test from scratch. Thisrecognizes there is a great deal of intellectual value embedded in the test vectors.Figure 3-20 shows how one might manually develop a digital test for several similarapplications. The key thing to note here is that both the test creation effort and eachdebug/porting effort may be an exhaustive process.

This model for developing and porting test vectors has been around for a longtime, even creating its own industry. It is natural at first, to imagine that you wouldwant to use the same model with Boundary-Scan tests. However, there are importantdifferences with Boundary-Scan tests that make this approach wasteful and evencounterproductive. Figure 3-21 shows how Boundary-Scan tests are developed forsimilar applications.

With Boundary-Scan you have Automatic Test Program Generation (ATPG)software that actually generates test vectors and diagnostic information used by thatsame test when it is executed. The ATPG software should be able to generate theentire test in a time frame measured in seconds rather than weeks. This is the firstmajor difference. The second comes from the realization that the manually generatedtest does not have diagnostic information accompanying it. It is essentially a go/no-go test. When it fails, you typically get a report that says something like “Outputpins 38, 39, 44 failed at test vector 19287”. For this same example, a Boundary-Scan

35 Automated test generation for general ICs is fairly youthful, and it tends to generate tests of

horrific size, unsuited for board/system test purposes.

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test will give a much more thorough diagnostic that can include input pindiagnostics.

36

If at all possible, when porting a Boundary-Scan test, you should not port the testvectors, but rather, port the basic information of the device(s) participating in thetest and the structure of their interconnect. This amounts to porting the BSDL andnetlist information for most applications. Then the ATPG software used by a givenapplication can (in a few seconds) construct a test optimized for that application,complete with sophisticated diagnostics. If instead, you port a Boundary-Scan testthe old way by translating its vectors, you will find that it will lose its diagnosticcapabilities, resulting in a go/no-go test only.

There is a language called Serial Vector Format (SVF) that is being maintainedby Asset Intertech Inc.37 This language can be used to port vectors among applica-tions, although with the problems mentioned above. This language will allow theporting of (many) Boundary-Scan tests and also has the advantage of beingcomparatively terse and thus frugal with disc space.

38

An objection sometimes heard about SVF is that it can only describe a subset oflegal 1149.1 state transition sequences. For example, the compliance verificationtest sequence given in section 5.1.10 (page 180) cannot be expressed in SVF. Thistype of test, in places, will specify a precise trajectory through the state diagram.This is where SVF, in the interest of being terse, breaks down. It cannot specify alllegal transitions. So beware that using SVF will first convert your full-featured

36 When an In-Circuit test for a non-scan IC fails, we can only report what we see failing, not

what might be the cause of the failure, unless we have used an extensive simulation that canprovide this correlation. This will add additional time to the test development process ifindeed it is practical at all. Further, the assumptions used by the simulation model may causeimproper diagnoses.37

Try the site map at www.asset-intertech.com to find a specification for SVF.38

This terseness also means that it is highly unreadable by humans, so don’t expect to debug atest written in SVF. It is advised that only mature, fully debugged tests be converted to SVF.

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diagnostic test into a go/no-go test, and that it may modify the state transitionsequences in your tests to fit the limitations of the language.

3.4 SUMMARY

To conclude, we have seen in detail how the 1149.1 architecture can be used toimplement IC, board-level and system-level tests. There is more that can be done; thisis the subject of the next chapter on advanced Boundary-Scan topics.

This chapter has highlighted some of the practical issues seen when attempting todo Boundary-Scan tests on real boards and systems. For example, the fanout ofcontrol cells to driver enables on-chip will interact with board-level interconnectiontopologies to create particular cases of faults that need special attention during test.

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CHAPTER 4

Advanced Boundary-Scan Topics

As this book goes to press, the 1149.1 Standard is in its ninth year of existence.Chapter 3 discussed the most basic and general uses of the Standard. This chapterwill examine some other uses that have been proposed or have been implemented insome quarters.

Some of these advanced uses are clearly devoted to testing. For example,individual ICs can be tested during production for DC parametric performance (see4.1). A system can be unobtrusively observed during its operation using SampleMode test (see 4.2 and 4.3). Devices that do not themselves contain Boundary-Scancan be tested by surrounding Boundary-Scan devices (see 4.4 and 4.5). Multi-ChipModules and other packaging hierarchies can be tested (see 4.7).

However, some of these topics, such as firmware development support (see 4.8)and In-System Configuration (see 4.9) are examples of applications that are notobviously aimed at testing. Indeed they show how 1149.1 may add value to a systembeyond the realm of testing, which makes Boundary-Scan appeal to a wideraudience. Even now, the promise for new applications is still strong.

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4.1 DC PARAMETRIC IC TESTS

Most of the attention paid to Integrated Circuit test is focused on the testing of thelogic; does the circuit meet its logical function? Yet there is another realm that isalso critical, that of ensuring an IC’s DC parameters are within specification. Someof these are:

Input voltage levels; verify that a range of voltages appearing on an input areperceived by the IC as logic “0” or logic “1”. These parameters are termedand respectively.

Output voltage levels; verify that voltages produced on outputs are withinspecifications for logic “0” and logic “1”. These parameters are termedand respectively.

Output current drive; verify that an IC output, while producing a valid voltagefor logic “0” or logic “1” is able to sink or source a rated current. Theseparameters are termed or respectively.

Disabled output leakage; verify that an IC output, when disabled, has aleakage current within specification.

Testing for these parameters may need voltage or current measurements, oftenrequiring the provision of specific DC loading while the measurement is taken. ICtesters containing analog test subsystems such as shown in Figure 4-1, routinelyperform these tests on ICs at wafer test or package test as appropriate. Theseparameters are typically not tested any other time.

A difficulty is that some of these parameters relate to specific conditions atoutput pins. These conditions, like driving an output high, low or disabling it, requireus to coax the internal logic of the component into setting them up for us. If the IC iscomplex, it can take a lot of work to set up these conditions. Sensitive currentmeasurements, particularly for small currents seen during leakage tests, may takesignificant time on the order of (say) milliseconds. If a component contains dynamiclogic, millisecond measurements could exceed the ability of the logic to retain itsstate without some (noisy) keep-alive sequencing being supplied to it.

Testing parameters such as and can also be difficult to set up. In essence,stimulus to the IC logic is supplied using marginal voltages for these parameters andif the outputs behave improperly, the test fails. It may be difficult to interpret theresult into a diagnostic indicting specific input pins.

Boundary-Scan ICs can avoid many of these difficulties since the Boundary-Scanfacility has direct control of IC outputs and can observe IC inputs

1. For example, it is

a simple matter (using HIGHZ or EXTEST instructions) to turn off output driversfor measurements. In principle, using 1149.1 it should be possible to completelyautomate the development of many DC parametric IC tests that today require muchtedious engineering to prepare. This automation will be immediately useful to ASICfoundries where the preparation of DC parametric tests for customer-supplied IC

1Warning! If an IC input pin is attached directly to a Boundary Register cell without an

intervening input buffer, then input parametric tests may prove that the Boundary Registerworks within DC parametric limits, but not prove the same for the System Logic.

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designs is currently a challenge. Indeed, they may actually be able to save theircustomers time and money because of 1149.1 rather than in spite of it.

4.2 SAMPLE MODE TESTS

The 1149.1 SAMPLE instruction is constructed to operate in Non-Invasive mode; itwill not disturb an operating component when it captures the values on its I/O pinsand shifts out the sampled data. We can sample on many components in a chainsimultaneously, which offers the promise of implementing a “logic analyzer”function through the 1149.1 port. For example, a microprocessor address and databus could be sampled as well as an upstream data buffer to see if data associatedwith an address is arriving at the processor inputs. Some early work in this area hasbeen reported [Swee88] [Lefe90].

Some practical problems exist with the SAMPLE function, having to do with thecoordination of the System Logic clock(s) and TCK. For a system consisting of acollection of ICs, there are skews in the system clock distribution that have to beaccounted for along with the setup and hold times of the various clocked elements.This can prove challenging for even a single clock. When we attempt to add asecond clock distribution path for TCK, we now must coordinate two independentlyclocked state machines, the system logic of the board and the 1149.1 logic. When the1149.1 logic is operating Non-Invasively, the two state machines are completelyindependent, except when the SAMPLE instruction is in effect. SAMPLE causes thecells of the Boundary Registers to capture (sample) data appearing on the I/O pins ofthe components, while these same pins are under control of the system clock.

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Figure 4-2 shows two hypothetical flip-flops feeding data to each other. Belowthe circuit diagram is a timing diagram for the circuit that shows the skews, setuptimes, hold times and propagation delays that must be properly accounted for. In thedistribution of SYSCLK, skews are introduced into the resulting buffered

2clock

signals CK1 and CK2, shown as skew1 and skew2. When a rising edge occurs onSYSCLK, both Q1 an Q2 retain their data for time thold1 and thold2, then becomeunpredictable until times tprop1 and tprop2—the flip-flop propagation delays—haveexpired. Then, to properly set up the data before the next SYSCLK occurs, timestsetup1 and tsetup2 must be observed.

Now consider Figure 4-3 where we have added TCK distribution to the samesimple circuit where components 1 and 2 now have Boundary-Scan. SAMPLE modeis driven by TCK and we now have an asynchronous sampling process going on inthe same ICs, driven by TCK.

2Differences in the propagation delays of these buffers represent a source of skew for this

example. Another source of skew is simply the wiring that distributes the clock signals. Onboards, ICs may be widely separated so that differences in path lengths may be significant.

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We see the same timing diagram for the system operation of the flip-flops. Belowthat is the timing for the operation of the Boundary-Scan SAMPLE function. There,we see skews on TCK distribution. The two TAPs are slightly skewed as they

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proceed from SELECT-DR-SCAN to CAPTURE-DR. Once in CAPTURE-DR, thenext rising edge of TCK will cause the data on Q1 and Q2 to be captured. Whatconcerns us is the relationship of the timing on Q1 and Q2 to the setup times of theCapture (CAP) flip-flops. As shown in Figure 4-3, there is not enough setup time forQ2 to be properly sampled by TCK1.

During SAMPLE mode, it is quite possible that the setup and hold timerequirements of the Capture (CAP) flip-flops will be violated unless some carefulmeasures are taken. Now, because many newly designed digital systems are beingclocked at rates that already stress technological limits, this problem of controllingerrors and skews in two asynchronously operating clock systems is a real challenge.

One possible solution (that is often not possible without specific design effort)involves interrupting the system clock very briefly while applying the critical TCKthat performs the data capture. This introduces the difficulty of interrupting a clockwithout creating hazardous clock slivers. Also, there is a propensity for many newcomponents to be internally clocked with their own clocking subsystems that arephase-locked to the board-level system clock. Phase-locked clocks cannot toleratethe phase jitter that an interrupted system clock would inject. These challenges,though not insurmountable, make SAMPLE mode testing much more difficult toimplement.

An approach to solving this problem has been documented [Jose93] where aspecial variant of the SAMPLE function was implemented. (It was given a newname since it was not compliant with the 1149.1 SAMPLE definition.) Thisinstruction effectively coordinates the capturing of data in CAPTURE-DR with thesystem clock, to control the timing problems shown above.

4.3 CONCURRENT MONITORING

Concurrent monitoring, proposed by Wagner and Williams of IBM, [Wagn91]utilizes the 1149.1 SAMPLE mode and pays special attention to the clockingproblems discussed in section 4.2. The technique uses the SAMPLE mode operationof 1149.1 in conjunction with diagnostic procedures (for example, test microcode) ina coordinated fashion to increase the fault coverage of the diagnostic procedures. Inessence, each scanned pin of the circuit can be sampled while diagnostics arerunning to obtain much higher visibility into the circuit’s operation.

The basic concept, shown in Figure 4-4, is to have the diagnostics set upconditions of interest in the system then, in a controlled manner, sample the ICs’ I/Opins. While the diagnostics continue, the sampled data can be shifted out andcollected in a signature collector, a multiple-input signature register (MISR)

3 in this

case. The resulting signature is then compared against an expected-good signaturecalculated by simulation or learned from a known-good board.

3Note that the IBM work [Wagn91] was not done with an 1149.1 compliant design although

there is no reason why it could not be as the authors point out. Locating the MISR thatmonitors several TDO pins in an 1149.1 compliant component may be stretching the rules ofthe Standard.

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The paper offers a probabilistic argument for how this technique will improvefault coverage. Intuitively, one can see how having hundreds of extra observationpoints available by means of concurrent sampling can help detect faults that mayhave been excited, but not propagated to a conventional observation point. In thecase of test microcode the observation point is the test-and-branch unit of the testcontroller actually executing the microcode.

4.4 NON-SCAN IC TESTING

Boards will still contain non-scan ICs that require testing for the foreseeable future[Hans89b] [Park89]. Such a situation is shown in Figure 4-5 where a non-scandevice (U7) is connected to some Boundary-Scan ICs and has some tester nail accessas well.

The non-scan IC can be tested by placing scanned ICs U3 and U4 in EXTEST.ICs U1 and U2 should be in BYPASS (or CLAMP or HIGHZ) to keep theircontribution to the shift chain as short as possible. ICs U3 and U4 will receive someof the output data from U7 (at CAPTURE-DR) and will supply some of the inputdata to U7 (at UPDATE-DR). Physical nails will supply the rest of the stimulus orreceive the remaining IC output signals. We must coordinate our physical naildrivers with UPDATE-DR and look for IC outputs on our physical receivers at

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152 Advanced Boundary-Scan Topics

CAPTURE-DR as in Figure 4-5. In this way, we can approximate fairly closely asimple unformatted “truth table”

4 test for U7.

4This cannot hope to approach the accuracy that a tester with full nodal access can enjoy,

since some of our resources are controlled by Boundary-Scan resources through interveningTAPs in several dispersed ICs. We do not have control of the skews and errors that these willintroduce.

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Some problems with this approach do exist:

If the component under test is not synchronizable and requires a homingsequence,

5this will introduce considerable complication into the Boundary-

Scan scanning process, perhaps to the point of being impractical.

A dynamic component may require a minimum test application rate thatcannot be achieved because of the length of the scan sequences.Serialization will greatly lengthen the overall test time, which couldsignificantly reduce throughput.A longer test has tester drivers overdriving upstream signals that may now beliable to overdrive damage.

If the original test was formatted, that is, it had waveform modulation imposedon its logical data [Park87], this will vastly lengthen the test if it is translatedverbatim.There is the problem of undetectable shorts, as shown in Figure 4-7.

Figure 4-7 shows a short between two Boundary-Scan drivers that creates aWired-AND of their data. The logic component they are to test also performs theAND of these signals, so the output of the target component does not show a failure.This short is not detectable, but it could degrade the lifetime of the drivers that itaffects so it may be of great concern. If the Boundary-Scan drivers are part of abidirectional construct, or are capable of monitoring their pad states (see 5.1.5 onpage 176) during EXTEST, then this short can be detected.

5 A homing sequence requires the tester to apply input patterns, examine component outputs,

and make decisions as to what patterns to apply next based on the observed outputs. If theoutputs that must be observed are only visible by means of the scan process, this greatlycomplicates the decision logic.

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These problems point out that while we could eliminate some test nails using thistechnique, we can also create a new set of test concerns.

4.5 NON-DIGITAL DEVICE TESTING

Can Boundary-Scan resources be used to test non-digital devices? This questioncould be asked when a circuit like that in Figure 4-8 is to be tested. Here, resistoris used to match the line impedance to eliminate nodal noise caused by signalreflections. In a DC sense, the node could perform perfectly even with the resistormissing. However its AC performance may not be adequate. Unfortunately,Boundary-Scan interconnect testing is slow enough to be essentially a DC test.

We can test this resistor very simply with an analog measurement if we have atester nail on this node (and of course, on the power node too). If we do not, then wewill have to use some planned feature that we deliberately add to our Boundary-Scanimplementation to sense the existence (not necessarily the value) of resistor

One approach might be to add a new instruction to the Boundary-Scaninstruction decoder in U1 (we could call it “LEAK”) that causes a small current flow

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from the driver pad to ground. We could then set up a test that turns off the driverenable in the driving IC U1 and captures the value seen at the receiving IC U2. If thepull-up resistor is in place, the receiving cell will see a “1”. If the resistor is missing,the small current flow will cause a “0” to appear. Of course, a resistor with thewrong value might not fail this test.

The point to be made is that the removal of nails from supposedly digital circuitsthat are scanned may not be practical in many cases without some plan of attack forall those analog components that are actually there but are logically invisible.

4.6 MIXED DIGITAL/ANALOG TESTING

Boundary-Scan is a digital testing technology. However, ICs do exist (and areexpected to become more common) that contain mixed digital/analog circuitry.Mixed-signal testing is a difficult problem, but Boundary-Scan can again play a roleby adding the ability to partition the analog and digital portions of the circuit asshown in Figure 4-9. (Note, mixed-signal ICs can also be implemented with 1149.4technology as described in Chapter 7.)

By partitioning the digital logic from the analog circuitry with the BoundaryRegister, it is possible to write tests that can test the digital portion of the componentdirectly. Further, one can set up digital values to stimulate the analog circuitrydirectly for subsequent analog measurements.

One great benefit of this partitioning is that it can make tests for the digital logiccompletely deterministic. Without Boundary-Scan, we might have to apply analoginputs to a device in hopes of setting up the proper digital stimulus conditions fortesting. However, analog circuits are inherently “noisy” from a testing point of view.The quantization of analog signals into digital values will often show variations thatare completely acceptable from an operational standpoint, but frustrate our effort toapply known, repeatable digital signals during a test. With Boundary-Scan, we canalso apply digital tests with extreme values that fall outside the domain of operation

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of the analog circuitry. For example, an analog filter front end to a digital circuitmight not be able to slew from an “all zeros” digital value to an “all ones” value intwo successive tests.

Figure 4-10 shows two ICs with Boundary-Scan that communicate by differentialsignaling. Differential signaling is an analog technology,6 but is a commontechnique often found in “digital” designs. Many digital designers would argue thatdifferential signaling is a digital technology, but it is not generally possible to insertBoundary-Scan cells directly in the differential pathway; they must be placed (asshown) before or after the differential conversion. This leaves us with a testingproblem because we have two signals controlled or observed by single cells. Thesesignals can suffer opens and shorts like any others. Today’s consensus is that thisproblem should be treated as follows:

design differential structures with Boundary-Scan as shown in Figure 4-10.

use the PORT_GROUPING attribute in a BSDL description (see 2.3.2 on page62) to identify the paired differential signals, whether they are voltage orcurrent signals, and which signals are positive and negative.

conduct test generation as before for the positive portion of each differentialpair. Test diagnostics routines must be made aware of the negative signalpairing for generating effective repair instructions.

To complicate matters a little more, differential signaling is not always utilized ina straightforward manner at the board level. Figure 4-11 shows three examples ofboard topologies that use differential drivers and/or receivers in ways that may betroublesome for Boundary-Scan software.

6From the point of view of the 1149.1 Working Group, differential drivers and receivers

should be viewed as instances of the analog/digital configuration shown in Figure 4-9.

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Figure 4-11A shows a case where the positive and negative legs of a differentialpair are swapped, yielding a “free” inversion in the logic. The effect of this on aBoundary-Scan test algorithm is that Serial Test Vector (STV) data from a driver isinverted upon reaching a receiver. If the algorithm is not prepared for this situation,it will try to diagnose a failure.

Figure 4-11B shows a case where a single-ended driver is connected to thepositive leg of a differential receiver while the negative leg is connected to areference voltage. (If the legs were swapped, as in the case above, then an inversionwould be implemented too.) Boundary-Scan software should prepare and execute atest for this case without problems, but defects in the reference circuitry would likelynot be diagnosed correctly.

Figure 4-11C shows a case where a single-ended driver is connected to thepositive leg of a differential receiver while the negative leg is driven by an activereference generator function. This function may change the generated reference level“on-the-fly”, with the effect that the output of the receiver has a selectable delay.Tester resources could be used to force the reference generator to produce a staticlevel to convert the problem into the same form as Figure 4-11B. The differentialquestion is revisited in Chapter 7 where 1149.4 resources are used to implementtests.

4.7 MULTI-CHIP MODULE TESTING

Multi-chip module (MCM) technology offers the ability to place a number ofIntegrated Circuit die

7 upon a single substrate within one package as shown in Figure

4-12. MCMs have been used for many specialized applications for a long time. Forexample, Hewlett-Packard has used mixed analog/digital MCMs as the front end of

7Other components may also be placed, such as surface mounted capacitors. Integral thin-film

resistors, capacitor, and even inductors may be part of the substrate as well.

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158 Advanced Boundary-Scan Topics

digital voltmeters for over twenty years. Today the desire is great to utilize MCMsmuch more broadly in many new applications

8. Because testing is a large contributor

to the cost of an MCM, Boundary-Scan has much to offer in the quest to bring MCMtechnology into mainstream applications [Poss91].

That said, there is little to add about what Boundary-Scan can do because anMCM is essentially a very small board, with little chance of being effectively probedwith In-Circuit probes. The various interconnect, bus, connection or BIST testsalready outlined are quite useful. Additional performance testing that may be neededwill not enjoy much enhancement because of Boundary-Scan—as is also the casewith boards.

It is important to note that 1149.1 does not form a hierarchy; for example, if youplace a number of 1149.1 components onto an MCM, you can test it as a smallboard. When you place the MCM onto a board with other MCMs and individual1149.1 ICs, you cannot visualize that MCM as a monolithic individual componentcontaining 1149.1. The MCM is still a collection of N 1149.1 ICs. For example,when programmed for BYPASS operation, the MCM does not have a single-bitBYPASS register; it is N bits long. The MCM contains N Instruction Registers, eachwith its own repertoire of instructions, and so forth. Thus, an MCM must bedocumented with its own netlist9 and set of BSDL descriptions. Note in the late1990’s we have seen the advent of “silicon core” technology, where several entire

8MCMs are expensive today, but offer decreased size/weight, higher reliability, and higher

operating frequencies (when properly utilized). The workstation (performance) and thelaptop/palmtop computer (size/weight) marketplaces are two areas where MCMs hold goodinterest.9

The netlist information need not be completely specified for board testing application if youassume that once successfully fabricated, the internal MCM interconnect will not break. It issufficient to document only those nodal connections that reach an MCM I/O pin. Leavinginternal interconnects undocumented may ease concern for those who want to keep thisinformation secret.

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ICs may be laid down on a monolithic piece of silicon. Some research [Jarw94] hasbeen done for this problem,

10 but it looks like we will have the same result as we

have see for MCMs. This could change if silicon cores are re-synthesized such thattheir 1149.1 circuitry is merged into a compliant design with a single BSDLdescription.

4.8 FIRMWARE DEVELOPMENT SUPPORT

For some time now, microprocessors have offered emulation support for hardwaredevelopment systems. These development systems allow a system designer (foreither hardware, firmware or software) to gain control of the microprocessor and useit as a tool to control and observe the system. For example, a hardware developmentsystem would allow a designer to halt the processor, examine or modify processorregisters, single-step it through a sequence of instructions, set software breakpoints,and so on. Add to this the ability to display the point in the program being executed(in both assembly code and higher-level code) and to display additionalmeasurements taken from important system signals (by clip-on probes) and you canappreciate the power of such a tool. Indeed, a new microprocessor entering themarketplace without such support available is likely to be unsuccessful.

The hardware development system is usually interposed between themicroprocessor and the system by means of an isolated and instrumented socket thatis placed into the board where the processor would be. The processor itself iscontained in a remote pod where the board signals are delivered and the developmentsystem can monitor them.

Today, several trends are making the traditional hardware development systemobsolete. First, the higher operating frequencies we are seeing, along with higherprocessor pin counts make sockets

11and umbilical cables quite unreliable. Second,

each new processor, even from the same vendor, requires a massive investment inthe design of a complementary development system. Third, yesterday’s singleprocessor is today’s family of processors, each with a smaller market share andshorter market lifetime. This adds up to a situation where traditional developmentsystems are increasingly costly to develop and yet each addresses a smaller share ofthe market with a shorter lifetime.

The 1149.1 Standard can help with this problem. After all, part of its name is“Standard Test Access Port”. If Boundary-Scan exists on a processor, it is arelatively simple matter to implement additional instructions that will help supporthardware development systems through the TAP port. This immediately solves thefirst problem concerning access and operating frequencies. Second, with somecooperation from IC merchants (who have much to gain if development support iseasily available) it is possible to standardize on a small set of development support

10Jarwala’s work specifically addressed MCMs but the problem discussed is the same.

11Packaging techniques such as Surface Mount Technology (SMT) and Ball-Grid Arrays are

rapidly making sockets obsolete.

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160 Advanced Boundary-Scan Topics

methodologies. Such standardization would allow one investment in a developmentsystem to support many processors.

An example of a processor with 1149.1 support for development is the AdvancedMicro Devices Am29035 [AMD91]. This IC allows access to a set of hardwaredevelopment support functions using the 1149.1 port. These same functions are alsoavailable from the processor edge pins, if you can get to them. Via 1149.1, you canaccess these functions through four wires without physically disturbing the board orsystem it is mounted in. Indeed the processor could be a member of a chain of1149.1 ICs and we could still access its support functions, as well as those of otherICs in the chain.

4.9 IN-SYSTEM CONFIGURATION

Field-programmable gate arrays (FPGAs) and complex programmable logic devices(CPLDs) have become increasingly popular. One factor driving this is that they aregetting quite dense, allowing major portions of a system to reside within them.Another factor that is decreasing the total systematic cost of these devices is that factthat they are specifically designed to be programmed after they have been mountedon a board. This is known as “In-System Configuration” or “ISC”.

ISC has several attractions; first, the design can be changed at any time byreprogramming the device(s). This is attractive for system maintenance, fieldupdates, and even as a run-time feature of the system itself. Second, if you programthese devices after they are placed on board, you do not need an inventory of pre-programmed devices.

12 This lowers your Work-in-Progress expenses. Third,

handling blank devices13

for a programming step before they are mounted on a boardinvites a lot of additional manufacturing defects.

CPLDs are getting very large and they represent a worst-case for conventionalIn-Circuit testing due to lack of models as discussed in section 1.1.1 on page 2.Worse, if you do conventional In-Circuit test you must first wait until the devices areprogrammed before they can be tested. This could be a lengthy period of time duringwhich device damage due to fault may occur. Then there is always the chance thatsome board-level fault causes the programming to fail. This will lead to diagnosticambiguity.

Because of such problems consumers have demanded that 1149.1 be included inprogrammable device designs. Thus, FPGA/CPLD vendors have invested in the fourextra pins for Boundary-Scan. It did not take long for them to realize that these samefour pins and serial protocol could be used for programming these devices as well. In1996, a group of these vendors, brokered by an ATE company, met to see if theycould agree on a common protocol for using 1149.1 for In-System configuration. It

12However, if the rate of programming failure is more than a few percent, this could translate

into a lot of board repair work dedicated to replacing programmable devices, which mightnegate these advantages.13

These devices are themselves becoming quite large with high pincounts, which aggravateshandling difficulty.

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delights me to say this group has now become a formal part of the 1149.1 WorkingGroup and has decided (after some initial misgivings) that full compliance with1149.1 is desirable. Thus this group, as this book goes to press, is working on a setof common protocols that will allow users to program multiple devices with somedegree of device family independence and vendor independence.

There are several underlying technologies used in FPGA/CPLD devices. Somelook a lot like EEPROMs and some are like FLASH RAMs. In most cases, thecommon thread is that you pump bits into them and then allow them to “cook” untilthe bits are successfully programmed. This can take anywhere from severalmicroseconds to tens of milliseconds, per “word” of data. When the time to movedata (serially) into one or more devices is a fraction of the cook time, it becomesattractive to program multiple devices in concurrently. By “concurrently”, I mean intime, not that we are using separate Boundary-Scan chains. Here is how it is done:

14

Step1: Initialize a chain containing one or more programmable devices andassure the integrity of the chain.

Step 2: Program each non-ISC device into a benign state (load BYPASS,CLAMP or HIGHZ as appropriate) and use PRELOAD on the ISC devices toset up their output drivers for a benign condition.

15

Step 3: Load the ISC device instruction registers with the ISC_ENABLEinstruction

16 while preserving the non-ISC instruction registers with the

choices made in Step 2.Step 4: Load the ISC device instruction registers with the ISC_PROGRAMinstruction. This is the workhorse instruction used to load programminginformation.

Step 5: Shift data/address information for all ISC devices into the chain. (Shiftappropriate “don’t care” data into the non-ISC device data registers.)Step 6: Proceed to the RUN-TEST/IDLE state and clock the chain until thelongest “cook” time has expired.Step 7: If there is more data for any ISC device, return to Step 5. If somedevices are completely programmed, simply reprogram their last address/dataover again.Step 8: Load the ISC device instruction registers with ISC_DISABLE. Go tothe RUN-TEST/IDLE state and clock the chain for the number required by thelongest ISC device.

14The ISC Working Group has not finalized this information, so be ready to obtain the final

document when it becomes available.15

Some ISC devices will not have their outputs controlled by the Boundary Register, butrather will simply disable all drivers. This mirrors the choice you have when implementingINTEST (see section 1.5.2 on page 37).16

ISC_ENABLE sets up an environment for ISC programming. It must be executed beforeany other ISC instruction. The ISC_DISABLE instruction removes this environment.

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162 Advanced Boundary-Scan Topics

Step 9: Proceed to TEST-LOGIC-RESET to bring the ISC devices into theirprogrammed operational states.

17

Other programming activities, such as readback verification of the programmedcontent or device erasure are supported in a similar fashion. An FPGA/CPLD devicecan be thought of as being in one of four macro states during its existence. These areshown in Figure 4-13.

Macro state 1 (Blank) is the macro state the device is in when first manufactured.In this macro state, the device has no programming (or at least it acts that way). TheBoundary-Scan facility is fully functional however and the Boundary Register cancontrol any I/O pin (for example, with EXTEST) as a fully bidirectional pin.

18 In this

macro state there is no “System Circuitry”, so INTEST, if offered, would actaccordingly. Vendors of these devices usually force the output drivers of blankcomponents to a disabled state. This is the “system behavior” of the outputs, so whennon-invasive instructions like BYPASS or IDCODE are executed, the drivers willremain disabled.

Macro state 2 (Being Programmed) is entered when the device, not currentlyenabled for programming, is now enabled by the ISC_ENABLE instructionsequence. As in macro state 1, the Boundary-Scan facility is fully functional (forexample, using EXTEST) and the Boundary Register can control any I/O pin as afully bidirectional pin. The ISC_ENABLE instruction itself has one of two optionsfor controlling the states of the I/O pins; either it disables all output driversindependently of the content of the Boundary Register, or the Boundary Registeritself (as set up by a PRELOAD sequence) has control of the I/O pins. We call thesetwo options “HIGHZ” behavior (see section 1.5.4) or “CLAMP” behavior (see

17Note you can bring the ISC devices into their operational states in a particular sequence by

loading their instruction registers with the BYPASS instruction one-by-one while the othersremain in ISC_DISABLE.

18 By customizing the BSDL description, any bidirectional pin can be pared down in scope to

a simple input or output only to fit the ultimate board application, if desired.

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section 1.5.5), because they mirror those two instructions, including targeting theBYPASS register. Note that all subsequent ISC instructions for any one device willuse the same option for controlling output drivers.

If while in macro state 2 a normal 1149.1 instruction is executed, it will behaveexactly as it is specified by the Standard. If another PRELOAD sequence is executedfor example, this will change the state of the Boundary Register content, which couldchange the state of the output drivers when an ISC instruction is restored to theinstruction register. The “system state” of the device with respect to INTEST, forexample, is still blank.

Macro state 3 (Programmed) is entered when an ISC_DISABLE instruction issequence is performed. This does not cause the device to take on its programmedbehavior (that happens in macro state 4) but rather, it is still behaving as a “blank”device including its I/O behavior. The device can return to macro state 2 for otherprogramming activities if another ISC_ENABLE sequence is performed. Thus thedevice could progress from a programming process to a readback process withoutever being in its system operational state. The device can also proceed to macro state1 (blank) if an ISC erasure procedure is executed or the TAP is reset. Macro state 3will persist until the instruction register (currently loaded with ISC_DISABLE) hasthat instruction displaced by a non-ISC instruction.

Macro state 4 (Operational as programmed) is entered by displacing theISC_DISABLE instruction from the instruction register with a non-ISC instruction.This can be done simply by putting the TAP in the TEST-LOGIC-RESET state, or bydeliberately loading an instruction such as BYPASS. This choice allows selecteddevices in the chain to be brought into operational status in a particular sequence ifdesired, or they can all be made operational simultaneously. Now, in contrast to theprevious three macro states, a non-invasive instruction such as BYPASS or IDCODEwould behave as you would expect for a conventional logic device; the device’snewly programmed system logic would control the output drivers and respond to theinputs.

4.10 HARDWARE FAULT INSERTION

Hardware fault insertion is a technique used to “simulate” faults in a hardwareimplementation rather than by more traditional software simulation techniques. Oneobvious advantage is speed; hardware executes its function at its native speed whilesoftware simulation is typically orders of magnitude slower. However, manyschemes for hardware fault insertion are cumbersome at best. A paper [Nade95]shows how a relatively simple addition to Boundary Register cells, along with asupporting instruction, can be used to perform hardware fault insertion.

Boundary-Scan-based hardware fault insertion takes advantage of themultiplexor function that most Boundary-Scan cells have between the Update Flip-Flop (UPD) and the output of the Boundary Register cell. This multiplexordetermines whether an input(output) is passed through the cell untouched, orwhether the content of the Update Flip-Flop is substituted in its place. If we think ofthe Update Flip-Flop as containing the value of a stuck-at fault, all we need is a way

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to selectively apply this fault value to an I/O pin. This is done with the a simple19

modification to a classic Boundary Register cell shown in Figure 4-14.

In this cell design, a “second” Update Flip-Flop is added, labeled “Update-FI”,(for “fault insertion”). For all the standard 1149.1 instructions, the first Update Flip-Flop is clocked by the Update-DR clock signal. But for a new instruction (let’s call it“Insert_Fault”) the Update-DR clock is deactivated and the Update-FI clock takes itsplace. Thus, when the Update-DR state in the TAP State Diagram is passed, theUpdate-FI Flip-Flop loads the data from the Capture Flip-Flop rather than the normalUpdate register.

The content of the Update-FI Flip-Flop is OR’ed with the Mode line supplied bythe TAP Instruction decoder. If Update-FI contains a “0”, then it has no effect on thenormal operation of what is essentially a BC_1 cell design. If the Update-FI Flip-Flop contains a “1”, then it overrides the Mode signal and forces the cell to insert thevalue contained in the Update Register cell, regardless of what instruction is loadedin the Instruction Register.

Here is how you would use this capability. First, as with any 1149.1 activity, youwould reset the chain of devices to the TEST-LOGIC-RESET state. This asserts theRESET signal so that the Update-FI Flip-Flop is cleared. Then you would execute aPRELOAD sequence (which is non-invasive) to preload the Boundary Register witha set of stuck-at “0” or “1” values for any pin(s) of interest, both input and output.

20

(Note you must to assign a “0” or “1” to all cells, but only those later “fault insertion

19 This modification is simpler than that shown in [Nade95]. The design in Figure 4-14 does

not support fault insertion while EXTEST is in effect. The design in [Nade95] is not strictlycompliant with the standard since it can interfere with the non-invasive definitions ofinstructions such as BYPASS, but it will work well with most tools.20

Note, if this cell design is applied to output enable control cells, then you can “fault” a 3-state driver, causing it to be “stuck-at-enabled” or “stuck-at-disabled”.

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enabled” will actually substitute faulty values.) Then you would load the instructionregister with the INSERT_FAULT instruction which targets the Boundary Register,but now clocks only the Update-FI Flip-Flops at the UPDATE-DR state. You wouldshift in a pattern of “0” and “1” bits such that only those pins that should be faulted(either high or low) are activated. Once passing UPDATE-DR the selection offaulted pins would be injected with faulty data specified in the PRELOAD sequence.

You can insert as many faults, of either polarity, to any set of equipped I/O pinson as many Boundary-Scan devices as you want. This can be used to evaluate theeffectiveness of other test/diagnostic techniques, such as background systemdiagnostic tests. This was a principle motivation for the [Nade95] work , done for thetelecommunications industry. The ability to add fault insertion Boundary-Scan cellsis offered by at least one EDA vendor, LogicVision as part of their “icBist” tool.

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CHAPTER 5

Design for Boundary-Scan Test

Design for Testability (DFT) is a subject covering a huge amount material. The 1983survey by Williams and Parker [Will83] is still remarkably current in its enumerationof DFT techniques (it lacks Boundary-Scan of course), but many of the contextshave changed. For example, signature analysis [Nadi77] testing is now conductedon-chip, though it started as a board-level technique. This reflects the incredibleincrease in the density of Integrated Circuit (IC) components. In 1983, the 1149.1Standard would have been largely impractical because the logic needed to implementit would have been a large fraction of an IC. Today, we are seeing ICs designed withsignificant amounts of on-chip testing circuitry, including 1149.1. Without DFT, aVLSI component might not be economical to produce in volume.

Other technologies are also driving the need for DFT. In the board domain, wesee VLSI components contained in ever-shrinking packages placed ever closertogether on boards fabricated with ever-smaller trace widths and increasing numbersof layers. Two-sided component placement, blind vias, Surface-Mount Technology(SMT), Tape Automated Bonding (TAB), Ball-Grid Arrays (BGAs), Chip-on-Board(COB), daughter-board structures, and Multi-chip Modules are some of the factorsthat threaten existing board testing technology. The phrase “yesterday’s system istoday’s board” is quite true.

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168 Design for Boundary-Scan Test

One complaint I have had about DFT literature (for which I am partlyresponsible) is that the word “Test” embedded in “DFT” is all-inclusive. It shouldnot be. As with the title of this chapter, DFT should be qualified by the type oftesting anticipated. For example, there should be Design for In-Circuit Testing(should this be called DFICT?) and Design for Edge-Connector Functional Testing(DFECFT?) and Design for Integrated Circuit Testing (DFICT? -- no, already taken.)and so on. The type of testing to be done greatly influences your DFT decisions. Forexample, many In-Circuit testing DFT rules [Bull87] are mechanical in nature, tofacilitate In-Circuit probing. These are irrelevant for edge-connector testing. Weneed to consider DFT as “DFxT” where “x” is the target test technology.

Along with the type of testing, we must not forget the target failure mechanisms,the “real” faults that we are trying to detect. Unfortunately, we are often guilty oftesting for failures that are not prevalent because they are convenient (that is,supported by our tools). Untold wealth has been spent simulating single-stuck-at(SSA) faults and calculating dictionaries for them when prevalent real defects, suchas shorts, are not adequately described by the SSA model. Fortunately we have beenlucky that SSA derived tests often will detect non-modeled failures, but accuratediagnosis has been a problem. Can we depend on luck in the future?

Boundary-Scan is primarily targeted at board level manufacturing faults—thehavoc of the production process—affecting digital components. These include, inrough order of prevalence:

solder defects creating opens (too little solder).

solder defects creating shorts (too much solder).

misloaded components, including wrong or missing components.dead components or components with electrical damage to input or outputbuffers.

Boundary-Scan does not directly attack problems such as AC timing (delay test)for example. If a device implementing 1149.1 does not contain a self-test capability(such as RUNBIST) then it can completely miss deeply embedded internal faultstoo. If either of these failure mechanisms are important to you, you need a differentstrategy for them.

IEEE/ANSI Standard 1149.1 [IEEE99] is the first standardized DFT technology.Other techniques exist [Will83] such as Level-Sensitive Scan Design (LSSD) andBuilt-in Logic Block Observer (BILBO), but they have not achieved the status of astandard. Generally, there is little available support (that is, software) for theseapproaches; and the support that does exist typically is not transferable.1 Forexample, an LSSD design system may have been used in the design of a board, but itcannot readily transfer test information to an ATE system from an outside vendor.

The 1149.1 Standard, along with BSDL, is a major step towards surmountingthese obstacles. The Standard gives the IC community, the Electronics Design

Of course within large, vertically integrated companies there may be vast quantities ofsoftware support for a particular DFT methodology. However, this software would be largelyinapplicable outside its native environment because of small differences in how othercompanies might define similar DFT techniques. (The avoidance of patents is another issue.)

1

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Automation (EDA) community, and the ATE community (among others) a commontarget. BSDL creates an interchange capability so that the customers common tothese communities can readily utilize a selection of tools from different vendors. Theselection of “Best-of-Class Tools” will be a revolution in our industry.

5.1 INTEGRATED CIRCUIT LEVEL DFT

We first look at Design for Test concerns that should be observed at the IC level.Some of these concerns have their effects later at the board or system levels, but thenit may be too late to redesign the IC.

5.1.1 TAP Pin PlacementWe noted in the section on chain integrity testing (see section 3.2.1 on page 119) thata short between the TDI and TDO pins on a package was particularly troublesome todiagnose. Figure 5-1 shows some TAP pin placements. It is natural for them to benear each other because they are the terminals of the Boundary Register that lies onthe circumference of the die.

Figure 5-1A shows a placement for TDI and TDO pins that maximizes the likeli-hood that a short could occur between them. This type of layout should be avoided.Figure 5-1B and Figure 5-1C show preferred layouts that reduce the probability oftheir shorting2. This leads to our first DFT rule.

The main cause of board shorts is the bridging of solder between adjacent pins, particularlywith fine-pitch spacing.

2

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170 Design for Boundary-Scan Test

DFT-1: Place TDI and TDO pins on the end or the corner of a package toreduce their likelihood of being bridged by solder.

Second, noting that many ICs today require a large number of power and groundpins, you could contrive placing some of them next to TDI and TDO as depicted inFigure 5-1C. In the event of a short, these pins will create a solid “0” or “1” if theybecome shorted to a TAP pin. Shorts to other signals might not have deterministicbehavior.

DFT-2: When possible, place power pins between TDI and TDO pins andother signal pins.

5.1.2 Power and Ground Distribution

Power and ground distribution is always a concern during IC design.3 A typicalVLSI component may have many power and ground pins to distribute leadinductance over many parallel pathways. If this distribution is not handled carefully,the result could be Ground-Bounce.

Note too that power and ground pins, by nature, are often highly redundant. This leads to testcoverage deficiencies that are often overlooked. See [Tege96] for a discussion.

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Ground-Bounce occurs when inductance and/or resistance in the powerdistribution pathway injects a voltage drop across internal circuit nodes that aresupposedly referenced to the same value (power or ground). This has the effect ofsuperimposing a voltage fluctuation on a signal. If this signal is TCK by chance, thenwe can lose synchronization with the TAP state diagram if the fluctuation is largeenough to inject a new TCK clock cycle. Figure 5-2 shows an actual Ground-Bounceon TCK for a VLSI component. This 1.38-volt bounce, approximately 25nanoseconds wide, is sufficient to add a new TCK cycle. The voltage seen inside thepackage is likely to be higher because the inductive contribution of the lead frameand bond wires will be added.

Inductive Ground-Bounce is worsened by the ability of Boundary-Scan to causemany drivers to switch state at the same time, causing a current surge. While thevalue of lead inductance L may be very small, high-speed current (i) transitionsamplify the effect because the voltage V is given by:

When a Ground-Bounce on TCK occurs, it is most likely to occur on the fallingedge of TCK while in UPDATE-IR or UPDATE-DR because this is when output pindrivers can switch. The effect is to inject a clock pulse on TCK some nanosecondsafter the falling edge. Now, since TMS is set to one at this time (needed to get intothe update state and then to get to SELECT-DR-SCAN), the TAP will proceed toSELECT-DR-SCAN, one cycle sooner than we expect. If our intent is to travel downthe data column again (which is often the case during testing) we will then issueanother TCK to get to SELECT-DR-SCAN, not realizing we are actually therebecause of the bounce. This sends the TAP to SELECT-IR-SCAN instead. Sincetraversing the data column and the instruction column take an identical protocol onTMS, we find ourselves attempting to do testing with the Instruction Registerbetween TDI and TDO rather than the Boundary Register! Of course, this isdisastrous to the integrity of our test.

A debugging tip: if an extra TCK pulse does occur at one of the update states,you can recognize the problem by examining the bits that are shifted out. Instead ofthe expected target register bits, you will see the Instruction Register capture pattern(because CAPTURE-IR was traversed) shift out. This is another argument for havingfixed bits in the Instruction Register capture pattern since more fixed bits will makeit easier to recognize that the IR column is being traversed.

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Consider the example shown in Figure 5-3. Here a large IC generates signals on apair of 32-bit buses. In this IC’s normal usage, the two buses are never active at thesame time, as shown in Figure 5-4. However, the figure also shows how the twobuses could behave when the device is in EXTEST. In this case, both buses canproduce transitions at the same time. In the worst case, guaranteed to occur in theinterconnect test algorithm4 shown in section 3.1.2 on page 112, all 64 drivers willchange at the same time.5

Deliberately adding skew to the update clocking of the Boundary Register cells[Maun90] will help to control the magnitude of the switching current transients. Thisis shown in Figure 5-5. Be careful to note that the delays are not inserted in thesystem data path so they have no effect on system performance. These delays,perhaps only a few nanoseconds apiece, are used to deliberately skew driver

4The Standard specifically disallows designers from specifying some maximum number of

simultaneously switching drivers that is less than all drivers. Further, designers may notattempt to outlaw certain combinations of states driven by drivers.

In this case, all drivers are at “0” and then switch to “1”. These two PTVs are used toeliminate aliasing with power/ground shorts, which are quite common.

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transitions in time so that the required supply current demands do not change asquickly in time. There is one fine point to be considered as well; your distribution ofcontrol signals to driver enables (a high-speed system path) will not be delayed. Themore drivers you gang together on a common control cell, the more likely you couldenable or disable a large current flow. Be alert for this when considering how manydriver enables to control with a single control cell, and make sure the delay schemeshown in Figure 5-5 is not compromised by grouping your control cells next to eachother in the Boundary Register.

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174 Design for Boundary-Scan Test

It is thus very important to do a worst-case analysis6 of Ground-Bounceaccounting for the maximum number of drivers switching states. It will also beimportant to separate the power distribution of the TAP logic from the System logicand the output drivers. Doubtless there are other schemes that are possible forcontrolling supply current surges that will work as well.

DFT-3: Ensure that worst-case switching of all IC drivers will not causepower/ground transients that disrupt the operation of the TAP controller.

5.1.3 Instruction Capture PatternThe bit pattern captured in the Instruction Register upon passing CAPTURE-IR hasuseful diagnostic properties as we saw in Chapter 3 in the discussion of 1149.1Integrity testing. Most 1149.1 components have Instruction Registers with more thanthe minimum of two bits. If you are creating 1149.1 components, you can increasethe usefulness of the instruction capture pattern by:

DFT-4: Use higher-order bits of the Instruction Register capture patternto implement an informal ID code. The bits captured must be predictable“0”s and “1”s.

This rule is especially important if you have identical pinouts for the TAP pinson several different components. For example, the Texas Instruments ICs74BCT8373 and 74BCT8374 have identical pinouts and identical eight-bit capturepatterns. Thus, if one IC is misloaded in place of the other, we cannot discover themisload during Integrity testing, nor will we see a failure during EXTEST functions.The only way to test for this problem is to perform a functional test on the IC’ssystem logic7 capable of discerning the slight difference between the ICs.

Other components have been implemented that capture design-specific data inthe higher-order bits of the capture pattern that are not predictable. They must belisted as “x” bits (“don’t know” bits) in the INSTRUCTION_CAPTURE attribute ofBSDL. The capture of design-specific data is sometimes done to increase visibilityinto the TAP decode logic for fault simulation, where critical TAP decode signalsare placed in the capture pattern, making the pattern a function of the previouslyloaded instruction. This eases the problem of testing the decode circuitry at IC test,but does nothing to help differentiate similar components at board test.

The capture of indeterminate data can also lead to indeterminate behavior of a1149.1 circuitry. This can happen if you follow this trajectory through the TAP statediagram: CAPTURE-IR to EXIT1-IR to UPDATE-IR. This sequence will load thedesign-dependent bits into the Instruction Register and make them the next effectiveinstruction. To prevent this from being a random instruction, we have our next DFTrule.

This analysis should also take into account any exceptional currents that may exist if shortedpin drivers conflict with each other or are tied to a supply voltage.

This test can be implemented using the 1149.1 INTEST function that both of these ICssupport. The test in this case needs to differentiate a latch (‘8373) from a flip-flop (‘8374).

6

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DFT-5: If design-dependent bits are captured in the Instruction Register,then any combination of these bits should decode to the same operation.

Since unused bit patterns are required to default to BYPASS, it may be easiest toarrange that a capture pattern containing random bits also decode to BYPASS.

5.1.4 Damage Resistant DriversEngineers rarely study the issue of damage caused by driver conflicts when theycreate the basic structures that will become the building blocks of an IntegratedCircuit. The typical reaction of an IC designer when confronted with the question“How long can your drivers be shorted together before they suffer (some form of)damage?” is to exclaim that they cannot tolerate any conflicts. Twenty-five years ofIn-Circuit and Functional testing, where driver conflicts are not only tolerated, butoften deliberately induced, say otherwise. The studies done into the question, such as[Robi83], [Bush84], and [Hewl85] were primarily conducted by ATE designers andusers, not semiconductor device physicists.

The studies (of that era) show that some amount of abuse8 can be tolerated. Thetwo primary damage mechanisms are thermal heating of transistor junctions andthermal heating that causes full or partial opening of bond wires. In either case, themechanisms take time to occur. In some worst-case situations, damage is projectedto occur in several hundred microseconds. In most, it is prudent not to exceeddurations of several milliseconds. Yet, functional test with manual probe backtracinghas been used for years. Such testing will power the board (and the conflicts on it)for many minutes. This tells us that while driver damage is definitely a concern, ourcomponents (at least for now) are relatively robust.

What about the IC components of the future? What affects will smaller transistorfeature sizes have? Will a move to reduced power voltages (such as 3.3 volts) makedamage less probable? What about non-silicon ICs (for example, GalliumArsenide)?

Since 1149.1 testing must be done with power applied to a board, we have threechoices. First, we learn the duration limits of our drivers to tolerate conflicts and staywithin those bounds. Unfortunately, those bounds may be too constraining. Second,we construct abuse-tolerant drivers. This requires that we understand the physics ofdamage. Third, when a fault is isolated that has resulted in driver abuse, we replacethe affected components even if they appear to have survived. This could be a veryexpensive option9 . Of course, we could continue with a fourth policy often followedin the past: ignore the problem.

Note that the abuse studied was In-Circuit overdrive abuse, which is likely to be morestressful than driver conflicts, since an In-Circuit tester driver is usually far stronger than anIC driver. Do note that drivers shorted to Power or Ground suffer worst-case current flows anddurations.9

However, in certain applications where the cost of failure due to reduced component lifetimeis extreme, this may be quite acceptable. Consider electronic health care products or airbornenavigation systems as examples.

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176 Design for Boundary-Scan Test

I prefer a mix of choices 1 and 2. Study (theoretically and empirically) thetolerance of driver structures to conflicts, then improve on them as needed. Thisneeds to be done in a context of some minimum required test duration. This durationcan be roughly calculated as follows; add the times to apply power, run theBoundary-Scan test10, and remove power. Then double that result. Times in the rangeof several seconds are quite possible.

DFT-6: Specify a tolerance period that drivers can withstand shorts toeach other or to Power/Ground voltages.

5.1.5 Output PinsUpon examining the example Boundary Register output cell designs shown in theStandard [IEEE99], denoted as cells BC_1, BC_2, or BC_6 in BSDL, one noticesthey have a common characteristic. While EXTEST is in effect, they all capture datafrom one of two places, the System Logic11, or the Update (UPD) flip-flop.However, upon reading the rules in the Standard concerning output cell construction,you see no rules that require one of these sources. This suggests an improved designas shown in Figure 5-6.

The self-monitoring output cell design (Figure 5-6) is capable of reading, duringEXTEST, the output state of the driver at CAPTURE-DR. This value should be thesame as what we previously loaded into the Update (UPD) flip-flop, unless there is aboard-level condition where this is no longer true. There are several such conditions:first, the driver is intentionally Wire-ANDed or Wired-ORed (2-state case) withsome other driver(s) on the board. Second, the driver is not enabled (3-state case);and third, a defect in the driver or a board-level fault such as a short prevents the

Be extremely wary to include the time to set up the tester, any reload times, and the time itrequires to determine if a conflict exists. The time cannot be reliably predicted by simplymultiplying the TCK cycle time by the number of TCK cycles in the longest expected test.11 The actual BSDL CELL_INFO triple for this is, for example, (Output2, EXTEST, PI). “PI”is the parallel input that, for an output cell, must be the System Logic.

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driver from operating correctly. It is this third case that makes the self-monitoringoutput cell very useful.

The BSDL description of this cell would look as follows12:

constant SMOC:CELL_INFO := Define a Self-MonitoringOutput Cell (SMOC)

((OUTPUT2, EXTEST, PO), (OUTPUT3, EXTEST, PO),(OUTPUT2, INTEST, PI), (OUTPUT3, INTEST, PI),(OUTPUT2, SAMPLE, PI), (OUTPUT3, SAMPLE, PI),(OUTPUT2, RUNBIST, PI), (OUTPUT3, RUNBIST, PI));

Here, the “PO” field (Parallel Output) implies the driver pad state because thecontext is that of an output cell.

Given that this cell design is used in an IC with the attendant BSDL description,software can look for pad value discrepancies that indicate a shorted node or faultydriver. This information will be especially valuable when a driver is connected to anode that does not terminate at a Boundary-Scan receiver; a self-monitoring driver cellwill still be able to participate in Interconnect shorts testing. In another situation, if aself-monitoring driver is connected to a node that has a single Boundary Registerreceiver, the self-monitoring property can be used by the diagnostic routines todifferentiate between a node shorted to Power/Ground and an open solder connection.This leads us to our next DFT rule.

DFT-7: Use self-monitoring output cells in the Boundary Register toimprove Boundary-Scan diagnosis of shorts and opens.

5.1.6 Bidirectional PinsBidirectional pins can be serviced several ways. For example, you may implement a 2-cell bidirectional structure with independent drive and receive cells. You mayimplement a single-cell bidirectional structure. The advantage of the single-cellstructure is that it reduces the number of stages (cell count) in your Boundary Register,which reduces shift time, saves storage space and increases test application rates. Theadvantage of the 2-cell design, before Supplement A [IEEE93] is that it could monitorthe state of the bidirectional pin (by virtue of the receive cell) regardless of whether thedriver was enabled. Supplement A to 1149.1 shows a much-improved bidirectionaldata cell design13 that is able to monitor its driver result at all times. This leads to thediagnostic advantages already outlined for self-monitoring output cells (see section5.1.5 above) combined with reduced Boundary Register length.

This description would be part of a user-defined VHDL package for cell design descriptionas described in section 2.6 on page 84. The package would be referenced in the entitydescription for the IC in a “use” statement. The “SMOC” name would appear in the cell fieldof the attribute BOUNDARY_REGISTER (see section 2.3.13 on page 72).

The bidirectional cell that has the lack of pin monitoring is known in BSDL as cell BC_6(see section 2.6.3 on page 91). The improved bidirectional cell design is known as BC_7. Youare urged to design out the BC_6 design if you currently use them, and use BC_7.

----

12

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DFT-8: For bidirectional pins, utilize a single-cell bidirectional design witha self-monitoring capability (such as cell BC_7).

The BSDL description of such a cell looks as follows:

constant BC_7:CELL_INFO := Self-MonitoringBidirectional Cell

((BIDIR_IN, EXTEST, PI), (BIDIR_OUT, EXTEST, PO),(BIDIR_IN, INTEST, PI), (BIDIR_OUT, INTEST, PO),(BIDIR_IN, SAMPLE, PI), (BIDIR_OUT, SAMPLE, PI),(BIDIR_IN, RUNBIST, UPD), (BIDIR_OUT, RUNBIST, UPD));

The triple “(BIDIR_IN, EXTEST, PI),” for example, shows (see section 2.6.2 onpage 89) that while behaving as an input during EXTEST, the cell captures data fromthe pad input buffer (PI = parallel input).

The triple “(BIDIR_OUT, EXTEST, PO),” for example, shows that while behavingas an output during EXTEST, the cell captures data from the pad driver (PO = paralleloutput). In the original issue of the Standard ([IEEE90], figure 10-22), the cell BC_6captured System Logic data (PI).

5.1.7 Post-Lobotomy BehaviorAs first discussed in Chapter 1, a complicated IC with Boundary-Scan, when yieldingpin-permission to an instruction such as EXTEST, will lose contact with its companionICs. These companion ICs as well may undergo Boundary-Scan testing. If they do not,then they see the Boundary-Scan test data going by. In either case, this is a totaldisruption of the environment these ICs constitute. If all IC TAPs are then placed backinto the TEST-LOGIC-RESET state the 1149.1 logic reverts to non-invasive mode, butthe system cannot resume normal operation as if nothing has happened. This situationwas called the Lobotomy problem. It is the responsibility of the IC designer to ensurethat the IC, when returning to a non-invasive instruction from a pin-permissioninstruction, does not suffer from internal conflicts or board-level conflicts. This gives:

DFT-9: When the 1149.1 logic executes a pin-permission instruction, thesystem logic should be forced into a state that prevents internal conflicts.

DFT-10: When the 1149.1 logic returns to non-invasive mode, the systemlogic should stay in a state that will not conflict with board level signals.

Thus, the system logic is placed in a quiescent state by pin-permission modeinstructions. It stays quiescent until the 1149.1 logic returns to non-invasive mode anda general reset sequence brings the system logic back into coordinated operation. Notethat RUNBIST may not operate correctly in a lobotomized component, requiring areset of the system logic.

5.1.8 IDCODEsThe 1149.1 IDCODE instruction is a very useful resource. It allows a component toidentify itself and give its revision level as well. This can detect problems where

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similar components or different revisions of the same component are misloaded on aboard14.

However, the IDCODE instruction does require resources: an instruction withdecode logic, a 32-bit IDCODE register, and so on. If this is not practical, it is stillpossible to do an informal ID code. We have already seen how higher-order bits of theinstruction capture pattern can be utilized for this (see section 5.1.3). Anotheropportunity exists to differentiate an IC informally, by having certain cells in theBoundary Register capture constant “0”s and “1”s.

During EXTEST, Boundary Register output and control cells are free to captureanything. We have already discussed having the output cells capture their driver padstates (in section 5.1.5), which is very useful. This leaves us with the driver enablecontrol cells that we can design to perform a similar trick during EXTEST. They canload a constant “0” or “1” into their Capture (CAP) flip-flop15. Because mostBoundary-Scan components will have three-state and/or bidirectional outputs, thereshould be one or several control cells. Each of these can provide a bit of our informalID code. The BSDL for two cells, one capturing a “0” and the other capturing a “1”,follows:constant Ctrl_0:CELL_INFO := Control cell that captures 0

for EXTEST((CONTROL, EXTEST, ZERO) , (CONTROLR, EXTEST, ZERO) ,(CONTROL, INTEST, PI), (CONTROLR, INTEST, PI),(CONTROL, SAMPLE, PI), (CONTROLR, SAMPLE, PI),(CONTROL, RUNBIST, PI), (CONTROLR, RUNBIST, PI));

constant Ctrl_1:CELL_INFO := Control cell that captures 1for EXTEST

((CONTROL, EXTEST, ONE), (CONTROLR, EXTEST, ONE),(CONTROL, INTEST, PI), (CONTROLR, INTEST, PI),(CONTROL, SAMPLE, PI), (CONTROLR, SAMPLE, PI),(CONTROL, RUNBIST, PI), (CONTROLR, RUNBIST, PI));

These BSDL descriptions allow software to predict the locations of “0”s and “l”sin the Boundary Register that form an informal ID code.

DFT-11: Use formal or informal ID codes to differentiate similarcomponents or revisions of components.

5.1.9 User-Defined InstructionsWe have already seen a case (see section 4.5) where a special 1149.1 user-definedinstruction called “LEAK” was used to perform a gross test for the existence of a nodaltermination resistor. “LEAK” is but one example of how some forethought can be used

14In the case where different revisions or manufacturing codes are permissible, you can edit

the BSDL attribute INSTRUCTION_CAPTURE to describe multiple device identification bitstrings. (See section 2.3.10 on page 69.)

If the control cell has been merged with an input cell, then it must capture the input pin statein that case.

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during IC design to solve sticky, board-level test problems. In practice, you might befrustrated by not having the privilege of controlling the design of all the ICs on yourboard. Thus, you must look for clever ways to test the problem nodes of your boardusing just those ICs you do have control over.

DFT-12: Consider board-level testing problems that will require user-defined instructions for their solutions, before final implementation of the1149.1 logic.

Notice that this rule is a guideline for management of the design process. Boardtestability needs to be an input to the IC design process.

5.1.10 Creation and Verification of BSDLIdeally, a BSDL description should be created as a natural part of the IC designprocess. Indeed, the same software that lays out the IC design can create it.Unfortunately, in some cases, a test engineer may create the BSDL description, withlittle input from the original IC designer. There is much opportunity for error.

Another source of error in BSDL comes from its distribution. How do you knowthat the BSDL you have received for a component is up-to-date with the componentitself? Has the device been revised since you last obtained its BSDL description?Another, really exasperating problem comes from the channel itself; BSDL is oftendistributed over the Internet via electronic mail. Errors injected by this channel aredisturbingly frequent. For example, many electronic mail handlers automaticallysplit longer lines (called “line-wrap”) into smaller lines. This can create syntaxerrors, usually when the tail ends of comments end up on new lines. Sometimesmailers will simply truncate lines, losing data. Sometimes HTML16 formatting infor-mation is included in the BSDL, causing syntax errors.17 Measures as simple aslimiting line lengths in your BSDL to less than 70 characters can often avoid someof these problems.

Errors in a BSDL description will have a devastating effect on the ability of aBoundary-Scan test to run properly. Furthermore, it will be difficult at a board orsystem level to determine where the problem is. It is highly recommended that aBSDL verification test be run on each 1149.1 component on an IC tester18 before thecomponent is used in a board or system test. A BSDL verification test should containat a minimum, the following elements:

verification of IDCODE, if it exists and what instruction is jammed into theInstruction Register at the TEST-LOGIC-RESET state.

verification of the Instruction Register capture pattern.

verification that the Bypass register captures a 0 at CAPTURE-DR.

Hyper-Text Markup Language (HTML) is a language used to construct pages accessed onthe World Wide Web. I have seen BSDL files containing HTML commands like “</Bigger>”.

One IC vendor I know, after receiving complaints about poor BSDL quality from their Website, downloaded some of their own files and verified them. Quite a few contained errors.18

If an IC has yet to be fabricated, then consider simulating the test patterns against a modelof the IC. This is a good strategy if the model and the resulting IC are good matches.

16

17

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verification of the USERCODE, if it exists.

passage through every state and transition in the TAP state diagram.

verification that each instruction opcode targets a register between TDI andTDO of the specified length and that bits are read into TDI on the rising edgeof TCK while TDO bits appear on the falling edge.19

verification of the mapping20 between each input pin (or bidirectional pinacting as an input) and the Boundary Register cells.

verification of the mapping between each output pin (or bidirectional pinacting as an output) and the Boundary Register cells.

verification of the mapping between each driver enable and the BoundaryRegister cells.

Verification that SAMPLE can capture values presented at all inputs andbidirectional pins acting as inputs.21

verification that the Capture (CAP) flip-flops of each cell perform as theirBSDL CELL_INFO constants specify.

Verification that HIGHZ, if it exists, targets the BYPASS register and disablesall IC outputs upon passing the UPDATE-DR state.

Verification that CLAMP, if it exists, targets the BYPASS register and controlsall IC outputs upon passing the UPDATE-DR state with a pattern set up byPRELOAD.

verification of the RUNBIST function if it exists. (Note, this will requirecomponents that both pass and fail RUNBIST.)

BSDL verification tests can be very long, with the mapping verification being an

complexity problem. They look for discrepancies between a BSDL description andthe actual silicon of the IC. A manufacturing test for the 1149.1 portion of the IC, oncethe 1149.1 implementation and BSDL are proven, may be much shorter. For example,a BSDL verification test for the Intel 80486DX, based on the elements above, containsapproximately 36,000 TCK cycles, excluding the test for RUNBIST. A manufacturingtest for the 1149.1 logic in the same IC, takes on the order of 7,000 TCK cycles, againexcluding RUNBIST. (The RUNBIST function takes over 1,250,000 TCK and CLKcycles.)

DFT-13: Verify that a BSDL description matches the siliconimplementation of 1149.1 on every component.

Creating a test solely from the BSDL and executing it against the IC on a tester (orsimulator) should perform this verification. For off-the-shelf merchant ICs, the vendorshould be able to provide BSDL and proof of its verification. Unfortunately, too many

19Private instructions may be omitted from this test.

The verification of mapping is done to ensure the cell information in the BSDL attributeBOUNDARY_REGISTER is correct, which can be done using the EXTEST instruction.

SAMPLE also captures System Logic values for outputs and control cells, but these cannotbe verified since the data captured cannot be determined from BSDL alone.

20

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182 Design for Boundary-Scan Test

IC vendors still do not have a good process for creating, certifying and maintainingBSDL. You should not assume that a vendor’s BSDL is verified and up-to-date. Askquestions like these:

How is your BSDL created?

How is it verified for syntactic and semantic correctness?

Is it verified against the actual silicon (or a simulation thereof)?

How is it distributed?

How do you notify users about updates or changes that may be needed?

5.2 BOARD-LEVEL DFT

Once we have ICs with robust implementations of 1149.1 and verified BSDL, we cantackle the problems presented by boards. Some of these problems will be easier tohandle since the ICs should have been designed (see DFT-12) with thought towardstheir solution.

5.2.1 Chain ConfigurationsMost of the discussion about Boundary-Scan chains has been in the context of simplechains. Other configurations are possible as well. These can offer some marginaladvantages, but it is important to look at the difficulties these will present to softwareas well.

A simple chain has a single TCK and TMS signal broadcast to all members of thechain. The TDO signal of the first component is cascaded into the TDI of the nextcomponent, and so on, until all components have been threaded together linearly.Throughout this discussion, the optional TRST* pins that may exist on some of thecomponents are assumed to be driven by a common signal, but we will generallyignore TRST*.

A board may have one or more simple chains. If two exist, for example, and wewant to perform interconnect testing on signals that connect the Boundary Registers ofthe two chains, we must operate the two chains in parallel. There is no reason to havethe two chains in different TAP states while testing progresses, so you could drive thetwo TCKs and TMSs from one tester driver each. This realization then suggests havingcommon TCK and TMS signals on the board, as shown in Figure 5-7. This is the firstexample of a Siamese chain.

The Siamese chain of Figure 5-7 effectively takes a single TDI/TDO data path andturns it into a multiple-bit bus. An obvious reason to do this would be to increase theamount of data shifted through the combined chains per TCK cycle. Note however,that the individual TDI/TDO paths will very likely have different lengths becausedifferent numbers of components exist in each chain, and each component may containregisters of differing lengths. This will require care to manage and if the disparity inlengths is great, it will reduce the throughput advantage.

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The second form of Siamese chain (shown in Figure 5-8) has a common TCKsignal. Then, two otherwise linear chains with independent TMS signals share theboard-level TDI and TDO signals, which can be done since TDO is disabled wheneverthe TAP is not in a shift state. It requires us to operate the chains separately, which canbe done by manipulating the separate TMS lines. This operation is a good bit morecomplex because whenever we want to shift data into one chain, we have to keep theother chain in a non-interfering state, such as PAUSE-IR or PAUSE-DR. While thisconfiguration will work in principle, it does not appear to be of much practical value; itsaves one TAP signal compared to the Siamese chain in Figure 5-7, but it does notsave any overall shift time and has a more complicated protocol.

Third, we have dynamically reconfigurable chains. These structures are essentiallya set of simple chains that have their TDI/TDO data paths linked together bymultiplexers or more complex switching networks

22. At least two commercial ICs exist

(the Texas Instruments 74ACT8997 and 74ACT8999) that will perform thesefunctions. While some software exists that can manage dynamic reconfiguration, amuch simpler test approach is to set a configuration, then freeze it for the duration ofthe test.

22The 1149.1 Working Group has not issued an opinion on the merits of dynamic

reconfiguration. This capability seems to be more properly the realm of system-level test busschemes, such as IEEE 1149.5.

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184 Design for Boundary-Scan Test

DFT-14: Before designing a board-level chain configuration, be sure thatthe software that will be used during testing will support it

Finally, we have field-programmable chains, where some number of the devices inthe chain are composed of field-programmable ICs. Since these devices could havetheir 1149.1 circuitry altered or even erased when they are programmed, they shouldbe considered volatile members of the chain. If these volatile members are distributedthroughout the length of the chain, then their programming could cut the chain intomany small segments which will reduce the value of the remaining 1149.1 devices.Therefore, it would probably be a good strategy to place all field-programmable ICstogether in the chain ordering, either at the beginning or end of the chain. This way, theremainder of the chain remains intact. You will need to provide access to the TDI andTDO signals of the non-volatile segment of chain.

DFT-15: If there are field-programmable components in a chain of 1149.1devices, group them together in the chain order and place the group ateither end of the chain.

23Smaller FPGAs may not contain a permanent 1149.1 facility because of cost considerations,

so the 1149.1 capability may be implemented by programming the devices to have one andlater overlaying that configuration with a mission configuration. The trend today is towardmuch larger devices containing permanent 1149.1 facilities.

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5.2.2 TCK/TMS DistributionIf an appreciable number of components in a simple chain on a board contain the1149.1 capability, then it may be necessary to buffer the TCK and TMS signals, asshown in Figure 5-9. This example shows a simple chain with two logically identicalnodes (TCK1 and TCK2) for TCK and (TMS1 and TMS2) for TMS24.

Now, a pair of simple buffers has been shown in Figure 5-9, but in many real cases,the distribution of the broadcast TCK/TMS signals is done using a more complexcomponent. This component might require conditioning (initialization or enabling) thatessentially interposes a complex function

25between the board-level TCK/TMS signals

and the simple chain. Automated software that attempts to identify the chain(s) on aboard for test generation may decide that the configuration of Figure 5-9 is really twoseparate simple chains.

26This is because it has no way of determining (without

intervention) that TCK1 and TCK2 are really buffered copies of TCK, and similarlyfor TMS. This leads us to another DFT consideration.

DFT-16: Utilize simple buffering (where possible) of the broadcastTCK/TMS signals. Document the enabling and initialization requirementsneeded to preserve the 1149.1 protocol through TCK/TMS distribution.

24The buffering IC cannot itself be an 1149.1 design in the same chain (unless it is maintained

in BYPASS) since its Boundary Register, during EXTEST, would prevent the TCK/TMSsignals from being distributed.25

See also the discussion of Boundary-Scan Masters in section 5.2.7.26 To manage the two separate chains, nodal access to the TDI/TDO node at the junction ofthe two chains will be necessary. Then it will not be possible to run the two chainssimultaneously, since driving TDI of the second chain overwrites TDO from the first.

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If a board-level oscillator is used to drive TCK, be wary of clock distributionbuffers. Such components are usually needed in sensitive clocked systems to producehigh-power low-skew copies of the main clock frequency. Such components maycontain a buffer tree as shown in Figure 5-10. The inversion in the signal path is usedto help maintain a 50% duty cycle. If the IC is simply used to buffer an oscillatoroutput for a system clock, there is no phase relationship to maintain between CLK andCLK1-4. However, if such a buffer is used for distributing TCK, then the inversion isindeed a critical matter since it may confuse software.

DFT-17: Do not allow logical inversion in the TCK or TMS pathways.

5.2.3 Mixed Logic FamiliesMixed logic families at the board level may require voltage level translation of thelogic signals between ICs. This will also be true of the TAP signals if some of the ICsof a chain are implemented in different families, such as pictured in Figure 5-11.

Here we see a simple chain with some ICs implemented in TTL logic and some inECL. We must translate the parallel signals between families as the upper converter in

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Figure 5-11 does. The question is, does this IC contain 1149.1 as well? If so, whatfamily does each of its TAP Pins belong to? If the upper converter is not an 1149.1 IC,how can software keep track of the data flowing from IC 3 to IC 4 through theconverter during interconnect testing?

The lower converter of Figure 5-11 translates the TAP signals for the ECL portionof the chain. The lower converter must not be an 1149.1 component since that wouldprevent the transmission of TAP signals to the ECL portion of the system when thelower converter was in EXTEST.

Figure 5-12 shows the same simple chain as in Figure 5-11, but with a Boundary-Scan implementation for the conversion of the parallel signals. Notice that theTDI/TDO data path is converted by the scanned converter IC as part of its TAP portfunction. The conversion of TCK and TMS must be done with a conventional non-scanned component.

27This introduces the same problems we saw (in section 5.2.2 on

page 185) with respect to buffered TCK/TMS distribution.

DFT-18: When mixed logic families are used on a board, use scanned levelconverters for the parallel signals and a non-scanned level conversion

27for

TCK/TMS distribution.

5.2.4 Board Level ConflictsOne very important point to continually emphasize is that Boundary-Scan drivenactivity on a board is radically different from normal activity. This means that nodalconstraints that are part of a board’s design will not be honored during Boundary-Scan

27 The device could be an 1149.1 device, but it must reside in another independent chain that

is not being tested at the same time; the converter would be in BYPASS.

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188 Design for Boundary-Scan Test

testing.28

This can lead to conflicts if we are testing a mixture of scan and non-scannedcomponents, such as we see in Figure 5-13.

Figure 5-13 shows a Boundary-Scan component with signals that propagate to twochip selects on RAMs not containing 1149.1. During normal operation, the two chipselects are always complementary (barring a fault). During testing, they may both haveenabling values that cause the RAM outputs to conflict. The duration and intensity ofthese conflicts are of concern since they could damage

29the RAMs. If such conflicts

are not tolerable, it may be necessary to remove these nodes from our list of nodes thatwill be tested by Boundary-Scan. The nodes could be constrained to safe states ratherthan be tested.

30We could use RAMs containing 1149.1, or redesign the circuit such

that the RAMs have an alternate method of being disabled not subject to Boundary-Scan signaling.

DFT-19: Check conventional portions of board circuitry that may beaffected by Boundary-Scan test data for damaging conflicts that may beinduced. Design disable methods into these portions that will make theminsensitive to this testing activity.

5.2.5 Control of Critical NodesDuring Boundary-Scan testing, it is important to be able to control certain nodes on aboard that may not have direct Boundary-Scan control. Typically, this occurs at theborder between scanned and non-scanned portions of the circuitry. Figure 5-14shows two such situations.

28Remember that these constraints will not be honored by failures either.

29Damage could occur in the driver circuitry, or if several drivers are in conflict on one IC,

their summed currents could damage power distribution wiring.30

If Boundary-Scan receivers are present on constrained nodes, then the constraints can becaptured and verified, yielding a partial test of the nodes.

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First, Figure 5-14 shows a Boundary-Scan node A between ICs U3 and U4 that canbe interconnect tested if conventional IC U1 can be turned off so as not to interfere. Tosupport this, we need a tester resource on the enable of IC U1 that can apply a disablevalue to U1 while Boundary-Scan tests are running.

DFT-20: Provide for the ability of a tester to disable conventional ICswhose outputs would otherwise conflict with nodes involved in Boundary-Scan tests.

Second, Figure 5-14 shows a digital node C that has weak drive capability becauseof the analog filtering it has undergone. A short between nodes B and C will not bevisible because C is too weak to interfere with the driver of B. Again, a tester resourcecan be used to supply a strong value to node C, such that a B-to-C short will cause B tofail.

DFT-21: Provide for the ability of a tester to create strong drive values onweak nodes.

Third, if any Boundary-Scan ICs possess compliance enable pins then the nodesattached to these pins need to be conditioned to the enabling state before and duringany Boundary-Scan testing. Note that some ICs may also have a Test Reset (TRST*)pin. It will be very important to locate all nodes attached to Test Reset pins so that theycan be held high during testing. (In this respect, they can be thought of as complianceenables too!) This leads to:

DFT-22: Make sure you locate and condition all Test Reset (TRST*)pinsand all compliance enable pins before executing any Boundary-Scan tests.

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190 Design for Boundary-Scan Test

In these cases we are arguing for additional tester resources, and access to criticalboard nodes. If this access is unavailable, we must find another means to accomplishour goals, or accept degraded test coverage.

5.2.6 Power DistributionOn boards with a hybrid analog/digital design, it may be very dangerous to runBoundary-Scan tests on the digital portion of the circuitry since the apparently randomdata may be having an undesirable impact on the analog circuitry. For example, theanalog circuitry may have considerable power handling capability and be subject tosevere damage (to devices, the board itself, the tester, and even the equipmentoperator) if improperly excited. Such risk could be alleviated if critical analog powersupplies are separated from the digital power supplies. Separation could allow thepowering of only the digital portion while Boundary-Scan tests are running.

DFT-23: Design analog and digital subsystems such that the analog powercan be shut off while Boundary-Scan testing is being done.

The non-powered analog nodes will now have no drive capability and couldtherefore not be tested for shorts to digital nodes. See section 5.2.5 for a discussion ofthis problem. If 1149.4 (see Chapter 7) is in place in mixed-signal ICs, then that maychange the nature of this consideration since 1149.4 can be used to disable key analogsignals.

5.2.7 Boundary-Scan MastersAt least two examples exist in the commercial IC market of ICs called Boundary-Scanmasters

31. These ICs form an interface between a microprocessor and the 1149.1 TAP

Port. They execute the useful function of performing a parallel-to-serial conversiondirectly in hardware from a “common” microprocessor interface as depicted in Figure5-15. They also contain some hardware support for testing functions.

31 They are the Texas Instruments 74ACT8990 and the AT&T 479AA.

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From a board-test point of view, Boundary-Scan masters have a completelydifferent effect. They convert a standard testability port into a non-standard parallelprotocol. Since general 1149.1 software is not likely to directly support this parallelprotocol,

32the Boundary-Scan master must be circumvented by an ATE system to gain

access, either logical or physical, to the 1149.1 port. Logical access could be obtainedby having a “transparent” mode where the master could pass through TAP signals fromthe parallel side. Physical access would consist of standard In-Circuit overdrive of the1149.1 side of the component; perhaps made easier by having the master disable itsTAP drivers. Nail access would have to be anticipated.

DFT-24: If a Boundary-Scan master is used in a board design, provide fortest equipment access and control of the 1149.1 side of the master’sinterface.

Other ICs called Scan-Path Linkers (like the Texas Instruments 74ACT8997) andScan-Port Selectors (the Texas Instruments 74ACT8999) may be mounted on a board.These ICs are not parallel-to-serial protocol converters. Rather, they take a set of1149.1-driven commands and create a pathway through an attached set of simplechains.

32The vendors of Boundary-Scan masters usually supply supporting software for their

components to facilitate prototyping and the development of microprocessor software orfirmware. Such software is usually not of general use outside of this environment.

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Once the path is set up as shown in Figure 5-16, it will behave as one expects an1149.1 chain to act, with the following exceptions: the start of a linked ormultiplexed simple chain is prepended with a single, additional shift-register stageand a selected register

33is appended to the end of the simple chain. The prepended

and appended stages are contained within the same Linker/Selector IC. If severalsimple chains are linked together, additional shift register stages are sprinkledthrough the concatenated result. This forms a rather exotic chain structure, whichmay prove troublesome for general 1149.1 software to comprehend. The foregoingDFT rule, DFT-24, applies here as well.

5.2.8 Post-Lobotomy Board BehaviorAs we saw in the case of Integrated Circuits, we must concern ourselves with thebehavior of a board after a Pin-Permission operation of any component(s) in a

33The selected register is a function of the instruction loaded into the TAP Instruction

Register of the Linker/Selector IC.

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Boundary-Scan chain has lobotomized the board. Assuming the 1149.1 componentstake care of themselves—for example, by staying in a quiescent state after a Boundary-Scan operation completes—we still must take care that a board will do the same. Thisis because a board might have non-scan components that are not privy to the facts of1149.1 life.

DFT-25: Ensure that a board, after any 1149.1 operation completes, willhave safe states on all components and nodes.

On complex boards where this analysis may be difficult, one could add a specialfeature to the board reset logic, a general hold-reset feature that can be triggered at thestart

34of 1149.1 testing. This hold-reset function would clamp the reset line(s) of the

circuit into the reset state such that all non-scan components would be held quiescent.After Boundary-Scan testing, a board-level general reset would clear out the hold-resetfunction and bring the board back to orderly operation. Perhaps the simplest way to dothis might be to cycle the power on the board.

It is important to be aware of any such precautions that may be built into a board,for it will influence the operation of subsequent tests. For example, if 1149.1 testingleaves the board lobotomized, then a general reset of some type will be necessary ifany later, conventional digital testing is to be done. If any board-level Built-In Self-Tests are to be executed with the aid of Boundary-Scan, these should not be disabledby the hold-reset function. Of course, the more ICs of a board that implement 1149.1,the less of a board-level problem you should have.

5.3 SYSTEM-LEVEL DFT

A system, for the purpose of this discussion, is any collection of boards, modules, orboxes that operate together. (This is a much higher level than the “System Logic”defined in the 1149.1 Standard as the mission logic of one IC.) If the 1149.1 Standardhas been used in their design, then it is desirable to reuse this investment for systemtesting.

It is quite easy to imagine that a system, of boards for example, each containing asimple Boundary-Scan chain, are simply concatenated together into one (very) longsimple chain. There is nothing wrong with this approach, in principle.

The practical problem of the length of the chain exists. However, the BYPASSfunction helps us eliminate useless shift positions. If the number of nodes that passbetween boards is limited, or if these nodes do not connect a significant percentage ofall system ICs, then one can imagine system-level interconnection tests that do notrequire terribly long shift paths. Again, many ICs would be in BYPASS mode.

Another problem is more significant; many systems may be populated with amixture of boards, and missing boards (empty slots) may be permissible. This leavesus with chains whose construction is a function of the mix of boards in the system, orchains that are broken by empty slots. We call this the multidrop problem.

34Of course, the access to nodes needed for this capability should have been provided as noted

in rule DFT-20.

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194 Design for Boundary-Scan Test

5.3.1 The MultiDrop ProblemFigure 5-17 shows an example of a system implemented with a single simple chain.Any missing board in the system causes a break in the TDI/TDO chain. This could behealed with a jumper board that connects TDI to TDO, but jumper boards are notpopular and are typically removed from a system as a design goal.

It is also a problem, from a software standpoint, to determine how, from a mix ofboards and empty slots, a system is populated. The concept of Blind Interrogation hasbeen proposed to identify which chips exist in a chain of components. BlindInterrogation is done by starting in TEST-LOGIC-RESET and proceeding directly tothe data column to shift out either the IDCODE registers or BYPASS registers of thechained components. If IDCODEs exist in enough ICs, then, in principle, you candeduce from the ID codes which chains (and thus which boards) exist in a system.Jumper boards will not be identified unless they contain an 1149.1 IC with the purposeof identifying the boards as jumpers.

If a mix of boards is allowed, then tests for such a system must be constructed afterthe mix is identified. Identification can take some time and require a potent computingresource rather than a simple test sequencer. In conflict with this in many cases is asystem test requirement for fast testing with a simple, inexpensive (perhaps portable)piece of controlling equipment. The sum of these objections has made system-level,1149.1-based testing problematic. See also the IEEE 1149.5 standard briefly discussedin section 5.3.2.

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DFT-26: Restrict 1149.1 implementations for system tests to simple systemarchitectures not containing a multidrop scheme.

5.3.2 Coordination with Other StandardsIEEE Standard 1149.5 [IEEE93b], the “Standard Module Test and Maintenance(MTM) Bus Protocol”, offers a way to add hierarchy to a system containing 1149.1-based boards. It allows—via an 1149.5 bus—the addressing of individual boards,sets of boards or all boards for an operation. Addressing of boards allows us amechanism for dealing with the multidrop problem. This entails having a 1149.5controlling IC on each board, as well as one other such IC in the test andmaintenance unit of the system. One such component is the “master” and all others(up to 250 or so) are “slaves.” Mastership can be passed to a slave. Once on a board,the 1149.5 protocol can be used to control an 1149.1 chain.

The possibility exists that other approaches to managing multiple 1149.1 chainswill become industry standards. We have already seen two ICs with this potential, the74ACT8997 and 74ACT8999 Linker and Selector ICs. The work by Whetsel[Whet92] shows how 1149.1 could be extended with the concept of an “AddressableShadow Port” device that uses a “shadow protocol” to link 1149.1 boards together in abackplane structure. This device is available as the 74ABT8996. The hurdle any suchICs must overcome to become de-facto standards is to gain widespread softwaresupport.

Much work has been published on ways to create a testing hierarchy (for example,see [Avra87], [Breu88] and [Derv88]). The work reported by Dervisoglu35 [Derv88]gives a case study of a real implementation successfully carried out for a workstationproduct.

It is interesting to note that the hierarchy problem is also occurring in themicrocosm of core-based ICs, or appropriately, Systems on a Chip. Here the problemis that several IC designs are integrated together onto a single silicon substrate. Whatdo you do if some of these designs also contain 1149.1? The effect of this has beenstudied in [Jarw94]. (On reflection you will note that this is just like the problem withMCMs that contain several 1149.1 compliant die.) The resulting IC is not itselfcompliant to the 1149.1 Standard, but can be thought of as a collection of 1149.1entities, each with a BSDL description. Jarwala [Jarw94] also made some othersuggestions; it is too early yet to see where the industry is going with this situation.

It is difficult to give solid design-for-test rules for scan-based systems other than tosay that if a standard should emerge for this, use it!

5.4 SUMMARY

Boundary-Scan offers great potential to solve emerging test problems that havestaggered yesterday’s testing technology. Many companies are well into 1149.1

35 The scan-based architecture reported by Dervisoglu predates the 1149.1 Standard and is

significantly different in the details.

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implementations and have progressed well up the learning curve. A statement from onetest engineer summed up his experience;

“I really like Boundary-Scan. Now I can work on improving test coveragerather than just getting a test to work at all.”

We have seen a growing percentage of ICs that contain Boundary-Scan,particularly among the larger ICs. Formerly troublesome FPGA/CPLD ICs are nowstandardizing on 1149.1. Automatic insertion of 1149.1 by synthesis tools is becominga reality as well as the automated production of BSDL. But all is not rosy. The singlemost detrimental problem still remains compliance to the Standard with accurateBSDL descriptions. This problem will be solved, but it seems we must cure theoffenses with economic pressure. You are wise to question the compliance efforts ofthe vendors you patronize and to take your business elsewhere when their sincerity isshown to questionable. IEEE 1149.1 has become a vital contributor to the progress ofthe electronics industry. As such, all parties need to treat it with respect.

One other warning must be given to manufacturers. If you have a manufacturingprocess that is capable of fairly good yields before testing, then 1149.1 is a goodtechnology to pursue. If your manufacturing process is of low or erratic yield, thenBoundary-Scan may be disappointing. You could spend a lot of time chasing chainintegrity problems rather than in fruitful testing. Keep this in mind when venturing intonew technologies such as Multi-Chip Module (MCM) technology.

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CHAPTER 6

Analog Measurement Basics

The preceding chapters of this book have confined the discussion to digital circuitsand test subjects. Most electronic engineers are experts in digital technology butmany will admit that their familiarity falls off quickly when the discussion turns toanalog topics, particularly analog testing. Before getting into IEEE 1149.4 AnalogBoundary-Scan, it will be important to lay a foundation for basic analogmeasurements used today in In-Circuit testers. While 1149.4 does have significantdifferences over classical In-Circuit test, there are a lot of similarities. Knowingwhere we came from will also help motivate where we are now going.

Nearly every board ever produced has analog components on it, even those called“digital”. This amounts to perhaps hundreds of analog components per “average”board. Over the last 25 years, it would be no exaggeration to claim that one billion

of these boards have been tested with In-Circuit techniques. So how have theseseveral hundred billion components been tested? It serves as excellent background totake a look at how In-Circuit testers do this.

6.1 ANALOG IN-CIRCUIT TESTING

How does a typical In-Circuit tester test analog components mounted on a board?First, assume we have a bed-of-nails fixture such as we saw in Figure 1-2 on page 6.

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This fixture gives us nodal access to every terminal of each analog device. Butbefore we jump into the discussion of testing these components, let’s first agree onwhat it is we are testing for.

6.1.1 Analog FailuresIn-Circuit test is a “divide-and-conquer” technology (when we have access). Thisprovides its strength in testing individual components rather than entire networks.When you test individual components, you verify the construction of a network ofarbitrary complexity. If a network is properly assembled from a set of components,each tested and verified to be the correct device and in working order, they shouldwork together as the designer of the network intended. If they do not, it could be dueto a reliance on unspecified parasitic relationships among some of the components.Commonly called “parasitics”, they can be modeled as additional components in anetwork, typically with small values. While the values may be small, they could besignificant to the operation of the network.

For example as in Figure 6-1, a filter’s performance may depend on parasiticcapacitance between a “real” capacitor C and the windings of a nearby inductorL. If an engineering change causes the network to be laid out a little differently, theparasitic component may be changed causing the circuit performance to change. Themanufacturing team (and the designer) may puzzle over this change for a while,looking for a cause.

It is not the primary role of In-Circuit test to test the overall functionality ofnetworks, but rather to prove their proper construction and to verify all the physical(i.e., non-parasitic) components are correct and operational. Parasitic relationshipsthat a network may depend upon for proper performance are tantamount tocomponents missing from a netlist description of the network. Since these devicesare not specified, the programming process for the In-Circuit test will be unable toaccount for their effects.

If unspecified parasitic relationships are important to the operation of a network,one may question the quality of the design of this network. In essence, to effectivelymanufacture the device, some new “tests” (often called “Performance Tests”) maybe needed to ensure the network performs as the designer intended.

For example, consider a capacitor that has one terminal connected to theoutermost surface of the plate structure. The parasitic capacitance between thissurface and another component nearby may be necessary for network performance.However, if the capacitor is reversed so that the opposite terminal is connected

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instead, the network may no longer perform correctly. Thus, an additional test isneeded that verifies the orientation of this ceramic capacitor (assuming we know ofthis requirement). Such a test may require a new process step such as visualinspection of the capacitor, which may significantly increase total test costs. Butmore costly may have been the process that discovered the need for this new test, orthe “bone pile” of functionally faulty boards that grew before this problem wasidentified. Then there is the problem that the vendor of the capacitor may changehow it is labeled (which serves as the visual clue to its construction) or a similar butdifferently constructed capacitor may be used from an alternate source.

In-Circuit test is able to measure the value of analog components1

such asresistors, inductors and capacitors. These devices have nominal values specified forthe design, and a tolerance on this value. For example, a resistor may have a nominalvalue of 4.7 Kohms, ± 5%. Thus if we measure the resistor we expect it to have avalue of 4.7 Kohms ± 235 ohms. In a sample of these resistors, we might expect tosee a truncated bell curve for the distribution of values as seen in Figure 6-2.

What if we measure this resistor and see a value that is high or low by 240 ohms?Is this a failure? The answer is clouded by the fact that the measurement processitself may inject errors (see section 6.1.3). It also happens that the circuit designitself could tolerate a 10% deviation, but the designer only has 5% resistors availableto save on inventory costs. In this case, testing for a 5% deviation could be failingperfectly functional boards. To avoid rejecting good boards, test engineers will add aguardband to the (true) tolerance on the device value. This might be an extra 1%, orit could be surprisingly large, for example, tripling the tolerance.

In summary, analog In-Circuit testing of a circuit can be used to prove theconstruction of a set of specified analog components. This may not be enough toensure the operation of the circuit when parasitic impedances are present. However,it is also true that In-Circuit test has practical limits on the range of component

1Real components, not parasitics.

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values that may be tested. As we see in section 6.1.3, combinations of components incertain interconnection topologies may be difficult to test.

6.1.2 Measuring an ImpedanceTo measure the value of an impedance R, we make use of Ohm’s law in one of thetwo configurations shown in Figure 6-3. Figure 6-3A shows an ideal current sourceforcing a known current through the impedance while a perfect voltmeter measuresthe voltage across the impedance. The value of R is computed by dividing themeasured voltage by the known current:

R = V/i

Of course, the world is neither ideal nor perfect, so in reality we would have totake some care that errors are not introduced. For example, the voltmeter provides analternate pathway around the device being measured so we may find some of thestimulus current taking that pathway rather than going through the device. However,since the input impedance of a voltmeter is typically ohms, the amount ofcurrent being sidetracked is likely to be insignificant.

Next, we should take a moment to think about the current source. An ideal sourcewill force a specified current, developing whatever voltage is required. However, ifthe device is a low-power device, it could conceivably be damaged by the powerdissipation (V*i) such a current and voltage would necessitate. Higher voltagescould also damage diode junctions by causing voltage breakdown.

2 This presents us

with a problem; in order to keep the voltages in safe operating limits, we need toknow an expected value (approximately) for the device being measured. But if it istruly an unknown value, then we need a compliance limit on the current source. Acompliance limit is an upper bound on the voltage the source will develop and hencea bound on the both the voltage and the energy it will supply.

Whenever we use the setup in Figure 6-3A, it is assumed that the current sourceis not in compliance (not limited). If the device to be measured is a true unknown,the first selected current setting may produce a compliance limit signal and adifferent (lower) current should be tried. This process should eventually converge

3

on a current setting that stays within the compliance limit and yet develops ameasurable voltage across the resistor. However, if the current source is set too low,then the voltage across the resistor will be small, perhaps sacrificing some voltmeteraccuracy as a result. Thus we look for a current setting that is high enough to utilizeour voltmeter accuracy, but not too high to damage the device under test. (Othercriteria will appear shortly.)

2As we will see later in this section, we also have to be careful of other devices surrounding

the device we are testing.3

There is the case where the impedance is infinite because of an open circuit. In this case theprocess of finding a current setting will converge on zero.

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Another stimulus/measurement configuration is shown in Figure 6-3B. Here weuse a voltage source to provide a known voltage across the resistor and a currentmeter to measure the resulting current. Note the ideal current meter has zero seriesimpedance, so there is no voltage drop across it. (This means the right side of theresistor is at zero volts.) The ideal voltage source will develop the desired voltagewith whatever current is required by the circuit. As before, this could result in adamaged resistor if the energy delivered is too great. Therefore we need a currentcompliance limit (an upper bound) on the voltage source current capability. Again, ifthe value of R is unknown, we may need to search for a voltage setting on thevoltage source that does not cause a compliance condition,

4 yet gives us good current

measurement accuracy from the current meter.

So we have seen it is not necessarily straightforward to measure the impedanceof a simple freestanding resistor. If its value is unknown, or if there is an anomalypresent such as a short or open circuit, this leads to special considerations. However,freestanding components will be the exception and not the rule when testing boards.The situation shown in Figure 6-4A will be quite common. Here, a resistor isconnected between board ground and an integrated circuit output. How do we goabout testing the value of the resistor?

In Figure 6-4A we have access to both sides of the resistor we want to test, butthere are other components connected to the resistor as well. Inside the silicon devicewe see two transistors connected to the resistor. What effect will these have on oursimple measurement process?

To answer this, we first remember that In-Circuit analog component testing isdone with no power applied to the board. This means that the transistors inside theIC are not turned on. Further, if we limit the voltages used during testing to valuesthat will not turn on a diode,

5 perhaps less than 0.2 volts, then the silicon junctions

within the IC will never conduct current. This makes the IC “disappear” from ourproblem. However, reality intrudes again when we consider the physical apparatusneeded to measure the resistor. This is the In-Circuit tester itself.

4It is possible that the search would converge on zero volts in the case where the value of R

was zero, such as in the case of a short circuit.5 Not shown in this figure are Electrostatic Discharge (ESD) protection diodes often found

between IC pins and the power rails. These diodes can provide additional conduction paths ifthey turn on.

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Figure 6-4B shows the elements of a typical In-Circuit tester. Nails from the bed-of-nails fixture touch the nodes A and G on either side of resistor R. Within thefixture, wire-wrap wires connect the nails to the fixed array of tester channels that, inthis diagram, are multiplexed to a measurement bus. The multiplexing is done withmechanical reed relays that have several desirable qualities. First, reed relays havevery low “on” resistance, perhaps only ohms. Second, when reed relays areopen, they have very high “off” resistance, perhaps ohms. They come close tobeing “perfect” switches.

6

From the measurement buses (Figure 6-4B) another layer of reed relaymultiplexing brings us to the stimulus and measurement resources of the In-Circuittester. This is where we find the various forcing functions for voltage and current aswell as measurement devices for current and voltage. Figure 6-4B shows how theappropriate relays are closed to set up the same voltage forcing measurement we sawin Figure 6-3B. The voltage source is set to less than 0.2 volts to prevent the siliconjunctions in U1 from turning on. (Not shown in Figure 6-4B are any controlfunctions for the relays and instrumentation.) With all of this complexity in themeasurement path it should not be surprising that we have new sources of error. This

6The switching time from open to closed is less than perfect, in the neighborhood of 500

microseconds. They often take longer to open.

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will be covered in section 6.1.3, but next we examine complications inmeasurements due to parallel device topologies such as seen in Figure 6-5.

The parallel impedance problem is personified by the delta configuration ofimpedances shown in Figure 6-5A. Here we have three resistors and three In-Circuitnails, plus a connected IC. We can make the IC “disappear” by doing unpoweredtests with low stimulus voltages as before. However, to measure the value of R when

and are present, we need something more to deal with the parallel pathproblem. This is shown in Figure 6-5B.

In Figure 6-5B we see the familiar voltage forcing configuration on nodes B andA seen originally in Figure 6-3B, but with a new addition; a third node C is

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grounded using a third nail. This is called guarding. Guarding uses low impedancepaths through reed relays to insert grounded points into the circuit.

7 If you examine

Figure 6-5B closely, you will see that current from the voltage source splits at nodeB and proceeds both to nodes A and C. However, because node C is grounded andbecause node A is also grounded (the current meter has zero impedance), the voltageacross is zero. No current can flow to node A from node C. This means thecurrent meter measures only current through R. Thus we know the voltage across R(the voltage source value) and the current through it which yields its impedance.Figure 6-5C shows a typical ATE setup for measuring the resistor in a deltaconfiguration.

6.1.3 Errors and CorrectionsAs noted earlier, an ATE system is constructed from imperfect components. Thisleads to unavoidable additional impedances in the measurement pathways. For theexample of measuring a simple resistance given in Figure 6-4B, we find impedancesinserted along measurement pathways contributed by relays, nail contacts

8and

wiring. This is shown in Figure 6-6A.

These error impedances will often be small compared to the value of the resistorR, so if they sum into its value, the error may be small compared to the toleranceassociated with R itself. However, for smaller values of R, the errors could cause ourtest to fail for some boards when the value of R is close to (but still within) itstolerance limit.

Errors can be controlled by taking additional measurements; one example isshown in Figure 6-6B. Note that our voltage source is sending a significant currentaround a loop containing the error impedances. If we make a new voltmetermeasurement

9as close as we can get to resistor R, we can get closer to the true

voltage appearing across it. This figure shows we can eliminate the errors in the ATEsystem itself, but we still are seeing the fixture errors.

Figure 6-6C shows a more realistic situation. Here we have a single voltmetermultiplexed to either path. We can get the same measurement result as in Figure6-6B, but with two voltmeter readings taken in succession on the paths. Someadditional error due to this slightly more complicated process will result, and theprocess takes more time.

Figure 6-6D shows how we could eliminate almost all error, by using a Kelvinmeasurement. The voltmeter pathway is virtually independent of the path that carriescurrent. The cost, however, is significant because we now need two additional In-

7An example at the macroscopic level of Heisenberg’s Uncertainty Principle. To measure the

value of a component with this technique, we must significantly perturb the circuit under test.8 Relays will have sub-ohm resistances typically, but nail contacts may have resistances of 2

ohms and higher depending on the cleanliness of the nail and board surfaces. Nail contactresistance may increase with time but may be restored by periodic cleaning of nails.9

Remember that because of its very high input impedance, the insertion of the voltmeter willnot seriously affect the current flow of the circuit.

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Circuit nails. This configuration is rarely used unless we need a very precisemeasurement of a very small resistance R.

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Similarly, the delta configuration of Figure 6-5 will also suffer from voltageerrors caused by currents traveling through relays, wires and nails. These are shownin Figure 6-7A. Of particular concern is the error impedance in the guard pathwhich raises the voltage at node C above ground. This allows an error current toflow into and subsequently through and on to the current meter. Ultimately, ahigher current reading yields a calculation of R that is lower than the actual value.Consider just if is 1 ohm and R is 10 Kohms while and are both 10ohms, the calculated value of R would be about 100 ohms. This is because thecurrent circumventing R is nearly 100 times as great as that traveling through R.

This error can be corrected with additional voltage measurements taken fromnodes A, B and C with three additional In-Circuit nails as shown in Figure 6-7B.This is known as a 6-wire measurement and is expensive in nails and the timerequired to do the additional measurements. Thus 6-wire measurements are donerarely, when the ratio of component values in the original delta configuration arelarge and there is need for good accuracy. See [Croo79] for more discussion of In-Circuit measurement errors and corrections.

6.1.4 Measurement HardwareCurrent meters are not usually supplied in ATE systems, but rather an operationalamplifier is used as shown in Figure 6-8, where it is monitoring the same delta

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configuration we have used in other examples. In this configuration (often called aMeasuring Operational Amplifier or MOA) the op-amp combined with the feedbackresistor will endeavor to keep node A at zero volts.

The value of R is calculated by this formula:

So far we have confined the discussion to the measurement of static DC values.To measure reactive components such as capacitors and inductors, we will need touse AC voltages and currents. One way to do this is with a tool called a dual slopeintegrator, which can be used for both DC and AC measurements. A dual slopeintegrator is constructed from a basic integrator such as shown in Figure 6-9.

This integrator is made from an operational amplifier with a high qualitycapacitor

10C in the feedback path. The voltage will be a highly linear ramp

given a DC input V, which is the solution to this equation:

which is both a function of V and the time constant of the system defined by theproduct of R and C.

10This capacitor doesn’t need to be accurate (only stable over the period of measurement) but

it should have excellent characteristics with respect to dielectric absorption.

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208 Analog Measurement Basics

A dual slope integrator is similar, as shown in Figure 6-10. It integrates theunknown voltage for a period of time T which produces a positive voltageThen a known negative reference voltage is switched in place of whichcauses a downward ramp on The time X to reach zero volts is recorded. Thedual slope integrator is a physical solution to the equation:

This equation, when solved for the unknown yields:

which is the product of the known with the ratio of integration times X and T.(Notice the time constant RC has dropped out of the equation.) Time is somethingwe can measure very precisely in digitally controlled systems. This allows us toconstruct (in this case) a very accurate DC voltmeter that is largely independent ofthe values of the component used.

As always, we do have to be wary of the non-ideal. Since we may not know theapproximate value of before we measure it, we will have to guess at a value ofintegration time T. If we guess too short, then very little ramp on will occur withan accuracy penalty. If our guess is too long, our integrator may ramp beyondthe linear region

11of the integrator’s operation. We could have a selection of values

for R and C, selected with switches, to help us stay within the operating range. Wecould also scale with a ranging amplifier before integrating it. We still need toknow if our first guess at their selection was appropriate. Therefore the controller forthis apparatus will have to make one (or more) guesses, selecting values of T, rangeamplification, and/or R and C, until a suitable ramp

12has been found.

11This region will be within the power supply rail voltages of the operational amplifier.

12To limit effects from environmental noise, we may restrict the values of T to those that will

mask out common sources such as low frequency power line noise.

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The dual slope integrator can also be used to measure AC voltages. We willconfine this discussion to sinusoidal waveforms of a known frequency, because in anATE system the stimulus portion of the hardware is under our control. Further, wewill also know the phase relationship of our AC sources so that we can lock thephase relation of the measurement to them. This will allow us to measure the realand imaginary components of a sinusoidal voltage waveform necessary formeasuring values of reactive components such as inductors and capacitors. For ACmeasurements, the dual slope integrator shown in Figure 6-11 may be used.

If we were to measure a simple sinusoid with our DC integrator, every completecycle of waveform would integrate to zero, leaving us no information. If we integratethe first ½ cycle and then invert the voltage and measure the second ½ cycle, we willget a non-zero result. Looking at Figure 6-11A, this is the purpose of switches D andE.

13 The sources are connected by either of switches A and B. The sinusoidal source

has a known phase so we can chose the portions of the sinusoid we are integrating

13 Actually, switches D and E are conceptual. The AC voltages are digitally constructed by the

system sources. The system has complete on-the-fly control of the frequency and phase.

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210 Analog Measurement Basics

and whether the unity-gain inverter complements that portion. The DC referencevoltage source serves the same function we saw in Figure 6-10 for DCmeasurements.

To measure an unknown AC signal first we integrate several full cycles of(with its known phase) taking care to invert the negative portions to positive until

time T has elapsed. Figure 6-11B shows this waveform. Then the negative DCsource is switched into the integrator replacing causing a downward ramp.The integrated waveforms yielding are shown in Figure 6-11C. As with the DCcase, the process continues until returns to zero while we measure time intervalX. As before, the measured value of is computed as:

which again is a function only of the magnitude of the reference voltage and the twotime intervals we can measure accurately.

By controlling when we open and close switches A and B, we can select a phaseoffset for a measurement. If we offset a measurement by 90° we can measure theimaginary

14component of a waveform. An offset of 0° gives us the real component.

These two measurements allow us to compute values of reactive devices innetworks. See the example in Figure 6-12.

In Figure 6-12 we want to measure a capacitor C. The In-Circuit nails give accessto both sides of C. An AC voltage source (we control its frequency and phase) isconnected to the capacitor through a known source impedance and the other sideof the capacitor is grounded. After we close the nail relays, we can successivelymeasure the voltage on both sides of the source resistor Note however that wewill offset the measurement by 90° with respect to the stimulus voltage source sothat we measure the imaginary voltage as shown in Figure 6-13. We then computethe imaginary current through the known resistor. This plus the imaginary voltage

14 Imaginary signal detection is sometimes called a quadrature measurement.

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across the capacitor (the measurement at the top of allows us to calculate thevalue of C.

6.2 LIMITED ACCESS TESTING

In-Circuit nail access to every circuit node is progressively harder to achieve. It isnow apparent that we must think about “bed-of-nails” testing with a restricted set ofnails. A central contribution of both the 1149.1 and 1149.4 standards is that theyallow us to continue testing for manufacturing faults even as access becomescompromised. However, even with the aid of 1149.4, we may find that nail pointswithin an analog circuit that are not associated with IC pins may be inaccessible.This problem begs the question, “can we test analog networks with less than 100%access?”

The answer is, of course, yes. We have always been able to fall back ontofunctional test techniques. However, this is unsatisfactory if you want to retaindiagnostic capabilities of a test. It is often nearly impossible to predict from a failinganalog functional test the precise nature of the defect in the circuit. The desire tocontinue enjoying In-Circuit test advantages such as automated programdevelopment and high-quality diagnoses has led to new research in In-Circuit test[Huan97, McDe98a, McDe98b]. Today’s In-Circuit approach tests analog networkswith board power turned off. Tomorrow’s 1149.4-based testing will, of necessity,turn the power on. In either case, we will need updated approaches to analogmeasurements for testing purposes.

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212 Analog Measurement Basics

6.2.1 Node Voltage AnalysisThe work presented in [McDe98a, McDe98b] and [Huan97] shows us a new way toapproach In-Circuit testing when access is limited. This can be shown by way ofexample. Consider the simple circuit shown in Figure 6-14.

The ATE system can switch a current source and ground path to the network, asshown. Each node will develop a voltage; node A will see and so on. (Allvoltages are referenced to ground node C.) Each node voltage can be observedbecause the circuit has full access. We will not use any of these test nails forconventional guarding as discussed in section 6.1.2.

Now assume the circuit is made up of perfect resistors at their nominal values.Then the node voltages will be equal to a mathematical prediction. These voltagesare labeled and so on. When the resistors vary as real resistors will, thenthere will be some differences. This is expressed in Table 6-1. It is important to notethat even varying only one resistor from nominal will change all three voltages.

This example was carefully chosen to have three voltage differences so that theycan be plotted in a three-dimensional coordinate system

15such as shown in Figure

6-15A.

Figure 6-15B shows a plot of many points forming a “cloud” of data. This data isthe result of performing thousands of Monte Carlo simulations of the 4-resistornetwork in Figure 6-14. Each simulation starts with a randomly selected set ofvariations for the four resistors and then computes the resulting node voltages. These

15The techniques shown here work for higher numbers of nodes and components. However it

is difficult to visualize higher-order dimensions.

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are compared to the nominal solution and the differences plotted as a single point inthe three-dimensional space. This technique can be used to plot all “good” circuitbehaviors by only using resistor variations that are within the tolerances allowed inthe design. Faulty behaviors can be plotted by varying one or more resistor valuesbeyond the specified tolerance. As you would expect, the cloud occupied by goodbehaviors is much smaller than the cloud where any variations are allowed. The nextsection shows how we can perform tests using node voltages.

6.2.2 Testing With Node VoltagesNode voltages can be used to test a circuit. One simple idea is to measure all thenode voltages for a circuit and check the point so defined for inclusion within thegood cloud. This gives us a Pass/Fail result, but says nothing about which resistor(s)may be out of specification if the circuit fails. This is because all combinations ofpassing and failing devices are encoded in the cloud of points. What happens if weput an upper bound on the number of resistors that are out of tolerance at any time?This is shown in the three graphs presented in Figure 6-16.

Figure 6-16A is constructed by plotting the differences in node voltages whenresistors R1, R2 and R4 are within tolerance limits, but R3 is outside its limits.Similarly, Figure 6-16B is a plot where only R2 is outside its tolerance limits. Figure6-16C shows a plot for R2 and R3 together. (For clarity we omit plots for R1 andR4.) Figure 6-16C shows us that observed changes in node voltages due to failure of

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214 Analog Measurement Basics

either R3 or R4 will have a “signature” that can be used to distinguish the two.Knowing this, we can test copies of this simple network and diagnose out-of-tolerance

16 components distinctly.

It is possible that there may be significant (or even total) overlap of the clouds ofpoints belonging to different failures. When this happens, you will see a failure ofthe circuit, but will only be able to say that “one or more of the following devices”

16Using AC voltages, we can also determine if a different type of component, for example, a

capacitor, has been misloaded in place of a resistor. With extreme miniaturization, manycomponents look the same and do not have enough space on them for labels.

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failed. This is called an ambiguity class. The next section describes how we can usenode voltage analysis for testing in a limited access environment.

6.2.3 Limited Access Node Voltage TestingSo far the discussion has assumed complete nodal access. Now we look at thesituation where some node voltages are not known. See the same example circuit inFigure 6-17 where we now have lost access to node B.

Removing access to a node deprives us of information in one dimension of ournode voltage space. In our example, this has the effect of projecting an image of ourthree-dimensional object onto a two-dimensional plane, as shown in Figure 6-18.

In this case, losing access to node B means we cannot measure for thisnode. Figure 6-19A shows the shadows of the clouds for R2 and R3 projected ontothe plane of voltages for and Because the shadows have distinct areas, wecan still perform a diagnosis if one of these devices should fail.

Figure 6-19B shows a different projection. Here, we have lost access to adifferent node (node A rather than node B) and thus we cannot measure Theshadows of the R2 and R3 clouds onto the plane of voltages for and are

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216 Analog Measurement Basics

completely overlapped. Thus, while we can see if the circuit is failing, the ambiguityclass contains two components so we cannot differentiate which of the two failed.

By analyzing projections of higher-dimensional objects in lower-dimensions wecan find out what nodal access is most valuable for diagnosis and also what access isnot needed. Experiments on real circuits are reported in [McDe98a]. For example,one circuit made from 14 resistors, 2 inductors and 20 capacitors with a total of 21nodes was analyzed. It was testable even though only 9 nodes were accessible. Thelargest ambiguity class contained three components. The CPU time (on a modestCPU) to construct a test for this 20-dimensional

17 problem was about two minutes.

(This is a one-time investment.) Nodal access was chosen by the manufacturer of thecircuit and was not optimal.

17One node is always used as the reference node for voltage measurements.

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6.3 THE MIXED-SIGNAL TEST ENVIRONMENT

There are many examples of mixed-signal boards and these have been in existencefor a very long time, yet until recently the IEEE itself did not recognize the term“mixed-signal.” The 1149.4 Working Group had to assure the IEEE that such a termexisted. The term mixed-signal refers to single devices, boards or systems wheresome information carrying signals exist that are digital in nature while others existthat are analog.

18

Digital signals utilize just two states (usually voltage states) to convey binarydigits of information. For example, a stream of “0” and “1” states on a Test ModeSelect (TMS) signal is used to navigate the 1149.1 TAP state diagram. Analogsignals convey information via continuous states

19of voltage and current. For

example, the signal representing a singer’s voice, as converted to electrical form by amicrophone, is a remarkably complex analog waveform. While this waveform can be“digitized” into a stream of bits, this process is always an approximation of theoriginal signal. Digital and analog signals may also be turned off such that noinformation is represented.

Analog designers quickly point out that all circuits are analog. It’s just that so-called digital circuits have chosen to convey information with two discrete statesseparated by a fairly wide unused voltage space that provides a noise margin. As

18Indeed, it is possible to have a single signal with both natures. Consider for example the

encoding of digital information within an analog television signal, used for closed-captioning.19

“Continuous” means non-quantized, to differentiate analog signals from multiple-valuedlogic signals that are still essentially digital in nature.

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operating frequencies increase and noise margins decrease, most digital designerstend to agree with the analog designers’ viewpoint! This is because yesterday’sdigital designs could ignore parametric factors such as impedance matching, signalreflections and ringing. Tomorrow’s designs must be concerned with these “analog”problems. Often the solution to these problems involves adding extra discrete analogdevices to the “digital” circuitry.

Figure 6-20 depicts a mixed-signal board. It contains purely digital ICs marked“D”, purely analog ICs marked “A” and some ICs marked “M” that contain bothtypes of circuitry. Then there are swarms of discrete components such as resistors,capacitors, inductors, diodes, transistors, and so on. Such a board may be the signalprocessor for a video camera, for example. Because of that it is probably quite smallso it can be compressed into a hand-held unit, and you could expect the reverse sideof this board to look similar to the side shown. These types of boards are difficult totest because of test access problems and the complex nature of mixed-signal testing.This is the type of board that both 1149.1 and 1149.4 are well suited to address.

Indeed, the cover of this book illustrates the access problem by showing ajuxtaposition of In-Circuit nails with old and new devices against a backdrop of acommon coin, a US Lincoln penny. A key to this photograph is presented in Figure6-21. If you have a penny, it is instructive to examine it.

The lettering on this penny is done with 10 mil lines.20

Some circuit boards todayuse signal traces only 4 mils wide. Some vias coming into use are also only 4 mils indiameter, fitting within the width of a trace. The diameter of the circular portion of a“nine” in the date “1996” is approximately 35 mils, which is the generally acceptedlower limit on a test pad diameter needed for reliable probing. Clearly, it will not befeasible to use 4 mil vias for test pads in the future since they are nearly a decadesmaller yet.

Ball-Grid Array technology is a major driver for smaller printed circuit boardtrace widths and “micro” via diameters. A BGA requires a great number ofconnections in a small area, so getting the required signals into this dense area ischallenging. Smaller traces and vias makes this possible and become the enabler forboth Chip-Scale packaging and Chip-on-Board attachments. In the past, BGA ICshad to be surrounded by an unpopulated perimeter in order to find room to route allthe signals. This perimeter was a good place to locate test pads. However, withhigher routing densities, these perimeters will shrink, leaving little room for testpads. Making room will amount to trading off test pads for ICs and other devices.

Also shown atop the penny in Figure 6-21 are three types of test nails, thecommon 100 mil nail, and 75 and 50 mil probes as well. In particular, notice the 50mil probe points to a discrete device in an “0402” Surface Mount Technology (SMT)package. This designation means it is 40 by 20 mils on a side. To relate to this size,compare it to President Lincoln’s bow tie. Soon we will see “0102” devices, whichare one-fourth the size and will easily fit within the circular portion of the “nine”.Conventional In-Circuit nails and test pads are rapidly dwarfing the size of discrete

20Printed circuit dimensions are often specified in English (Imperial) units. A “mil” is 0.001

inch, or about 25 micrometers.

218 Analog Measurement Basics

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components. Thus asking board designers for thousands of test pads is becoming aserious design issue.

Why not just shrink the nails and pads? This is a surprisingly complexmechanical issue. Suffice it to say that the accumulated mechanical tolerances onboards and fixtures makes it very difficult to target thousands of probes reliably overlarge areas, and remember that each nail is a spring-loaded assembly that contacts

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220 Analog Measurement Basics

the board with a notable21

force. This is a source of mechanical deviation, stress andfailure. But if we could somehow shrink nails and pads to (say) 15 mils, this is stillabout 4 times the size of a modern signal trace and about the same size of today’ssmaller components. Designers have also questioned how fat test pads may impactsignal integrity on far narrower controlled impedance signal paths. Figure 6-22compares the relative sizes of some of the items discussed in this section.

One last note; today’s more advanced IC geometries are based on features.These are 100 times smaller than a single mil and are shrinking with time. Mechan-ical probing technology has essentially already reached its practical economic limits.

6.4 SUMMARY

This chapter has set the stage for discussing the resources provided for analog testingby IEEE 1149.4. It will certainly be the case that today’s In-Circuit test techniqueswill still be used in the future, even as nail access becomes increasingly limited.IEEE 1149.4 will be a powerful tool for providing measurement access to manyphysically inaccessible points in a network.

The newly defined node voltage technique will allow us to continue to enjoy testdevelopment automation and high-quality diagnostics. The dependence on guardingthat has been a mainstay of In-Circuit ATE will, of necessity, give way to the lessbrutish non-guarded approach. Of course, for the foreseeable future, every techniquewe know will continue to have value since it is not likely that boards with 100%IEEE 1149.1/1149.4 implementations will become very common.

21 Consider a board requiring 4000 nails, each with 0.5 pounds of spring force. That comes to

2000 pounds (nearly 1 metric ton) of spring force distributed across a board and fixture.

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CHAPTER 7

IEEE 1149.4 Analog Boundary-Scan

IEEE Standard 1149.4 [IEEE99]1 is titled “Mixed Signal Test Bus” but has become

known popularly as “Analog Boundary-Scan”. It is natural to ask, what is “AnalogBoundary-Scan”? The digital paradigm we have been using is confusing when wehear the word analog. Could it mean we somehow capture analog voltages andsomehow shift them out for viewing (as proposed in [Wagn88])? The answer is“no”. The simplest concept of the 1149.4 Standard is to imagine that we haveintegrated a portion of an ATE system’s analog measurement bus and multiplexingsystem into an IC, eliminating the need for bed-of-nails access to it. Since these testresources have been converted from discrete relays, wire wrap and nails into silicon,they will scale with silicon technology as it continues to shrink.

The 1149.1 Standard since its inception, has studiously avoided anyconsideration of analog pins. Essentially, they were completely ignored. In the early1990s, the P1149.4 Working Group was chartered to study the question of howanalog testing could be facilitated with a standardized approach. This group hadextensive debates on just what it was they were trying to standardize. This debate

Caution: The 1149.4 Standard draft is being completed as this book goes to press. The authorbelieves that the material presented here is substantially similar to that ultimately published bythe IEEE. However, you should obtain the latest IEEE document.

1

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222 IEEE 1149.4 Analog Boundary-Scan

crystallized during a panel session at the International Test Conference (ITC) in1992 when the debate was presented to an audience of potential users. The usersessentially said, “Forget about measuring complex parameters like gain anddistortion. Give us the ability to find shorts, opens, and misloaded components inmixed signal circuits.” They wanted to find manufacturing faults, not performfunctional tests. This change in emphasis was a turning point for P1149.4 and led toa proposed architecture in 1993 [Park93] that has since been refined into what wehave today.

The extremely difficult practical problems of high frequency testing usuallyneeded for functional testing can be avoided when considering manufacturing faults.So the first important characteristic to note about the IEEE 1149.4 Standard is that itis intended for use with lower2 frequencies; from DC to around 1 MHz. If this seemslike a serious limitation, consider the fact that virtually all the boards tested with In-Circuit test equipment over the last 25 years have had their analog components testedat 10 kHz or less.

The second thing to notice about 1149.4 is the obvious fact that to use it, theboard must have power applied to it. Just as is the case for 1149.1, this producessome nervousness when first realized. It means some number of shorts and manyanalog defects on the board that were detectable with the power off (when we havefull nodal access) will have to be detected after the power is turned on. A good boarddesign will also take into account that the test process may generate unusual signalson the board which could cause other powered elements to react. These reactionsmay need to be controlled or otherwise suppressed.

A third thing to notice about 1149.4 is that it augments a traditional ATE systemwith new resources on-chip for switching measurement currents and voltages.However, these resources are implemented in silicon rather than with traditional reedrelays and wires. The impedances inherent in these new resources are significantlyhigher3 than those achieved by relays and wire. This immediately rules out testingactivities based upon traditional guarding techniques seen in section 6.1.3 on page204. IEEE 1149.4 does not support brute-force insertion of virtual grounds. Thus,new metrologies [Park93, McDe98] are needed that use the available resources innew ways that respect these limitations.

7.1 1149.4 VOCABULARY AND BASICS

IEEE Standard 1149.4 has been carefully designed to be fully compatible with theexisting 1149.1 standard. In many ways it can be thought of as a pure superset of1149.1. For example, it uses an identical Test Access Port (TAP) controller fully

This isn’t to say you could not engineer an 1149.4 implementation to function at higherfrequencies. You can add special functions that have elevated performance, though this couldbe expensive.

There are two reasons for this; first, there is a fundamental limit to what could be achieved atany cost. Second, for 1149.4 to be economical it must consume a small area of an IC. Lowerimpedance switches consume larger areas. In 1998 technologies, you should expect to seeeconomical silicon switches with on-impedances from hundreds to thousands of ohms.

2

3

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described in Chapter 1 (see section 1.3.1 beginning on page 10). An 1149.4compliant IC can participate cooperatively with 1149.1 ICs to perform interconnecttesting such as described in Chapter 3, but adds the ability to address analog IC pinsas well.

As a superset standard, 1149.4 adds the ability to test analog devices andfunctions as well as simple interconnect. First, we need a model of what we aretesting.

7.1.1 The Target Fault SpectrumFigure 7-1 shows a mixed-signal circuit consisting of several mixed-signal ICs, somedigital ICs and a collection of discrete analog components. Just as is the case with1149.1, the 1149.4 standard has mandatory features that are used to test a target faultspectrum. Parts of this fault spectrum are interconnection defects such as shorts andopens, as shown in the figure. In addition, there are defects such as misloaded analogcomponents, for example, substituting a capacitor for a resistor. Also considered areanalog components with values that are wrong due to misloading or that are notwithin their tolerances.

It is important to note that shorts and opens will not discriminate analog fromdigital. A solder short may connect an analog pin to a digital pin. An open maydisconnect a discrete component from the circuit.

The 1149.4 standard also contains optional, codified features that may be used totest functions within a given 1149.4 conformant IC, again, just like 1149.1 does.(See section 7.3.5 and 7.3.6.) Further, 1149.4 allows designer-specified extensionsthat allow virtually unlimited test support for internal functions within an IC. See forexample [Lofs96a, Lofs96b].

7.1.2 Extended InterconnectThe 1149.1 standard viewed “interconnect” as simple wires that connect IC pins.However, even “pure” digital boards may have discrete analog components,typically series termination resistors, between IC pins rather than simple wiring. Thisleads to the necessity of viewing interconnect in two forms, “logical” and

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224 IEEE 1149.4 Analog Boundary-Scan

“physical”. Logical interconnect considers information flow, eliminating thephysical details such as series terminations. Some test software packages completelyignore the physical details of a circuit and work solely in the logical domain. Whensuch a model sees a failure in the circuit behavior, the resulting diagnosis must omitthe additional physical detail that could be very useful in locating the offendingdefect.

The 1149.4 standard defines interconnect into categories; simple interconnect(wires), and extended interconnect. It also notes the existence of differentialinterconnections, where a pair of wires is used to transmit a single signal. Figure 7-2shows some examples of these interconnect categories.

Extended interconnect is defined as “non-wire” interconnections between devicepins. For example, two IC pins may be connected through a discrete analogcomponent such as a resistor, inductor or capacitor. It could be true that there is alogical behavior of this extended interconnect that is equivalent to simple wiring asyou might expect for low-valued termination resistors. However, this may not betrue, so you will have to account for the effects of the discrete components whenconstructing interconnect tests. As noted in [Park97] special care may be neededwith reactive components that store energy. For example, the capacitor connectingtwo pins in Figure 7-2 may have an initial stored voltage that could be added intosubsequent test signals, causing confusion4 if not accounted for.

It seems reasonable to ask, “how much longer will there be a need for discreteanalog devices?” After all, are we not seeing increased integration giving us themeans to replace analog functions with digital equivalents? If this happened,extended interconnect could soon disappear. It turns out that there are a number of

4Voltage addition by the capacitor could also cause signals to go out of normal operating

range with possibly damaging effect.

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reasons why we still see discrete components, and many of these are not amenable toobsolescence by integration. Discrete components are used for:

Impedance matching; while completely customized ICs have on-chipimpedance matching resistances, merchant ICs will not likely have thesebecause it makes assumptions about their end use.

Power dissipation; if a discrete resistor will dissipate significant power, thismay be incompatible with integration.

Larger inductances and capacitances; reactive components may be expensiveto integrate. Note that small resistances can consume expensive amounts ofsilicon real estate.

Customization; some ICs have their range of functionality extended byconnecting external discrete reference devices.

Precision; it is difficult to integrate analog functions with high absoluteprecision.5

These and other factors tell us that we will still see discrete components in thefuture, but it is likely that more and more analog functionality will be integrated intomixed-signal ICs. This trend will likely mean that while we will see discretenetworks of analog devices, the size of these networks will diminish in time. Insteadof one large network, we may see several smaller, independent networks surroundinglarge mixed-signal ICs. If these ICs comply with 1149.4, we will have a powerfultool to use for testing these networks.

7.1.3 Digital PinsBoth IEEE 1149.1 and 1149.4 treat digital pins identically. However, the 1149.4standard has introduced a change in nomenclature; it describes all the BoundaryRegister test circuitry needed to support a single digital pin as a “Digital BoundaryModule” or DBM (see section 7.2.5).

A DBM may contain one or more Boundary Register cells as discussed at lengthin Chapter 1. Because the 1149.1 standard allows the shift order of BoundaryRegister cells to be assigned completely randomly, a DBM does not imply a shiftorder. Indeed the Boundary Register cells contained within several DBMs may beintermixed at random with respect to their shift positions.6 A DBM is a method fororganizing our thinking of the test resources for a single digital pin. The “BoundaryModule” concept is also used to describe those resources needed for analog pins, asdiscussed next.

Relative precision is possible. For example, resistances can be matched on a single IC, buttheir absolute values may vary significantly from IC to IC.

While random ordering is allowed, you will often find the Boundary Cells associated with apin are indeed adjacent in the Boundary Register. All figures in this chapter will show suchadjacency even though it is not required.

5

6

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226 IEEE 1149.4 Analog Boundary-Scan

7.1.4 Analog PinsIEEE 1149.4 directly addresses analog pins, rather than ignoring them as IEEE1149.1 has done for over eight years. Analog pins are assigned test resourcescontained in an “Analog Boundary Module”, or ABM, covered in section 7.2.4. Asjust discussed, an ABM will contain Boundary Register cells which are notconstrained in their ordering, either within the ABM itself, or in their ordering withany other Boundary Register cells in other ABMs or DBMs. An ABM also containsadditional resources needed to support analog test functions, and control logic forthese resources.

An ABM is capable of two major modes of test operation. It supports theemulation of 1149.1-style interconnection testing and it supports analog stimulus andmeasurement capabilities needed for analog tests. If two analog pins on 1149.4conformant ICs are connected with a simple wire, then the 1149.1 emulationcapability will be sufficient to test that wire for shorts and opens. If these same twopins had extended interconnect, say with a low-valued series resistance, then 1149.1emulation will still be sufficient to test the interconnect, plus the analog capabilitieswill allow testing of the resistor itself.

If there is extended interconnect between two pins that does not allow 1149.1-type interconnect tests, then the 1149.1 emulation will not be usable forinterconnection testing, but it may still be useful for shorts testing. Suppose there is asmall capacitor between these two pins such as we saw in Figure 7-2. For thepurposes of interconnect tests (which are essentially DC tests) the small capacitorlooks like an open circuit. Modeling the two pins as logically independent nodes, wecan test for shorts between them (or across the capacitor) with standard 1149.1interconnection tests. Later, an analog test may be used to measure the capacitor’svalue.

This brings us to another important point about how 1149.4 treats analog pins.The 1149.1 standard takes great pain to treat digital pins, for testing purposes, ashaving the same nature during test as they do when not being tested. Thus there are“input” DBMs, “output” DBMs and “bidirectional” DBMs. When first examininganalog pins, it seems this paradigm continues, but soon examples of analog pins arefound that do not have a clearly definable I/O nature.

For example, consider two analog pins intended for connection to a crystalfrequency reference. Are these pins inputs or outputs? The answer may not be clear.And as just seen with the example of a small capacitor, the two pins connected to thecrystal are not “connected” to each other in the traditional 1149.1 sense because theimpedance of the crystal is very high. If we give each of these analog pins the abilityto be driven and simultaneously sensed, then we can include them in 1149.1interconnection tests. Any shorts between them or other 1149.1 pins can then bedetected. So even though these pins are not recognizably inputs or outputs, bytreating them as bidirectional we can still perform useful 1149.1-style shorts tests.Thus an important feature of ABMs is that they do not mimic the system nature ofthe analog pins to which they are attached but rather treat every analog pin as if itwere bidirectional while supporting 1149.1-style tests.

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An ABM also provides new test capabilities in support of analog test that arecovered extensively in section 7.2.4. It could happen that these new resources are notneeded because (in a particular application) there are no analog components orparameters that one wished to test that are associated with that analog pin. However,it is also possible that you have pins that are clearly digital in nature connected todiscrete analog components. If you are implementing a custom IC where you knowthis will happen, then the 1149.4 standard allows you to replace a DBM with anABM. This allows superset test capability over simple 1149.1, giving a formerlydigital pin the ability to participate in 1149.1-style interconnect testing as well assupporting analog tests.

7.2 GENERAL ARCHITECTURE OF AN 1149.4 IC

Figure 7-3 shows a high level general architecture of an 1149.4 IC. This is a minimalimplementation as additional features are also allowed. This will be described later.

The important high level features of this implementation are:A test control block containing an 1149.1 TAP, instruction register and thefamiliar four (optionally five) TCK, TMS, TDI, TDO (and TRST*) signals.These elements are described completely by 1149.1 (see section 1.3 beginningon page 8).

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228 IEEE 1149.4 Analog Boundary-Scan

Digital I/O pins served by Digital Boundary Modules (DBMs) made up of1149.1 Boundary Register cells as described in section 1.3.4 starting on page21. DBMs are discussed in 7.2.5 on page 242.

An “Analog Test Access Port” (ATAP) where analog stimulus andmeasurements can be conducted to/from the IC. This port (in the minimalconfiguration) is made up of two I/O pins labeled AT1 and AT2. (See section7.2.2.) As an option, the ATAP can be extended by adding two additional pins,AT1N and AT2N. These are used to support differential stimulus andmeasurement. (See section 7.4.1 on page 250.)

A “Test Bus Interface Circuit” (TBIC) which controls connections of theATAP to an internal analog test bus (AB1 and AB2 in the minimalconfiguration) that is distributed to all ABMs. The control mechanism for theTBIC is composed of Boundary Register cells that are part7 of the overallBoundary Register. (See section 7.2.3 on page 231.) As an option, the internalanalog bus can be extended by adding two signals, AB1N and AB2N. Theseare used to support differential stimulus and measurement. (See section 7.4.1on page 250.) A separate option allows a TBIC to generate a partitionedinternal analog bus structure to improve internal loading and noisecharacteristics. (See section 7.4.3 on page 253.)

Analog IC pins connected to Analog Boundary Modules (ABMs). The ABMshave access to the internal analog test bus as well as (up to) three referencevoltages labeled and G. (See section 7.2.4 on page 236.)

The Boundary Register cells within a TBIC may also be intermixed randomly with otherBoundary Register cells. Drawings shown in this book will keep them together.

7

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Just as is the case with 1149.1, the 1149.4 standard connects selected registersbetween TDI and TDO as shown in Figure 7-4. Mandatory registers include theInstruction Register (described in section 1.3.2 on page 16), the Bypass Register(described in section 1.3.3 on page 20) and a Boundary Register. The BoundaryRegister is identical in nature to that described in 1149.1 (see section 1.3.4 on page21) but contains additional cells that are used to control the actions of ABMs and theTBIC.

7.2.1 Silicon “Switches”Throughout this chapter we will be using switching structures implemented insilicon to perform test functions. The TBIC and ABMs contain these switches inspecifically defined configurations.

In silicon processes such as CMOS, switches can be implemented rather easilywith Metal Oxide Semiconductor Field Effect Transistor (MOSFET) structures that(roughly) approximate the nature of mechanical relays. In other silicon processes,bipolar buffers (that can be turned off) may be used as a “switch”. Table 7-1 shows acomparison of several switch characteristics for various implementations.

A perfect switch is a component connected to two nodes. When closed, it joinsthe two nodes into one so there is no voltage difference between them and itconducts current in either direction. When open the two nodes are completelyindependent. The ideal switching time would be zero and the size would benegligible. As you can see from the table, a typical mechanical surface mount relayis near perfect except for switching time (slow!) and size (huge!). A CMOS switchhas an on-resistance four or more decades higher than a relay, but it is 4 milliontimes smaller and hundreds of times faster. It is bidirectional, but it should be notedthat it is somewhat nonlinear over larger signal swings. A bipolar switch can bemade from a buffer that can be turned off. As such it really doesn’t have an on-resistance.8 In an 1149.4 implementation implemented in a bipolar process, some(buffer) switches are required to conduct current (the AT1 and AB1 paths) andothers (the AT2 and AB2 paths) are required to convey voltage. (The 1149.4

8

A buffer-type switch does have an upper limit on the magnitude of the signal it can transmitwhich, if exceeded, will be distorted.

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230 IEEE 1149.4 Analog Boundary-Scan

standard does not require that switches be bidirectional.) Bipolar implementationswill require careful characterization since buffer offset may not be zero and gain maynot be unity for practical reasons.

Figure 7-5 shows symbols used in the following discussions to reflect the natureof switches. In some cases (see the two left-hand symbols) we show the switcheswithout a control mechanism to avoid clutter. Other times we will show the controlsignal, as on the two right-hand symbols. When a switch is open, it has infiniteimpedance for practical purposes. However, when closed, it has non-negligible seriesimpedance that is represented with the integral “resistor” shown. This symbolism isused to remind the reader that we do not have low impedance switching we onceenjoyed with relays.9

7.2.2 The Analog Test Access Port (ATAP)The 1149.4 standard contains the 1149.1 Test Access Port which is four (optionallyfive) digital signals. In addition to this it contains an Analog Test Access Port or“ATAP”. In a minimum configuration, this port consists of two analog signalslabeled AT1 and AT2 as originally shown in Figure 7-3. This port is used to connectexternal analog stimulus and measurement resources to an 1149.4 conformant IC.

Typically, the AT1 port is used for stimulus into the IC and the AT2 port is usedfor transmitting a response back to a measurement resource.10 It is intended that oneor more compatible ICs would have their ATAP signals connected in parallel, just asTCK and TMS are connected in parallel as shown in Figure 7-6 creating a simplechain. However, it is not required that two ICs that do have common TCK and TMSsignals also have common AT1 and AT2. For example, one IC may generate a greatdeal of internal noise and the other may be required to have a very quietenvironment, so it may be undesirable to connect the two ATAPs together whenoptimum system performance is required. In this case, the external test equipmentused for analog testing will need access to both of the ATAPs.

9To this day these switches are known as “crummy switches” within the 1149.4 Working

Group. (For non-English speakers, “crummy” means “low quality”.) The term constantlyreminds us that these switches have serious limitations.

If the switches used in an implementation are bidirectional (for example in a CMOStechnology) then the pins AT1 and AT2 may have their roles reversed.

10

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7.2.3 The Test Bus Interface Circuit (TBIC)The TBIC function first introduced in Figure 7-3 (on page 227) is used for threemajor purposes. First, it is used to connect or isolate the internal analogmeasurement buses AB1 and AB2 to/from AT1 and AT2. Second, it is used toperform 1149.1-type interconnect tests on the AT1 and AT2 pins. Third, it supportscharacterization11 processes that may be needed to improve the accuracy of analogmeasurements. A switching structure meeting the requirements of 1149.4 is shownin Figure 7-7.

Switches S1 through S4, along with the one-bit digitizers that generate signalsand are used to support 1149.1-style interconnect tests. (The destination

of these digitized signals is found in Figure 7-8.) The digitization is performed inrelation to some threshold voltage shown as Because this digitization need onlybe coarse rather than a precise operation, this threshold reference may not physicallyexist except as a physical property12 of the silicon implementation. The goal is tocheaply obtain a one-bit measure of the voltage on the pin. (Lofstrom [Lofs96a]shows how to avoid undesirable current surges when an input voltage is near thethreshold.) In general, with the additional goal that a short betweenAT1 and AT2 will not produce an intermediate voltage that approximates

In other literature (including 1149.4) you will see the word “calibrate” rather than“characterize” used in this context. The 1149.4 standard does not have any adjustable featuresthat can be calibrated, so instead we characterize the operational parameters of importantfeatures and record them for mathematical corrections performed later.

For example, a simple logic buffer has an inherent threshold somewhere between a “low”voltage value and a “high” value. There is no “comparison” done with an actual threshold.

11

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It is an interesting feature of 1149.4 that it can execute a conventional Boundary-Scan interconnect test on its ATAP pins. When testing a board full of 1149.1 and1149.4 devices, one first checks the integrity of the TAP signals using a (digital)integrity test. Then one tests the simple wiring for interconnect defects. At this pointin time, 1149.4 can also check each ATn port for shorts and opens as well. Later, theATn pins can be used for analog tests with the assurance that these tests will not bedefeated by connectivity defects in the ATAP infrastructure.

Switches S5 and S6 are used to connect/isolate the AT1/AT2 signals to/from theinternal AB1/AB2 signals. When these two switches are open, then the ABn signalsare isolated which could cause them to float and thus become susceptible to noise.Switches S9 and S10 are optional but serve the purpose of clamping the internalABn signals to a safe voltage to eliminate unwanted noise or parasitic effects whenthese signals are not in use for test purposes. Switch S9 is always in the oppositestate as S5; S10 is always in the opposite state as S6.

Closing S5 and S7 (or S6 and S8) allow us to characterize the AT1/AT2 pathwayvia a loopback test. This characterization will allow us to correct for the manyparasitic parameters13 that will exist on the board and the ATAP pins.

Figure 7-7 contains ten switches so there are 1024 possible combinations of theseswitches opened and closed. However, only ten switching patterns have been definedas meaningful by the 1149.4 Standard. These are enumerated as patterns P0 throughP9 in Table 7-2. A “1” (“0”) in the table indicates a closed (open) switch.

Testing software will often need to know the value of parasitic parameters in the AT1/AT2paths, both within the IC (mainly resistive impedance or gain factors, see section 7.4.4) and atthe board level (mainly capacitance). These parameters can then be modeled as additionaldevices in the overall network being tested.

13

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The (minimal) TBIC control structure14 for the switches in Figure 7-7 is shown inFigure 7-8. This control structure makes use of four Boundary Register cells15 andtwo control mode signals “Mode1” (M1) and “Mode2” (M2) from the TAPcontroller, which are a function of the instruction currently loaded in the instructionregister. The four Boundary Register cells are named16 “Calibrate” (Ca), “Control”(Co), “Data1” (D1) and “Data2” (D2).

Note that the capture stages of D1 and D2 capture the and signalsgenerated within the switching structure shown in Figure 7-7. (The capture stages ofcells Ca and Co are uncommitted.17) Cells Co, D1 and D2 form a pair of self-monitoring output cells with a shared control cell that can be used for 1149.1-styleinterconnect tests of the AT1/2 pins.

See section 7.4.3 for the control needed for more elaborate TBIC structures that handlepartitioned internal analog buses.

The order of these cells is arbitrary and they may be intermixed with other cell in theBoundary Register.

Boundary Register cells in 1149.1 were implicitly named “control”, “data”, and so on. The1149.4 standard has chosen to explicitly name the cells it uses in both the TBIC and ABMs.

It is recommended in 1149.4 that these uncommitted capture cells should capture internalTBIC signals with poor observability to improve the testability of the TBIC implementation.

14

15

16

17

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234 IEEE 1149.4 Analog Boundary-Scan

The next question is “what is the ‘TBIC Control Decode Logic’” in Figure 7-8.This logic is used to select from the switching patterns (P0 through P9) given inTable 7-2 for the switches in Figure 7-7. We need to know how this logic will selectthem. First, TAP instructions must be associated with the mode lines M1 and M2. Apossible assignment is shown in Table 7-3. (Most of these instructions are familiar,but more description will be presented in section 7.3 where their effects in an 1149.4environment are detailed.)

Now that M1 and M2 are assigned, Table 7-4 shows how the bits contained inthe four Boundary Register cells Ca, Co, D1 and D2 are used to select switchpatterns. An asterisk (“*”) in some table entries indicates that there is no switchingpattern yet assigned for this combinations of mode and cell values. Future versionsof the 1149.4 standard may assign patterns to these uncommitted combinations, sothey should be considered “reserved”. Application software designed to support thecurrent edition of the standard should avoid these reserved combinations.

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Table 7-4 may seem confusing, so it is useful to point out that there are somesimple relationships that make it more understandable.18

When all four bits are “0”, the ATn port is disconnected from the ABn bus andthe ATn pins are in a high impedance state.

When Ca = 0 (i.e., the first eight rows) the test circuitry is configured for testpurposes. Otherwise it is configured for characterization.

When Ca and Co are both “0” (i.e., the first four rows) then none, one, or bothof the ATn ports are connected to ABn. The AT1 connection is governed bythe D1 cell and the AT2 connection is governed by the D2 cell.

When Ca = 0 and Co = 1 (i.e., the second set of four rows) then AT1 and AT2are enabled to drive digital interconnect test signals out from the IC19 whilemonitoring the pin state. In this mode, D1 is a bidirectional data cell for AT1

18 The following list of statements assumes Model and Mode2 are not “10” (HIGHZ) or “00”

(BYPASS, etc.). When they are, no pattern of bits in the TBIC control cells has any effect onthe mission operation of the IC nor on the state of the ATn pins, which are disconnected.19

Note one slight difference here as compared with conventional 1149.1 drivers. When Co is“0” which disables the ATn drivers, the data cells have a possible, small parasitic effect on theIC by enabling switches S5 and/or S6 if D1 and D2 are not both “0”.

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236 IEEE 1149.4 Analog Boundary-Scan

and D2 is a bidirectional data cell for AT2. Cell Co is the enable control forboth.

Finally, Table 7-5 shows a set of logic equations (for the mode assignments usedin this example) that will implement the switch pattern selections given in Table 7-4.

This concludes the discussion of a minimal TBIC. The TBIC can be extended tosupport a differential ATAP (see section 7.4.1 on page 250) which may be used tosupport differential measurements (if desired) on ICs that have differential I/O. TheTBIC can also be expanded to support partitioned internal ABn buses (see section7.4.3 on page 253) when an IC designer desires to separate potential parasiticcoupling between (for example) sensitive input amplifiers and large signal outputbuffers.

7.2.4 The Analog Boundary Module (ABM)The ABM function first introduced in Figure 7-3 (on page 227) is used for two majorpurposes. First, it supports 1149.1-style interconnect tests. Second, it supports analogtest metrologies aimed at testing off-chip analog components in “extendedinterconnect”. Figure 7-9 shows a structure of an ABM meeting the requirements of1149.4 that may be used at any analog system pin.20

Starting on the left side of Figure 7-9 is the analog core circuitry that performsthe mission of the IC. For test purposes, this core will need to be disconnected fromthe analog pin on the right side. This disconnection property is shown as a discreteswitch SD, but it is quite important to note that this switch may not physically existas shown in the implementation of an ABM. In some cases, usually for analogoutputs, it may be a function that exists in the analog core that can be controlled as ifit were a switch in the location shown. In other cases (for example, analog inputs)this switch may not exist because the input has a very high impedance and thuscannot interfere with test activities. In yet another instance (again, for an analog

Note, the AT1/AT2 pins are not analog system pins, but part of the 1149.4 test resource set.20

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input) the switch may not exist, but the control signal that controls it is used in theanalog core to desensitize the core function to test signals appearing on the pin.Because the core disconnect switch SD may not actually exist as a physical entity,we call it a conceptual switch [Park93].

Next in Figure 7-9 we see a one-bit digitizer that creates a digital interpretationof the voltage on the analog I/O pin. This signal will appear later in Figure 7-10.This digitized signal is used to support 1149.1-style interconnect tests. Thedigitization is performed in relation to some threshold voltage shown asBecause this digitization need only be coarse rather than a precise operation, thisthreshold may not physically exist except as a physical property of the siliconimplementation. The goal is to cheaply obtain a one-bit measure of the voltage onthe pin (see [Lofs96a]). In general, with the additional goal that a shortbetween neighboring analog pins should not produce an intermediate voltage thatapproximates

Also in Figure 7-9 we see three DC voltages labeled and which can beconnected to the analog pin with three switches respectively labeled SL, SH and SG.Voltages and are used to create digital voltage levels on the analog pin insupport of 1149.1-style interconnect tests. Voltage is used in support of analogmetrology. Therefore should be a reference quality voltage, which means it is avoltage source capable of sourcing or sinking current over a defined range without anoticeable change in voltage, and it should be stable with respect to time. If an IChas a connection to system ground, this would make an excellent choice for Ifeither or has the “reference quality” property, then it may be used as

Switches SH and SL may also be conceptual if, for example, there is already apin driver present that can produce both and as a test function. The drivercontrol circuitry can be modified to activate it when the control signals for SH andSL are activated. An obvious advantage of using an existing driver is that it willlikely have a much larger current drive capability than 1149.4 switches would havein the interest of keeping the 1149.4 circuitry a small fraction of the IC’s area. If apin driver is capable of driving (say) a 50 ohm load, then it might be reasonable toexpect that such a load is likely to exist external to the IC. It is doubtful that small

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(cheap) switches could drive such a load, making it impossible for that pin toparticipate in 1149.1-style interconnect tests.21

Next in Figure 7-9 we see the internal measurement bus wires AB1 and AB2 thatcan be connected to the analog pin via switches SB1 and SB2. It is required thatAB1 be able to provide a current to the pin, and that AB2 be able to monitor the pinvoltage. (If the ABM is constructed with CMOS switches, then AB1 and AB2 couldbe interchangeable in these roles.)

The 1149.4 Standard has defined twenty switch settings (labeled P0 through P19)for the switches shown in Figure 7-9. These are shown in Table 7-6.

This does not necessarily mean a loss of fault coverage since shorts and opens can bedetected as a side effect of testing extended interconnect. However, the considerable speedadvantage of 1149.1-style testing would be lost.

21

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In Table 7-6, only 20 of the possible 64 switch settings are listed. This is becausemany settings are nonsensical, such as connecting and simultaneously to apin. The rational for these settings are:

P0 isolates the pin completely from the core and all test resources.P1 through P5 are used for testing extended interconnect by connecting one orboth analog buses and the reference voltageP6 and P7 can be used to characterize the quality of the reference.P0, P8 and P12 are, respectively, Hi-Z, drive low and drive high when used for1149.1-style interconnect tests.P9 through P11 and P13 through P15 allow characterization of andsources, or biasing external devices while measurements are made.P16 connects the pin to the core and disconnects all test circuitry. Used for“mission mode” operation of the pin.P17 through P19 are used to support the requirements of the PROBE andINTEST instructions (see sections 7.3.4 and 7.3.6, on pages 247 and 248).

The ABM control structure for the switches shown in Figure 7-9 is shown inFigure 7-10. This control structure makes use of four Boundary Register cells andtwo control mode signals “Mode1” (M1) and “Mode2” (M2) from the TAPcontroller which are a function of the currently active instruction. The four BoundaryRegister cells are named “Bus1” (B1), “Bus2” (B2), “Control” (C) and “Data” (D).

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Note that the capture stage of D captures the state of the signal generated inFigure 7-9. The C and D cells form a two-cell bidirectional structure (full pinmonitoring) for the support of 1149.1-style interconnect tests. The capture stages ofthe other three cells, C, B1 and B2 are uncommitted. It is recommended that these beused to capture embedded, hard-to-observe signals within the ABM to improve thetestability of the implementation.

So now the question is “what is the ‘ABM Control Decode Logic’” shown inFigure 7-10. Table 7-7 shows how the four Boundary Register cells C, D, B1 and B2are used to select from the twenty switch patterns P0 through P19. An asterisk (“*”)in an entry indicates there is no switch pattern (yet) assigned for this combination ofcontrol bits and they should be considered “reserved” for future assignment by the1149.4 Working Group. As before in the discussion of the TBIC control, we need toassociate values for Mode1 (M1) and Mode2 (M2) with instructions. This is done inTable 7-3 on page 234, the same assignment used for the TBIC.

Table 7-7 also contains some simple relationships that make it moreunderstandable.22

22 The following list of statements assumes Mode1 and Mode2 are not “00” or “10”. When

they are “00”, then no pattern of bits in the ABM control cells has any effect on the missionoperation of the IC. If they are “10” then the pin is HIGHZ regardless of cell content.

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When cell C = 0 (the first 8 rows), cell D determines whether the referenceis connected to the pin. These rows are used for analog measurements.

When cell C = 1 (the last 8 rows), cell D controls the logic state of the pin for1149.1-style interconnect tests. Thus cell C can be envisioned as a driverenable cell and cell D is a self-monitoring data cell23 for the pin.

In all rows, cell B1 controls the connection of AB1 to the pin and cell B2controls the connection of AB2 to the pin.

The logic equations for controlling the six ABM switch functions (remember,some of the switches themselves may be conceptual) are given in Table 7-8.

There is one last detail shown in Figure 7-9 on page 237. Note the electrostaticdischarge protection circuitry next to the pin pad. The existence of this circuitry mustbe accounted for with respect to the connection layout of AB1 and AB2 and the pinitself. The AB1 path conducts current, so there may be a voltage drop when thiscurrent traverses the series resistance in the protection circuitry. This is only aproblem if the voltage sensing path for AB2 is inside this path so that the true pinvoltage is not being measured. Figure 7-11 shows a pin ESD protection networkbefore and after 1149.4 is added. The redundant paths allow us to remove the effectsof the voltage drop within the protection circuit. This is an important point becauseIC layout processes may put a common metalization path with significant sharedimpedance in place of the two independent paths [Nuri97b, Park97].

This concludes the discussion of the ABM architecture. Soon the 1149.4instruction set will be described which will make use of the ABM structures. Thisshould answer some questions the reader has probably generated concerning how ananalog pin is supposed to behave during the execution of these instructions.

Note however that cells B1 and B2 do have a parasitic effect of closing the switches on theanalog ABn bus to the pin. To prevent this, load B1 and B2 with “00” while doing 1149.1-style testing. Cell D should also be set to “0” when the 1149.1 “driver” is not enabled, toprevent the reference from being connected to the pin.

23

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7.2.5 The Digital Boundary Module (DBM)Digital Boundary Modules can be constructed in many ways, as discussed in section1.3.4. The term “module”, introduced by 1149.4, is used to refer to all the BoundaryRegister cells associated with a given pin.24 This added nomenclature in no waychanges how 1149.1 relates to digital pins or how 1149.1 is implemented.

The philosophy behind DBM design is different that that behind the ABM. WhileABMs treat all pins homogeneously, DBMs strive to mimic the system nature of thepins they control. That is why in 1149.1 you see “input”, “output” and“bidirectional” DBMs. In 1149.4 you see a standardized ABM, though theimplementation details may indeed reflect the nature of the pin by using some of thenative resources for that pin.

In a mixed signal IC, there is very likely to be an analog-to-digital and/or digital-to-analog interface between the two domains. The 1149.1 standard has alwaysrequired that there be DBMs located at the interface between digital and analogdomains. The 1149.4 standard allows an option, shown in Figure 7-12. If the IC doesnot support INTEST or RUNBIST, the DBMs used to partition the analog domainfrom the digital are not required.

24A clean assignment of cells to pins is somewhat blurred by the fact that in 1149.1, a single

driver enable control cell may be shared by several pins. Then there is cell merging (seesection 2.4.1) to further cloud this concept. Neither concept exists for cells in TBIC or ABMstructures governed by 1149.4.

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7.3 THE 1149.4 INSTRUCTION SET

The 1149.4 instruction set is a superset of the 1149.1 instruction set in two ways.First, there is a new, mandatory instruction called PROBE described in section 7.3.3.Second, the instructions that target the Boundary Register such as EXTEST (section7.3.1) and INTEST (section 7.3.6) have expanded definitions that take into accountthe fact that analog pins are now included.

Some 1149.1 instructions are identical in definition within 1149.4. For example,BYPASS, PRELOAD, IDCODE and USERCODE are exactly the same in that theyare non-invasive. They have no effect on analog pins. This means they connect theanalog pin to the core circuit and open all other switches to isolate the pins(including the ATn pins) from the test circuitry.

The HIGHZ instruction is also the same, but expanded to include the analog pins,all of which float, completely isolated from the core and test circuitry. The SAMPLEinstruction is the same, but it also captures a digitization of the voltages appearing onthe analog pins.

25 The remaining instructions described in the following sections

deserve a bit more discussion.

25Both HIGHZ and SAMPLE act upon the ATn pins as if they were system digital pins.

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7.3.1 The EXTEST InstructionThe mandatory EXTEST instruction (see section 1.5.1 on page 36) is still thefundamental workhorse of 1149.4. It is used in the familiar role of implementing1149.1-style interconnect tests. (See Chapter 3.) It is also used to support analogmeasurements for the testing of external analog components that make up extendedinterconnect.

On digital pins, EXTEST behaves exactly as described in 1149.1. On analogpins, EXTEST may emulate “digital” behavior by either disabling an analog pin, orby connecting it to a low or high voltage, or (See switch patterns P0, P8 andP12 in Table 7-6.) This allows many analog pins to participate in interconnect tests.However, some analog pins may be connected to extended interconnect that preventsthem from emulating digital signals. In one case, the external impedance (forexample, a 50 ohm termination to ground) may be too low for the drive capability ofABM to overcome in order to establish both logic states. When this occurs, theinterconnect test must treat the pin as fixed. Later, when analog measurements aremade of the external impedance, problems such as shorts and opens will be detected,albeit sequentially and at much slower speed.

In another case, the extended interconnect presents very high impedance, suchthat two nodes are logically independent. For example, in Figure 7-2 on page 224 wesaw two analog pins connected through a capacitor. If this capacitor is (say) 100picofarads, then the two nodes connected to it are going to be logically independent.In this case, they should be treated by the interconnect test algorithm as two distinctnodes with their own interconnect serial test vectors (STVs) as discussed in Chapter3. This works because an ABM has bidirectional capability, allowing it tosimultaneously control and observe its pin.

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When EXTEST is used to support analog measurements, then a given ABMinvolved in this process

26 will use switch patterns P1 through P5 in Table 7-6. Note

that while some ABMs are used for analog measurements, all the other ABMs plusthe DBMs can be set up to disable or statically condition their respective pins insupport of these measurements. This is crucial because it stabilizes the circuit beingmeasured and reduces general system noise.

It is useful to see how a simple analog measurement is actually made with thesupport of EXTEST. Consider the circuit shown in Figure 7-13 where an ATEsystem, using only the six-wire 1149.4 port, can measure the value of an externalimpedance Z connected to an IC [Park93, Lofs96a, Nuri97b, Park97].

First, the ATE system must provide power to the board containing the circuitry.This also establishes a reference for subsequent measurements and a return path for

current used to stimulate the circuit.

26The TBIC must also be set up to connect one or both of ATn to ABn signals as needed.

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Next, the ATE system uses its digital sequencer to supply test patterns to theTAP pins. First, TAP integrity patterns are applied to assure the 1149.4 devices (orchain of 1149.1 and 1149.4 devices) is working. At this point it might then execute1149.1-style interconnect tests to test all the board wiring. Then we begin themeasurement of impedance Z. Refer now to Figure 7-14.

To measure impedance Z we first instruct the ATE system’s current source toproduce a small current. This current proceeds along AT1 to the IC’s TBIC where itis routed onto the internal AB1 bus. From there it travels to ABM1 where it getsrouted out onto pin 1 and the impedance. It travels through Z to pin 2 and back intothe IC where ABM2 routes it to the reference supply This reference completesthe path back through the IC ground and the current source.

Now that a known current is flowing through impedance Z, we need to measurethe voltage across it so we can uses Ohm’s law to calculate Z. Figure 7-14A showsthat the ATE system’s voltmeter is connected to AT2. From there, the TBICconnects AT2 to internal bus AB2. ABM1 connects AB2 to pin 1, completing thevoltage measurement circuit (ground referenced). This allows the ATE system torecord the voltage at pin 1. Similarly, in Figure 7-14B (for the same current stimulusconfiguration) we can measure the voltage at pin 2. Subtracting these two voltagesyields the voltage across the impedance that results when a known current travelsthrough it. An example from [Park93] assumes the nominal value of Z is 50 ohmsand that the pathway impedance through the switches is much larger, totaling 5000ohms. A 50 microampere DC current is used which develops a voltage of 0.2525volts at the AT1 terminal and only 2.5 millivolts across Z. Assuming a 4½ digitvoltmeter with a 10 microvolt resolution, there will be 20 microvolts of potentialerror in the two voltage measurements. This translates to +/- 0.4 ohms of error, or0.8 percent in the final calculated value of Z.

Ther e are practical issues (see [Park97]). The magnitude and type of current usedto stimulate the impedance must be selected such that for the expected value of Z,the resulting voltages will be within operating range of all parts of this circuit. Keepin mind the total impedance of the pathway must be considered, which includes theseries impedance of the three switches that conduct the stimulus current. A voltagecompliance limit on this current source must be set to keep it from exceeding theseoperating ranges in the event there is an open circuit, or if Z has been misloaded witha much larger valued device. If the component Z blocks DC current (for example, Zis a capacitor) then an AC source may be needed as discussed in [Park97].

This example has illustrated the basic idea of using 1149.4 resources and theEXTEST instruction to provide access to external impedances. Of course it will benecessary to deal with networks of these impedances, and [Park93] showed how thiscan be accomplished27 with more manipulations of the switches, and so on. But theidea is the same; inject a known current and make a series of node voltagemeasurements. The node voltage analysis technique [McDe98a, McDe98b]presented in section 6.2.1 on page 212 is a perfect match for this process, and alsoshows us how we can reduce the number of nodes that must be measured to obtain a

27This 1993 work was based on an extremely useful network analysis theorem given by

Tellegen [Tell52].

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result. This is particularly important when there are nodes in the network-under-testthat are not connected to either 1149.4 resources or test system probes.

7.3.2 The CLAMP InstructionThe optional CLAMP instruction (see section 1.5.5 on page 39) is used to freeze thestates of digital outputs for the duration of some testing operation while placing theBYPASS register between TDI and TDO for fast shifting.

In 1149.4, digital pins are treated identically. Analog pins too are frozen as wellas the state of the TBIC. Thus you can have an analog pin held to (say) or youcould even have a measurement setup frozen if it doesn’t need to change during a setof analog measurements. The CLAMP instruction will most likely be used to keepthe both analog and digital circuitry quiescent while either digital or analog testing isunderway.

7.3.3 The HIGHZ InstructionIn 1149.1, the optional HIGHZ instruction (see section 1.5.4 on page 39) whenloaded and activated, disables all output and bidirectional pins. The 1149.4 behavioris identical for digital pins. For analog pins, the behavior is also to disable all pins byopening the core disconnect function (switch SD in Figure 7-9 on page 237) anddisconnecting all test resources. The TBIC is also disabled.

7.3.4 The PROBE InstructionThe mandatory PROBE instruction is the only instruction unique to the 1149.4standard. It targets the Boundary Register between TDI and TDO. The designer maychoose the instruction bit pattern that decodes to PROBE. The PROBE instruction isanalogous to SAMPLE, but in the analog domain and with the restriction that only

28one of the analog pins can be sampled at one time. This is because there is only oneset of ABn wires available to perform analog sampling.

When the PROBE instruction is active, all DBMs are set to allow digital pins tobe connected to the core circuitry. Also, all core disconnect functions (labeled SD inFigure 7-9, page 237) are closed so that all analog pins are connected to the corecircuitry. Further, the TBIC switches are also governed by the content of the TBICcontrol register so that ATn to ABn connections may be made as desired.

ABM switch patterns P16 through P19 in Table 7-6 are used by the PROBEinstruction to connect none, one or both of the ABn lines to an analog pin. If AB2 isconnected (and AB2 is connected to AT2 by the TBIC) then the voltage appearingon any analog pin can be monitored at AT2 in real time.

29 In all other respects the IC

28In CMOS technology, AB1 and AB2 could be electrically identical such that you could

monitor two pins at the same time.29

This pathway is not a high frequency path because there is the significant series impedanceof the ABM and TBIC switches plus the external (mainly capacitive) loading on AT2.However, for lower frequencies, or testing experiments contrived to operate at lowfrequencies, this is a powerful feature.

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is fully operational although there could be some small parasitic effect from havingthe AB2 switch closed. If AB1 is also enabled (and AT1) then one can inject a small(attenuated) stimulus into any analog pin while the IC is otherwise fully operational.This could be useful for testing experiments where one wants to measure the effectof an externally applied voltage, current, at frequency, such as in noise measure-ments.

30

7.3.5 The RUNBIST InstructionThe optional RUNBIST instruction (see section 1.5.3 on page 38) is identical to its1149.1 definition. This instruction targets a register (that can be the BoundaryRegister) between TDI and TDO that will collect the RUNBIST test result uponcompletion of the RUNBIST action. This result can be shifted out to determine if thetest passed. As in 1149.1, there are two choices for I/O pin behavior whileRUNBIST is active. The first choice is to mimic the HIGHZ instruction, disablingall output drivers. The second choice is to mimic CLAMP, controlling all outputs viathe content of the Boundary Register.

Analog pins must behave the same way as the digital pins (HIGHZ or CLAMPbehavior). The signature developed by RUNBIST that is finally read out may or maynot give an indication of the health of the internal analog circuitry. In either case, thisresult should be completely independent of any externally generated analog signalsappearing on analog inputs just as the signature is required to be independent of anyexternal digital signals.

7.3.6 The INTEST InstructionThe optional INTEST instruction (see section 1.5.2 on page 37) is used to test theinternal circuitry of an IC while that IC is mounted on a board. In the 1149.1 world,it does this by replacing each I/O pin with one or more Boundary Register cells andusing these cells to present inputs and collect outputs in parallel. If an 1149.4 devicesupports INTEST, then the Boundary Register must include interface cells betweenthe digital and analog portions of the system circuitry as shown in Figure 7-12B backon page 243. This is because this interface contains I/O for both the digital andanalog portions of the device that must be controlled and observed in order to testeach.

Just as with RUNBIST, there are two choices for I/O pin behavior while INTESTis active. However there is a difference; the choices only apply to digital pins. Thefirst choice is to mimic the HIGHZ instruction, disabling all output drivers. Thesecond choice is to mimic CLAMP, controlling all outputs via the content of theBoundary Register. Analog pins remain connected to the core during INTEST; thatis, the SD switch function is closed (see Figure 7-9 on page 237). Further, eachanalog pin may be connected to none, one, or both of ABn

31 as controlled by the

30The ability to inject analog stimulus on a pin is why the PROBE feature is not considered an

extension of SAMPLE which is completely non-invasive.31

Connecting either AB1 or AB2 requires that the TBIC also be controlled to connect theappropriate ATn pins.

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content of the ABM control bits. (Switch patterns P16 through P19 in Table 7-6,page 238, are used.)

With 1149.4, the digital core can be tested with INTEST exactly as is done with1149.1. Digital test patterns can be shifted in, applied to the core, and the resultshifted out (see section 3.1.5). The Boundary Register cells between the analog anddigital portions of the core ensure that the two portions are isolated and unable toaffect each other. Because of this, any activity on the analog I/O of the IC will notpropagate to the digital portion of the IC. This is shown in Figure 7-15.

In 1149.4, INTEST can also be used to test the analog core as depicted in Figure7-16. Here, the digital portion of the core is no longer the focus.32 Instead, the analogcore is controlled and observed at the internal digital-to-analog interface by DBMs,and the analog I/O can be stimulated/observed via the ABMs. Of course, only onepin33 can be stimulated and one observed, though all may interact with externalcircuitry. One can use other ATE resources to control the external circuitry, if sodesired.

32 There is no difference in the operation of the test logic, just in the focus. In principle, you

could conduct testing on both the analog and digital portions of the circuit simultaneously,though this would likely be cumbersome. Usually you would focus on one portion and leavethe other in a quiescent state.33

Two pins (each) may be tested if the differential option (see section 7.4.1) is implemented.

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INTEST and PROBE are similar in that they both allow the analog core toremain connected to external circuitry. They differ in that PROBE allows the internaldigital circuitry to interact with the analog core, while INTEST disconnects thedigital core and supplies control and observation capability over their interface. Seesection 7.4.2 for a discussion of how INTEST is used to test differential signaltransmissions.

7.4 OTHER PROVISIONS OF 1149.4

What has been described to this point is a (near) minimal 1149.4 implementation.Additions are provided for by the standard. These include adding a second TBICcreating a differential ATAP port, a differential ABn bus, and the ability to partitionthe ABn bus to isolate groups of analog pins more completely.

7.4.1 Differential ATAP PortThe 1149.4 standard allows for the addition of a second TBIC that provides two newtest pins AT1N and AT2N to an 1149.4 IC. Inside the IC, this second TBIC isconnected to a second ABn bus with wires labeled AB1N and AB2N. It is intendedthat the ABn bus service the positive side of differential function pins and that the

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ABnN bus service the negative side.34

The section immediately following describeshow 1149.4 addresses differential function I/O.

7.4.2 Differential I/ODifferential I/O has been a surprisingly difficult topic for both the 1149.1 and 1149.4Working Groups to deal with. Until only recently, the 1149.1 stance was that if apair of differential signals had a clear “digital” nature, then you would treat them asif they were ordinary digital outputs, with a DBM structure devoted to each.However, if they were not digital, then you would either ignore them, or place aDBM at the boundary of the analog-to-digital interface (see Figure 4-10 on page156).

The 1149.4 Working Group had the charter for dealing with analog pins, so thisgroup couldn’t advise you to “just ignore” differential pins of either nature. The firstrecommendation from this group was simple; put an ABM on all differential pins.However, this led to some debate.

Debate Item 1: Differential drivers are often “special” designs that always createopposite states on their pin pairs.

35 Since 1149.4 can emulate 1149.1 for interconnect

test purposes, this requires that differential pins must not be constrained to oppositestates, at least during EXTEST-based testing. To actually do this in a differentialdriver design may be quite difficult (costly).

Debate Item 2: Placing ABMs on differential pin pairs may be fine formanufacturing tests of individual boards where noise may be non-existent. However,if you need to perform a system test of a differential pathway in a noisyenvironment, you really do need to transmit data across the path in differential form.You could try to coordinate two ABMs on the driver side to create the oppositestates, but the two ABMs on the receiving side do not have the ability to removecommon-mode noise.

First, we examine Debate Item 1 a bit more. There are two scenarios. In onescenario, we have only simple interconnect between the differential driver andreceiver such as we saw back in Figure 4-10 (page 156). Thus an ABM that simplydisconnects (or places into a high impedance state) the differential driver andsubstitutes its own (weak) drive high/low capability on the pin will be sufficient todo interconnect testing. All that is required of the differential driver design is that itbe disconnected on demand by the core disconnect signal.

36 In scenario two, there is

extended interconnect between the differential driver and receiver, typically, low-valued termination resistors. An ABM’s weak drive high/low capability would be

34A designer may also opt to add the second TBIC to provide for differential access to private

functions governed by private instructions.35

For digital pins, this means opposite voltage states. For analog pins, this may be representedby the polarity of current flow, as one example.36

This signal is “SD” in Table 7-8. Note the differential receiver should also be able totolerate non-differential signals that occur during interconnect testing. The SD signal may beused to govern this behavior.

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insufficient to create logic states into this loading. We can try to design thedifferential driver to act as the source of and for the ABM as 1149.4 allows ifthat is practical. If not, we will have to omit these differential signals from 1149.1-style interconnect testing. This means we will have to determine the integrity of theinterconnect with analog measurements of the external impedances. This will detectinterconnect faults, but at the price of a sequence of slow analog measurements andpotentially degraded diagnostic resolution.

Then there is Debate Item 2, how to verify the noise rejection capability ofdifferential signaling. For this discussion, examine Figure 7-17.

This figure shows an example of analog differential signaling and how you couldmarry the 1149.1 and 1149.4 approaches to differential signaling. It places ABMs atthe I/O periphery and places DBMs at the boundary where the system changesto/from differential signaling. From first appearances, the DBMs give you the abilityto drive and receive differential information and that seems sufficient to performsystem tests for noise rejection. You might imagine that EXTEST will be the waythis gets done. However, this is an example of the “EXTEST Paradox”. When youload EXTEST into the Instruction Register, this indeed will set up the DBMs tocontrol the differential driver and observe the differential receiver. However, theABMs also respond to EXTEST by disconnecting the pins from the differentialdriver and receiver. Thus you cannot test the noise rejection capability of thisdifferential pathway using EXTEST!

There is a solution. If you examine Figure 7-17 closely, you will notice that itconforms to the general concept of separating analog and digital cores that wasshown in Figure 7-16. In essence there is no analog core per se, just the digital-analog interface. Note too that Figure 7-16 illuminates the behavior of INTEST. Thisis our solution; use INTEST to test for noise rejection of differential signaling.

To do this, set U1 and U2 in Figure 7-17 to perform INTEST. This allows thetwo DBMs shown to control/observe the differential port. Remember that while inINTEST, the ABMs leave the I/O pins connected to their respective analog cores,which in this case are the differential driver and receiver. Is this a perversion of the

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meaning of INTEST, you may ask? I’d have to say yes, but I can also hedge bysaying you are testing an ensemble of internal circuitry spanning two ICs.

7.4.3 Partitioned Internal Test BusesFor practical reasons, it may be undesirable to have a single ABn bus distributed toall ABMs. A single bus could be a parasitic pathway for noise to travel from large-signal outputs back to small-signal inputs. If an IC has multiple power supplies, thensome portions of the IC may have voltage levels that are incompatible with an ABnbus that visits other regions of the IC supplied by other voltages. Thus 1149.4supports the partitioning of ABn buses.

Partitioning may be done such that a single set of ATn pins can be connected to ksets of ABn wires, labeled (AB1a, AB2a), (AB1b, AB2b), … (AB1k, AB2k). If k=1,then the TBIC is exactly as discussed in section 7.2.3 beginning on page 231. The1149.4 standard allows for k>1 extensions of the TBIC, where each extensioncontains six additional switches (four are mandatory) and two additional BoundaryRegister control cells. Figure 7-18 shows an example where a single ATn portservices two ABn ports (k=2). This structure is expandable to an arbitrary number ofextensions.

Table 7-9 displays the switching patterns defined by the 1149.4 Standard forextension k.

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To control an extension we need two more Boundary Register control cells suchthat we can control the switches in the extension independently of the main body ofthe TBIC. The main body contains the non-replicated switches S1 through S4 plusthe first set of switches S5 through S10 (all given the suffix “a”). The controlstructure (for a single extension) is depicted in Figure 7-19. Additional extensionsmay be added in similar fashion.

The control for partition “a” (the main body) is identical to that shown in Figure7-8 (page 234), governed by Table 7-2 through Table 7-5. In general, since theremay be any number of extensions, Table 7-9 shows the switching patterns for theextension.

Then Table 7-10 describes how Boundary Register cells Ca plus two additionalcells D1k and D2k in the extension are used to select switch patterns. As before,the asterisks in some entries indicate the definition of switching patterns that arereserved for future definition.

It is useful to point out, for Table 7-10, that there are some simple relationshipsthat make it more understandable.37

When Ca = 0, the test circuitry is configured for test purposes. Otherwise it isconfigured for characterization.

When Ca = 0 (selecting the first four rows of the table) then none, one, or bothof the ATn ports are connected to ABnk. Cell D1k governs AB1k and cellD2k governs AB2k.

When all three bits are “0”, the ATn port is disconnected from the ABnk bus.

Table 7-11 lists the logic equations for the control of the TBIC extention.

The following list of statements assumes Mode1 and Mode2 are not “00” or “10”. Whenthey are, no pattern of bits in the TBIC control cells has any effect on the mission operation ofthe IC.

37

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With this control structure, any extension can be connected to the ATn lines, and,any ABn bus can be characterized independently.

7.4.4 Specifications and LimitsThe 1149.4 standard gives specifications for items like path impedance, currentcarrying capacity, gain variation versus bandwidth, and so on. Some of these arebeyond the scope of this book,38 so just a few of these are given here to give thereader an idea of what is expected of an implementation.39 When implementing an1149.4 IC, it is very important to analyze these specifications ahead of time.

In CMOS-type technologies, the 1149.4 switching structures are most easilyimplemented with complementary field effect transistor pairs linked in parallel, togive bidirectional current flow. Here are some basic specifications on these switches.

The impedance of the pathway from the AT1 pin (through TBIC switch S5)onto AB1 and through an ABM to a system pin (through ABM switch SB1)should be the lesser of: 10 Kohms; or an impedance that will allowto flow through the path when the voltage drop across the path is

The path impedance from AT2 (through TBIC switch S6) onto AB2 andthrough an ABM to a system pin (through ABM switch SB2) should be lessthan 10 Kohms.

The impedance of the switch that connects or to a pin (when switchesare used) should be less that 10 Kohms.

The impedance of the switch that connects VG to a pin is the lesser of 10Kohms or an impedance that will allow to flow through the pathwhen the voltage drop across the path is This measurementis made with a 1 KHz AC source.

These expectations of perhaps thousands of ohms in the pathways used foranalog measurements are an acknowledgement that for 1149.4 to be cost effective,the switches must be very small. Indeed, in the earliest days of the 1149.4development, the working group had to give up on the idea of low-impedance

38Others are beyond the scope of the author!

39See [Vinn98], Chapter 7, where Steve Sunter gives additional guidance on characterization.

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switching (which could support guarded measurements) and find a metrology thatwould work with high-impedance switches. The experimental ICs developed foranalysis [Lofs96a, Nuri97b, Park97] have switches with hundreds to thousands ofohms impedance and yet measurements of devices could be achieved with accuracybetter than one percent.

If instead of CMOS-type switches, 1149.4 will be implemented in a bipolar-typeprocess, then buffers that can be disabled must be used in the measurementpathways. Here are some specifications for these buffers. In the pathway from AT1to a pin:

they should be able to deliver any current between to

The absolute value of the gain should be between 0.5 and 1.5.

Input currents that exceed the capability of the buffer should cause the bufferto saturate with a recognizable voltage output that indicates saturation.

In the voltage AT2 pathway from any pin:

buffers should be capable of monitoring any voltage betweenand

The maximum absolute value of gain should be 1.0.

Input voltages that exceed the capability of the buffer should cause the bufferto saturate with a recognizable voltage output that indicates saturation.

It is recommended that buffers have less than 5% variation in gain between 10Hz and 10 KHz and have a 3 dB bandwidth of 0-100 KHz.

Characterizing the buffers compensates for the fairly loose specifications (forexample on gain). This is one thing the TBIC loopback switches (S7, S8) may beused for.

7.5 DESIGN FOR 1149.4 TESTABILITY

We have precious little experience (at this writing) on which to build a Design forTest lore for the 1149.4 standard. However, embedded in the previous sections issome rationale for some DFT rules at the IC level. Rules for board level DFT areharder to come by for lack of experience. And at the system level (depending onwhat a “system” is) we have less still. However, this section presents a collection ofDFT guidelines we can imagine today.

7.5.1 Integrated Circuit LevelWe have already had hints of DFT rules show up in previous sections. For example,in Figure 7-11 (page 242) we saw that we need to take care in laying out ESDprotection circuitry. Since the AB1 bus may conduct a significant current to a pin,we want to avoid errors that can occur if we connect the AB2 path at a point wherewe are no longer measuring the voltage of the pin itself. This becomes moreimportant as the line widths of metalization paths become narrower with decreases inIC geometries. This leads us to our first rule.

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DFT-27: Eliminate all common conductive paths between a system pinpad and the ATn switches (SB1 and SB2).

In section 7.4.3 we saw that we can implement multiple ABn busses withseparate switching. This adds isolation between groups of pins that may otherwisewant to “talk” to each other over the parasitic impedances that can exist. Otherreasons to break the ABn buses into smaller groups are 1) to reduce the accumulatedleakages in any one bus that are the sum of the small leakages that each switchcontributes, and 2) to reduce the accumulated capacitance that each switch willcontribute. Excessive leakage or capacitance may damage the ability of the circuit toperform analog measurements during testing. An IC designer is well suited toevaluate the sensitivity of his/her design with respect to these criteria.

DFT-28: Partition internal analog test buses (per section 7.4.3) to controlon-chip cross talk, leakage, and capacitance.

In some cases the switches themselves, due to their parasitics, may introduce aworrisome amount of coupling between portions of the circuitry. All the switchesshown to this point are simple transmission structures that take a minimum area butmay not provide optimum isolation. For cases where there is sensitivity to theseparasitics, a pair of switches in series with a shunt switch that connects the middlenode to a quiescent reference voltage (called a “T” switch) can be used to greatlyimprove the isolation of the two sides of the overall switch structure as shown inFigure 7-20. On a local scale of a single switch, this is similar to the effect we arepursuing via bus partitioning examined in the previous DFT rule (DFT-28).

As IC feature geometries continue to shrink, the leakage in these switch struc-tures will rise. The “T” switch will be very useful for controlling this leakage. Sowhile the “T” switch is a larger structure, smaller feature sizes will mitigate the cost.

DFT-29: Examine the location of switches for places where the circuitmay be sensitive to parasitic coupling and leakage. Use enhanced switchdesigns in these areas to reduce these effects.

Continuing on the topic of parasitic effects, consider how your ATAP pins arepositioned in the IC’s physical pinout. If they are adjacent to each other, can theyinfluence each other via leakage and capacitance? How about if they are adjacent toactive digital signals, will they be disturbed by these signals during functions such asPROBE? The layout of the ATn pins with respect to power and ground pins may beused to mitigate parasitic effects. Consider placing the reference voltage pinbetween them since subsequent measurements will use this voltage reference.

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DFT-30: Analyse the layout of the ATn pins with respect to leakage andparasitic effects between them and other signals.

Finally, consider implementing the optional INTEST instruction since this givesthe ability to isolate the digital and analog portions of the IC for tests done later atthe board or system level (see DFT-34 on page 261).

7.5.2 Board LevelBoard DFT for 1149.4 deals with the fact that two ICs containing 1149.4 may not becompatible with respect to the reference voltages they use internally. These voltagesmay appear at system pins or the ATn pins. Assume that if two ICs have their systempins connected, this implies they are compatible at those pins. However, since theATn pins can be driven and received, some choice had to be made for the voltagesthat are used on these pins. It is possible that they are not compatible from IC to IC.In Figure 7-6 (page 231) we saw ICs with their respective TAP and ATAP pinsconnected together. It may turn out that the TAPs are all implemented in a commontechnology, (say, 3.3 volt CMOS) but that and used in their respectiveATAPs are not compatible. This would be a reason why a chain of devices, asviewed by the 1149.1 standard may require separated ATAP ports. If this isnecessary, then plan on grouping compatible ATAPs together with common wiring,independently of how the TAPs are chained. This will necessitate test access tomultiple ATAP ports even if there is only one TAP chain on board. Formanufacturing test, this should not present any problems (as long as we have accessto all the ATn ports) since the ATE system can choose which of the ATn ports toaccess. However, if a design goal is to implement an embedded self-test using theseresources, the additional ATn ports will have to be accommodated, perhaps withmultiplexing to the board level stimulus and measurement resources.

DFT-31: Group compatible ATAPs together on common ATn buses. Beprepared to accommodate more ATAP buses than there are TAP chains.

With respect to leakage between ATn signals, an extension of DFT-30 may beconsidered at the board level. In analog designs, it is a well-known board layouttechnique to place a “guard wire” between two sensitive signal wires. This wire isconnected to a quiescent reference voltage40 also used in measurements (typicallyground) as suggested in Figure 7-21. Board leakage may be exacerbated by “no-clean” board manufacturing processes where ionic contamination from manufac-turing (typically soldering) is often still present.

40In extreme cases, for example, ultra-high resolution voltmeters, this guard wire completely

surrounds a sensitive wire in a “box”. Further, it may be a “driven guard”, where an amplifiercopies the signal from the sensitive wire onto the guard to keep the guard wire at the samepotential. Thus there is no voltage between the guard and the target wire and any leakage fromsurrounding circuitry is absorbed by the guard. Obviously, care must be taken with this type ofguard design. It is unlikely that driven guards would be needed in 1149.4 designs.

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The decision to use a guard wire during layout can be made by examining whattypes of values will be measured by a given ATn port. If lower impedances (forexample, termination resistors) will be measured, then guarding will not be needed.If high impedance, high precision devices (many megohms) are the measurementtarget, then a guard wire may be important. Note that in Figure 7-21, guards areshown connected to ground. In general, the board node connected to an IC’s pinis what should be used for the guard. It is possible that two identical ICs on the sameboard may have their pins connected to different voltages. If guard wires areneeded for both ICs, then they should probably have independent ATn ports.

DFT-32: For ATn ports expected to be used in measurements of very highimpedances, place a board-level guard wire between the ATn signals.

7.5.3 System LevelAt the system level, it may be important to make analog measurements utilizing theanalog test facilities of 1149.4. Or, it may not! This is a strong function of what a“system” looks like and what type of analog measurements may be required of thesystem. The full suite of analog measurements of interest at board test may beoverkill at system test. This will determine how many ATn ports need to be madeaccessible to a system level analog stimulus/measurement facility.

My favorite hypothetical example comes from the automotive industry. Theengine control system for an automobile could be implemented with 1149.1/1149.4technology to support system level testing and diagnosis. Interconnect tests would bevery important since it is well known that interconnections (cabling and connectors)in cars are a weak point. Though there may be many analog components too, it maybe too difficult (expensive) to make analog measurements on all of these if doing sorequires routing several ATn domains back to a central analog stimulus andmeasurement resource. However, certain analog devices may be wear items that areexpected to degrade in time. These could be serviced with a port while most otheritems are not.

DFT-33: Consider which of all ATn ports in a system will be needed forsystem test and provide access to them.

Finally, at system test, we may want to test differential signaling and itsimmunity to system noise. This is a digital test, but requires the 1149.4 resource for

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differential testing provided by the INTEST instruction (see section 7.4.2 on page251). This gives us our last DFT rule.

DFT-34: Consider if noise-immunity testing of differential signaling isrequired in the system.

7.6 SUMMARY

This single chapter describing the 1149.4 standard is breathtakingly short when youconsider the scope of the Mixed Signal Test Bus standard. This brevity is in part dueto the fact that the 1149.1-emulation capability contained within 1149.4 is covered inprevious chapters. But another reason is that the whole concept of 1149.4 is verynew and we have much yet to learn from experiences with it. Test ICs [Lofs96a,Nuri97b, Park97] have been invaluable for proving concepts and gaining experience.

I have been asked many times to speculate on the rate of adoption of the 1149.4standard. I see several factors in this.

To its advantage, 1149.4 builds upon the growing infrastructure of 1149.1tools, products, knowledge and experience. Indeed it is possible to performuseful digital interconnect tests (even in extended interconnect cases) with1149.4 using today’s software, unmodified [Park97].The level of concern that people have today about limited physical probingaccess is quite high. People perceive a lack of alternatives and a motivation to“make it work”. These people will also expect IC vendors to make good-faithefforts to support their test needs. (This is true for 1149.1 as well.)While not often admitted by 1149.4 Working Group members, the 1149.4standard is CMOS-centric. The good news is that CMOS-type technologiesare becoming more prevalent in mixed-signal IC designs, if for no otherreason than the densities it can achieve for the digital portions of the ICs.To its disadvantage, 1149.4 is harder to implement because, after all, it is ananalog design problem.The “market size” of mixed-signal designs, while growing respectably, is stilla good bit smaller than that of digital designs. This may retard investment inadvanced tools for a time.The 1149.4 standard will more sensitive to the accuracy of data you haveabout the construction of a board and its ICs. It is fitting to end this book withthe same warning that appeared on the first page, that if you are not in controlof your data, then Garbage In, Garbage Out will be the result.

Pressed for a prediction, I say that I expect the adoption of 1149.4 to be similar to1149.1 which took a longer period than proponents had anticipated. However, Ipersonally have seen mixed-signal products on drawing boards for which there areextraordinary testing problems that only 1149.4 can solve. Until 1149.4 comes ofage, we are likely to see such products cost more than they should and be late tomarket. This will be an incentive for larger manufacturers who see 1149.4 as astrategic opportunity. I find it interesting that globally, 1149.1 was adopted last in

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262 IEEE 1149.4 Analog Boundary-Scan

the Far East. Today, I see high levels of interest with significant participation in1149.4 from the Far East. This should be raising eyebrows in rest of the world.

7.7 EPILOG: WHAT NEXT FOR 1149.1/1149.4?

To reiterate some history scattered about this book, the 1149.1 Standard came intobeing as a digital standard. It essentially ignored analog signals on an IC. After sometime and a large amount of debate, thought and research, the 1149.4 Standardproposed a method for treating analog signals. This method recognized the value of1149.1-style interconnection tests and showed how the salient features of 1149.1could in essence be emulated by 1149.4 such that wiring tests could be supported aswell as analog metrologies.

In the 1993 time frame, the 1149.4 Working Group was talking about how analogmetrology and 1149.1-style interconnect tests were essentially “orthogonal”, andhow an ABM could, in effect, provide independent hardware to support these twogoals. Again debate swirled for a time. Ultimately this realization was accepted afterit was shown, by actually analyzing test chip designs, that an orthogonal implemen-tation was not much different in cost to a seemingly cheaper design that integrated(i.e. encoded) control for the analog and interconnect test problems.

Around 1996, Lee Whetsel proposed that the 1149.1 Working Group considerextracting the interconnect test capability for analog wiring supported by 1149.4 andmerge it back into 1149.1.41 This would take the “analog blinders” off of 1149.1.Then by coordinating 1149.4 with this change in direction, ultimately 1149.4 wouldbecome a true “analog” standard rather than one that “fixed up” 1149.1.

As this book goes to press, this process is still under way. I cannot reliablypredict what the final result will be. In one case, we could see both 1149.1 and1149.4 stay they way they are, with one ignoring analog pins and the other fillingthat gap. In another scenario, 1149.1 will become the “interconnect test” standard forall wiring, and 1149.4 will be the “analog metrology” standard. In either case, youshould expect that the two will continue their shared goals of interoperability.Indeed, they will likely become inseparably bound together when printed by theIEEE. One last time I urge the reader to keep up-to-date with the two Standards, aschange is to be expected as we learn more about testing digital, analog and mixedsignal designs.

This idea had been hypothesized for some time. Lee proposed the actual Boundary Registercell designs within 1149.1 that could make this happen. These proposal cells wereimmediately called “Whet-cells” by the two working groups.

41

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APPENDIX A

BSDL Syntax Specifications

This Appendix is a condensed listing of 19991 BSDL lexicography and syntax. Itdoes not include the myriad semantic rules found in the BSDL specification asprovided by the IEEE. This information may be helpful to someone contemplatingwriting a BSDL parser, or to someone needing a quick reference guide for BSDLsyntax when writing a BSDL description. It is assumed the reader is familiar withformalized specification of language.

A.1 CONVENTIONS

All reserved words, predefined words, and punctuation are shown in CourierNew type within this document. VHDL reserved and predefined words will beshown in lowercase letters, and BSDL reserved words will be shown inUPPERCASE letters. (BSDL itself is case-insensitive; this convention is adopted fordescriptive clarity.)

1Caution: A revision to IEEE 1149.1, including BSDL, is being completed as this book goes

to press. The author believes that the material presented here is substantially similar to thatultimately published by the IEEE. However, you should obtain the latest IEEE document.

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A.2 LEXICAL ELEMENTS OF BSDL

The lexical elements of BSDL are a subset and standard practice of those of VHDLas defined in IEEE Std 1076-1993. The following sections enumerate the lexicalelements needed to understand the BSDL language definition.

A.2.1 Character setUpper- and lowercase letters: A to Z and a to z (the language is not casesensitive)

Digits: 0 to 9

Special characters:

Logical separators: The space character, horizontal tabulation, verticaltabulation, carriage return, line feed, and form feed.

A.2.2 IdentifiersIdentifiers are user-supplied names and reserved words functioning as names.Identifiers start with a letter and may contain letters, digits, or the underscorecharacter. For example, the following are valid identifiers:

Boundary_ScanIEEE_Std_1149_1

There is no limit to the number of characters in an identifier. The underscorecharacter (_) is not allowed as the last character in an identifier (by VHDL).

IEEE_STD_1149_ -- This is not a legal identifier.

Adjacent underscore characters (– –) are not allowed.

A.2.3 BSDL reserved wordsThe identifiers listed in this section are BSDL reserved words with a fixedsignificance in the language. These identifiers cannot be used for any other purposein a BSDL description. For example, a reserved word cannot be used as an explicitlydeclared identifier. BC_0 to BC_99 are variable names used in the Standard VHDLPackage. Names BC_0 through BC_7 are used today, while BC_8 through BC_99are reserved for future use. Similarly, the names STD_1149_1_1990,STD_1149_1_1993, STD_1149_1_1994 and STD_1149_1_1999 have beenreserved, with the potential for new names to be added later. Therefore, avoid usingidentifiers that start with “STD_1149_”.

"&‘()*,-.:; < = >

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A.2.4 VHDL reserved and predefined wordsThe identifiers listed below are called VHDL (IEEE Std 1076-1993) reserved andpredefined words with a fixed significance in the language. These identifiers may notbe used for any other purpose in a BSDL description. For example, a reserved wordcannot be used as an explicitly declared identifier. Reserved words shown in the list

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below in lowercase letters are part of the BSDL subset of VHDL. Those in uppercaseletters are not part of BSDL, but should not be used as identifiers. The latest editionof the VHDL standard [IEEE93b] shall be consulted as the final authority.

A.2.5 StringsA string is defined as a sequence of zero or more characters enclosed betweenquotation marks. A quotation mark character is not allowed within a string in BSDL.For example,

"Mary had a little lamb" -- Allowed"Fred said ""HELP""" -- Not allowed

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Strings are used extensively in BSDL. Because many of the BSDL strings arepotentially much longer than a single line, the concatenation operator & is used tobreak them into manageable pieces. For example,

"Jack be nimble," &" Jack be quick."

is a single string, identical to

"Jack be nimble, Jack be quick."

BSDL does not permit replacement of the quotation mark with any othercharacter. A string literal must fit on one line since it is a lexical element.

A.2.6 CommentsAny text between a double dash (--) symbol and the end of a line is treated as acomment. The text is allowed to contain any characters allowed by VHDL.Comments syntactically terminate a line of a description. Comments may beinterspersed with lexical elements. For example, the following represents a singleVHDL string:

"This is" & -- An example of a string split by a comment" a single string"

A.3 NOTES ON SYNTAX DEFINITION

A.3.1 BNF conventionsAny item enclosed in chevrons (i.e., between the character “<” and thecharacter “>”) is the name of a syntax item that will be defined in thisappendix.

Items enclosed by braces (i.e., between the character “{” and the character“}”) may be omitted or included one or more times.

Items enclosed between square brackets (i.e., between the character “[” andthe character “]”) may be omitted or included only one time.

Items enclosed between the symbols and may appear in any order.

Except with regard to case, text shown in Courier New type font has to beincluded exactly as it is presented in this appendix.

Alternative syntaxes are separated by a vertical bar (“|” ).

The symbol “::=” should be read as “is defined as.” Note that the non-boldface“::=” is only part of a BNF description; in the BSDL file, the boldfacecharacters “:=” are used to indicate assignment.

White space (spaces, tabulation, carriage returns, etc.) is used in these BNFdescriptions to enhance readability and is not part of the syntax. However,white space needed for resolving lexical ambiguity is required.

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268 BSDL Syntax Specifications

A.3.2 Lexical atomsA <VHDL identifier> is a valid identifier, chosen as a name for an item.

An <integer> is an unsigned VHDL integer made up of an unsigned numericcharacter sequence not containing an underscore (_) character and not using anexponent field.

A <real number> is a VHDL real number of the form <integer>.<integer> or<integer>.<integer>E<integer> all written contiguously without spaces orformat effectors. Note 1E3 is not real because it does not contain a decimalpoint. The number 20.0E6 is real, as is 20000000.0.

A <pattern> is a contiguous sequence of one or more 0, 1, and X characterscontaining no spaces. For example, 001X00 and XX010X are legal. However,100 X00 is not legal because of the embedded space. A low state is denotedby 0, a high state is denoted by 1, and a don’t-care value is denoted by X.

A <32-bit pattern> is a <pattern> with exactly 32 characters in its charactersequence.

A <left bracket> is the left bracket character ([).

A <right bracket> is the right bracket character (]).

Lexical ambiguity exists in certain situations and has to be resolved by context.For example, a <pattern> that starts with an X has to be differentiated from a<VHDL identifier> by context derived from the syntax. Similarly, a <pattern> thatdoes not contain an X has to be differentiated from an integer such as 100 (onehundred).

A.3.3 Commonly used syntactic elementsA <port ID> identifies a component signal that may be used to interface toexternal signals. A port may be dimensioned as a bit or a bit_vector.Subscripted names are allowed only when bit_vector-dimensioned portsignals are used.

<port ID>::= <port name> | subscripted port name><port name>::= <VHDL identifier><subscripted port name>::= <VHDL identifier> (<subscript>)<subscript>::= <integer>

An <instruction name> is an instruction name defined in this standard or aname given to an instruction by the manufacturer of a component.

<instruction name>::= BYPASS | CLAMP | EXTEST | HIGHZ |IDCODE | INTEST | PRELOAD |RUNBIST |SAMPLE | USERCODE | <VHDL identifier>

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The Boundary-Scan Handbook 269

A.4 BSDL SYNTAX

The BSDL entity description must have the following structure:

<BSDL description>:: =entity <component name> is<generic parameter><logical port description><standard use statement>{<use statement>}<component conformance statement><device package pin mappings>[<grouped port identification>]<scan port identification>[<compliance enable description>]<instruction register description>[<optional register description>][<register access description>]<boundary-scan register description>[<runbist description>][<intest description>]{<BSDL extensions>}[<design warning>]

end <component name>;

<component name>::= <VHDL identifier>

<generic parameter>::=generic (PHYSICAL_PIN_MAP: string); |generic (PHYSICAL_PIN_MAP: string :=

<default device package type>);<default device package type>::= " <VHDL identifier> "<logical port description>::= port (<pin spec>

{; <pin spec});<pin spec>::= <identifier list>: <pin type> <port dimension><identifier list>::= <port name> {,<port name>}

<pin type>::= in | out | buffer | inout | linkage<port dimension>::= bit | bit_vector (<range>)<range>::= <integer_1> to <integer_2> |

<integer_2> downto <integer_1><integer_1>::= <integer><integer_2>::= <integer><standard use statement>::=

use <standard VHDL package identifier>.all;<standard VHDL package identifier>::= STD_1149_1_1990 |

STD_1149_1_1994 | STD_1149_1_1999 |<other package identifier>

<other package identifier>::= <VHDL identifier><use statement>::= use <user VHDL package identifier>.all;<user VHDL package identifier>::= <VHDL identifier>

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270 BSDL Syntax Specifications

<component conformance statement>:: =attribute COMPONENT_CONFORMANCE of

<component name>: entity is <conformance string>;<conformance string>::= " <conformance identification> "<conformance identification>::=

STD_1149_1_1990 | STD_1149_1_1993 | STD_1149_1_1999<device package pin mappings>::=

<pin map statement> <pin mappings><pin map statement>::=

attribute PIN_MAP of <component name>: entity isPHYSICAL_PIN_MAP;

<pin mappings>::= <pin mapping> {<pin mapping>}<pin mapping>::=

constant <pin mapping name>: PIN_MAP_STRING:=<map string>;

<pin mapping name>::= <VHDL identifier><map string>::= " <port map> {, <port map>} "<port map>::= <port name>: <pin list><pin list>::= <pin ID> | (<pin ID> {, <pin ID>})<pin ID>::= <VHDL identifier> | <integer><grouped port identification>::=attribute PORT_GROUPING of <component name>: entity is

<group table string>;<group table string>::= " <group table> "<group table>::= <twin group entry> {, <twin group entry>}<twin group entry>::= <twin group type> (<twin group list>)<twin group type>::= DIFFERENTIAL_VOLTAGE |

DIFFERENTIAL_CURRENT<twin group list>::= <twin group> {, <twin group>}<twin group>::= (<representative port>, <associated port>)<representative port>::= <port ID><associated port>::= <port ID><scan port identification>::= <TCK stmt> <TDI stmt>

<TMS stmt> <TDO stmt> [<TRST stmt>]<TCK stmt>::=

attribute TAP_SCAN_CLOCK of <port ID> : signal is(<clock record>);

<TDI stmt>::=attribute TAP_SCAN_IN of <port ID> : signal is true;

<TMS stmt>::=attribute TAP_SCAN_MODE of <port ID>: signal is true;

<TDO stmt>::=attribute TAP_SCAN_OUT of <port ID>: signal is true;

<TRST stmt>::=attribute TAP_SCAN_RESET of <port ID> : signal is true;

<clock record>::= <real number> , <halt state value><halt state value>::= LOW | BOTH<compliance enable description>::=

attribute COMPLIANCE_PATTERNS of <component name> :entity is <compliance pattern string> ;

<compliance pattern string>::= " ( <compliance port list> )( <pattern list> )"

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The Boundary-Scan Handbook 271

<compliance port list>::= <port ID> { , <port ID>}<pattern list>::= <pattern> { , <pattern> }<instruction register description>:: =

<instruction length stmt><instruction opcode stmt><instruction capture stmt>[<instruction private stmt>]

<instruction length stmt>::=attribute INSTRUCTION_LENGTH of <component name>

: entity is <integer>;<instruction opcode stmt>::=

attribute INSTRUCTION_OPCODE of <component name> :entity is <opcode table string>;

<instruction capture stmt>::=attribute INSTRUCTION_CAPTURE of <component name> :

entity is <pattern list string>;<instruction private stmt>::=

attribute INSTRUCTION_PRIVATE of <component name> :entity is <instruction list string>;

<opcode table string>::=" <opcode description> {, <opcode description>} "

<pattern list string>::=" <pattern list> "<pattern list>::= <pattern> {, <pattern>}<instruction list string>::= " <instruction list> "<instruction list>::= <instruction name>

{, <instruction name>}<opcode description>::=<instruction name> (<pattern list>)<optional register description>::=

<idcode statement> [<usercode statement>]<idcode statement>::=

attribute IDCODE_REGISTER of <component name>: entity is<32-bit pattern list string>;

<usercode statement>::=attribute USERCODE_REGISTER of <component name>

: entity is <32-bit pattern list string>;<32-bit pattern list string>::= " <32-bit pattern list> "<32-bit pattern list>::= <32-bit pattern>

{, <32-bit pattern>}<register access description>:: =

attribute REGISTER_ACCESS of <component name>: entity is<register string>;

<register string>::=" <register association> {, <register association>} "

<register association>::=<register> (<instruction capture list>)

<instruction capture list>::=<instruction capture> {, <instruction capture>}

<instruction capture>::=<instruction name> [CAPTURES <pattern>]

<register>::= BOUNDARY | BYPASS | DEVICE_ID |<VHDL identifier> <left bracket> <register length>

<right bracket><register length>::= <integer>

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272 BSDL Syntax Specifications

<boundary-scan register description>:: =<boundary length stmt> <boundary register stmt>

<boundary length stmt>::=attribute BOUNDARY_LENGTH of <component name>: entity is

<integer>;<boundary register stmt>::=

attribute BOUNDARY_REGISTER of <component name>: entity is <cell table string>;

<cell table string>::= " <cell table> "<cell table>::= <cell entry> { , <cell entry> }<cell entry>::= <cell number> ( <cell info> )<cell number>::= <integer><cell info>::= <cell spec> [ , <disable spec> ]<cell spec>::= <cell name> , <port ID or null> , <function> ,

<safe bit><cell name>::= <VHDL identifier><port ID or null>::= <port ID> | *<function>::= INPUT | OUTPUT2 | OUTPUT3 | CONTROL |

CONTROLR | INTERNAL | CLOCK | BIDIR | OBSERVE_ONLY<safe bit>::= 0 | 1 | X<disable spec>::= <ccell> , <disable value> ,

<disable result><ccell>::= <integer><disable value>::= 0 | 1<disable result>::= Z | WEAK0 | WEAK1 | PULL0 |

PULL1 | KEEPER<runbist description>::=

attribute RUNBIST_EXECUTION of <component name>: entity is " <runbist spec> ";

<runbist spec>::= <wait spec> , <pin spec> , <signature spec><wait spec>::= WAIT_DURATION (<duration spec>)<duration spec>::= <clock cycles list> |

<time> [ , <clock cycles list> ]<clock cycles list>::= <clock cycles> { , <clock cycles> }<time>::= <real number><clock cycles>::= <port ID> <integer><pin spec>::= OBSERVING <condition> AT_PINS<condition>::= HIGHZ | BOUNDARY<signature spec>::= EXPECT_DATA <det pattern><det pattern>::= <bit> { <bit> }<bit>::= 0 | 1<intest description>::=

attribute INTEST_EXECUTION of <component name>: entity is " <intest execution sequence> ";

<intest execution sequence>::= <wait spec> , <pin spec><BSDL extensions>::= <BSDL extension> { <BSDL extension> }<BSDL extension>::= <extension declaration> |

<extension definition><extension declaration>::=

attribute <extension name> : BSDL_EXTENSION;<extension definition>::= attribute <extension name> of

<component name> : entity is<extension parameter string>;

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The Boundary-Scan Handbook 273

<extension name>::= <entity defined name> |<VHDL package defined name>

<entity defined name>::= <VHDL identifier><VHDL package defined name>::= <VHDL identifier><extension parameter string>::= <string><design warning>::=

attribute DESIGN_WARNING of <component name> : entity is<string> ;

A.5 USER PACKAGE SYNTAX

<user package>::= package <user package name> is<standard use statement>{ <extension declaration> }{ <deferred constant> }

end <user package name> ;

<user package body>::= package body <user package name> is<standard use statement>{ <cell description constant> }

end <user package name> ;

<user package name>::= <VHDL identifier><deferred constant>::= constant <cell name> : CELL_INFO;<cell name>::= <VHDL identifier><cell description constant>::=constant <cell name> : CELL_INFO := (

<capture descriptor list> ) ;<cell name>::= <VHDL identifier><capture descriptor list>::= <capture descriptor>

{ , <capture descriptor> }<capture descriptor>::= ( <cell context> ,

<capture instruction> , <data source> )<cell context>::= INPUT | OUTPUT2 | OUTPUT3 |

INTERNAL | CONTROL | CONTROLR | CLOCK |BIDIR_IN | BIDIR_OUT | OBSERVE_ONLY

<capture instruction>::= EXTEST | SAMPLE | INTEST<data source>::= PI | PO | CAP | UPD | ZERO | ONE | X

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[Yau89]

“JTAG Boundary-Scan: Diagnosing Module Level Functional Failures”, J.Sweeney, National Communications Conference, 1988, pp 1801-1804“Thermal Analysis of Backdriven Output Transistors”, R. L. Swent and M. J.Ward, Proceedings, International Test Conference, pp 295-303, Washington DC,Sept 1986

“Opens Board Test Coverage: When is 99% Really 40%?”, M. V. Tegethoff, K. P.Parker and K. Lee, Proceedings, International Test Conference, pp 333-339,Washington DC, Oct 1996

“A General Network Theorem with Applications”, B. D. H. Tellegen, PhillipsResearch Report No. 7, pp 259-269, 1952“ASSET Diagnostic System Overview”, (Literature SATT113), TexasInstruments, Inc., 1990

“54BCT8244/74BCT8244 Octal Buffer with Boundary-Scan”, Texas Instruments,Inc., 1991

“54BCT8374/74BCT8374 Octal D Flip-Flop with Boundary-Scan”, TexasInstruments, Inc., 1991

“Towards a Test Standard for Board and System Level Mixed-SignalInterconnects”, C. W. Thatcher and R. E. Tulloss, Proceedings, International TestConference, pp 300-308, Baltimore MD, Oct 1993“Powered Testing of Mixed Conventional/Boundary-Scan Logic”, United StatesPatent 5,260,649, Nov 1993

“Interconnect Testing with Boundary-Scan”, P. T. Wagner, Proceedings,International Test Conference, pp 52-57, Washington DC, Sept 1987“Design for Testability of Mixed-Signal Integrated Circuits”, K. D. Wagner andT. W. Williams, Proceedings, International Test Conference, pp 823-828,Washington DC, Oct 1988“Analog and Mixed-Signal Test”, B. Vinnakota, Editor, Prentice Hall, UpperSaddle River, NJ, 1998

“Enhancing Board Functional Self-Test by Concurrent Sampling”, K. D. Wagnerand T. W. Williams, Proceedings, International Test Conference, pp 633-640,NashvilleTN, Oct 1991“Event Qualification: a Gateway to At-Speed System Testing”, L. Whetsel,Proceedings, International Test Conference, pp 135-141, Washington DC, Sept1990

“A Proposed Method of Accessing 1149.1 in a Backplane Environment”, L.Whetsel, Proceedings, International Test Conference, pp 206-216, Baltimore MD,Sept 1992

“Improved Boundary Scan Design”, L. Whetsel, Proceedings, International TestConference, pp 851-860, Washington DC, Oct 1995

“Design for Testability — A Survey”, T. W. Williams and K. P. Parker,Proceedings of the IEEE, vol. 71, No. 1, Jan 1983“XC 4000 Logic Cell Array Family”, Xilinx Inc. 1990

“Boundary-Scan Emulator for XC 3000”, Application Note XAPP-007.0, XilinxInc. 1992

“The Programmable Logic Data Book”, Xilinx Inc, 1998

“A New Framework for Analyzing Test Generation and Diagnosis Algorithms forWiring Interconnects”, C. W. Yau and N. Jarwala, Proceedings, International TestConference, pp 63-70, Washington DC, Aug 1989

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INDEX

1149 461149.11149.41149.5

22, 197

46, 195

AAddressable Shadow Port 195

128AliasingAmbiguity Class 215, 216AMD Am29030 160Analog Boundary Module (ABM) 226, 227,

236, 238-242, 244, 245, 247, 249,256

Analog Boundary-Scan 221Analog Test Access Port (ATAP) 228, 230,

232, 236, 250AT1 228-233, 235, 236, 246, 248,

254, 256, 257AT1N 228, 250AT2 228-233, 235,236, 246,

247, 254, 256, 257

AT2N 228, 250Analog Test Bus

AB1 228, 229, 231-233, 238, 241,246,

248, 254, 256AB1N 228, 250AB2 228, 229, 231-233, 238, 241,

246, 247, 248, 254, 256AB2N 228, 250

Anti-aliasing PTV 131Application Specific IC (ASIC) 114-116,

146AT&T 479AA 190Automatic Test Equipment (ATE) 2, 3,6,

13, 15, 31, 39, 43, 49, 50, 52, 98,113-116, 118, 127, 138, 153, 160,168, 169, 175, 191, 202, 204, 206,209, 220-222, 249

Automatic Test Program Generation (ATPG)144

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282 Index

BBall-Grid Array 65, 129, 159, 167, 218Blind Interrogation 34, 194Boundary Register 2, 15, 21, 30, 37, 42, 229Boundary Register Cell

abstraction of 90Analog Boundary Module 226BC_0 87, 91, 264, 265BC_1 73,79, 87, 89, 91, 92, 102, 164,

176BC_2 79, 87, 92, 93, 95, 99, 176BC_3BC_4BC_5BC_6BC_7

88, 93, 9488, 94, 95

88, 95, 96, 98, 9979, 88, 96, 97, 102, 176

88, 93, 96, 97, 98, 177, 178, 264BC_99 91

74898990

bidirbidir_inbidir_outcapture datacell count 24, 79, 177clock 74, 89constant "0/1" capture 179control 23, 74, 89controlr 74, 89Digital Boundary Module 225flawed design 24general design 21hardware fault insertion 163input 74, 89internal 31,74, 89internal cell 26logical symbol 26merged cells 78observe_only 27, 39, 74, 80, 89optimizing 27output2 74, 89output3 74, 89parallel in 21, 27parallel out 21, 27reversible cell 24self-monitoring output 176shift in 22

2224232623

shift outsignal inversionsingle-cell bidirectionalthree-cell bidirectionaltwo-cell bidirectional

Boundary-Scan Description Language(BSDL) 2, 24, 34, 41, 43, 49

certifying 182

damaged by electronic mail 180180180

verificationverification test

Boundary-Scan master 190BSDL

attribute See BSDL Attribute belowautomated creation 103Boundary-Scan Register Description 72,

102Cell Description Constants 89

58commentcomponent conformance 64, 102damaged by electronic mail 60Design Warnings 77Device Package Pin Mapping 65entity 58, 61, 101extensions 100generic parameter 62grouped port identification 66, 75, 102Identifier 58IEEE version 51, 64, 68, 71initial (1990) version 51Instruction Register description 69, 102INTEST Execution Description 76

625762628575

logical portpad-to-pin mappingPHYSICAL_PIN_MAPPIN_MAPpre-defined constantsRUNBIST Execution Descriptionsafe bit 73, 113scope 52

635857

standard use statementstringstructuresubset and standard practice of VHDL 50TAP port identification 67, 102to/from synthesis systems 55type CELL_INFO 176use as test driver 52Use statements 64, 102user defined boundary cells 177

177user defined packageUser Extensions 77Version 0.0 parser 104version control 64VHDL package 58, 84VHDL package body 58, 84writing 101

BSDL AttributeBOUNDARY_LENGTH 72, 73, 75, 86,

265, 272

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BOUNDARY_REGISTER 72, 73, 78,79, 86, 91, 113, 116, 181, 265, 272

BSDL_EXTENSION 101COMPLIANCE_PATTERNS 68, 87,

265, 270COMPONENT_CONFORMANCE 64,

85, 265, 270DESIGN_WARNING 77, 87, 265, 273IDCODE_REGISTER 70, 86, 265, 271INSTRUCTION_CAPTURE

INSTRUCTION_OPCODE 69, 70, 86,265, 271

INSTRUCTION_PRIVATE 69, 70, 72,86, 265, 271

INTEST_EXECUTION 76, 86, 265,272

PIN_MAP 65, 85, 265, 269,270

PORT_GROUPING 66, 86, 156, 265,270

REGISTER_ACCESS 71, 72, 76, 86,265, 271

RUNBIST_EXECUT1ON 76, 86, 265,272

TAP_SCAN_CLOCK 67, 85, 265, 27067, 85, 265, 27067, 85, 265, 27067, 85, 265, 27067, 85, 265, 270

TAP_SCAN_INTAP_SCAN_MODETAP_SCAN_OUTTAP_SCAN_RESETUSERCODE_REGISTER 70, 86, 265,

271buffer See BSDL, logical portBypass Register 10, 20, 30, 33, 39, 52,

121, 229capture bit 20

CCapture Flip-Flop (CAP) 21, 27, 35, 89,

90, 99, 111, 150, 179Chains 31

analog busing 230194184182183192119192

brokenchain orderingconfigurationsdynamically reconfigurableextra shift stages (pad bits)integritylinkedmultidrop system 193, 195multiple simple 32

Siamese 32, 119, 182-184simple 31, 119, 182, 185, 192, 193,230testing 119

Chip-on-Board 167, 218Chip-Scale Packaging 218Complex Programmable Logic Device(CPLD) 114, 160, 161, 162, 196Compliance Enable Pins 41, 68, 75, 102,

189Compliance limit

current 201voltage 200, 246

Confounding 128Counting Sequence 123, 130, 131

DData Register 10, 11, 20

Boundary Register 2, 15, 21, 30, 37, 42,72

Bypass 10, 20, 30, 33, 39, 52, 121, 229capture data 14Device Identification 10, 12, 18, 20, 33,

34, 52, 70halt shifting 15

101514932021

mode of operationparallel hold latchesshift portionshift rippletarget registeruser-defined

Design for Testability (DFT) 167182board level

Built-in Logic Block Observer (BILBO)168

Integrated Circuit level 169168Level Sensitive Scan Design (LSSD)

system level 193Designated driver 126, 127Device Identification Register 10, 12, 18,

20, 33, 34, 52, 70, 71, 72capture pattern 20

Device Under Test (DUT) 3, 5Differential Signaling 66, 156, 251

EXTEST Paradox 252252noise rejection

Digital Boundary Module (DBM) 225, 227,242

Drive conflicts 118, 119, 125board level 187duration 125, 188

Driver"Keepers" 74asymmetrical 39, 74, 75, 78, 80

INSTRUCTION_LENGTH 69, 86, 265,271

69,70, 86,107,120,174,179, 265, 271

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284 Index

damage resistant 175Disable Result See Table 2-3disabling 188ECL Open Emitter 75

75TTL Open CollectorDual-Slope Integrator 207-209

EElectronic Design Automation (EDA)

45, 50, 16943,

Electrostatic Discharge (ESD)Emulation 7,41Extended Interconnect 223

252EXTEST Paradox

FFault

detected 3dictionary 116failure mechanism 3

3modelField-Programmable Gate Array (FPGA)

Field-Programmable IC 26, 30, 45, 68“cook” time 161blank page 30

30hard-wiredin chains 184input/output blocks (IOBs) 30parallel programming 161programming 41, 160

Fine-Pitch 6

GGallium Arsenide 175Garbage In, Garbage Out 1, 261Grandfathering 65Ground-Bounce 170

199GuardbandGuarding

analog 204, 212, 220, 222digital 39errors 206

HHardware Description Language 57

5757

VerilogVHDL

Hardware Fault Insertion 163153180

Homing sequenceHyper-Text Markup Language (HTML)

IIEEE 1149 Testability Bus Standards 46

50IEEE Standard 1076IEEE Standard 1149.1 1, 7, 16, 46, 52, 168

architecture summary 2944automation

Basic Architecture 8Benefits 43Conformance and DocumentationRequirements 49

42365340

Costscritical missionensuring complianceExtensibilitygate overhead 42, 79increased design time 43inserted delay 43,79lack of discipline 43lack of hierarchy 158Non-Invasive Mode 33

42364040444441454042

pad overheadPin-Permission Modeprivate instructionspublic instructionsreuse of testsstandardized accessSubordinationTrendsuser-defined instructionsyield loss

IEEE Standard 1149.4 46, 221Analog Boundary Modules 228

228228227228

Analog Test Access PortDigital Boundary Modulesgeneral architectureTest Bus Interface Circuit

IEEE Standard 1149.5 7, 46, 47, 183, 194,195

IEEE/ANSI Standard 1149.1Supplement A 96

IEEE/ANSI Standard 1149.1-1990 168Supplement A 2, 24, 64, 136, 177Supplement B 2

in bit See BSDL, logical portin bit_vector See BSDL, logical portIn-Circuit Test

analog 197Bed-of-Nails 5-7, 115, 122, 137, 138,

151, 152, 154, 155, 191, 197,202-206, 210-212, 218-221

Fixturing 5, 6, 114, 197, 202, 204, 220multiplexed resources 116

105, 121, 241

26,114, 160, 161, 162, 196

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The Boundary-Scan Handbook 285

overdrive damage 39, 125, 153inout See BSDL, logical portInstitute of Electrical and ElectronicsEngineers (IEEE) 2Instruction Mode 10Instruction Register 10-14,

16-19, 29, 30, 33-35, 53, 69, 70, 102,107, 108, 110, 112, 116, 118, 120,121, 158, 171, 174, 175, 180, 192,229

capture patternhalt shifting 13length 69opcodes 69parallel hold rank 16sample cell design 19shift rank 16shift ripple 13, 16shifting 13

In-System Configuration (ISC) 41, 145, 160Intel 8008 4Intel 80486DX 43, 181Intel Pentium Pro 43Interconnect

adjacent nodes 140counting sequence 123differential 224extended 224interaction test 138logical 223opens 105, 125, 131physical 224pin-level diagnostic (shorts) 141shorting radius 140shorts 105, 124, 126test length 127, 128testing 122undetected opens 133walking-bit sequence 128

JJoint Electron Device Engineering Council(JEDEC) 33Joint Test Action Group (JTAG) 1,113

KKelvin measurement 204

LLarge Scale Integration (LSI) 4Level-Sensitive Scan Design (LSSD) 41, 68,

92, 168Linear Feedback Shift Register (LFSR) 41,

141linkage See BSDL, logical portLobotomy Problem 8, 36, 178, 192Logic Simulator 3

MManufacturing Faults 222

168168168168

dead componentmissing componentopen soldersolder shortswrong component 168, 174

Matsushita Electric Industries 46Measurement errors 204Measuring impedance 200

6-wire measurement 206imaginary waveform 210reactive devices 210real waveform 210

Measuring Operational Amplifier (MOA)207Mixed Logic Families 186Mixed-Signal 217Modes of Operation

Extensible 8Non-Invasive 7, 147, 178Pin-Permission 7, 108, 178, 192

Monte Carlo simulations 212Motorola 68040 42Multi-Chip Module (MCM) 145, 157, 158,

167, 196Multidrop Systems 193Multiple IDCODEs 71

NNode Voltage Analysis 212, 213

Limited Access 215

OOperational amplifier 206-208out bit See BSDL, logical port

PP1149.2 46P1149.3 46Packaging Hierarchy 145Parallel Test Vector (PTV) 112, 127Parasitic devices 198Performance Tests 198Power

Applying 125, 176Cycling (reset) 193distribution 190Removal (safety) 176

13, 17, 69, 107, 171, 174

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286 Index

separate analog and digital 190Power/Ground Distribution 170Private Instructions 70

RReed relay 202, 204, 222

area 229off-resistance 202, 229on-resistance 202, 229switching time 229

Reference voltages 228G 228VH 228, 231VL 228, 231VTH 231

SScan-Path Linker 191Self-Monitoring Output 37Sentinel bits 121, 122Sequential Response Vector (SRV) 112, 126Sequential Test Vector (STV) 112, 126, 127,

128Serial Vector Format (SVF) 144shorting radius 140Silicon switches 229

“T” switch 258area 229bipolar 229conceptual 237crummy 230leakage 258off-resistance 229on-resistance 229parasitic coupling 258switching time 229symbols 230

Simple Interconnect 224Single Stuck-at fault model 3Source

current 200, 201, 212, 246voltage 201, 202, 204, 210, 237

STD_1149_1_1990 64, 83STD_1149_1_1993 64STD_1149_1_1994 58STEM 149_1_1999 64, 85, 89Surface-Mount Technology (SMT) 5, 6, 44,

45, 159, 167, 218, 229Synchronizing Sequence 10, 107System Logic 7, 8, 29, 33, 35-39,

42, 79, 116-118, 147

TTAP Controller 10, 12-16, 18, 20, 22, 32,

41, 108, 174, 233, 239asynchronous reset 10data column states 11,12finite state machine 10instruction column states 11, 12power-up reset 12state diagram 10, 11, 107state transitions 11synchronizing sequence 10temporary state 12, 13, 14

TAP Controller StateCAPTURE-DR 14, 15, 16, 52, 72, 109,

139, 150, 176CAPTURE-IR 13, 15, 16, 18, 70,107,

120, 174EXIT1-DR 14, 15, 110EXIT1-IR 13, 15, 18, 107EXIT2-DR 15EXIT2-IR 14, 18PAUSE-DR 15PAUSE-IR 13, 18RUN-TEST/IDLE 12, 111, 118, 141,

161SELECT-DR-SCAN 12, 171SELECT-IR-SCAN 12, 111SHIFT-DR 14, 15, 109, 141SHIFT-IR 13, 16, 18, 107TEST-LOGIC-RESET 12, 18, 57, 107,

162, 178Update-DR 164UPDATE-DR 15, 111, 171UPDATE-IR 14-18, 71, 108, 171

TAP InstructionBYPASS 12, 18, 20, 33, 34, 36, 57, 69,

71, 103, 106, 109, 121, 141, 151,158, 161-163, 175, 181, 187, 193,194, 243, 265, 268, 271

CLAMP 39, 106, 151, 161, 162, 181,247, 265, 268

EXTEST 36, 37, 39, 57, 69, 70, 71, 89,99, 103, 106, 109, 111, 112,117,146, 151, 153, 162, 176, 179, 185,244, 246, 265, 268, 273

HIGHZ 39, 76, 96, 99, 106, 146, 151,161, 162, 181, 240, 243, 247, 265,268, 272

IDCODE 12, 18, 20, 33, 34, 36, 70-72,99, 103, 106, 109, 121, 162,163,178-180, 194, 243, 265, 268, 271

INTEST 37, 38, 39, 43, 54, 74-76, 89,

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92-94, 96, 102, 106, 116-118,161-163, 174, 242, 248, 249, 250,

265, 268, 272, 273ISC_DISABLE 161, 163ISC_ENABLE 161, 162ISC_PROGRAM 161PRELOAD 35, 38, 39, 57, 70, 76, 106,

112, 118, 161, 162, 163, 164, 181,243, 265, 268

PROBE 239, 243, 247, 248, 250, 258RUNBIST 12, 38, 39, 75, 96, 99, 102,

106, 118, 119, 141, 168, 178, 181,242, 248, 265, 268, 272

SAMPLE 35, 36, 57, 70, 89, 103, 106,147-150, 181, 243, 248, 265, 268,273

USERCODE 20, 34, 70, 181, 243, 265,268, 271

user-defined 21,71, 102, 179Tape Automated Bonding (TAB) 167Target Register 15, 20, 33, 38, 57, 76, 110,

171TCK

buffered 185falling edge 11, 14-16, 171ground bounce 171level translation 187maximum clock frequency 68rising edge 10, 13-15stop state 68Test Clock 10

TDIpin placement 169shorted to TDO 120, 169Test Data In 10

TDOactively driving 15disabled 15shifting data 15Test Data Out 10

Test Access Port (TAP) 8, 29, 159, 230compatibility with 1149.4 222Test Clock (TCK) 10Test Data In (TDI) 10Test Data Out (TDO) 10Test Mode Select (TMS) 10Test Reset (TRST*) 10

Test Bus Interface Circuit (TBIC) 228, 229,231, 233-236, 245, 247, 248, 250,251, 253, 255

Test Reset (TRST*) 189

TestingAd-Hoc 1analog In-Circuit 197background system diagnostics 165Basic BIST Test Algorithm 118Basic Test Algorithm 112, 126board-level self-test 41Boundary-Scan chains 119Built-in Self-Test (BIST) 118, 141, 193chain integrity 13, 17, 18, 119, 169, 174CMOS IDDQ 10Concurrent Monitoring 150Connection 122, 136control of critical nodes 188Customized 141DC parametrics (IC) 146differential pins 251Edge Connector Functional 2, 168, 211Emulationfunctions 159fault dictionary 116hardware development support 159high frequency 222Hot Mock-Ups 2, 3hybrid digital/analog 41IC 7, 116IC BIST 118In-Circuit 4, 46, 113In-Circuit Boundary-Scan 114, 115Interaction 138Interconnect 122Interconnect Opens 131Interconnect Shorts 126Limited Access 211, 215,218,261Limited Access Node Voltage 215logic analyzer 35Mixed Digital/Analog 155Module 7Multi-chip Modules 157node voltage 213noise rejection 252Non-Digital devices 154Non-Scan ICs 151parallel impedances 203performance 198personal tester 113Printed Circuit Board 7pseudo-random patterns 141Sample mode 147self-test 12, 38Signature Analysis 41, 141, 150, 167Simulator-based Functional 4stop-on-first-fail 113, 128

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288 Index

System Level 7undetectable shorts 153unpowered analog 201unpowered shorts testing 115, 137X-Ray Laminography 129

Texas Instruments 74ABT8996 195Texas Instruments 74ACT8990 190Texas Instruments 74ACT8997 183, 191,

195Texas Instruments 74ACT8999 183, 191.

195Texas Instruments 74BCT8244 40, 42Texas Instruments 74BCT8373 174Texas Instruments 74BCT8374 58, 70, 78,

80, 174Through-Hole Pin 5TMS

buffered 185level translation 187Test Mode Select 10

Tolerancedistribution 199nominal values 199of component values 199, 204, 214

TRST*

assertion 10Test Reset 10

UUpdate Flip-Flop (UPD) 21, 27, 35-37, 39,

73, 90, 163, 176Update Flip-Flop (UPD) 111UUT See Device Under Test (DUT)

VVery Large-Scan Integration (VLSI) 42,

115, 167, 170, 171VHDL identifiers See BSDL, identifierVHSIC Hardware Description Language

(VHDL) 50Vias 7

blind 167

WWalking-bit sequence 128, 130

XX-Ray Laminography 129X-Y Coordinate Location Data 7, 140