IEEE 1149.1 JTAGBoundary Scan Standard

Shaahin HessabiDepartment of Computer EngineeringDepartment of Computer Engineering

Sharif University of TechnologyAdapted with modifications from lecture notesAdapted, with modifications, from lecture notes

prepared by the book authors

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Outline

Bed-of-nails testerd Motivation for boundary scan standard System view of boundary scan hardwareSystem view of boundary scan hardware Elementary scan cell Test Access Port (TAP) controller Test Access Port (TAP) controller Boundary scan instructions Summary Summary

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Bed-of-Nails Tester Concept

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Bed-of-Nails Tester

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Motivation for Standard Bed-of-nails printed circuit board tester gone

W t t b th id f PCB & We put components on both sides of PCB & replaced DIPs with flat packs to reduce inductance

Nails would hit components Nails would hit components

Reduced spacing between PCB wires

Nails would short the wires Nails would short the wires

PCB Tester must be replaced with built-in test delivery system -- JTAG does that

Need standard System Test Port and Bus

Integrate components from different vendors

One chip has test hardware for other chips

Test bus identical for various components

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Purpose of Standard Lets test instructions and test data be serially fed

into CUTinto CUT

Allows reading out test results

Allows RUNBIST command as an instructionAllows RUNBIST command as an instruction

Too many shifts to shift in external tests

JTAG can operate at chip PCB & system levels JTAG can operate at chip, PCB, & system levels

Allows control of tri-state signals during testing

Lets other chips collect responses from CUT Lets other chips collect responses from CUT

Lets system interconnect be tested separately from componentscomponents

Lets components be tested separately from wires

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System Test Logic

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I t ti R i t L di ith JTAGInstruction Register Loading with JTAG

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System View of Interconnect

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Boundary Scan Chain ViewBoundary Scan Chain View

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Elementary Boundary Scan Celly y

11 Normal mode:Normal mode:1.1. Normal mode: Normal mode: ModeMode--control = control = 00

2. Scan mode: Shift DR = 1First scan FF is driven by TDI, Last scan FF drives TDOFirst scan FF is driven by TDI, Last scan FF drives TDO

3. Capture mode: Shift DR = 04. Update mode: Mode-control = 1

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4. Update mode: Mode control 1

Sharif University of Technology Lecture 28: Boundary Scan

Serial Board / MCM Scan

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Parallel Board / MCM ScanParallel Board / MCM Scan

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Independent Path Board / MCM ScanIndependent Path Board / MCM Scan

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Tap Controller Signals Test Access Port (TAP) includes these signals:

Test Clock Input (TCK) -- Clock for test logic Test Clock Input (TCK) Clock for test logic

Can run at different rate from system clock

Test Mode Select (TMS) -- Switches system from Test Mode Select (TMS) Switches system from functional to test mode

Test Data Input (TDI) -- Accepts serial test data Test Data Input (TDI) Accepts serial test data and instructions -- used to shift in vectors or one of many test instructions

Test Data Output (TDO) -- Serially shifts out test results captured in boundary scan chain (or device

h i l i )ID or other internal registers)

Test Reset (TRST) -- Optional asynchronous TAP t ll t

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controller reset

Tap Controller State Diagram

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States of TAP Controller Test-Logic-Reset: normal mode

T / dl i f i l h ST Run-Test/Idle: wait for internal test such as BIST Select-DR-Scan: initiate a data-scan sequence Capture-DR: load test data in parallel Shift-DR: load test data in series Exit1-DR: finish phase-1 shifting of data Pause-DR: temporarily hold the scan operation (e.g., allow the

b l d d )bus master to reload data) Exit2-DR: finish phase-2 shifting of data Update-DR: parallel load from associated shift registersNote: Controls for IR are similar to those for DR.

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Tap Controller TimingTap Controller Timing

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TAP Controller Power Up Reset LogicTAP Controller Power-Up Reset Logic

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B d S I t tiBoundary Scan Instructions

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Basic Operationsp1. Instruction sent (serially) through TDI into instruction register.

S l d i i fi d d h i i2. Selected test circuitry configured to respond to the instruction.3. Test pattern shifted into selected data register and applied to

l i t b t t dlogic to be tested4. Test response captured into some data register5 C d hif d hif d i5. Captured response shifted out; new test pattern shifted in

simultaneously6 Steps 3 5 repeated until all test patterns are applied6. Steps 3-5 repeated until all test patterns are applied.

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Major Modes of Operationj p Non-invasive mode: standard provides resources guaranteed to

be independent of s stem logicbe independent of system logic These resources enable asynchronous communication with the outside

world (serially read in test data and instructions or serially read out test ( y yresults)

Activities are invisible to the normal IC behavior

Pin-permission modes: takes control of the IC I/O pins, thus disconnecting the system logic from the outside world. All t ti f th t i t t t l f t Allow testing of the system interconnect separately from component

testing, and vice-versa. The testing activities totally disrupt the normal IC behavior.g y p

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SAMPLE / PRELOAD Instruction-- SAMPLEPurpose:1 Get snapshot of normal chip input/output signals1. Get snapshot of normal chip input/output signals2. Put data on boundary scan chain before next instruction

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SAMPLE / PRELOAD Instruction PRELOADSAMPLE / PRELOAD Instruction -- PRELOAD

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EXTEST Instruction Purpose: Test offPurpose: Test off--chip circuits and boardchip circuits and board--level interconnectionslevel interconnections

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Execution of EXTEST Instruction

Phase 1:Shift-DR (Chip1)

Phase Phase 22::UpdateUpdate--DR DR (Chip(Chip11))CaptureCapture--DR (ChipDR (Chip22))

Phase Phase 33::ShiftShift--DR (ChipDR (Chip22))

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Execution of INTEST InstructionPurpose:

1. Shifts external test patterns onto component2. External tester shifts component responses out

Phase 1: Shift-DRPhase 1: Shift DR

Phase Phase 22: Update: Update--DRDRpp

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Execution of INTEST Instruction (cont’d)( )

Phase 3: Capture-DR

Phase Phase 44: Shift: Shift--DRDR

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RUNBIST Instruction Purpose: Allows you to issue BIST command to

component through JTAG hardwarecomponent through JTAG hardware Optional instruction Lets test logic control state of output pins Lets test logic control state of output pins

1. Can be determined by pin boundary scan cell2 Can be forced into high impedance state2. Can be forced into high impedance state

BIST result (success or failure) can be left in boundary scan cell or internal cellscan cell or internal cell Shift out through boundary scan chain

May leave chip pins in an indeterminate state (reset May leave chip pins in an indeterminate state (reset required before normal operation resumes)

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CLAMP Instruction

Purpose: Forces component output signals to be driven by p p p g yboundary-scan register

Bypasses the boundary scan chain by using the one-bit Bypass Register

Optional instruction May have to add RESET hardware to control on-chip logic

so that it does not get damaged (by shorting 0’s and 1’s onto i l b )an internal bus, etc.)

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IDCODE Instruction Purpose: Connects the component device identification

register serially between TDI and TDOregister serially between TDI and TDO In the Shift-DR TAP controller state

Allows board level test controller or external tester to read out Allows board-level test controller or external tester to read out component ID

Required whenever a JEDEC identification register is Required whenever a JEDEC identification register is included in the design JEDEC: Joint Electron Device Engineering Councilg g

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Device ID Register --JEDEC Code

MSB LSB27 12

Part11 1Manufacturer

0‘1’

31 28 31 28 V iV i

MSB LSB

PartNumber(16 bits)

ManufacturerIdentity(11 bits)

1

(1 bit)

VersionVersion((4 4 bits)bits)

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USERCODE Instruction

Purpose: Intended for user-programmable components (FPGA’s, EEPROMs, etc.) Allows external tester to determine user programming of component

S l t th d i id tifi ti i t i ll t d b t Selects the device identification register as serially connected between TDI and TDO

User-programmable ID code loaded into device identification register User programmable ID code loaded into device identification register On rising TCK edge

Required when Device ID register included on user-programmable q g p gcomponent

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HIGHZ Instruction Purpose: Puts all component output pin signals into high-

impedance stateimpedance state Control chip logic to avoid damage in this mode May have to reset component after HIGHZ runs May have to reset component after HIGHZ runs Optional instruction

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BYPASS Instruction Purpose: Bypasses scan chain with 1-bit register

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Optional / Required Instructionsp q

InstructionBYPASS

StatusM dBYPASS

CLAMPEXTEST

MandatoryOptional

MandatoryEXTESTHIGHZ

IDCODE

MandatoryOptionalOptional

INTESTRUNBIST

SAMPLE / PRELOAD

pOptionalOptional

M dSAMPLE / PRELOADUSERCODE

MandatoryOptional

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Summaryy Boundary Scan Standard has become absolutely

essential;essential; No longer possible to test printed circuit boards with

bed of nails testerbed-of-nails tester Not possible to test multi-chip modules at all without it Supports BIST external testing with ATE and Supports BIST, external testing with ATE, and

boundary scan chain reconfiguration as BIST pattern generator and response compacterg p p

Now getting widespread usage Use scanedu for practicing with JTAG conceptsUse scanedu for practicing with JTAG concepts

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