brushless dc motor flash mcu ht45fm2c - holtek...co pa e mat h output mode..... 9 ti e /counte mode...

Brushless DC Motor Flash MCU

HT45FM2C

Revision: V1.30 Date: De�e��e� 1�� 01�De�e��e� 1�� 01�

Rev. 1.30 � De�e��e� 1�� 01� Rev. 1.30 3 De�e��e� 1�� 01�

HT45FM2CBrushless DC Motor Flash MCU


Table of Contents

Features ............................................................................................................ 7CPU Featu�es ......................................................................................................................... 7Pe�iphe�al Featu�es ................................................................................................................. 7

General Description ......................................................................................... 8Block Diagram .................................................................................................. 8Pin Assignment ................................................................................................ 9Pin Description .............................................................................................. 10Absolute Maximum Ratings .......................................................................... 13D.C. Characteristics ....................................................................................... 13A.C. Characteristics ...................................................................................... 14A/D Converter Characteristics ...................................................................... 15D/A Converter Characteristics ...................................................................... 15Operational Amplifier Characteristics ......................................................... 16Comparator Electrical Characteristics ........................................................ 16Power on Reset Electrical Characteristics .................................................. 16System Architecture ...................................................................................... 17

Clo�king and Pipelining ......................................................................................................... 17P�og�a� Counte� ................................................................................................................... 18Sta�k ..................................................................................................................................... 19A�ith�eti� and Logi� Unit – ALU ........................................................................................... 19

Flash Program Memory ................................................................................. 20St�u�tu�e ................................................................................................................................ �0Spe�ial Ve�to�s ..................................................................................................................... �0Look-up Ta�le ........................................................................................................................ �0Ta�le P�og�a� Exa�ple ........................................................................................................ �1In Ci��uit P�og�a��ing ......................................................................................................... ��

RAM Data Memory ......................................................................................... 23St�u�tu�e ................................................................................................................................ �3

Special Function Register Description ........................................................ 25Indi�e�t Add�essing Registe�s – IAR0� IAR1 ......................................................................... �5Me�o�y Pointe�s – MP0� MP1 .............................................................................................. �5Bank Pointe� – BP ................................................................................................................. ��A��u�ulato� – ACC ............................................................................................................... ��P�og�a� Counte� Low Registe� – PCL .................................................................................. ��Look-up Ta�le Registe�s – TBLP� TBHP� TBLH ..................................................................... �7Status Registe� – STATUS .................................................................................................... �7

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EEPROM Data Memory .................................................................................. 30EEPROM Data Me�o�y St�u�tu�e ........................................................................................ 30EEPROM Registe�s .............................................................................................................. 30Reading Data f�o� the EEPROM ......................................................................................... 31W�iting Data to the EEPROM ................................................................................................ 3�W�ite P�ote�tion ..................................................................................................................... 3�EEPROM Inte��upt ................................................................................................................ 3�P�og�a��ing Conside�ation ................................................................................................. 3�P�og�a��ing Exa�ples ........................................................................................................ 33

Oscillator ........................................................................................................ 34Os�illato� Ove�view ............................................................................................................... 34System Clock Configurations ................................................................................................ 34Inte�nal �0MHz RC Os�illato� – HIRC ................................................................................... 35Inte�nal 3�kHz Os�illato� – LIRC ........................................................................................... 35Supple�enta�y Clo�ks .......................................................................................................... 35

Operating Modes and System Clocks ......................................................... 36Syste� Clo�ks ...................................................................................................................... 3�Syste� Ope�ation Modes ...................................................................................................... 38Cont�ol Registe� .................................................................................................................... 39Fast Wake-up ........................................................................................................................ 40Ope�ating Mode Swit�hing and Wake-up .............................................................................. 41NORMAL Mode to SLOW Mode Swit�hing ........................................................................... 41SLOW Mode to NORMAL Mode Swit�hing ........................................................................... 41Ente�ing the SLEEP Mode .................................................................................................... 43Ente�ing the IDLE0 Mode ...................................................................................................... 43Ente�ing the IDLE1 Mode ...................................................................................................... 43Stand�y Cu��ent Conside�ations ........................................................................................... 44Wake-up ................................................................................................................................ 44

Watchdog Timer ............................................................................................. 45Wat�hdog Ti�e� Clo�k Sou��e .............................................................................................. 45Wat�hdog Ti�e� Cont�ol Registe� ......................................................................................... 45Wat�hdog Ti�e� Ope�ation ................................................................................................... 4�

Reset and Initialisation .................................................................................. 47Reset Fun�tions .................................................................................................................... 47Reset Initial Conditions ......................................................................................................... 49

Input/Output Ports ......................................................................................... 53Pull-high Resisto�s ................................................................................................................ 53Po�t A Wake-up ..................................................................................................................... 54I/O Po�t Cont�ol Registe�s ..................................................................................................... 54I/O Pin St�u�tu�es .................................................................................................................. 5�P�og�a��ing Conside�ations ................................................................................................ 57

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Timer Modules – TM ...................................................................................... 58Int�odu�tion ........................................................................................................................... 58TM Ope�ation ........................................................................................................................ 58TM Clo�k Sou��e ................................................................................................................... 58TM Inte��upts ......................................................................................................................... 58TM Exte�nal Pins ................................................................................................................... 59TM Input/Output Pin Cont�ol Registe�s ................................................................................. 59P�og�a��ing Conside�ations ................................................................................................ �0

Compact Type TM – CTM .............................................................................. 61Co�pa�t TM Ope�ation ......................................................................................................... ��Co�pa�t Type TM Registe� Des��iption................................................................................ ��Co�pa�t Type TM Ope�ating Modes .................................................................................... �9Co�pa�e Mat�h Output Mode ............................................................................................... �9Ti�e�/Counte� Mode ............................................................................................................. 7�PWM Output Mode ................................................................................................................ 7�Buzze� �ont�ol ....................................................................................................................... 74

Capture Timer Module – CAPTM .................................................................. 75Captu�e Ti�e� Ove�view ....................................................................................................... 75Captu�e Ti�e� Registe� Des��iption ..................................................................................... 75Captu�e Ti�e� Ope�ation ....................................................................................................... 79

Infrared Receiver ........................................................................................... 80Fun�tional Des��iption ........................................................................................................... 80RMT Ti�ing ........................................................................................................................... 81Noise Filte� Registe�s Des��iption ......................................................................................... 81Re�ote Cont�ol Ti�e� – RMT ............................................................................................... 8�RMT Registe� Des��iption ..................................................................................................... 83

Analog to Digital Converter .......................................................................... 84A/D Ove�view ........................................................................................................................ 84A/D Conve�te� Registe� Des��iption ...................................................................................... 85A/D Conve�te� Data Registe�s – ADRL� ADRH ..................................................................... 85A/D Conve�te� Cont�ol Registe�s – ADCR0� ADCR1� ANCSR0� ANCSR1� ADDL................. 8�A/D Conve�te� Bounda�y Registe�s – ADLVDL� ADLVDH� ADHVDL� ADHVDH ......................89A/D Ope�ation ....................................................................................................................... 90A/D Input Pins ....................................................................................................................... 91Su��a�y of A/D Conve�sion Steps ....................................................................................... 91P�og�a��ing Conside�ations ................................................................................................ 9�A/D T�ansfe� Fun�tion ........................................................................................................... 9�A/D P�og�a��ing Exa�ple ................................................................................................... 93

Over-current Detection .................................................................................. 95Ove�-�u��ent Fun�tional Des��iption ..................................................................................... 95Ove�-�u��ent Registe� Des��iption ......................................................................................... 95

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Linear Hall Sensor Detection ........................................................................ 97Hall Senso� Dete�tion Fun�tion Des��iption .......................................................................... 97Linea� Hall Senso� Cont�ol Registe� Des��iption ................................................................... 98

BLDC Motor Control Circuit .......................................................................... 99Fun�tional Des��iption ........................................................................................................... 99PWM Counte� Cont�ol Ci��uit ............................................................................................. 100PWM Registe� Des��iption .................................................................................................. 101Mask Fun�tion ..................................................................................................................... 103Registe� Des��iption ............................................................................................................ 10�Othe� Fun�tions ................................................................................................................... 107Hall Senso� De�ode� ........................................................................................................... 109Hall Senso� De�ode� Registe� Des��iption ...........................................................................114Moto� P�ote�tion Fun�tion ....................................................................................................11�Moto� P�ote�tion Fun�tion Des��iption .................................................................................117Moto� Position Dete�tion Methods ...................................................................................... 1�1

DC Motor Control ......................................................................................... 122�-pin DC Moto� Cont�ol ....................................................................................................... 1��1-pin DC Moto� Cont�ol ....................................................................................................... 1�3Registe� Des��iption ............................................................................................................ 1�4

Interrupts ...................................................................................................... 125Inte��upt Registe�s ............................................................................................................... 1�5Inte��upt Ope�ation .............................................................................................................. 135Exte�nal Inte��upt 0 .............................................................................................................. 137Exte�nal Inte��upt 1 .............................................................................................................. 137Co�pa�ato� Inte��upt ........................................................................................................... 137Multi-fun�tion Inte��upt ........................................................................................................ 137A/D Conve�te� Inte��upt ....................................................................................................... 138Fault Inte��upt ...................................................................................................................... 138Pause Inte��upt .................................................................................................................... 138PWM Module Inte��upts ...................................................................................................... 138Ti�e Base Inte��upt ............................................................................................................. 139CAPTM Module Inte��upt .................................................................................................... 140TM Inte��upt ......................................................................................................................... 140RMT Module Inte��upt ......................................................................................................... 140EEPROM Inte��upt .............................................................................................................. 141LVD Inte��upt ....................................................................................................................... 141Inte��upt Wake-up Fun�tion ................................................................................................. 141P�og�a��ing Conside�ations .............................................................................................. 14�

Low Voltage Detector – LVD ....................................................................... 142LVD Registe� ....................................................................................................................... 14�LVD Ope�ation ..................................................................................................................... 143

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Application Circuits ..................................................................................... 144Hall Senso� × 3 ................................................................................................................... 144Hall Senso� × 1 ................................................................................................................... 145Non-Hall Senso� .................................................................................................................. 14�

Instruction Set .............................................................................................. 147Int�odu�tion ......................................................................................................................... 147Inst�u�tion Ti�ing ................................................................................................................ 147Moving and T�ansfe��ing Data ............................................................................................. 147A�ith�eti� Ope�ations .......................................................................................................... 147Logi�al and Rotate Ope�ation ............................................................................................. 148B�an�hes and Cont�ol T�ansfe� ........................................................................................... 148Bit Ope�ations ..................................................................................................................... 148Ta�le Read Ope�ations ....................................................................................................... 148Othe� Ope�ations ................................................................................................................. 148Inst�u�tion Set Su��a�y ..................................................................................................... 149

Instruction Definition ................................................................................... 151Package Information ................................................................................... 160

1�-pin NSOP (150�il) Outline Di�ensions ......................................................................... 1�1�8-pin SOP (300�il) Outline Di�ensions ........................................................................... 1��8-pin SSOP (150�il) Outline Di�ensions ......................................................................... 1�344-pin LQFP (10��×10��) (FP�.0��) Outline Di�ensions ........................................... 1�4

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Features

CPU Features• Operating Voltage:

♦ fSYS=32kHz ~ 20MHz: 4.5V~5.5V

• Upto0.2μsinstructioncyclewith20MHzsystemclockatVDD=5V

• Powerdownandwake-upfunctionstoreducepowerconsumption

• Twooscillators: ♦ Internal20MHzRC-HIRC ♦ Internal32kHzRC-LIRC

• Multi-modeoperation:NORMAL,SLOW,IDLEandSLEEP

• Allinstructionsexecutedinoneortwoinstructioncycles

• Tablereadinstructions

• 63powerfulinstructions

• Upto8-levelsubroutinenesting

• Bitmanipulationinstruction

Peripheral Features• FlashProgramMemory:4K×15

• RAMDataMemory:256×8

• TrueEEPROMMemory:128×8

• WatchdogTimerfunction

• Upto28bidirectionalI/Olines

• Sixpin-sharedexternalinterrupts

• SupportIRcordNoiseFilterfunction

• Four10-bitCTMsforBuzzer,RMT,up/downorleft/rightfan-head

• Single16-bitCTMforBLDCsensorlessapplication

• Single16-bitCAPTMformotorprotect

• Two8-bitRMTsforIRdecode

• Apairof10-bitPWMwithcomlementaryoutputsforBLDCapplication

• 9-channel10-bitresolutionA/Dconverter

• Time-Basefunctionforgenerationoffixedtimeinterruptsignal

• SingleoperationalAmplifierforcurrentdetect

• Twocomparatorswithinterruptfunctions

• Dual8-bitD/AConverter

• Lowvoltageresetfunction

• Lowvoltagedetectfunction

• Packagetypes:16-pinNSOP,28-pinSOP/SSOP/SKDIP,44-pinLQFP

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General DescriptionThisdeviceisFlashMemorywith8-bithighperformanceRISCarchitecturemicrocontrollerdevicewhichincludesahostoffullyintegratedspecialfeaturesspecificallydesignedforthebrushlessDCmotorapplications.

Theadvantagesoflowpowerconsumption,I/Oflexibility,MultipleandextremelyflexibleTimerModules,oscillatoroptions,multi-channelA/DandD/AConverter,PulseWidthModulationfunction,16-bitCaptureTimerModulefunction,dualcomparatorfunctions,MotorProtectModule,LinerHallSensordetection,8-bitRMTModule,TimeBasefunction,LVD,trueEEPROM,power-downandwake-upfunctions,althoughespeciallydesignedforbrushlessDCmotorapplications,theenhancedversatilityof thisdevicealsomakesitapplicableforusinginawiderangeofA/Dapplicationpossibilitiessuchassensorsignalprocessing,motordriving,industrialcontrol,consumerproducts,subsystemcontrollers,etc.

Block Diagram

8-�it RISC MCU Co�e

Inte��upt

10-�it CTMx1

WDT

LVR

4kx15Flash

�5�x8RAM

IR Noise Filte�

VDD

VSS

1�8x8 EEPROM

1�-�itCAPTMx1

BLDCMCTL

PB�/RX_IN/INT1/TP�_0

PA0/AN0/INT0APA1/AN1/INT0BPA�/AN�/INT0C

PA�/AN�/FH0_LI/TP3_0

PB3/Is

PC�/Fault/TP5_0PC0/GATPC1/GABPC�/GBTPC3/GBBPC4/GCTPC5/GCB

PB4/TCK�

PB0

PB5/TP1_0

PB�/TP0_0

PD1/FH1_SAT/TP1_1

PB1/TP�_1

PD0/FH1_SBT/TP0_1

PB7/TCK0 PA3/AN3/TCK5

10-�it CTM &8-�it RMTx�

PC7/Pause/TP5_1

PA4/AN4/FH0_SAT/TCK3PA5/AN5/FH0_SBT/TP3_1

PA7/AN7/FH0_RI/TCK1

LVD DAC x� &CMP x�

OPA

PD�/FH1_LIPD3/FH1_RI

10-�itCTM

10-�it CTM

DCMCTL1

DCMCTL0

1�-�it CTMx1

I/O Po�t

9-�h 10-�it

ADC x 1

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Pin Assignment�8�7��5�4�3��1�01918171�15

1�345�78910111�1314

HT45FM2C28 SOP-A

PA3/AN3/TCK5PA4/AN4/FH0_SAT/TCK3

PA5/AN5/FH0_SBT/TP3_1PA�/AN�/FH0_LI/TP3_0PA7/AN7/FH0_RI/TCK1

PB3/IsVSS/AVSSVDD/AVDD

PB�/RX_IN/INT1/TP�_0PB1/TP�_1

PB0PC0/GATPC1/GABPC�/GBT

PA�/AN�/INT0CPA1/AN1/INT0BPA0/AN0/INT0APC7/Pause/TP5_1PC�/Fault/TP5_0PB4/TCK�PB5/TP1_0PB�/TP0_0PB7/TCK0PD0/FH1_SAT/TP0_1PD1/FH1_SBT/TP1_1PC5/GCBPC4/GCTPC3/GBB

�8�7��5�4�3��1�01918171�15

1�345�78910111�1314

HT45FM2C28 SSOP-A

PA4/AN4/FH0_SAT/TCK3PA5/AN5/FH0_SBT/TP3_1

PA�/AN�/FH0_LI/TP3_0PA7/AN7/FH0_RI/TCK1

PB3/IsVSS/AVSSVDD/AVDD

PB�/RX_IN/INT1/TP�_0PB1/TP�_1

PB0PC0/GATPC1/GABPC�/GBTPC3/GBB

PA3/AN3/TCK5PA�/AN�/INT0CPA1/AN1/INT0BPA0/AN0/INT0APC7/Pause/TP5_1PC�/Fault/TP5_0PB4/TCK�PB5/TP1_0PB�/TP0_0PB7/TCK0PD0/FH1_SAT/TP0_1PD1/FH1_SBT/TP1_1PC5/GCBPC4/GCT

1�1514131�1110

9

1�345�78

PA4/AN4/FH0_SAT/TCK3PB3/Is

VSS/AVSSVDD/AVDD

PB�/RX_IN/INT1/TP�_0PB0

PC0/GATPC1/GAB

PA3/AN3/TCK5PA�/AN�/INT0CPA1/AN1/INT0BPA0/AN0/INT0APC5/GCBPC4/GCTPC3/GBBPC�/GBT

HT45FM2C16 NSOP-A

NCPB3/IsAVSS

VSSAVDD

VDDPB�/RX_IN/INT1/TP�_0

PB1/TP�_1NCNCNC

PD

0/FH1_SA

T/TP0_1

PD

1/FH1_SB

T/TP1_1

PD

�/FH1_LI

PD

3/FH1_R

IP

C5/G

CB

PC

4/GC

TP

C3/G

BB

PC

�/GB

TP

C1/G

AB

PC

0/GA

TP

B0

HT45FM2C44 LQFP-A

1�345�7891011

1� 131415 1�17 1819 �0 �1��3�4�5��7�8�930313�33

34353�37383940414�4344NCNCPC7/Pause/TP5_1PC�/Fault/TP5_0PB4/TCK�PB5/TP1_0PB�/TP0_0PB7/TCK0NCNCNC

NC

NC

PA0/A

N0/IN

T0APA

1/AN

1/INT0B

PA�/AN

�/INT0C

PA3/A

N3/TC

K5

PA4/A

N4/FH

0_SAT/TC

K3

PA5/A

N5/FH

0_SBT/TP

3_1P

A�/A

N�/FH

0_LI/TP3_0

PA

7/AN

7/FH0_R

I/TCK

1N

C

Note:1.Ifthepin-sharedpinfunctionshavemultipleoutputssimultaneously,itspinnamesattherightsideofthe“/”signcanbeusedforhigherpriority

2.VDD&AVDDmeanstheVDDandAVDDarethedoublebonding.

3.VSS&AVSSmeanstheVSSandAVSSarethedoublebonding.

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Pin Description

Pin Name Function OP I/T O/T Description

PA0/AN0/INT0A

PA0 PAWU PAPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led

pull-up and wake-up.

AN0 ANCSR0 AN — A/D �hannel 0

INT0A INTC0 ST — Exte�nal inte��upt input

PA1/AN1/INT0B

PA1 PAPUPAWU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led



INT0B INTC0 ST — Exte�nal inte��upt input

PA�/AN�/ INT0C

PA� PAPUPAWU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led


AN� ANCSR0 AN — A/D �hannel �

INT0C INTC0 ST — Exte�nal inte��upt input

PA3/AN3/TCK5




TCK5 — ST — TM5 input

PA4/AN4/FH0_SAT/TCK3




FH0_SAT DCMCR1 — — DC FAN Head po�t output


PA5/AN5/FH0_SBT/TP3_1




FH0_SBT DCMCR1 — — DC FAN Head po�t output

TP3_1 TMPC0 ST CMOS TM3 I/O

PA�/AN�/FH0_LI/TP3_0

PA� PAPUPAWU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led


AN� ANCSR0 AN — A/D �hannel �

FH0_LI DCMCR1 — — DC FAN Head po�t output


PA7/AN7/FH0_RI/TCK1




FH0_RI DCMCR1 — — DC FAN Head po�t output

TCK1 — ST CMOS TM1 input

PB0 PB0 PBPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led pull-up.

PB1/TP�_1PB1 PBPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led

pull-up.

TP�_1 TMPC0 — CMOS TM� I/O

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PB�/RX_IN/INT1/TP�_0

PB� PBPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led pull-up.

RX_IN INTC0 ST — IR Re�eive input pin

INT1 INTC0 ST — Exte�nal inte��upt input

TP�_0 TMPC0 ST CMOS TM� I/O

PB3/IsPB3 PBPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led

pull-up.

Is OPOMS ST — Operational amplifier input pin

PB4/TCK�PB4 PBPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led

pull-up.

TCK� — ST — TM� input

PB5/TP1_0PB5 PBPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led

pull-up.


PB�/TP0_0PB� PBPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led

pull-up.


PB7/TCK0PB7 PBPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led

pull-up.


PC0/GATPC0 PCPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led

pull-up.

GAT PWMC — CMOS Pulse Width Modulation �o�pli�enta�y output

PC1/GABPC1 PCPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led

pull-up.

GAB PWMC — CMOS Pulse Width Modulation �o�pli�enta�y output

PC�/GBTPC� PCPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led

pull-up.

GBT PWMC — CMOS Pulse Width Modulation �o�pli�enta�y output

PC3/GBBPC3 PCPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led

pull-up.

GBB PWMC — CMOS Pulse Width Modulation �o�pli�enta�y output

PC4/GCTPC4 PCPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led

pull-up.

GCT PWMC — CMOS Pulse Width Modulation �o�pli�enta�y output

PC5/GCBPC5 PCPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led

pull-up.

GCB PWMC — CMOS Pulse Width Modulation �o�pli�enta�y output

PC�/Fault/TP5_0

PC� PCPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led pull-up.

Fault MPTC1 ST — PWM Disa�le input pin. A�tive Low

TP5_0 TMPC1 ST CMOS CAPTM I/O

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PC7/Pause/TP5_1

PC7 PCPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led pull-up.

Pause MPTC1 ST — PWM Pause input pin

TP5_1 TMPC1 ST CMOS CAPTM I/O

PD0/FH1_SAT/TP0_1

PD0 PDPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led pull-up.

FH1_SAT DCMCR1 — — DC FAN Head po�t output


PD1/FH1_SBT/TP1_1

PD1 PDPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led pull-up.

FH1_SBT DCMCR1 — — DC FAN Head po�t output


PD�/FH1_LIPD� PDPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led

pull-up.

FH1_LI DCMCR1 — — DC FAN Head po�t output

PD3/FH1_RIPD3 PDPU ST CMOS Bidi�e�tional 8-�it I/O po�t. Registe� ena�led

pull-up.

FH1_RI DCMCR1 — — DC FAN Head po�t output

VSS VSS — PWR — Negative powe� supply� g�ound

AVSS AVSS — PWR —G�ound �onne�tion fo� A/D �onve�te�. The VSS and AVSS a�e the sa�e pin at �8 pin pa�kage

VDD VDD — PWR — Positive powe� supply

AVDD AVDD — PWR —Powe� supply �onne�tion fo� A/D �onve�te�. The VDD and AVDD a�e the sa�e pin at �8 pin pa�kage

Note:I/T:Inputtype; O/T:Outputtype

OP:Optionalbyconfigurationoption(CO)orregisteroption

PWR:Power; CO:Configurationoption; ST:SchmittTriggerinput

CMOS:CMOSoutput; NMOS:NMOSoutput

AN:Analoginputpin

VDDisthedevicepowersupplywhileAVDDistheADCpowersupply.

VSSisthedevicegroundpinwhileAVSSistheADCgroundpin.

AsthePinDescriptionSummarytableappliestothepackagetypewiththemostpins,notalloftheabovelistedpinsmaybepresentonpackagetypeswithsmallernumbersofpins.

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Absolute Maximum RatingsSupplyVoltage ................................................................................................VSS−0.3VtoVSS+6.0V InputVoltage ..................................................................................................VSS−0.3V to VDD+0.3V StorageTemperature ....................................................................................................-50˚Cto125˚C OperatingTemperature ..................................................................................................-40˚C to 85˚C IOH Total ....................................................................................................................................-80mA IOL Total ..................................................................................................................................... 80mA TotalPowerDissipation ........................................................................................................ 500mW

Note:Thesearestressratingsonly.Stressesexceeding therangespecifiedunder"AbsoluteMaximumRatings"maycausesubstantialdamagetothisdevice.Functionaloperationofthisdeviceatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicesreliability.

D.C. CharacteristicsTa=25˚C

Symbol ParameterTest Conditions

Min. Typ. Max. UnitVDD Conditions

VDD Ope�ating Voltage — fSYS=3� ~ �0000kHz 4.5 — 5.5 V

IDDOpe�ating Cu��ent(HIRC OSC) 5V

No load� fH=�0MHz� ADC off�WDT ena�le� Moto�_CTL off� IR_RX off

— 8 10 �A

ISTB Stand�y Cu��ent — LIRC and LVR on� LVD off� WDT ena�le — �0 100 μA

VILInput Low Voltage fo� I/O Po�ts� TCKn� INT0A� INT0B� INT0C� INT1 — — 0 — 0.3VDD V

VIHInput High Voltage fo� I/O Po�ts� TCKn� INT0A� INT0B� INT0C� INT1 — — 0.7VDD — VDD V

VLVR LVR Voltage Level — LVR Ena�le� 3.15V option -5% 3.15 +5% VVLVD LVD Voltage Level — LVDEN=1� VLVD=3.�V -5% 3.� +5% VVOL Output Low Voltage fo� I/O Po�ts 5V IOL=�0�A — — 0.5 VVOH Output High Voltage fo� I/O Po�ts 5V IOH=-7.4�A 4.5 — — VRPH Pull-high Resistan�e fo� I/O Po�ts 5V — 10 30 50 kΩ

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A.C. Characteristics Ta=25˚C



fSYS Syste� Clo�k — 4.5V~5.5V 3� — �0000 kHz

fHIRC Syste� Clo�k (HIRC) 4.5V~5.5VTa=-40˚C~85˚C -1�% �0 +4% MHzTa=-20˚C~85˚C -9% �0 +4% MHzTa=25˚C -�% �0 +�% MHz

fTIMER Ti�e� Input Pin F�equen�y — — — — 1 fSYS

tINT Inte��upt Pulse Width — — 1 — — tSYS

tLVR Low Voltage Width to Reset — — 1�0 �40 480 μstLVD Low Voltage Width to Inte��upt — — �0 45 90 μstLVDS LVDO sta�le ti�e — — 15 — — μstEERD EEPROM Read Ti�e — — — 45 90 μstEEWR EEPROM W�ite Ti�e — — — � 4 �s

tSSTSyste� Sta�t-up Ti�e� Pe�iod(Wake-up f�o� HALT) — fSYS=HIRC — 15~1� — tSYS

tRSTD

Syste� Reset Delay Ti�e(Powe� On Reset) — — �5 50 100 �s

Syste� Reset Delay Ti�e(Any Reset ex�ept Powe� On Reset)

— — 8.3 1�.7 33.3 �s

Note:1.tSYS=1/fSYS

2.TomaintaintheaccuracyoftheinternalHIRCoscillatorfrequency,a0.1μFdecouplingcapacitorshouldbeconnectedbetweenVDDandVSSandlocatedasclosetothedeviceaspossible.

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A/D Converter CharacteristicsTa=25˚C


Min. Typ. Max. UnitVDD Condition

AVDD A/D Conve�te� Ope�ating Voltage — — VLVR 5.0 5.5 V

IOP A/D Conve�te� Ope�ating Cu��ent3V — — 0.8 — �A5V — — 1 — �A

ISTBY ADC Stand�y Cu��ent — digital input no �hange — — 1 μAVREF A/D Conve�te� Refe�en�e Voltage — — � AVDD AVDD+0.1 VT�onv A/D Conve�sion Ti�e — — 14 Tad�k

DNL A/D Diffe�ential non-linea�ity — — — — ±� LSBINL A/D Integ�al non-linea�ity — — — ±� — LSBGe�� Gain E��o� — — — — ±� LSBTad�k ADCLK pe�iod — — — 0.1�� — μsT�kh ADCLK high width — — — 83 — nsT�kl ADCLK low width — — — 83 — nsTst1 Setup ti�e fo� ADON — — � — — nsTst� Setup ti�e fo� START lat�h — — � — — nsTsth START high width — — �5 — — nsTdeo� EOCB output delay — AVDD=5V — 3 — nsTdout Output delay — AVDD=5V — 3 — nsTon ADC wake up ti�e — — � — — μsToff ADC sleep ti�e — — — — 5 ns

D/A Converter CharacteristicsTa=25˚C



VDD D/A Ope�ating Cu��ent — — VLVR — 5.5 V

VDA D/A Output Voltage — 00h ~ FFh� no load 0.01 — 0.99 VDD

tDAC D/A Conve�sion Ti�e — VDD=5V� CL=10P — — � μsRO D/A Output Resistan�e — — — 10 — kΩ

8-�it R-�R D/A Conve�te�(Analog Conditon VDD=5V� CL=10P)

Model Corner TT SF FS SS FFTe�pe�atu�e �5 �5 �5 90 -40Ope�ating Ave�age Cu��ent(VDD=5V� CL=10P) 352μA 330μA 374μA 297μA 413μA

Analog Output00000000 (B) ~11111111 (B) 0~4.98V 0~4.981V 0~4.98V 0~4.98V 0~4.981V

Conve�sion Ti�e ≤2μs ≤2μs ≤2μs ≤2μs ≤2μs

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Operational Amplifier CharacteristicsTa=25˚C



IOPR1 Ope�ating Cu��ent 5V — — �50 — μAIOFF1 Powe� Down Cu��ent 5V — — — 0.1 μA

VOPOS1 Input Offset Voltage 5V Without �ali��ation� OPOF[3:0]=1000B -15 — +15 �V

VOPOS� Input Offset Voltage 5V By �ali��ation -4 — +4 �VVCM Co��on Mode Voltage Range — — VSS — VDD-1.4V VPSRR Powe� Supply Reje�tion Ratio 5V — �0 80 — dBCMRR Co��on Mode Reju�tion Ratio 5V VCM=0 ~ VDD-1.4V �0 80 — dBSR Slew Rate+� Slew Rate- 5V No load 1.8 �.5 — V/μsGBW Gain Band Width 5V RL=1MΩ, CL=100pF — �.5 — MHz

Comparator Electrical CharacteristicsTa=25˚C



IOPR0 Co�pa�ato� ope�ating voltage 5V — — �00 300 μAIOFF0 Co�pa�ato� powe� down �u��ent 5V — — — 0.1 μAVOS Co�pa�ato� input offset voltage — — -10 — +10 �V

VCMCo�pa�ato� �o��on �ode input voltage �ange — — VSS — VDD-1.4V V

tPDCo�pa�ato� �esponse ti�e(100�V ove�d�ive) — — — 4 8 μs

Power on Reset Electrical CharacteristicsTa=25˚C



VPOR VDD Sta�t Voltage to ensu�e Powe�-on Reset — — — — 100 �VRRVDD VDD Rise Rate to ensu�e Powe�-on Reset — — 0.035 — — V/�s

tPORMini�u� Ti�e fo� VDD to �e�ain at VPOR to ensu�e Powe�-on Reset — — 1 — — �s

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System ArchitectureAkeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributedtotheirinternalsystemarchitecture.TherangeofdevicestakeadvantageoftheusualfeaturesfoundwithinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance.Thepipeliningscheme is implemented insuchaway that instruction fetchingand instructionexecutionareoverlapped,hence instructionsareeffectivelyexecuted inonecycle,with theexceptionofbranchorcallinstructions.An8-bitwideALUisusedinpracticallyallinstructionsetoperations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulatorandtheALU.CertaininternalregistersareimplementedintheDataMemoryandcanbedirectlyor indirectlyaddressed.Thesimpleaddressingmethodsof theseregistersalongwithadditionalarchitectural featuresensure thataminimumofexternalcomponents is required toprovideafunctionalI/OandA/Dcontrolsystemwithmaximumreliabilityandflexibility.Thismakesthisdevicesuitableforlow-cost,high-volumeproductionforcontrollerapplications.

Clocking and PipeliningThemainsystemclock,derivedfromeitheraHIRCorLIRCoscillator issubdivided intofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounter is incrementedat thebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutiveinstructioncycles, thepipeliningstructureof themicrocontrollerensures that instructionsareeffectivelyexecuted inone instructioncycle.Theexception to thisare instructionswhere thecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwilltakeonemoreinstructioncycletoexecute.

For instructions involvingbranches,suchas jumporcall instructions, twomachinecyclesarerequired tocomplete instructionexecution.Anextracycle is requiredas theprogramtakesonecycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethebranch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintimingsensitiveapplications.

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System Clocking and Pipelining

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Instruction Fetching

Program CounterDuringprogramexecution, theProgramCounter isused tokeep trackof theaddressof thenext instruction tobeexecuted. It isautomatically incrementedbyoneeach timean instructionis executed except for instructions, such as “JMP” or “CALL” that demand a jump to anon-consecutiveProgramMemoryaddress.Onlythelower8bits,knownastheProgramCounterLowRegister,aredirectlyaddressablebytheapplicationprogram.

Whenexecuting instructions requiring jumps tonon-consecutiveaddresses suchas a jumpinstruction,asubroutinecall, interruptorreset,etc., themicrocontrollermanagesprogramcontrolbyloadingtherequiredaddressintotheProgramCounter.Forconditionalskipinstructions,oncetheconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduringthepresentinstructionexecution,isdiscardedandadummycycletakesitsplacewhilethecorrectinstructionisobtained.

Program Counter

Program Counter High Byte PCL RegisterPC11~PC8 PCL7~PCL0

Program Counter

Thelowerbyteof theProgramCounter,knownastheProgramCounterLowregisterorPCL,isavailableforprogramcontrolandisareadableandwriteableregister.Bytransferringdatadirectlyintothisregister,ashortprogramjumpcanbeexecuteddirectly;however,asonlythis lowbyteisavailableformanipulation, the jumpsare limited to thepresentpageofmemory, that is256locations.Whensuchprogramjumpsareexecuted itshouldalsobenoted thatadummycyclewillbeinserted.ManipulatingthePCLregistermaycauseprogrambranching,soanextracycleisneededtopre-fetch.

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StackThisisaspecialpartofthememorywhichisusedtosavethecontentsoftheProgramCounteronly.Thestackhaseightlevelsandisneitherpartofthedatanorpartoftheprogramspace,andisneitherreadablenorwriteable.TheactivatedlevelisindexedbytheStackPointer,andisneitherreadablenorwriteable.Atasubroutinecallor interruptacknowledgesignal, thecontentsof theProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.

Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgesignalwillbeinhibited.WhentheStackPointerisdecremented,byRETorRETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowallowingtheprogrammertousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutineinstructioncanstillbeexecutedwhichwillresultinastackoverflow.Precautionsshouldbetakentoavoidsuchcaseswhichmightcauseunpredictableprogrambranching.

Ifthestackisoverflow,thefirstProgramCountersaveinthestackwillbelost.

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Arithmetic and Logic Unit – ALUThearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmeticandlogicoperationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALUreceivesrelatedinstructioncodesandperformstherequiredarithmeticor logicaloperationsafterwhichtheresultwillbeplacedinthespecifiedregister.AstheseALUcalculationoroperationsmayresultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyupgratedtoreflectthesechanges.TheALUsupportsthefollowingfunctions:

• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAA

• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLA

• RotationRRA,RR,RRCA,RRC,RLA,RL,RLCA,RLC

• IncrementandDecrementINCA,INC,DECA,DEC

• Branchdecision,JMP,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,CALL,RET,RETI

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Flash Program MemoryTheProgramMemoryisthelocationwheretheusercodeorprogramisstored.ForthisdevicetheProgramMemoryisFlashtype,whichmeansitcanbeprogrammedandre-programmeda largenumberoftimes,allowingtheusertheconvenienceofcodemodificationonthesamedevice.Byusingtheappropriateprogrammingtools,thisFlashdeviceofferuserstheflexibilitytoconvenientlydebuganddevelop their applicationswhilealsoofferingameansof fieldprogrammingandupdating.

StructureTheProgramMemoryhasacapacityof4K×15bits.TheProgramMemoryisaddressedby theProgramCounterandalsocontainsdata,tableinformationandinterruptentries.Tabledata,whichcanbesetupinanylocationwithintheProgramMemory,isaddressedbyaseparatetablepointerregister.

Special VectorsWithintheProgramMemory,certainlocationsarereservedfortheresetandinterrupts.Thelocation000His reservedforuseby thisdevice reset forprograminitialisation.Afteradevice reset isinitiated,theprogramwilljumptothislocationandbeginexecution.

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Program Memory Structure

Look-up TableAnylocationwithintheProgramMemorycanbedefinedasalook-uptablewhereprogrammerscanstorefixeddata.Tousethelook-uptable,thetablepointermustfirstbesetupbyplacingtheaddressof thelookupdatatoberetrievedinthetablepointerregister,TBLPandTBHP.Theseregistersdefinethetotaladdressofthelook-uptable.

After settingup the tablepointer, the tabledatacanbe retrieved from theProgramMemoryusing the"TABRDC[m]"or"TABRDL[m]" instructions,respectively.Whenthe instructionisexecuted, the lowerorder tablebyte fromtheProgramMemorywillbe transferred to theuserdefinedDataMemoryregister[m]asspecifiedintheinstruction.ThehigherordertabledatabytefromtheProgramMemorywillbetransferredtotheTBLHspecialregister.Anyunusedbitsinthistransferredhigherorderbytewillbereadas“0”.

Theaccompanyingdiagramillustratestheaddressingdataflowofthelook-uptable.

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Table Program ExampleThefollowingexampleshowshowthetablepointerandtabledataisdefinedandretrievedfromthemicrocontroller.ThisexampleusesrawtabledatalocatedintheProgramMemorywhichisstoredthereusingtheORGstatement.ThevalueatthisORGstatementis"F00H"whichreferstothestartaddressofthelastpagewithinthe4KProgramMemoryofthedevice.Thetablepointer issetupheretohaveaninitialvalueof"06H".ThiswillensurethatthefirstdatareadfromthedatatablewillbeattheProgramMemoryaddress"F06H"or6locationsafterthestartofthelastpage.Notethatthevalueforthetablepointerisreferencedtothefirstaddressofthepresentpageifthe"TABRDC[m]"instructionisbeingused.ThehighbyteofthetabledatawhichinthiscaseisequaltozerowillbetransferredtotheTBLHregisterautomaticallywhenthe"TABRDC[m]"instructionisexecuted.

Because theTBLHregister isaread-onlyregisterandcannotberestored,careshouldbe takentoensure itsprotection ifboth themain routineand InterruptServiceRoutineuse table readinstructions. Ifusing the tableread instructions, theInterruptServiceRoutinesmaychange thevalueoftheTBLHandsubsequentlycauseerrorsifusedagainbythemainroutine.Asaruleitisrecommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However, insituationswheresimultaneoususecannotbeavoided,theinterruptsshouldbedisabledpriortotheexecutionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequiretwoinstructioncyclestocompletetheiroperation.

Table Read Program Exampletempreg1 db ? ; temporary register #1tempreg2 db ? ; temporary register #2 ::mov a,06h ; initialise low table pointer - note that this address ; is referencedmov tblp, a ; to the last page or present page mov a, 07h ; initialise high table pointermov tbhp, a::tabrdl tempreg1 ; transfers value in table referenced by table pointer ; data at program memory address “F06H” transferred to ; tempreg1 and TBLHdec tblp ; reduce value of table pointer by onetabrdl tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address “F05H” transferred to ; tempreg2 and TBLH in this example the data “1AH” is ; transferred to tempreg1 and data “0FH” to register tempreg2::org F00h ; sets initial address of program memorydc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh::

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In Circuit ProgrammingTheprovisionofFlashtypeProgramMemoryprovides theuserwithameansofconvenientandeasyupgradesandmodificationstotheirprogramsonthesamedevice.

Asanadditionalconvenience,Holtekhasprovidedameansofprogrammingthemicrocontrollerin-circuitusinga5-pininterface.Thisprovidesmanufacturerswiththepossibilityofmanufacturingtheircircuitboardscompletewithaprogrammedorun-programmedmicrocontroller,and thenprogrammingorupgradingtheprogramatalaterstage.Thisenablesproductmanufacturerstoeasilykeeptheirmanufacturedproductssuppliedwiththelatestprogramreleaseswithoutremovalandre-insertionofthedevice.

MCU Programming Pins FunctionPA0 Se�ial Data Input/OutputPA� Se�ial Clo�kPB0 In Ci��uit P�og�a��ing Mode SetVDD Powe� SupplyVSS G�ound

TheProgramMemoryandEEPROMdatamemorycanbothbeprogrammedseriallyin-circuitusingthis5-wireinterface.Dataisdownloadedanduploadedseriallyonasinglepinwithanadditionallinefortheclock.TwoadditionallinesarerequiredforthepowersupplyandincircuitprogrammingModeset.Thetechnicaldetailsregardingtheincircuitprogrammingof thedeviceisbeyondthescopeofthisdocumentandwillbesuppliedinsupplementaryliterature.

DuringtheprogrammingprocessthePB0pinwillbeusedtosettheincircuitprogramingModeandtakingcontrolofthePA0andPA2I/Opinsfordataandclockprogrammingpurposes.Theusermusttheretakecaretoensurethatnootheroutputsareconnectedtothesetwopins.

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Note:*mayberesistororcapacitor.Theresistanceof*mustbe greaterthan1kΩorthecapacitanceof*mustbelessthan1nF.

Programmer Pin MCU PinsICPMS PB0ICPDA PA0ICPCK PA�

Programmer and MCU Pins

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RAM Data MemoryTheDataMemoryisavolatileareaof8-bitwideRAMinternalmemoryandisthelocationwheretemporaryinformationisstored.Thecapacityofthisdeviceis256×8.

StructureDividedintotwosections,thefirstoftheseisanareaofRAM,knownastheSpecialFunctionDataMemory.Herearelocatedregisterswhicharenecessaryforcorrectoperationofthedevice.Manyoftheseregisterscanbereadfromandwrittentodirectlyunderprogramcontrol,however,someremainprotectedfromusermanipulation.

ThesecondareaofDataMemoryisknownastheGeneralPurposeDataMemory,whichisreservedforgeneralpurposeuse.Alllocationswithinthisareaarereadandwriteaccessibleunderprogramcontrol.TheSpecialPurposeDataMemoryregistersareaccessibleinallbanks,withtheexceptionof theEECregisterataddress40H,which isonlyaccessible inBank1.SwitchingbetweenthedifferentDataMemorybanksisachievedbysettingtheBankPointertothecorrectvalue.ThestartaddressoftheDataMemoryforalldevicesistheaddress00H.

00H

7FH80H

FFH

Data Memory Structure

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Special Purpose Data Memory

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Special Function Register DescriptionMostoftheSpecialFunctionRegisterdetailswillbedescribedintherelevantfunctionalsection,howeverseveralregistersrequireaseparatedescriptioninthissection.

Indirect Addressing Registers – IAR0, IAR1TheIndirectAddressingRegisters,IAR0andIAR1,althoughhavingtheirlocationsinnormalRAMregisterspace,donotactuallyphysicallyexistasnormalregisters.ThemethodofindirectaddressingforRAMdatamanipulationuses theseIndirectAddressingRegistersandMemoryPointers, incontrasttodirectmemoryaddressing,wheretheactualmemoryaddressisspecified.ActionsontheIAR0andIAR1registerswillresultinnoactualreadorwriteoperationtotheseregistersbutrathertothememorylocationspecifiedbytheircorrespondingMemoryPointers,MP0orMP1.Actingasapair,IAR0andMP0cantogetheraccessdatafromBank0whiletheIAR1andMP1registerpaircanaccessdatafromanybank.AstheIndirectAddressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressingRegistersindirectlywillreturnaresultof“00H”andwritingtotheregistersindirectlywillresultinnooperation.

Memory Pointers – MP0, MP1TwoMemoryPointers, knownasMP0andMP1areprovided.TheseMemoryPointers arephysicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormalregistersprovidingaconvenientwaywithwhichtoaddressandtrackdata.WhenanyoperationtotherelevantIndirectAddressingRegistersiscarriedout,theactualaddressthatthemicrocontrollerisdirectedto,istheaddressspecifiedbytherelatedMemoryPointer.MP0,togetherwithIndirectAddressingRegister,IAR0,areusedtoaccessdatafromBank0,whileMP1andIAR1areusedtoaccessdatafromallbanksaccordingtoBPregister.DirectAddressingcanonlybeusedwithBank0,allotherBanksmustbeaddressedindirectlyusingMP1andIAR1.

ThefollowingexampleshowshowtoclearasectionoffourDataMemorylocationsalreadydefinedaslocationsadres1toadres4.

Indirect Addressing Program Exampledata .section dataadres1 db ?adres2 db ?adres3 db ?adres4 db ?block db ?code .section at 0 codeorg 00hstart: mov a,04h ; setup size of block mov block,a mova,offsetadres1 ;AccumulatorloadedwithfirstRAMaddress movmp0,a ;setupmemorypointerwithfirstRAMaddressloop: clrIAR0 ;clearthedataataddressdefinedbyMP0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loopcontinue:

Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecificRAMaddresses.

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Bank Pointer – BPTheDataMemoryisdividedintotwobanks.SelectingtheDataMemoryareaisachievedusingtheBankPointer.Bit0oftheBankPointerisusedtoselectDataMemoryBanks0or1.

TheDataMemoryis initialised toBank0afterareset,exceptforaWDTtime-outreset in thePowerDownMode,inwhichcase,theDataMemorybankremainsunaffected.DirectlyaddressingtheDataMemorywillalways result inBank0beingaccessed irrespectiveof thevalueof theBankPointer.Accessingdatafrombanksother thanBank0mustbeimplementedusingIndirectaddressing.

BP Register

Bit 7 6 5 4 3 2 1 0Na�e — — — — — — — DMBP0R/W — — — — — — — R/WPOR — — — — — — — 0

Bit7~1 Unimplemented,readas“0”Bit 0 DMBP0:SelectDataMemoryBanks

0: Bank 01:Bank1

Accumulator – ACCTheAccumulator iscentral to theoperationofanymicrocontrollerand isclosely relatedwithoperationscarriedoutby theALU.TheAccumulator is theplacewhereall intermediateresultsfromtheALUarestored.Without theAccumulator itwouldbenecessary towrite theresultofeachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc., totheDataMemoryresultinginhigherprogrammingandtimingoverheads.Data transferoperationsusually involvethetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetweenoneuserdefinedregisterandanother, it isnecessary todo thisbypassingthedata throughtheAccumulatorasnodirecttransferbetweentworegistersispermitted.

Program Counter Low Register – PCLToprovideadditionalprogramcontrolfunctions, the lowbyteof theProgramCounter ismadeaccessibletoprogrammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.Bymanipulatingthisregister,directjumpstootherprogramlocationsareeasilyimplemented.LoadingavaluedirectlyintothisPCLregisterwillcauseajumptothespecifiedProgramMemorylocation,however,astheregisterisonly8-bitwide,onlyjumpswithinthecurrentProgramMemorypagearepermitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.

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Look-up Table Registers – TBLP, TBHP, TBLHThesethreespecialfunctionregistersareusedtocontroloperationof thelook-uptablewhichisstoredintheProgramMemory.TBLPandTBHParethetablepointerandindicates thelocationwhere the tabledata is located.Theirvaluemustbesetupbeforeany tablereadcommandsareexecuted.Theirvaluecanbechanged,forexampleusingthe“INC”or“DEC”instructions,allowingforeasytabledatapointingandreading.TBLHisthelocationwherethehighorderbyteofthetabledataisstoredafteratablereaddatainstructionhasbeenexecuted.Notethatthelowerordertabledatabyteistransferredtoauserdefinedlocation.

Status Register – STATUSThis8-bitregistercontainsthezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Thesearithmetic/logicaloperationandsystemmanagementflagsareusedtorecordthestatusandoperationofthemicrocontroller.

WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddition,operationsrelatedtothestatusregistermaygivedifferentresultsduetothedifferentinstructionoperations.TheTOflagcanbeaffectedonlybyasystempower-up,aWDTtime-outorbyexecutingthe"CLRWDT"or"HALT"instruction.ThePDFflagisaffectedonlybyexecutingthe"HALT"or"CLRWDT"instructionorduringasystempower-up.

TheZ,OV,ACandCflagsgenerallyreflectthestatusofthelatestoperations.

• Cissetifanoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.

• ACissetifanoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.

• Zissetiftheresultofanarithmeticorlogicaloperationiszero;otherwiseZiscleared.

• OVissetifanoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.

• PDFisclearedbyasystempower-uporexecutingthe“CLRWDT”instruction.PDFissetbyexecutingthe“HALT”instruction.

• TOisclearedbyasystempower-uporexecutingthe“CLRWDT”or“HALT”instruction.TOissetbyaWDTtime-out.

Inaddition,onenteringaninterruptsequenceorexecutingasubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.

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STATUS Register

Bit 7 6 5 4 3 2 1 0Na�e — — TO PDF OV Z AC CR/W — — R R R/W R/W R/W R/WPOR — — 0 0 x x x x

"x" unknownBit7,6 Unimplemented,readas“0”Bit 5 TO:WatchdogTime-Outflag

0:Afterpoweruporexecutingthe“CLRWDT”or“HALT”instruction1:Awatchdogtime-outoccurred.

Bit 4 PDF:Powerdownflag0:Afterpoweruporexecutingthe“CLRWDT”instruction1:Byexecutingthe“HALT”instruction

Bit 3 OV:Overflowflag0:Nooverflow1:Anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbitorviceversa.

Bit 2 Z:Zeroflag0:Theresultofanarithmeticorlogicaloperationisnotzero1:Theresultofanarithmeticorlogicaloperationiszero

Bit1 AC:Auxiliaryflag0:Noauxiliarycarry1:Anoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction

Bit 0 C:Carryflag0:Nocarry-out1:Anoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation

Cisalsoaffectedbyarotatethroughcarryinstruction.

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System Control Register – CTRL

Bit 7 6 5 4 3 2 1 0Na�e FSYSON — — — — LVRF LRF WRFR/W R/W — — — — R/W R/W R/WPOR 0 — — — — × 0 0

" x" unknownBit 7 FSYSON: fSYSControlinIDLEMode

0:Disable1:Enable

Bit6~3 Unimplemented,readas"0"Bit 2 LVRF:LVRfunctionresetflag

0:Notoccurred1:Occurred

Thisbitcanbeclearedto“0”,butcannotbesetto“1”.Bit1 LRF:LVRControlregistersoftwareresetflag


Thisbitcanbeclearedto“0”,butcannotbesetto“1”.Bit 0 WRF:WDTControlregistersoftwareresetflag


Thisbitcanbeclearedto“0”,butcannotbesetto“1”.

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EEPROM Data MemoryThedevicecontainsanareaof internalEEPROMDataMemory.EEPROM,whichstands forElectricallyErasableProgrammableReadOnlyMemory, isby itsnatureanon-volatile formof re-programmablememory,withdata retentionevenwhen itspowersupply is removed.Byincorporating thiskindofdatamemory,awholenewhostofapplicationpossibilitiesaremadeavailabletothedesigner.TheavailabilityofEEPROMstorageallowsinformationsuchasproductidentificationnumbers,calibrationvalues,specificuserdata,systemsetupdataorotherproductinformationtobestoreddirectlywithin theproductmicrocontroller.TheprocessofreadingandwritingdatatotheEEPROMmemoryhasbeenreducedtoaverytrivialaffair.

EEPROM Data Memory StructureTheEEPROMDataMemorycapacityis128×8bits.UnliketheProgramMemoryandRAMDataMemory,theEEPROMDataMemoryisnotdirectlymappedintomemoryspaceandisthereforenotdirectlyaddressableinthesamewayastheothertypesofmemory.ReadandWriteoperationstotheEEPROMarecarriedoutinsinglebyteoperationsusinganaddressanddataregisterinBank0andasinglecontrolregisterinBank1.

EEPROM RegistersThreeregisterscontroltheoveralloperationoftheinternalEEPROMDataMemory.Thesearetheaddressregister,EEA,thedataregister,EEDandasinglecontrolregister,EEC.AsboththeEEAandEEDregistersarelocatedinBank0,theycanbedirectlyaccessedinthesamewasasanyotherSpecialFunctionRegister.TheEECregisterhowever,beinglocatedinBank1,cannotbeaddresseddirectlyandcanonlybereadfromorwritten to indirectlyusing theMP1MemoryPointerandIndirectAddressingRegister,IAR1.BecausetheEECcontrolregisterislocatedataddress40HinBank1,theMP1MemoryPointermustfirstbesettothevalue40HandtheBankPointerregister,BP,settothevalue,01H,beforeanyoperationsontheEECregisterareexecuted.

EEPROM Register List

NameBit

7 6 5 4 3 2 1 0EEA — D� D5 D4 D3 D� D1 D0EED D7 D� D5 D4 D3 D� D1 D0EEC — — — — WREN WR RDEN RD

EEA Register

Bit 7 6 5 4 3 2 1 0Na�e — D� D5 D4 D3 D� D1 D0R/W — R/W R/W R/W R/W R/W R/W R/WPOR — x x x x x x x

“x” unknownBit7 Unimplemented,readas“0”Bit6~0 DataEEPROMaddress

DataEEPROMaddressbit6~bit0

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EEC Register

Bit 7 6 5 4 3 2 1 0Na�e — — — — WREN WR RDEN RDR/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Undefined,readas“0”Bit 3 WREN:DataEEPROMWriteEnable

0:Disable1:Enable

This is theDataEEPROMWriteEnableBitwhichmustbesethighbeforeDataEEPROMwriteoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMwriteoperations.

Bit 2 WR:EEPROMWriteControl0:Writecyclehasfinished1:Activateawritecycle

This is theDataEEPROMWriteControlBitandwhensethighbytheapplicationprogramwillactivateawritecycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthewritecyclehasfinished.SettingthisbithighwillhavenoeffectiftheWRENhasnotfirstbeensethigh.

Bit 1 RDEN:DataEEPROMReadEnable0: Disable1:Enable

This is theDataEEPROMReadEnableBitwhichmustbesethighbeforeDataEEPROMread operationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMreadoperations.

Bit 0 RD:EEPROMReadControl0:Readcyclehasfinished1:Activateareadcycle

This is theDataEEPROMReadControlBitandwhensethighbytheapplicationprogramwill activateareadcycle.Thisbitwillbeautomaticallyresettozerobythehardwareaftertheread cyclehasfinished.SettingthisbithighwillhavenoeffectiftheRDENhasnotfirstbeenset high.

Note:TheWREN,WR,RDENandRDcannotbesetto“1”atthesametimeinoneinstruction.TheWRandRDcannotbesetto“1”atthesametime.

Reading Data from the EEPROMToreaddatafromtheEEPROM,thereadenablebit,RDEN,intheEECregistermustfirstbesethightoenablethereadfunction.TheEEPROMaddressofthedatatobereadmustthenbeplacedintheEEAregister.IftheRDbitintheEECregisterisnowsethigh,areadcyclewillbeinitiated.SettingtheRDbithighwillnotinitiateareadoperationif theRDENbithasnotbeenset.Whenthereadcycleterminates,theRDbitwillbeautomaticallyclearedtozero,afterwhichthedatacanbereadfromtheEEDregister.ThedatawillremainintheEEDregisteruntilanotherreadorwriteoperationisexecuted.Theapplicationprogramcanpoll theRDbit todeterminewhenthedataisvalidforreading.

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Writing Data to the EEPROMTowritedatatotheEEPROM,thewriteenablebit,WREN,intheEECregistermustfirstbesethigh toenable thewritefunction.TheEEPROMaddressof thedata tobewrittenmust thenbeplacedintheEEAregisterandthedataplacedintheEEDregister.IftheWRbitintheEECregisterisnowsethigh,aninternalwritecyclewillthenbeinitiated.SettingtheWRbithighwillnotinitiateawritecycleiftheWRENbithasnotbeenset.AstheEEPROMwritecycleiscontrolledusinganinternaltimerwhoseoperationisasynchronoustomicrocontrollersystemclock,acertaintimewillelapsebeforethedatawillhavebeenwrittenintotheEEPROM.DetectingwhenthewritecyclehasfinishedcanbeimplementedeitherbypollingtheWRbitintheEECregisterorbyusingtheEEPROMinterrupt.Whenthewritecycleterminates, theWRbitwillbeautomaticallyclearedtozerobythemicrocontroller,informingtheuserthatthedatahasbeenwrittentotheEEPROM.TheapplicationprogramcanthereforepolltheWRbittodeterminewhenthewritecyclehasended.

Write ProtectionProtectionagainst inadvertentwriteoperation isprovided inseveralways.After thedevice ispowered-on theWriteEnablebit in thecontrol registerwillbeclearedpreventinganywriteoperations.Alsoatpower-ontheBankPointer,BP,willbereset tozero,whichmeansthatDataMemoryBank0willbeselected.AstheEEPROMcontrolregisterislocatedinBank1,thisaddsafurthermeasureofprotectionagainstspuriouswriteoperations.Duringnormalprogramoperation,ensuringthattheWriteEnablebitinthecontrolregisterisclearedwillsafeguardagainstincorrectwriteoperations.

EEPROM InterruptTheEEPROMwriteorreadinterruptisgeneratedwhenanEEPROMwriteorreadcyclehasended.TheEEPROMinterruptmust firstbeenabledbysetting theEPWEbit in therelevant interruptregister.Howeveras theEEPROMiscontainedwithinaMulti-functionInterrupt, theassociatedmulti-function interruptenablebitmustalsobeset.WhenanEEPROMwritecycleends, theEPWFrequestflaganditsassociatedmulti-functioninterruptrequestflagwillbothbeset.If theglobal,EEPROMandMulti-function interruptsareenabledand thestack isnot full,a jumptotheassociatedMulti-functionInterruptvectorwill takeplace.WhentheinterruptisservicedonlytheMulti-functioninterruptflagwillbeautomaticallyreset, theEEPROMinterruptflagmustbemanuallyresetbytheapplicationprogram.MoredetailscanbeobtainedintheInterruptsection.

Programming ConsiderationCaremustbe taken thatdata isnot inadvertentlywritten to theEEPROM.ProtectioncanbeenhancedbyensuringthattheWriteEnablebitisnormallyclearedtozerowhennotwriting.AlsotheBankPointercouldbenormallyclearedtozeroasthiswouldinhibitaccesstoBank1wheretheEEPROMcontrolregisterexist.Althoughcertainlynotnecessary,considerationmightbegivenintheapplicationprogramtothecheckingofthevalidityofnewwritedatabyasimplereadbackprocess.

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Programming Examples

Reading data from the EEPROM – polling methodMOV A,EEPROM_ADRES ;userdefinedaddressMOV EEA,AMOV A,040H ;setupmemorypointerMP1MOV MP1,A ;MP1pointstoEECregisterMOV A,01H ;setupBankPointerMOV BP,ASET IAR1.1 ;setRDENbit,enablereadoperationsSET IAR1.0 ;startReadCycle-setRDbitBACK:SZ IAR1.0 ;checkforreadcycleendJMP BACKCLR IAR1 ;disableEEPROMread/writeCLR BPMOV A,EEDATA ;movereaddatatoregisterMOV READ_DATA,A

Writing data from the EEPROM – polling methodMOV A,EEPROM_ADRES ;userdefinedaddressMOV EEA,AMOV A,EEPROM_DATA ;userdefineddataMOV EED,AMOV A,040H ;setupmemorypointerMP1MOV MP1,A ;MP1pointstoEECregisterMOV A,01H ;setupBankPointerMOV BP,ASET IAR1.3 ;setWRENbit,enablewriteoperationsSET IAR1.2 ;startWriteCycle-setWRbitBACK:SZ IAR1.2 ;checkforwritecycleendJMP BACKCLR IAR1 ;disableEEPROMread/writeCLR BP

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OscillatorVariousoscillatoroptionsoffer theuserawide rangeof functionsaccording to theirvariousapplication requirements.The flexible featuresof theoscillator functionsensure that thebestoptimisationcanbeachievedintermsofspeedandpowersaving.Oscillatorselectionsandoperationareselectedthroughacombinationofconfigurationoptionsandregisters.

Oscillator OverviewInadditiontobeingthesourceofthemainsystemclocktheoscillatorsalsoprovideclocksourcesfortheWatchdogTimerandTimeBaseInterrupt.Fullyintegratedinternaloscillators,requiringnoexternalcomponents,areprovidedtoformawiderangeofbothfastandslowsystemoscillators.Thehigherfrequencyoscillatorprovideshigherperformancebutcarrywithit thedisadvantageofhigherpowerrequirements,whiletheoppositeisofcoursetrueforthelowerfrequencyoscillators.Withthecapabilityofdynamicallyswitchingbetweenfastandslowsystemclock,thisdevicehavetheflexibility tooptimize theperformance/powerratio,afeatureespecially important inpowersensitiveportableapplications.

Type Name Freq.Inte�nal High Speed RC HIRC �0MHzInte�nal Low Speed RC LIRC 3�kHz

Oscillator Types

System Clock ConfigurationsThereare twomethodsofgeneratingthesystemclock,ahighspeedoscillatoranda lowspeedoscillator.Thehighspeedoscillatoristheinternal20MHzRCoscillator.Thelowspeedoscillatoristheinternal32kHzRCoscillator.SelectingwhethertheloworhighspeedoscillatorisusedasthesystemoscillatorisimplementedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterandasthesystemclockcanbedynamicallyselected.

HIRC

LIRC

High SpeedOscillation

Low SpeedOscillation

fH

fH/64

fH/32

fH/16

fH/8

fH/4

fH/2

6-stage Prescaler

fL

fSUB

fSYS

HLCLK, CKS2~CKS0 bits

System Clock Configurations

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Internal 20MHz RC Oscillator – HIRCTheinternalRCoscillatorisafullyintegratedsystemoscillatorrequiringnoexternalcomponents.The internalRCoscillatorhas a fixed frequenciesof20MHz.Device trimmingduring themanufacturingprocessandtheinclusionof internalfrequencycompensationcircuitsareusedtoensurethat theinfluenceof thepowersupplyvoltage, temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresult,atapowersupplyof5Vandatatemperatureof25˚Cdegrees,thefixedoscillationfrequencyof20MHzwillhaveatolerancewithin2%.

Internal 32kHz Oscillator – LIRCTheInternal32kHzSystemOscillatorisalowfrequencyoscillatorchoice.It isafullyintegratedRCoscillatorwitha typicalfrequencyof32kHzat5V,requiringnoexternalcomponentsfor itsimplementation.Devicetrimmingduringthemanufacturingprocessandtheinclusionof internalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationson theoscillationfrequencyareminimised.Asaresult,atapowersupplyof5Vandatatemperatureof25˚Cdegrees,thefixedoscillationfrequencyof32kHzwillhaveatolerancewithin10%.

Supplementary ClocksThelowspeedoscillator,inadditiontoprovidingasystemclocksourcearealsousedtoprovideaclocksourcetootherdevicefunctions.ThesearetheWatchdogTimerandtheTimeBaseInterrupt.

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Operating Modes and System ClocksPresentdayapplicationsrequirethat theirmicrocontrollershavehighperformancebutoftenstilldemandthattheyconsumeaslittlepoweraspossible,conflictingrequirementsthatareespeciallytrueinbatterypoweredportableapplications.Thefastclocksrequiredforhighperformancewillbytheirnatureincreasecurrentconsumptionandofcourseviceversa,lowerspeedclocksreducecurrentconsumption.AsHoltekhasprovided thisdevicewithbothhighand lowspeedclocksourcesandthemeanstoswitchbetweenthemdynamically,theusercanoptimisetheoperationoftheirmicrocontrollertoachievethebestperformance/powerratio.

System ClocksThedevicehasmanydifferentclocksourcesforboththeCPUandperipheralfunctionoperation.Byprovidingtheuserwithawiderangeofclockoptionsusingconfigurationoptionsandregisterprogramming,aclocksystemcanbeconfiguredtoobtainmaximumapplicationperformance.

Themainsystemclock,cancomefromeitherahighfrequency,fH,orlowfrequency,fL,source,andisselectedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregister.ThehighspeedsystemclockcanbesourcedfromHIRCoscillator.ThelowspeedsystemclocksourcecanbesourcedfrominternalclockfL. If fLisselectedthenitcanbesourcedbytheLIRCoscillator.Theotherchoice,whichisadividedversionofthehighspeedsystemoscillatorhasarangeoffH/2~fH/64.

Therearetwoadditionalinternalclocksfor theperipheralcircuits, thesubstituteclock,fSUB,andtheTimeBaseclock,fTBC.EachoftheseinternalclocksissourcedbytheLIRCoscillator.ThefSUB clockisusedtoprovideasubstituteclockforthemicrocontrollerjustafterawake-uphasoccurredtoenablefasterwake-uptimes.

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System Clock Configurations

Note:WhenthesystemclocksourcefSYSisswitchedtofLfromfH,thehighspeedoscillationwillstoptoconservethepower.ThusthereisnofH~fH/64forperipheralcircuittouse.

ThefSisusedastheclocksourcefortheWatchdogtimer.TogetherwithfSYS/4,thefTBCclockisalsousedasasourcefortheTimeBaseinterruptfunctionandfortheTMs.

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System Operation ModesThere are fivedifferentmodesofoperation for themicrocontroller, eachonewith its ownspecial characteristics andwhichcanbe chosenaccording to the specificperformanceandpowerrequirementsof theapplication.Thereare twomodesallowingnormaloperationof themicrocontroller, theNORMALModeandSLOWMode.Theremainingthreemodes, theSLEEP,IDLE0andIDLE1ModeareusedwhenthemicrocontrollerCPUisswitchedofftoconservepower.

Operation Mode

Description

CPU fSYS fSUB fS fTBC

NORMAL Mode On fH~fH/�4 On On OnSLOW Mode On fL On On OnIDLE0 Mode Off Off On On OnIDLE1 Mode Off On On On OnSLEEP Mode Off Off On On On

• NORMALModeAsthenamesuggeststhisisoneofthemainoperatingmodeswherethemicrocontrollerhasallofitsfunctionsoperationalandwherethesystemclockisprovidedbythehighspeedoscillator.ThismodeoperatesallowingthemicrocontrollertooperatenormallywithaclocksourcewillcomefromHIRCoscillator.Thehighspeedoscillatorwillhoweverfirstbedividedbyaratiorangingfrom1to64,theactualratiobeingselectedbytheCKS2~CKS0andHLCLKbitsintheSMODregister.Althoughahighspeedoscillatorisused,runningthemicrocontrolleratadividedclockratioreducestheoperatingcurrent.

• SLOWModeThisisalsoamodewherethemicrocontrolleroperatesnormallyalthoughnowwithaslowerspeedclocksource.Theclocksourceusedwillbefromthelowspeedoscillator,LIRC.Runningthemicrocontroller in thismodeallows it torunwithmuchloweroperatingcurrents. In theSLOWMode,thefHisoff.

• SLEEPModeTheSLEEPModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterislow.IntheSLEEPModetheCPUwillbestopped.

• IDLE0ModeTheIDLE0ModeisenteredwhenaHALTinstruction isexecutedandwhentheIDLENbitintheSMODregister ishighandtheFSYSONbit intheCTRLregister is low.IntheIDLE0ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutsomeperipheralfunctionswillremainoperationalsuchastheWatchdogTimerandTMs.IntheIDLE0Mode,thesystemoscillatorwillbestopped.IntheIDLE0ModetheWatchdogTimerclock,fS,willbealwayson.

• IDLE1ModeTheIDLE1ModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheCTRLregisterishigh.IntheIDLE1ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutmaycontinuetoprovideaclocksourcetokeepsomeperipheralfunctionsoperationalsuchastheWatchdogTimerandTMs.IntheIDLE1Mode,thesystemoscillatorwillcontinuetorun,andthissystemoscillatormaybehighspeedorlowspeedsystemoscillator.IntheIDLE1ModetheWatchdogTimerclock,fS,willbe on.

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Control RegisterAsingleregister,SMOD,isusedforoverallcontroloftheinternalclockswithinthisdevice.

SMOD Register

Bit 7 6 5 4 3 2 1 0Na�e CKS� CKS1 CKS0 FSTEN LTO HTO IDLEN HLCLKR/W R/W R/W R/W R/W R R R/W R/WPOR 0 0 0 0 0 0 1 1

Bit 7~5 CKS2~CKS0:ThesystemclockselectionwhenHLCLKis“0”000: fL(fLIRC)001:fL(fLIRC)010:fH/64011:fH/32100:fH/16101:fH/8110:fH/4111:fH/2

Thesethreebitsareusedtoselectwhichclockisusedasthesystemclocksource.Inadditiontothesystemclocksource,whichcanbetheLIRC,adividedversionofthehighspeedsystemoscillatorcanalsobechosenasthesystemclocksource.

Bit 4 FSTEN:FastWake-upControl0:Disable1:Enable

This is theFastWake-upControlbitwhichdetermines if the fSUBclocksource isinitiallyusedafterthisdevicewakeup.Whenthebitishigh,thefSUBclocksourcecanbeusedasatemporarysystemclocktoprovideafasterwakeuptimeasthefSUBclockisavailable.

Bit 3 LTO:Lowspeedsystemoscillatorreadyflag0:Notready1:Ready

Thisisthelowspeedsystemoscillatorreadyflagwhichindicateswhenthelowspeedsystemoscillator isstableafterpoweronresetorawake-uphasoccurred.Theflagwillchangetoahighlevelafter1~2clockcyclesiftheLIRCoscillatorisused.

Bit 2 HTO:Highspeedsystemoscillatorreadyflag0:Notready1:Ready

Thisisthehighspeedsystemoscillatorreadyflagwhichindicateswhenthehighspeedsystemoscillatorisstable.Thisflagisclearedto“0”byhardwarewhenthisdeviceispoweredonandthenchangestoahighlevelafterthehighspeedsystemoscillatorisstable.Thereforethisflagwillalwaysbereadas“1”bytheapplicationprogramafterdevicepower-on.TheflagwillbelowwhenintheSLEEPorIDLE0Modebutafterawake-uphasoccurred,theflagwillchangetoahighlevelafter15~16clockcyclesiftheHIRCoscillatorisused.

Bit1 IDLEN:IDLEModecontrol0:Disable1:Enable

This is theIDLEModeControlbitanddetermineswhathappenswhentheHALTinstructionisexecuted.If thisbit ishigh,whenaHALTinstructionisexecutedthisdevicewillenter theIDLEMode. In theIDLE1Mode theCPUwillstoprunningbut thesystemclockwillcontinue tokeep theperipheral functionsoperational, ifFSYSONbitishigh.IfFSYSONbitislow,theCPUandthesystemclockwillallstopinIDLE0Mode.IfthebitislowthisdevicewillentertheSLEEPModewhenaHALTinstructionisexecuted.

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Bit 0 HLCLK:Systemclockselection0: fH/2~fH/64orfL1:fH

Thisbit isusedtoselect if thefHclockor thefH/2~fH/64orfLclockisusedas thesystemclock.When thebit ishigh the fH clockwillbe selectedand if low thefH/2~fH/64orfLclockwillbeselected.WhensystemclockswitchesfromthefHclocktothefLclockandthefHclockwillbeautomaticallyswitchedofftoconservepower.

Fast Wake-upTominimisepowerconsumptionthisdevicecanentertheSLEEPorIDLE0Mode,wherethesystemclocksourcetothisdevicewillbestopped.Howeverwhenthisdeviceiswokenupagain,itcantakeaconsiderabletimefortheoriginalsystemoscillatortorestart,stabiliseandallownormaloperationtoresume.ToensurethedeviceisupandrunningasfastaspossibleaFastWake-upfunctionisprovided,whichallowsfSUB,namelytheLIRCoscillator,toactasatemporaryclocktofirstdrivethesystemuntiltheoriginalsystemoscillatorhasstabilised.AstheclocksourcefortheFastWake-upfunctionisfSUB,theFastWake-upfunctionisonlyavailableintheSLEEPandIDLE0modes.TheFastWake-upenable/disablefunctioniscontrolledusingtheFSTENbitintheSMODregister.

If theHIRCoscillatororLIRCoscillator isusedasthesystemoscillator thenitwill take15~16clockcyclesof theHIRCor1~2cyclesof theLIRCtowakeupthesystemfromtheSLEEPorIDLE0Mode.TheFastWake-upbit,FSTENwillhavenoeffectinthesecases.

System Oscillator

FSTEN Bit

Wake-up Time (SLEEP Mode)

Wake-up Time (IDLE0 Mode)

Wake-up Time (IDLE1 Mode)

HIRC x 15~1� HIRC �y�les 1~� HIRC �y�lesLIRC x 1~� LIRC �y�les 1~� LIRC �y�les

Wake-Up Times

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Rev. 1.30 40 De�e��e� 1�� 01� Rev. 1.30 41 De�e��e� 1�� 01�



Operating Mode Switching and Wake-upThisdevicecanswitchbetweenoperatingmodesdynamicallyallowingtheusertoselect thebestperformance/powerratiofor thepresent taskinhand.Inthiswaymicrocontrolleroperationsthatdonotrequirehighperformancecanbeexecutedusingslowerclocksthusrequiringlessoperatingcurrentandprolongingbatterylifeinportableapplications.

Insimple terms,ModeSwitchingbetween theNORMALModeandSLOWMode isexecutedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterwhileModeSwitchingfromtheNORMAL/SLOWModestotheSLEEP/IDLEModesisexecutedviatheHALTinstruction.WhenaHALTinstructionisexecuted,whetherthisdeviceentertheIDLEModeortheSLEEPModeisdeterminedbytheconditionof theIDLENbit in theSMODregisterandFSYSONintheCTRLregister.

WhentheHLCLKbitswitchestoalowlevel,whichimpliesthatclocksourceisswitchedfromthehighspeedclocksource,fH,totheclocksource,fH/2~fH/64orfL.IftheclockisfromthefL,thehighspeedclocksourcewillstoprunningtoconservepower.WhenthishappensitmustbenotedthatthefH/16andfH/64internalclocksourceswillalsostoprunning,whichmayaffecttheoperationofotherinternalfunctionssuchastheTMs.Theaccompanyingflowchartshowswhathappenswhenthisdevicemovebetweenthevariousoperatingmodes.

NORMAL Mode to SLOW Mode SwitchingWhenrunningintheNORMALMode,whichusesthehighspeedsystemoscillator,andthereforeconsumesmorepower,thesystemclockcanswitchtorunintheSLOWModebysettheHLCLKbitto“0”andsettheCKS2~CKS0bitsto“000”or“001”intheSMODregister.Thiswillthenusethelowspeedsystemoscillatorwhichwillconsumelesspower.Usersmaydecidetodothisforcertainoperationswhichdonotrequirehighperformanceandcansubsequentlyreducepowerconsumption.

TheSLOWModeissourcedfromtheLIRCoscillatorandthereforerequiresthisoscillator tobestablebeforefullmodeswitchingoccurs.ThisismonitoredusingtheLTObitintheSMODregister.

SLOW Mode to NORMAL Mode SwitchingInSLOWMode thesystemuses theLIRClowspeedsystemoscillator.Toswitchback to theNORMALMode,wherethehighspeedsystemoscillatorisused,theHLCLKbitshouldbesetto“1”orHLCLKbitis“0”,butCKS2~CKS0issetto“010”,“011”,“100”,“101”,“110”or“111”.Asacertainamountoftimewillberequiredforthehighfrequencyclocktostabilise,thestatusoftheHTObitischecked.Theamountoftimerequiredforhighspeedsystemoscillatorstabilizationdependsuponwhichhighspeedsystemoscillatortypeisused.

Rev. 1.30 4� De�e��e� 1�� 01� Rev. 1.30 43 De�e��e� 1�� 01�



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Rev. 1.30 4� De�e��e� 1�� 01� Rev. 1.30 43 De�e��e� 1�� 01�



Entering the SLEEP ModeThereisonlyonewayforthisdevicetoentertheSLEEPModeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“0”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandTimeBaseclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruction.

• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.

• TheWDTwillbeclearedandresumecounting.

• TheI/Oportswillmaintaintheirpresentconditions.

• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.

Entering the IDLE0 ModeThereisonlyonewayforthisdevicetoentertheIDLE0Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andtheFSYSONbitinCTRLregisterequalto“0”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• The systemclockwill be stoppedand the applicationprogramwill stopat the “HALT”instruction,buttheTimeBaseclockandfSUBclockwillbeon.





Entering the IDLE1 ModeThereisonlyonewayforthisdevicetoentertheIDLE1Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andtheFSYSONbitinCTRLregisterequalto“1”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandTimeBaseclockandfSUBclockwillbeonandtheapplicationprogramwillstopatthe“HALT”instruction.





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Standby Current ConsiderationsAsthemainreasonforenteringtheSLEEPorIDLEModeistokeepthecurrentconsumptionofthisdevicetoaslowavalueaspossible,perhapsonlyintheorderofseveralmicro-ampsexceptintheIDLE1Mode, thereareotherconsiderationswhichmustalsobetakenintoaccountbythecircuitdesigner if thepowerconsumptionis tobeminimised.SpecialattentionmustbemadetotheI/Opinsonthisdevice.Allhigh-impedanceinputpinsmustbeconnectedtoeitherafixedhighor lowlevelasanyfloating inputpinscouldcreate internaloscillationsandresult in increasedcurrentconsumption.Thisalsoappliestodeviceswhichhavedifferentpackagetypes,astheremaybeunbondedpins.Thesemusteitherbesetupasoutputsorifsetupasinputsmusthavepull-highresistorsconnected.

Caremustalsobetakenwiththeloads,whichareconnectedtoI/Opins,whicharesetupasoutputs.Theseshouldbeplacedinaconditioninwhichminimumcurrent isdrawnorconnectedonlytoexternalcircuits thatdonotdrawcurrent,suchasotherCMOSinputs.Alsonote thatadditionalstandbycurrentwillalsoberequirediftheconfigurationoptionshaveenabledtheLIRCoscillator.

In theIDLE1Mode thesystemoscillator ison, if thesystemoscillator is fromthehighspeedsystemoscillator,theadditionalstandbycurrentwillalsobeperhapsintheorderofseveralhundredmicro-amps.

Wake-upAfterthesystementerstheSLEEPorIDLEMode,itcanbewokenupfromoneofvarioussourceslistedasfollows:

• Anexternalreset

• AnexternalfallingedgeonPortA

• Asysteminterrupt

• AWDToverflow

If thesystemiswokenupbyanexternal reset, thisdevicewillexperiencea full systemreset,however,ifthisdevicearewokenupbyaWDToverflow,aWatchdogTimerresetwillbeinitiated.Althoughbothof thesewake-upmethodswill initiatearesetoperation, theactualsourceof thewake-upcanbedeterminedbyexaminingtheTOandPDFflags.ThePDFflag isclearedbyasystempower-uporexecutingtheclearWatchdogTimerinstructionsandissetwhenexecutingthe“HALT”instruction.TheTOflagissetifaWDTtime-outoccurs,andcausesawake-upthatonlyresetstheProgramCounterandStackPointer,theotherflagsremainintheiroriginalstatus.EachpinonPortAcanbesetupusingthePAWUregistertopermitanegativetransitiononthepintowake-upthesystem.WhenaPortApinwake-upoccurs,theprogramwillresumeexecutionattheinstructionfollowingthe“HALT”instruction.If thesystemiswokenupbyaninterrupt, thentwopossiblesituationsmayoccur.Thefirstiswheretherelatedinterruptisdisabledortheinterruptisenabledbutthestackisfull,inwhichcasetheprogramwillresumeexecutionattheinstructionfollowingthe“HALT”instruction.Inthissituation,theinterruptwhichwoke-upthisdevicewillnotbeimmediatelyserviced,butwillratherbeservicedlaterwhentherelatedinterruptisfinallyenabledorwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterruptisenabledandthestackisnotfull,inwhichcasetheregularinterruptresponsetakesplace.Ifaninterruptrequestflag issethighbeforeentering theSLEEPorIDLEMode, thewake-upfunctionof therelatedinterruptwillbedisabled.

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Watchdog TimerTheWatchdogTimerisprovidedtopreventprogrammalfunctionsorsequencesfromjumpingtounknownlocations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.

Watchdog Timer Clock SourceTheWatchdogTimerclocksourceisprovidedbytheinternalclock,fS,whichcanbesourcedfromtheLIRCoscillator.TheWatchdogTimersourceclockisthensubdividedbyaratioof28 to 218 to givelongertimeouts,theactualvaluebeingchosenusingtheWS2~WS0bitsintheWDTCregister.TheLIRCinternaloscillatorhasanapproximateperiodof32kHzatasupplyvoltageof5V.

However,itshouldbenotedthatthisspecifiedinternalclockperiodcanvarywithVDD,temperatureandprocessvariations.

Watchdog Timer Control RegisterAsingleregister,WDTC,controlstheoveralloperationoftheWatchdogTimer.Anyresetofthisdevice,theinitialvalueoftheWDTCisalways“01010011”,anditwillnotbechangedinPowerDownMode.

WDTC Register

Bit 7 � 5 4 3 � 1 0Na�e WE4 WE3 WE� WE1 WE0 WS� WS1 WS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 0 1 1

Bit 7~3 WE4~WE0:WDToperation10101or01010:EnableOthervalues:MCUreset(Resetwillbeactiveafter1~2LIRCclockfordebouncetime.)

If theMCUresetcausedbytheWE[4:0]inWDTCsoftwarereset, theWRFflagofCTRLregisterwillbeset)

Bit 2~0 WS2~WS0:WDTtime-outperiodselection000: 28/fS

001:210/fS

010:212/fS

011:214/fS

100:215/fS

101:216/fS

110:217/fS

111:218/fS

These threebitsdetermine thedivisionratioof theWatchdogTimersourceclock,whichinturndeterminesthetimeoutperiod.

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Watchdog Timer OperationNote that theWatchdogTimer function isalwaysenabled.TheWatchdogTimeroperatesbyprovidingadeviceresetwhenitstimeroverflows.ThismeansthatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallycleartheWatchdogTimerbeforeitoverflowstoprevent theWatchdogTimer fromexecutinga reset.This isdoneusing theclearwatchdoginstruction.Iftheprogrammalfunctionsforwhateverreason,jumpstoanunkownlocation,orentersanendlessloop,theseclearinstructionswillnotbeexecutedinthecorrectmanner,inwhichcasetheWatchdogTimerwilloverflowandresetthedevice.Therearefivebits,WE4~WE0,intheWDTCregister toofferacontroloftheWatchdogTimer.IfWE4~WE0bitsareset toaspecificvalueof"10101"or"01010",theWDTisalwayenable.AnyothervaluesforthesebitswillkeeptheMCUreset.

Undernormalprogramoperation,aWatchdogTimertime-outwill initialiseadeviceresetandsetthestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimertime-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStackPointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer.Thefirstisanexternalhardwarereset,thesecondisusingtheWatchdogTimersoftwareclearinstructionandthethirdisviaaHALTinstruction.

TocleartheWatchdogTimeristousethesingle“CLRWDT”instruction.Asimpleexecutionof"CLRWDT"willcleartheWDT.

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Reset and InitialisationAresetfunctionisafundamentalpartofanymicrocontrollerensuringthat thedevicecanbesettosomepredeterminedcondition irrespectiveofoutsideparameters.Themost important resetconditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase, internalcircuitrywillensure that themicrocontroller,afterashortdelay,willbe inawelldefinedstateandready toexecutethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisterswillbesettodefinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgramCounter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthelowestProgramMemoryaddress.

Another typeofreset iswhentheWatchdogTimeroverflowsandresets themicrocontroller.Alltypesofresetoperationsresultindifferentregisterconditionsbeingsetup.AnotherresetexistsintheformofaLowVoltageReset,LVR,wherethepowersupplyvoltagefallsbelowacertainthreshold.

Reset FunctionsThereare fourways inwhichamicrocontroller resetcanoccur, througheventsoccurringbothinternallyandexternally:

• Power-onResetThemostfundamentalandunavoidableresetistheonethatoccursafterpowerisfirstappliedtothemicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryaddress,apower-onresetalsoensuresthatcertainotherregistersarepresettoknownconditions.AlltheI/Oportandportcontrolregisterswillpowerupinahighconditionensuringthatallpinswillbefirstsettoinputs.

VDD

Powe�-on Reset

SST Ti�e-out

tRSTD

Note:tRSTDispower-ondelay,typicaltime=50ms

Power-on Reset Timing Chart

• LowVoltageReset–LVRThismicrocontrollercontainsalowvoltageresetcircuitinordertomonitorthesupplyvoltageofthisdevice,whichiscontrolledbyLVRCregister.Ifthesupplyvoltageofthedevicedropstowithinarangeof0.9V~VLVRsuchasmightoccurwhenchangingthebattery, theLVRwillautomaticallyreset thedevice internallyandset theLVRFin theCTRLregister tohigh .TheLVRincludesthefollowingspecifications:ForavalidLVRsignal,alowvoltage,i.e.,avoltageintherangebetween0.9V~VLVRmustexistforgreaterthanthevaluetLVRspecifiedintheA.C.characteristics.IfthelowvoltagestatedoesnotexceedtLVR,theLVRwillignoreitandwillnotperformaresetfunction.

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Note:tRSTDispower-ondelay,typicaltime=16.7ms

Low Voltage Reset Timing Chart

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LVRC Register

Bit 7 � 5 4 3 � 1 0Na�e LVS7 LVS� LVS5 LVS4 LVS3 LVS� LVS1 LVS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 1 0 1

Bit 7~3 LVS7~LVS0:LVRvoltageselect01010101:3.15V00110011:3.15V10011001:3.15V10101010:3.15VOthervalues:MCUreset(Resetwillbeactiveafter2~3LIRCclockfordebouncetime.)

IftheMCUresetcausedbytheLVRCsoftwarereset,theLRFflagofCTRLregisterwillbeset.

• WatchdogTime-outResetduringNormalOperationTheWatchdogtime-outflagTOwillbesetto“1”.

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WDT Time-out Reset during Normal Operation Timing Chart

• WatchdogTime-outResetduringSLEEPorIDLEModeTheWatchdogtime-outResetduringSLEEPorIDLEModeisalittledifferentfromotherkindsofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStackPointerwillbeclearedto“0”andtheTOflagwillbesetto“1”.RefertotheA.C.Characteristicsfor tSSTdetails.

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Note:ThetSSTis15~16clockcyclesifthesystemclocksourceisprovidedbyHIRC. ThetSSTis1~2clockforLIRC.

WDT Time-out Reset during SLEEP or IDLE Timing Chart

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Reset Initial ConditionsThedifferent typesofresetdescribedaffect theresetflagsindifferentways.Theseflags,knownasPDFandTOare located in thestatus registerandarecontrolledbyvariousmicrocontrolleroperations,suchas theSLEEPorIDLEModefunctionorWatchdogTimer.Thereset flagsareshowninthetable:

TO PDF RESET Conditions0 0 Powe�-on �esetu u LVR �eset du�ing NORMAL o� SLOW Mode ope�ation1 u WDT ti�e-out �eset du�ing NORMAL o� SLOW Mode ope�ation1 1 WDT ti�e-out �eset du�ing IDLE o� SLEEP Mode ope�ation

“u” stands fo� un�hangedThefollowingtableindicatesthewayinwhichthevariouscomponentsofthemicrocontrollerareaffectedafterapower-onresetoccurs.

Item Condition After RESETP�og�a� Counte� Reset to ze�oInte��upts All inte��upts will �e disa�ledWDT Clea� afte� �eset� WDT �egins �ountingTi�e�/Event Counte� TM �odules will �e tu�ned offInput/Output Po�ts I/O po�ts will �e setup as inputs� and AN0~AN7 is as A/D input pin.Sta�k Pointe� Sta�k Pointe� will point to the top of the sta�k

Thedifferentkindsofresetsallaffecttheinternalregistersofthemicrocontrollerindifferentways.Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs,itisimportanttoknowwhatconditionthemicrocontrolleris inafteraparticularresetoccurs.Thefollowingtabledescribeshoweachtypeofresetaffectseachof themicrocontroller internalregisters.Note thatwheremorethanonepackagetypeexiststhetablewillreflectthesituationforthelargerpackagetype.

Register Reset(Power On)

WDT Time-out(Normal Operation) LVR Reset WDT Time-out

(IDLE)MP0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuuMP1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuuBP ---- ---0 ---- ---0 ---- ---0 ---- ---uACC xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuuPCL 0000 0000 0000 0000 0000 0000 0000 0000TBLP xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuuTBLH -xxx xxxx -uuu uuuu -xxx xxxx -uuu uuuuTBHP ---- xxxx ---- uuuu ---- xxxx ---- uuuuSTATUS --00 xxxx --1u uuuu --uu xxxx --11 uuuuSMOD 0000 0011 0000 0011 0000 0011 uuuu uuuuLVDC --00 -000 --00 -000 --00 -000 --uu –uuuLVRC 0101 0101 0101 0101 0101 0101 uuuu uuuuWDTC 0101 0011 0101 0011 0101 0011 uuuu uuuuTBC 0011 ---- 0011 ---- 0011 ---- uuuu ----INTC0 -000 0000 -000 0000 -000 0000 -uuu uuuuINTC1 0000 0000 0000 0000 0000 0000 uuuu uuuuINTC� 0000 0000 0000 0000 0000 0000 uuuu uuuuINTC3 0000 0000 0000 0000 0000 0000 uuuu uuuuMFI0 -000 -000 -000 -000 -000 -000 -uuu -uuu

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(IDLE)MFI1 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u – - u uMFI� - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u uMFI3 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u uMFI4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uMFI5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uMFI� - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - u u u - u u uMFI7 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u uMFI8 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u uPAWU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPAPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPAC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPBPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PBC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPCPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPCC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPDPU - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uPD - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - u u u uPDC - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - u u u uNF_VIH 0 - - 1 1 0 0 1 0 - - 1 1 0 0 1 0 - - 1 1 0 0 1 u - - u u u u uNF_VIL - - - 0 1 0 1 0 - - - 0 1 0 1 0 - - - 0 1 0 1 0 - - - u u u u uRMTC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uRMT0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uRMT1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uHCHK_NUM - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - u u u u uHNF_MSEL - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uCAPTC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uCAPTC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uCAPTMDL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uCAPTMDH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uCAPTMAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uCAPTMAH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uCAPTMCL x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uCAPTMCH x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uOPOMS 0 0 - - - 0 1 0 0 0 - - - 0 1 0 0 0 - - - 0 1 0 u u - - - u u uOPCM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uLHMC - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u uHACM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTMPC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTMPC1 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uCTRL 0 - - - - x 0 0 0 - - - - x 0 0 0 - - - - x 0 0 u - - - - u u uEEC - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uEEA - x x x x x x x - x x x x x x x - x x x x x x x - u u u u u u uEED x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uADRL x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u

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(IDLE)ADRH - - - - - - x x - - - - - - x x - - - - - - x x - - - - - - u uADCR0 0 11 - 0 0 0 0 0 11 - 0 0 0 0 0 11 - 0 0 0 0 u u u - u u u uADCR1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uANCSR0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uANCSR1 - - - - - - - 1 - - - - - - - 1 - - - - - - - 1 - - - - - - - uADDL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uADLVDL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uADLVDH x x x x x x 0 0 x x x x x x 0 0 x x x x x x 0 0 u u u u u u u uADHVDL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uADHVDH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uPWMC - - 0 0 0 - - 0 - - 0 0 0 - - 0 - - 0 0 0 - - 0 - - u u u - - uDUTRL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uDUTRH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uPRDRL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPRDRH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPWMRL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPWMRH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uMCF - - - - 0 1 0 0 - - - - 0 1 0 0 - - - - 0 1 0 0 - - - - u u u uMCD - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uDTS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPLC - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uHDCR 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 u u u u u u u uHDCD - - - - - 0 0 0 - - - - - 0 0 0 - - - - - 0 0 0 - - - - - u u uHDCT0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uHDCT1 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uHDCT� - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uHDCT3 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uHDCT4 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uHDCT5 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uHDCT� - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uHDCT7 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uHDCT8 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uHDCT9 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uHDCT10 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uHDCT11 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uMPTC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uMPTC� 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM5C0 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - u u u u u - - -TM5C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM5DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM5DH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM5AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM5AH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM5RP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uOPACAL - 0 0 1 0 0 0 0 - 0 0 1 0 0 0 0 - 0 0 1 0 0 0 0 - u u u u u u uDCMCR0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 u u u u u u u uDCMCR1 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - u u u u u

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(IDLE)TM0C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0DH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uTM0AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0AH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uTM1C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1DH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uTM1AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1AH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uTM�C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM�C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM�DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM�DH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uTM�AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM�AH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uTM3C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM3C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM3DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM3DH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uTM3AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM3AH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

Note:“-”standsfornotimplement

“u”standsforunchanged

“x”standsforunknown

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Input/Output PortsHoltekmicrocontrollersofferconsiderableflexibilityontheirI/Oports.Withtheinputoroutputdesignationofeverypinfullyunderuserprogramcontrol,pull-highselectionsforallportsandwake-upselectionsoncertainpins,theuserisprovidedwithanI/Ostructuretomeettheneedsofawiderangeofapplicationpossibilities.

Thisdeviceprovidebidirectionalinput/outputlineslabeledwithportnamesPA~PDTheseI/Oportsaremappedto theRAMDataMemorywithspecificaddressesasshownin theSpecialPurposeDataMemorytable.Allof theseI/Oportscanbeusedforinputandoutputoperations.Forinputoperation,theseportsarenon-latching,whichmeanstheinputsmustbereadyattheT2risingedgeofinstruction“MOVA,[m]”,wheremdenotestheportaddress.Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.

I/O Register List

Register Name

Bit

7 6 5 4 3 2 1 0PAWU D7 D� D5 D4 D3 D� D1 D0PAPU D7 D� D5 D4 D3 D� D1 D0

PA D7 D� D5 D4 D3 D� D1 D0PAC D7 D� D5 D4 D3 D� D1 D0

PBPU D7 D� D5 D4 D3 D� D1 D0PB D7 D� D5 D4 D3 D� D1 D0

PBC D7 D� D5 D4 D3 D� D1 D0PCPU D7 D� D5 D4 D3 D� D1 D0

PC D7 D� D5 D4 D3 D� D1 D0PCC D7 D� D5 D4 D3 D� D1 D0

PDPU — — — — D3 D� D1 D0PD — — — — D3 D� D1 D0

PDC — — — — D3 D� D1 D0

Pull-high ResistorsManyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringtheuseofanexternal resistor.Toeliminate theneedfor theseexternal resistors,all I/Opins,whenconfiguredasaninputhavethecapabilityofbeingconnectedtoaninternalpull-highresistor.Thesepull-highresistorsareselectedusingregisters,namelyPAPU~PDPU,andareimplementedusingweakPMOStransistors.

PAPU Register

Bit 7 6 5 4 3 2 1 0Na�e D7 D� D5 D4 D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

PBPU Register


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PCPU Register


Bit7~0 I/OPortbit7~bit0pull-highcontrol

PDPU Register

Bit 7 6 5 4 3 2 1 0Na�e — — — — D3 D� D1 D0R/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas“0”Bit3~0 PortDbit3~bit0pull-highcontrol

Port A Wake-upTheHALTinstructionforcesthemicrocontrollerintotheSLEEPorIDLEModewhichpreservespower,afeature that is importantforbatteryandother low-powerapplications.Variousmethodsexisttowake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePortApinsfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenupviaexternalswitches.EachpinonPortAcanbeselectedindividuallytohavethiswake-upfeatureusingthePAWUregister.

PAWU Register


Bit 7~0 PAWU:PortAbit7~bit0Wake-upControl0:Disable1:Enable

I/O Port Control RegistersEach I/Oporthas itsowncontrol registerknownasPAC~PDC, to control the input/outputconfiguration.With this control register, eachCMOSoutput or input canbe reconfigureddynamicallyundersoftwarecontrol.Eachpinof theI/Oports isdirectlymappedtoabit in itsassociatedportcontrolregister.FortheI/Opintofunctionasaninput,thecorrespondingbitofthecontrolregistermustbewrittenasa“1”.Thiswillthenallowthelogicstateoftheinputpintobedirectlyreadbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa“0”,theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructionscanstillbeusedtoreadtheoutputregister.However,itshouldbenotedthattheprogramwillinfactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.

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PAC Register


PBC Register


PCC Register


Bit7~0 I/Oportbit7~bit0Input/Outputcontrol

PDC Register

Bit 7 6 5 4 3 2 1 0Na�e — — — — D3 D� D1 D0R/W — — — — R/W R/W R/W R/WPOR — — — — 1 1 1 1

Bit7~4 Unimplemented,readas“0”

Bit3~0 I/OPortbit3~bit0Input/OutputControl0:Output1:Input

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I/O Pin StructuresTheaccompanyingdiagrams illustrate the internalstructuresofsomegeneric I/Opin types.AstheexactlogicalconstructionoftheI/Opinwilldifferfromthesedrawings,theyaresuppliedasaguideonlytoassistwiththefunctionalunderstandingoftheI/Opins.Thewiderangeofpin-sharedstructuresdoesnotpermitalltypestobeshown.

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Generic Input/Output Structure

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A/D Input/Output Structure

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Programming ConsiderationsWithintheuserprogram,oneofthefirstthingstoconsiderisportinitialisation.Afterareset,alloftheI/Odataandportcontrolregisterswillbesethigh.ThismeansthatallI/Opinswilldefaulttoaninputstate, thelevelofwhichdependsontheotherconnectedcircuitryandwhetherpull-highselectionshavebeenchosen.Iftheportcontrolregisters,PAC~PDC,arethenprogrammedtosetupsomepinsasoutputs,theseoutputpinswillhaveaninitialhighoutputvalueunlesstheassociatedportdataregisters,PA~PD,arefirstprogrammed.Selectingwhichpinsareinputsandwhichareoutputscanbeachievedbyte-widebyloadingthecorrectvaluesintotheappropriateportcontrolregisterorbyprogrammingindividualbits intheportcontrolregisterusingthe“SET[m].i”and“CLR[m].i”instructions.Notethatwhenusingthesebitcontrolinstructions,aread-modify-writeoperationtakesplace.Themicrocontrollermustfirstreadinthedataontheentireport,modifyittotherequirednewbitvaluesandthenrewritethisdatabacktotheoutputports.

PortAhas theadditionalcapabilityofprovidingwake-upfunctions.When thedevice is in theSLEEPorIDLEMode,variousmethodsareavailabletowakethedeviceup.OneoftheseisahightolowtransitionofanyofthePortApins.SingleormultiplepinsonPortAcanbesetuptohavethisfunction.

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Timer Modules – TMOneofthemostfundamentalfunctionsinanymicrocontrollerdeviceistheabilitytocontrolandmeasuretime.Toimplement timerelatedfunctionseachdeviceincludesseveralTimerModules,abbreviated to thenameTM.TheTMsaremulti-purpose timingunits and serve toprovideoperationssuchasTimer/Counter,InputCapture,CompareMatchOutputandSinglePulseOutputaswellasbeing the functionalunit for thegenerationofPWMsignals.Eachof theTMshaseithermultipleinterrupts.TheadditionofinputandoutputpinsforeachTMensuresthatusersareprovidedwithtimingunitswithawideandflexiblerangeoffeatures.

ThecommonfeaturesofthedifferentTMtypesaredescribedherewithmoredetailedinformationprovidedintheindividualCompactandStandardTMsections.

IntroductionThedevicecontainsfiveTMshavingareferencenameofTM0,TM1,TM2,TM3andTM5.EachindividualTMcanbecategorisedasacertaintype,namelyCompactTypeTM,four10-bitCTMandone16-bitCTM.Themainfeaturesaresummarisedintheaccompanyingtable.

Function CTMTi�e�/Counte� √I/P Captu�e —Co�pa�e Mat�h Output √PWM Channels 1Single Pulse Output —PWM Align�ent EdgePWM Adjust�ent Pe�iod & Duty Duty o� Pe�iod

TM Function Summary

TM OperationTMofferadiverserangeoffunctions,fromsimpletimingoperationstoPWMsignalgeneration.ThekeytounderstandinghowtheTMoperatesistoseeitintermsofafreerunningcounterwhosevalue is thencomparedwith thevalueofpre-programmedinternalcomparators.Whenthefreerunningcounterhasthesamevalueasthepre-programmedcomparator,knownasacomparematchsituation,aTMinterruptsignalwillbegeneratedwhichcanclear thecounterandperhapsalsochangetheconditionoftheTMoutputpin.TheinternalTMcounterisdrivenbyauserselectableclocksource,whichcanbeaninternalclockoranexternalpin.

TM Clock SourceTheclocksourcewhichdrives themaincounter ineachTMcanoriginatefromvarioussources.TheselectionoftherequiredclocksourceisimplementedusingtheTnCK2~TnCK0bitsintheTMcontrolregisters.TheclocksourcecanbearatioofeitherthesystemclockfSYSortheinternalhighclockfH,thefTBCclocksourceortheexternalTCKnpin.Notethatsettingthesebitstothevalue101willselectanundefinedclockinput, ineffectdisconnectingtheTMclocksource.TheTCKnpinclocksourceisusedtoallowanexternalsignaltodrivetheTMasanexternalclocksourceorforeventcounting.

TM InterruptsTheCompact typeTMhas twointernal interrupts,oneforeachof the internalcomparatorAorcomparatorP,whichgenerateaTMinterruptwhenacomparematchconditionoccurs.

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TM External PinsEachoftheTMs,irrespectiveofwhattype,hasoneTMinputpin,withthelabelTCKn.TheTMinputpin,isessentiallyaclocksourcefortheTMandisselectedusingtheTnCK2~TnCK0bitsintheTMnC0register.ThisexternalTMinputpinallowsanexternalclocksourcetodrivetheinternalTM.ThisexternalTMinputpinissharedwithotherfunctionsbutwillbeconnectedtotheinternalTMifselectedusingtheTnCK2~TnCK0bits.TheTMinputpincanbechosentohaveeitherarisingorfallingactiveedge.

TheTMseachhavetwooutputpinswiththelabelTPn.WhentheTMis intheCompareMatchOutputMode,thesepinscanbecontrolledbytheTMtoswitchtoahighorlowlevelortotogglewhenacomparematchsituationoccurs.TheexternalTPnoutputpinisalsothepinwheretheTMgeneratesthePWMoutputwaveform.AstheTMoutputpinsarepin-sharedwithotherfunction,theTMoutputfunctionmustfirstbesetupusingregisters.AsinglebitinoneoftheregistersdeterminesifitsassociatedpinistobeusedasanexternalTMoutputpinorifitistohaveanotherfunction.

AllTMoutputpinnameshavea“_n”suffix.Pinnamesthatincludea“_0”or“_1”suffixindicatethattheyarefromaTMwithmultipleoutputpins.ThisallowstheTMtogenerateacomplimentaryoutputpair,selectedusingtheI/Oregisterdatabits.

CTM0 CTM1 CTM2 CTM3 CTM5TP0_0�TP0_1 TP1_0�TP1_1 TP�_0�TP�_1 TP3_0�TP3_1 TP5_0�TP5_1

TM Output Pins

TM Input/Output Pin Control RegistersSelectingtohaveaTMinput/outputorwhethertoretainitsothersharedfunction,isimplementedusingoneortworegisters,withasinglebitineachregistercorrespondingtoaTMinput/outputpin.SettingthebithighwillsetupthecorrespondingpinasaTMinput/output, ifresettozerothepinwillretainitsoriginalotherfunction.

RegistersBit

7 6 5 4 3 2 1 0TMPC0 T3CP1 T3CP0 T�CP1 T�CP0 T1CP1 T1CP0 T0CP1 T0CP0TMPC1 — — — — — — T5CP1 T5CP0

TM Input/Output Pin Control Registers List

TMPC0 Register

Bit 7 6 5 4 3 2 1 0Na�e T3CP1 T3CP0 T�CP1 T�CP0 T1CP1 T1CP0 T0CP1 T0CP0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit 7 T3CP1:TP3_1pinControl0:Disable1:Enable



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Bit1 T0CP1:TP0_1pinControl0:Disable1:Enable


TMPC1 Register

Bit 7 6 5 4 3 2 1 0Na�e — — — — — — T5CP1 T5CP0R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas“0”Bit1 T5CP1:TP5_1pinControl

0:Disable1:Enable


Programming ConsiderationsTheTMCounterRegistersandtheCapture/CompareCCRAis10-bitor16-bitregister,havealowandhighbytestructure.Thehighbytescanbedirectlyaccessed,butasthelowbytescanonlybeaccessedviaaninternal8-bitbuffer,readingorwritingtotheseregisterpairsmustbecarriedoutinaspecificway.Theimportantpointtonoteisthatdatatransfertoandfromthe8-bitbufferanditsrelatedlowbyteonlytakesplacewhenawriteorreadoperationtoitscorrespondinghighbyteisexecuted.

Data Bus

8-�it Buffe�

TMxDHTMxDL

TMxAHTMxAL

TM Counte� Registe� (Read only)

TM CCRA Registe� (Read/W�ite)

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Thefollowingstepsshowthereadandwriteprocedures:

• WritingDatatoCCRA ♦ Step1.WritedatatoLowByteTMxAL

– notethatheredataisonlywrittentothe8-bitbuffer. ♦ Step2.WritedatatoHighByteTMxAH

– heredataiswrittendirectlytothehighbyteregistersandsimultaneouslydataislatchedfromthe8-bitbuffertotheLowByteregisters.

• ReadingDatafromtheCounterRegistersandCCRA ♦ Step1.ReaddatafromtheHighByteTMxDHorTMxAH

– heredataisreaddirectlyfromtheHighByteregistersandsimultaneouslydataislatchedfromtheLowByteregisterintothe8-bitbuffer.

♦ Step2.ReaddatafromtheLowByteTMxDLorTMxAL – thisstepreadsdatafromthe8-bitbuffer.

Compact Type TM – CTMAlthoughthesimplestformoftheTMtypes, theCompactTMtypestillcontainsthreeoperatingmodes,whichareCompareMatchOutput,Timer/EventCounterandPWMOutputmodes.TheCompactTMcanalsobecontrolledwithanexternalinputpinandcandrivetwoexternaloutputpins.Thesetwoexternaloutputpinscanbethesamesignalortheinversesignal.

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Compact Type TM Block Diagram (n=0, 1, 2, 3, 5)

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Compact TM OperationAtitscoreisa10-bitor16-bitcount-upcounterwhichisdrivenbyauserselectableinternalorexternalclocksource.Therearealsotwointernalcomparatorswiththenames,ComparatorAandComparatorP.Thesecomparatorswillcompare thevalue in thecounterwithCCRPandCCRAregisters.TheCCRPisthreebitswidewhosevalueiscomparedwiththehighestthreebitsoreightbits inthecounterwhiletheCCRAisthetenbitsorsixteenbitsandthereforecompareswithallcounterbits.

Theonlywayofchangingthevalueofthe10-bitor16-bitcounterusingtheapplicationprogram,istoclearthecounterbychangingtheTnONbitfromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.TheCompactTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontrolanoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

Compact Type TM Register DescriptionOveralloperationof theCompactTMiscontrolledusingsixregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitor16-bitvalue,whilearead/writeregisterpairexiststostore theinternal10-bitor16-bitCCRAvalue.TheremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodesaswellasthethreeoreightCCRPbits.

Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0TMnC0 TnPAU TnCK� TnCK1 TnCK0 TnON TnRP� TnRP1 TnRP0TMnC1 TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLRTMnDL D7 D� D5 D4 D3 D� D1 D0TMnDH — — — — — — D9 D8TMnAL D7 D� D5 D4 D3 D� D1 D0TMnAH — — — — — — D9 D8

10-bit Compact TM Register List(n=0, 1, 2, 3)

Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0TM5C0 T5PAU T5CK� T5CK1 T5CK0 T5ON T5RP� T5RP1 T5RP0TM5C1 T5M1 T5M0 T5IO1 T5IO0 T5OC T5POL T5DPX T5CCLRTM5DL D7 D� D5 D4 D3 D� D1 D0TM5DH D15 D14 D13 D1� D11 D10 D9 D8TM5AL D7 D� D5 D4 D3 D� D1 D0TM5AH D15 D14 D13 D1� D11 D10 D9 D8TM5RP D7 D� D5 D4 D3 D� D1 D0

16-bit Compact TM Register List

TMnDL Register(n=0, 1, 2, 3) — 10-bit CTM

Bit 7 6 5 4 3 2 1 0Na�e D7 D� D5 D4 D3 D� D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit 7~0 TMnDL:TMnCounterLowByteRegisterbit7~bit0TMn10-bitCounterbit7~bit0

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TMnDH Register(n=0, 1, 2, 3) — 10-bit CTM

Bit 7 6 5 4 3 2 1 0Na�e — — — — — — D9 D8R/W — — — — — — R RPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 TMnDH:TMnCounterHighByteRegisterbit1~bit0

TMn10-bitCounterbit9~bit8

TMnAL Register(n=0, 1, 2, 3) — 10-bit CTM


Bit 7~0 TMnAL:TMnCCRALowByteRegisterbit7~bit0TMn10-bitCCRAbit7~bit0

TMnAH Register(n=0, 1, 2, 3) — 10-bit CTM

Bit 7 6 5 4 3 2 1 0Na�e — — — — — — D9 D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 TMnAH:TMnCCRAHighByteRegisterbit1~bit0

TMn10-bitCCRAbit9~bit8

TM5DL Register — 16-bit CTM


Bit 7~0 TM5DL:TM5CounterLowByteRegisterbit7~bit0TM516-bitCounterbit7~bit0

TM5DH Register — 16-bit CTM

Bit 7 6 5 4 3 2 1 0Na�e D15 D14 D13 D1� D11 D10 D9 D8R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit 7~0 TM5DH:TM5CounterHighByteRegisterbit7~bit0TM516-bitCounterbit15~bit8

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TM5AL Register — 16-bit CTM


Bit 7~0 TM5AL:TM5CCRALowByteRegisterbit7~bit0TM516-bitCCRAbit7~bit0

TM5AH Register — 16-bit CTM


Bit 7~0 TM5AH:TM5CCRAHighByteRegisterbit8~bit0TM516-bitCCRAbit15~bit8

TMnC0 Register(n=0, 1, 2, 3) — 10-bit CTM

Bit 7 6 5 4 3 2 1 0Na�e TnPAU TnCK� TnCK1 TnCK0 TnON TnRP� TnRP1 TnRP0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit 7 TnPAU:TMnCounterPauseControl0:Run1:Pause

Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.

Bit 6~4 TnCK2~TnCK0:SelectTMnCounterclock000: fSYS/4001:fSYS

010:fH/16011:fH/64100:fTBC

101:Reserved110:TCKnrisingedgeclock111:TCKnfallingedgeclock

These threebits areused to select theclock source for theTM0.Selecting theReservedclockinputwilleffectivelydisable the internalcounter.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfTBCareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

Bit 3 TnON:TMnCounterOn/OffControl0: Off1:On

Thisbitcontrolstheoverallon/offfunctionoftheTMn.Settingthebithighenablesthecounter torun,clearingthebitdisables theTMn.Clearingthisbit tozerowillstop thecounterfromcountingand turnoff theTMnwhichwill reduce itspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillbereset tozero,howeverwhenthebitchangesfromhighto low, the internal

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counterwill retain its residualvalue. If theTMnis in theCompareMatchOutputModethentheTMnoutputpinwillberesettoitsinitialcondition,asspecifiedbytheTnOCbit,whentheTnONbitchangesfromlowtohigh.

Bit 2~0 TnRP2~TnRP0:TMnCCRP3-bitregister,comparedwiththeTMnCounterbit9~bit7ComparatorPMatchPeriod000:1024TMnclocks001:128TMnclocks010:256TMnclocks011:384TMnclocks100:512TMnclocks101:640TMnclocks110:768TMnclocks111:896TMnclocks

ThesethreebitsareusedtosetupthevalueontheinternalCCRP3-bitregister,whichare thencomparedwith the internalcounter’shighest threebits.Theresultof thiscomparisoncanbeselectedtoclear theinternalcounterif theTnCCLRbit isset tozero.SettingtheTnCCLRbit tozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighest threecounterbits, thecomparevaluesexist in128clockcyclemultiples.Clearingall threebits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.

TMnC1 Register(n=0, 1, 2, 3) — 10-bit CTM

Bit 7 6 5 4 3 2 1 0Na�e TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit 7~6 TnM1~TnM0:SelectTMnOperatingMode00:CompareMatchOutputMode01:Undefined10:PWMMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremadetotheTnM1andTnM0bits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.

Bit 5~4 TnIO1~TnIO0:SelectTPn_0,TPn_1outputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Undefined

Timer/counterModeunused

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ThesetwobitsareusedtodeterminehowtheTMnoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMnisrunning.IntheCompareMatchOutputMode,theTnIO1andTnIO0bitsdeterminehowtheTMnoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMnoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthebitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheTMnoutputpinshouldbesetupusingtheTnOCbit intheTMnC1register.NotethattheoutputlevelrequestedbytheTnIO1andTnIO0bitsmustbedifferentfromtheinitialvaluesetupusingtheTnOCbitotherwisenochangewilloccurontheTMnoutputpinwhenacomparematchoccurs.AftertheTMnoutputpinchangesstateitcanberesettoitsinitiallevelbychangingtheleveloftheTnONbitfromlowtohigh.In thePWMMode, theTnIO1andTnIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits. It isnecessarytoonlychangethevaluesof theTnIO1andTnIO0bitsonlyafter theTMnhasbeen switchedoff.UnpredictablePWMoutputswilloccuriftheTnIO1andTnIO0bitsarechangedwhentheTMisrunning.

Bit 3 TnOC:TPn_0,TPn_1OutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh

PWMMode0:Activelow1:Activehigh

This is theoutputcontrolbit for theTMnoutputpin. ItsoperationdependsuponwhetherTMnisbeingusedintheCompareMatchOutputModeorinthePWMMode.Ithasnoeffect if theTMnis in theTimer/CounterMode. In theCompareMatchOutputModeitdetermines the logic levelofheTMnoutputpinbeforeacomparematchoccurs.InthePWMModeitdeterminesif thePWMsignal isactivehighoractivelow.

Bit 2 TnPOL:TPn_0,TPn_1OutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheTPn_0orTP0_1outputpin.Whenthebit issethightheTMnoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheTMnisintheTimer/CounterMode.

Bit1 TnDPX:TMnPWMperiod/dutyControl0:CCRP-period;CCRA-duty1:CCRP-duty;CCRA-period

Thisbit,determineswhichoftheCCRAandCCRPregistersareusedforperiodanddutycontrolofthePWMwaveform.

Bit 0 TnCCLR:SelectTMnCounterclearcondition0:TMnComparatorPmatch1:TMnComparatorAmatch

Thisbit isused toselect themethodwhichclears thecounter.Remember that theCompactTMncontainstwocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtoclear the internalcounter.With theTnCCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheTnCCLRbitisnotusedinthePWMMode.

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TM5C0 Register—16-bit CTM

Bit 7 6 5 4 3 2 1 0Na�e T5PAU T5CK� T5CK1 T5CK0 T5ON — — —R/W R/W R/W R/W R/W R/W — — —POR 0 0 0 0 0 — — —

Bit 7 T5PAU:TM5CounterPauseControl0:Run1:Pause

Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.

Bit 6~4 T5CK2~T5CK0:SelectTM5Counterclock000: fSYS/4001:fSYS

010:fH/16011:fH/64100:fTBC

101:Reserved110:TCK5risingedgeclock111:TCK5fallingedgeclock

These threebits areused to select theclock source for theTM5.Selecting theReservedclockinputwilleffectivelydisable the internalcounter.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfTBCareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

Bit 3 T5ON:TM5CounterOn/OffControl0: Off1:On

Thisbitcontrolstheoverallon/offfunctionoftheTM5.Settingthebithighenablesthecounter torun,clearingthebitdisables theTM5.Clearingthisbit tozerowillstop thecounterfromcountingand turnoff theTM5whichwill reduce itspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillbereset tozero,howeverwhenthebitchangesfromhighto low, the internalcounterwill retain its residualvalue. If theTM5is in theCompareMatchOutputModethentheTM5outputpinwillberesettoitsinitialcondition,asspecifiedbytheT5OCbit,whentheT5ONbitchangesfromlowtohigh.

Bit2~0 Unimplemented,readas"0"

TM5C1 Register — 16-bit CTM

Bit 7 6 5 4 3 2 1 0Na�e T5M1 T5M0 T5IO1 T5IO0 T5OC T5POL T5DPX T5CCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit 7~6 T5M1~T5M0:SelectTM5OperatingMode00:CompareMatchOutputMode01:Undefined10:PWMMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremadetotheT5M1andT5M0bits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.

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Bit 5~4 T5IO1~T5IO0:SelectTP5_0,TP5_1outputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode00:PWMoutputinactivestate01:PWMoutputactivestate10:PWMoutput11:Undefined

Timer/counterModeunused

ThesetwobitsareusedtodeterminehowtheTM5outputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTM5isrunning.IntheCompareMatchOutputMode,theT5IO1andT5IO0bitsdeterminehowtheTM5outputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTM5outputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthebitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheTM5outputpinshouldbesetupusingtheT5OCbit intheTM5C1register.NotethattheoutputlevelrequestedbytheT5IO1andT5IO0bitsmustbedifferentfromtheinitialvaluesetupusingtheT5OCbitotherwisenochangewilloccurontheTM5outputpinwhenacomparematchoccurs.AftertheTM5outputpinchangesstateitcanberesettoitsinitiallevelbychangingtheleveloftheT5ONbitfromlowtohigh.In thePWMMode, theT5IO1andT5IO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits. It isnecessarytoonlychangethevaluesof theT5IO1andT5IO0bitsonlyafter theTM5hasbeen switchedoff.UnpredictablePWMoutputswilloccuriftheT5IO1andT5IO0bitsarechangedwhentheTMisrunning.

Bit 3 T5OC:TP5_0,TP5_1OutputcontrolbitCompareMatchoutputMode0:Initiallow1:Initialhigh

PWMMode0:Activelow1:Activehigh

This is theoutputcontrolbit for theTM5outputpin. ItsoperationdependsuponwhetherTM5isbeingusedintheCompareMatchOutputModeorinthePWMMode.Ithasnoeffect if theTM5is in theTimer/CounterMode. In theCompareMatchOutputModeitdetermines the logic levelofheTM5outputpinbeforeacomparematchoccurs.InthePWMModeitdeterminesif thePWMsignal isactivehighoractivelow.

Bit 2 T5POL:TP5_0,TP5_1outputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheTP5_0orTP5_1outputpin.Whenthebit issethightheTM5outputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheTMnisintheTimer/CounterMode.

Bit1 T5DPX:TM5PWMperiod/dutyControl0:CCRP-period;CCRA-duty1:CCRP-duty;CCRA-period

Thisbit,determineswhichoftheCCRAandCCRPregistersareusedforperiodanddutycontrolofthePWMwaveform.

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Bit 0 T5CCLR:SelectTM5Counterclearcondition0:TM5ComparatorPmatch1:TM5ComparatorAmatch

Thisbit isused toselect themethodwhichclears thecounter.Remember that theCompactTM5containstwocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtoclear the internalcounter.With theT5CCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheT5CCLRbitisnotusedinthePWMMode.

TM5RP Register – 16-bit CTM


Bit7~0 TM5CCRP8-bitregister,comparedwiththeTM5Counterbit15~bit8ComparatorPMatchPeriod0:1024TMnclocks1~255:256×(1~255)TM5clocks

ThesethreebitsareusedtosetupthevalueontheinternalCCRP8-bitregister,whichare thencomparedwith the internalcounter’shighesteightbits.Theresultof thiscomparisoncanbeselectedtoclear theinternalcounterif theT5CCLRbit isset tozero.SettingtheT5CCLRbit tozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighesteightcounterbits, thecomparevaluesexist in256clockcyclemultiples.Clearingall threebits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.

Compact Type TM Operating ModesTheCompactTypeTMcanoperateinoneofthreeoperatingmodes,CompareMatchOutputMode,PWMModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheTnM1andTnM0bitsintheTMnC1register.

Compare Match Output ModeToselectthismode,bitsTnM1andTnM0intheTMnC1register,shouldbesetto“00”respectively.Inthismodeoncethecounterisenabledandrunningitcanbeclearedbythreemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheTnCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchoccursfromComparatorP, theotheriswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HerebothTnAFandTnPFinterruptrequestflagsfortheComparatorAandComparatorPrespectively,willbothbegenerated.

IftheTnCCLRbitintheTMnC1registerishighthenthecounterwillbeclearedwhenacomparematchoccurs fromComparatorA.However,hereonly theTnAFinterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenTnCCLRishighnoTnPFinterruptrequestflagwillbegenerated.IftheCCRAbitsareallzero,thecounterwilloverflowwhenitsreachesitsmaximum10-bit,3FFHex,or16-bit,FFFFHex,value,howeverheretheTnAFinterruptrequestflagwillnotbegenerated.

As thenameof themodesuggests,afteracomparison ismade, theTMoutputpinwillchangestate.TheTMoutputpinconditionhoweveronlychangesstatewhenaTnAFinterruptrequestflag

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isgeneratedafteracomparematchoccursfromComparatorA.TheTnPFinterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectontheTMoutputpin.Thewayinwhich theTMoutputpinchangesstatearedeterminedby theconditionof theTnIO1andTnIO0bitsintheTMnC1register.TheTMoutputpincanbeselectedusingtheTnIO1andTnIO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.Theinitialconditionof theTMoutputpin,which issetupafter theTnONbitchangesfromlowtohigh,issetupusingtheTnOCbit.NotethatiftheTnIO1andTnIO0bitsarezerothennopinchangewilltakeplace.

Counte� Value

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM O/P Pin

Ti�e

CCRP=0

CCRP > 0

Counte� ove�flowCCRP > 0Counte� �lea�ed �y CCRP value

Pause

Resu�e

Stop

Counte� Resta�t

TnCCLR = 0; TnM [1:0] = 00

Output pin set to initial Level Low if TnOC=0

Output Toggle with TnAF flag

Note TnIO [1:0] = 10 A�tive High Output sele�tHe�e TnIO [1:0] = 11

Toggle Output sele�t

Output not affe�ted �y TnAF flag. Re�ains High until �eset �y TnON �it

Output PinReset to Initial value

Output �ont�olled �y othe� pin-sha�ed fun�tion

Output Inve�tswhen TnPOL is high

0x3FF o� 0xFFFF

Compare Match Output Mode – TnCCLR=0

Note:1.WithTnCCLR=0,aComparatorPmatchwillclearthecounter2.TheTMoutputpiniscontrolledonlybytheTnAFflag3.TheoutputpinisresettoitsinitialstatebyaTnONbitrisingedge4.n=0,1,2,3,5

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CCRP

CCRA

0x3FF o� 0xFFFF

CCRA = 0Counte� ove�flows

CCRP Int.Flag TnPF

CCRA Int.Flag TnAF

CCRA > 0 Counte� �lea�ed �y CCRA value

TM O/P Pin

TnON �it

Pause Counte�Reset

Output PinReset to initial value

Output Pin set to Initial LevelLow if TnOC = 0

Output Togglewith TnAF flag

He�e TnIO1� TnIO0 = 11Toggle Output Sele�t

Now TnIO1� TnIO0 = 10 A�tive High Output Sele�t

TnPAU �it

Resu�eStop

Ti�e

TnPF notgene�ated

No TnAF flaggene�ated on CCRA ove�flow

Output doesnot �hange

CCRA = 0

Output inve�tswhen TnPOL is high

TnPOL �it

TnCCLR = 1; TnM[1� 0] = 00

Output �ont�olled �yothe� pin-sha�ed fun�tion

Output not affe�ted �yTnAF flag �e�ains Highuntil �eset �y TnON �it

Counte� Value

Compare Match Output Mode – TnCCLR=1

Note:1.WithTnCCLR=1,aComparatorAmatchwillclearthecounter2.TheTMoutputpiniscontrolledonlybytheTnAFflag3.TheoutputpinisresettoitsinitialstatebyaTnONbitrisingedge4.TheTnPFflagisnotgeneratedwhenTnCCLR=15.n=0,1,2,3,5

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Timer/Counter ModeToselectthismode,bitsTnM1andTnM0intheTMnC1registershouldbesetto11respectively.TheTimer/CounterModeoperates in an identicalway to theCompareMatchOutputModegeneratingthesameinterruptflags.TheexceptionisthatintheTimer/CounterModetheTMoutputpin isnotused.Therefore theabovedescriptionandTimingDiagramsfor theCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.

PWM Output ModeToselectthismode,bitsTnM1andTnM0intheTMnC1registershouldbesetto10respectively.ThePWMfunctionwithintheTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol, illuminationcontroletc.Byprovidingasignalof fixedfrequencybutofvaryingdutycycleontheTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.In thePWMmode, theTnCCLRbithasnoeffectonthePWMoperation.Bothof theCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrol thedutycycle.Whichregister isusedtocontroleitherfrequencyordutycycle isdeterminedusing theTnDPXbit in theTMnC1register.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.

Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.TheTnOCbitintheTMnC1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoTnIO1andTnIO0bitsareusedtoenablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.TheTnPOLbitisusedtoreversethepolarityofthePWMoutputwaveform.

10-bit CTM, PWM Mode, Edge-aligned Mode, TnDPX=0

CCRP 001b 010b 011b 100b 101b 110b 111b 000bPe�iod 1�8 �5� 384 51� �40 7�8 89� 10�4Duty CCRA

If fSYS=16MHz,TMclocksourceisfSYS/4,CCRP=100bandCCRA=128,

TheCTMPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=7.8125kHz,duty=128/512=25%.

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.


CCRP 001b 010b 011b 100b 101b 110b 111b 000bPe�iod CCRADuty 1�8 �5� 384 51� �40 7�8 89� 10�4

ThePWMoutputperiod isdeterminedbytheCCRAregistervalue togetherwith theTMclockwhilethePWMdutycycleisdefinedbytheCCRPregistervalue.

Rev. 1.30 7� De�e��e� 1�� 01� Rev. 1.30 73 De�e��e� 1�� 01�




CCRP 1~255 0Pe�iod CCRP×�5� �553�Duty CCRA

If fSYS=16MHz,TMclocksourceisfSYS/4,CCRP=2andCCRA=128,

TheCTMPWMoutput frequency=(fSYS/4)/(2×256)=fSYS/2048=7.8125 kHz, duty=128/(2×256)=25%.

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.


CCRP 1~255 0Pe�iod CCRADuty CCRP×�5� �553�

ThePWMoutputperiod isdeterminedbytheCCRAregistervalue togetherwith theTMclockwhilethePWMdutycycleisdefinedbythe(CCRP×256)exceptwhentheCCRPvalueisequalto0.

Counte� Value

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM O/P Pin(TnOC=1)

Ti�e

Counte� �lea�ed �y CCRP

Pause Resu�e Counte� Stop if TnON �it low

Counte� Reset when TnON �etu�ns high

TnDPX = 0; TnM [1:0] = 10

PWM Duty Cy�le set �y CCRA

PWM �esu�es ope�ation

Output �ont�olled �y othe� pin-sha�ed fun�tion Output Inve�ts

when TnPOL = 1PWM Pe�iod set �y CCRP

TM O/P Pin(TnOC=0)

PWM Mode – TnDPX=0

Note:1.HereTnDPX=0–CounterclearedbyCCRP2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesevenwhenTnIO[1:0]=00or014.TheTnCCLRbithasnoinfluenceonPWMoperation5.n=0,1,2,3,5

Rev. 1.30 74 De�e��e� 1�� 01� Rev. 1.30 75 De�e��e� 1�� 01�



Counte� Value

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM O/P Pin(TnOC=1)

Ti�e

Counte� �lea�ed �y CCRA

Pause Resu�e Counte� Stop if TnON �it low

Counte� Reset when TnON �etu�ns high

TnDPX = 1; TnM [1:0] = 10

PWM Duty Cy�le set �y CCRP

PWM �esu�es ope�ation

Output �ont�olled �y othe� pin-sha�ed fun�tion Output Inve�ts

when TnPOL = 1PWM Pe�iod set �y CCRA

TM O/P Pin(TnOC=0)

PWM Mode – TnDPX=1

Note:1.HereTnDPX=1–CounterclearedbyCCRA2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesevenwhenTnIO[1:0]=00or014.TheTnCCLRbithasnoinfluenceonPWMoperation5.n=0,1,2,3,5

Buzzer control

Buzze�

HT45FM�C

10-�it CTMTM�

The10-bitCTMcandriveanexternalbuzzerusingitsPWMmodetoprovidevolumecontrol.

Rev. 1.30 74 De�e��e� 1�� 01� Rev. 1.30 75 De�e��e� 1�� 01�



Capture Timer Module – CAPTMTheCaptureTimerModule isa timingunitspecificallyusedforMotorControlpurposes.TheCAPTMiscontrolledbyaprogramselectableclocksourceandbythreeinterruptsourcesfromthemotorpositioninghallsensors.

Capture Timer OverviewAtthecoreoftheCaptureTimerisa16-bitcount-upcounterwhichisdrivenbyauserselectableinternalclocksourcewhichissomemultipleofthesystemclockorbythePWM.Thereisalsoaninternalcomparatorwhichcompares thevalueof this16-bitcounterwithapre-programmed16-bitvaluestoredin tworegisters.Thereare twobasicmodesofoperation,aCompareModeandaCaptureMode,eachofwhichcanbeusedtoresettheinternalcounter.Whenacomparematchsituationisreachedasignalwillbegeneratedtoreset theinternalcounter.Thecountercanalsobeclearedwhenacapturetrigger isgeneratedbythethreeexternalsources,INT0A,INT0BandINT0C.

NoiseFilte�

x3

Rising/Falling/Dou�le edge

Dete�to�

Co�pa�e Registe�CAPTMAH/CAPTMAL

�o�pa�e

CAPTMCH/CAPTMCL

Clea� �aptu�e �ounte�

CLR CapTM_Ove�

CapTM_C�p

INT0A

INT0B

INT0C

CAPS1/CAPS0

16-bitCAPTM

CLK

CAPTCK[�:0]

PWMOfSYS/�

fSYS/1�8fSYS/�4

Ha_Int Hb_Int Hc_Int

Rising/Falling/Dou�le edge

Dete�to�

HaHbHc

Capture Timer Block Diagram

Capture Timer Register Description OveralloperationoftheCaptureTimeriscontrolledusingeightregisters.Areadonlyregisterpairexiststostoretheinternalcounter16-bitvalue,whilearead/writeregisterpairexiststostoretheinternal16-bitcomparevalue.Anadditionalreadonlyregisterpairisusedtostorethecapturevalue.Theremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodes.

Rev. 1.30 7� De�e��e� 1�� 01� Rev. 1.30 77 De�e��e� 1�� 01�



Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0CAPTC0 CAPTPAU CAPTCK� CAPTCK1 CAPTCK0 CAPTON — CAPS1 CAPS0CAPTC1 CAPEG1 CAPEG0 CAPEN CAPNFT CAPNFS CAPFIL CAPCLR CAMCLR

CAPTMDL D7 D� D5 D4 D3 D� D1 D0CAPTMDH D15 D14 D13 D1� D11 D10 D9 D8CAPTMAL D7 D� D5 D4 D3 D� D1 D0CAPTMAH D15 D14 D13 D1� D11 D10 D9 D8CAPTMCL D7 D� D5 D4 D3 D� D1 D0CAPTMCH D15 D14 D13 D1� D11 D10 D9 D8

Capture Timer Register List

CAPTC0 Register

Bit 7 6 5 4 3 2 1 0Na�e CAPTPAU CAPTCK� CAPTCK1 CAPTCK0 CAPTON — CAPS1 CAPS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit 7 CAPTPAU:CAPTMCounterPauseControl0:Run1:Pause

Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheCAPTMwillremainpowerupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain

Bit 6~4 CAPTCK2~CAPTCK0:SelectCAPTMCounterclock000:PWMO001:fH/2010:fH/4011:fH/8100:fH/16101:fH/32110:fH/64111:fH/128

ThesethreebitsareusedtoselecttheclocksourcefortheCAPTM.TheclocksourcefHisthehighspeedsystemoscillator.

Bit 3 CAPTON:CAPTMCounterOn/OffControl0: Off1:On

Thisbitcontrols theoverallon/off functionof theCAPTM.Setting thebithighenablesthecountertorun,clearingthebitdisablestheCAPTM.Clearingthisbit tozerowillstopthecounterfromcountingandturnofftheCAPTMwhichwillreduceitspowerconsumption.When thebitchangesstate fromlowtohigh the internalcountervaluewillberesettozero,howeverwhenthebitchangesfromhightolow,theinternalcounterwillretainitsresidualvalue.

Bit2 Unimplemented,readas"0"Bit1~0 CAPS1~CAPS0: capturesourceselect

00:INT0A01:INT0B10:INT0C11:Unused

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CAPTC1 Register

Bit 7 6 5 4 3 2 1 0Na�e CAPEG1 CAPEG0 CAPEN CAPNFT CAPNFS CAPFIL CAPCLR CAMCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit 7~6 CAPEG1~CAPEG0:DefinesCAPTMcaptureactiveedge00:DisabledCAPTMcapture01:Risingedgecapture10:Fallingedgecapture11:Dualedgecapture

Bit 5 CAPEN:CAPTMCaptureinputcontrol0:Disable1:Enable

Thisbitenables/disablestheCAPTMcaptureinputsource.Bit 4 CAPNFT:DefinesCAPTMNoiseFiltersampletimes

0:Twice1:4times

TheCAPTMNoiseFiltercircuit requiressampling twiceor4 timescontinuously,when theyareall thesame, thesignalwillbeacknowledged.Thesample time isdecidedbyCAPNFS.

Bit 3 CAPNFS:CAPTMNoiseFilterclocksourceSelect0: tSYS

1:4tSYS

TheclocksourceforCaptureTimerModuleCounterisprovidedbyfSYS or fSYS /4.Bit 2 CAPFIL:CAPTMcaptureinputfilterControl

0:Disable1:Enable

Thisbitenables/disablestheCAPTMcaptureinputfilter.Bit1 CAPCLR:CAPTMCountercaptureauto-resetControl

0:Disable1:Enable

Thisbit enables/disables the automatic reset of the counterwhen thevalue inCAPTMDLandCAPTMDHhave been transferred into the capture registersCAPTMCLandCAPTMCH.

Bit 0 CAMCLR:CAPTMCountercomparematchauto-resetControl0:Disable1:Enable

Thisbitenables/disablestheautomaticresetofthecounterwhentheacomparematchhasoccurred.

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CAPTMDL Register


Bit 7~0 CAPTMDL:CAPTMCounterLowByteRegisterbit7~bit0CAPTM16-bitCounterbit7~bit0

CAPTMDH Register


Bit 7~0 CAPTMDH:CAPTMCounterHighByteRegisterbit7~bit0CAPTM16-bitCounterbit15~bit8.

CAPTMAL Register


Bit 7~0 CAPTMAL:CAPTMCompareLowByteRegisterbit7~bit0CAPTM16-bitCompareRegisterbit7~bit0.

CAPTMAH Register

Bit 7 6 5 4 3 2 1 0Na�e D15 D14 D13 D1� D11 D10 D9 D8R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit 7~0 CAPTMAH:CAPTMCompareHighByteRegisterbit7~bit0CAPTM16-bitCompareRegisterbit15~bit8.

CAPTMCL Register

Bit 7 6 5 4 3 2 1 0Na�e D7 D� D5 D4 D3 D� D1 D0R/W R R R R R R R RPOR x x x x x x x x

"x"unknownBit 7~0 CAPTMCL:CAPTMCaptureLowByteRegisterbit7~bit0

CAPTM16-bitCaptureRegisterbit7~bit0

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CAPTMCH Register

Bit 7 6 5 4 3 2 1 0Na�e D15 D14 D13 D1� D11 D10 D9 D8R/W R R R R R R R RPOR x x x x x x x x

"x"unknownBit 7~0 CAPTMCH:CAPTMCaptureHighByteRegisterbit7~bit0

CAPTM16-bitCaptureRegisterbit15~bit8.

Capture Timer OperationTheCaptureTimerisusedtodetectandmeasureinputsignalpulsewidthsandaperiods.ItcanbeusedinbothaCaptureorCompareMode.Thetimerinputsare thethreecaptureinputsINT0A,INT0BandINT0C.Eachof thesecapture inputshas itsownedgedetectorselection, tochoosebetweenhigh,loworbothedgetriggertypes.

TheCAPTONbitisusedtocontroltheoverallCaptureTimerenable/disablefunction.DisablingtheCaptureModulewhennotusedwillreducethedevicepowerconsumption.Additionallythecaptureinputcontrol isenabled/disabledusingtheCAPENcontrolbit.ThetriggeredgeoptionaresetupusingtheCAPEG1andCAPEG0bits,toselecteitherpositiveedge,negativeedgeorbothedges.

Capture Mode OperationThecapturetimermodulecontains2captureregisters,CAPTMCLandCAPTMCH,whichareusedtostorethepresentvalueinthecounter.WhentheCaptureModuleisenabled,theneachtimeanexternalpinreceivesavalidtriggersignal,thecontentofthefreerunning16-bitcounter,whichiscontainedintheCAPTMDLandCAPTMDHregisters,willbecapturedintothecaptureregisters,CAPTMCLandCAPTMCH.When thisoccurs, theCAPOF interrupt flagbit in the interruptcontrolregisterwillbeset.Ifthisinterruptisenabledbysettingtheinterruptenablebit,CAPOE,high,aninterruptwillbegenerated.IftheCAPCLRbitissethigh,thenthe16-bitcounterwillbeautomaticallyresetafteracaptureeventoccurs.

Compare Mode OperationWhenthetimerisusedinthecomparemode,theCAPTMALandCAPTMAHregistersareusedtostorethe16-bitcomparevalue.Whenthefreerunningvalueofthecount-up16-bitcounterreachesavalueequaltotheprogrammedvaluesinthesecompareregisters,theCAPCFinterruptflagwillbesetwhichwillgenerateaninterruptifitsrelatedinterruptenablebitisset.IftheCAMCLRbitissethigh, thenthecounterwillbereset tozeroautomaticallywhenacomparematchconditionoccurs.Therotorspeedorastalledmotorconditioncanbedetectedbysettingthecompareregisterstocomparethecapturedsignaledgetransitiontime.Ifarotorstallconditionoccurs,thenacompareinterruptwillbegenerated,afterwhichthePWMmotordrivecircuitcanbeshutdowntopreventamotorburnoutsituation.

Noise FilterThetimeralsoincludesanoiseFilterwhichisusedtofilteroutunwantedglitchesorpulsesonthetriggerinputpins.ThisfunctionisenabledusingtheCAPFILbit.Ifthenoisefilterisenabled,thecaptureinputsignalsmustbesampledeither2or4times,inordertorecognizeanedgeasavalidcaptureevent.Thesampling2or4timeunitsarebasedoeithertSYSor4×tSYSdeterminedusingtheCAPNFSbit.

Rev. 1.30 80 De�e��e� 1�� 01� Rev. 1.30 81 De�e��e� 1�� 01�



I/P

O/P

Noise Filte�

Sa�pling

Noise Filter with CAPNFT and CATNFS = 0

Infrared ReceiverThedevicecontainsafunctionblocktoreceivesignalsfrominfraredremotecontrols.Thesecircuitsassistwiththeimplementationofintegratedremotecontrolfunctionsforremotemotorcontrol.

Functional DescriptionTheinfraredreceiverfunctionalblockcontainsanumberofunitstofacilitatetheimplementationofinfraredsignaldecodingsuchasIRcodereceivercircuit,noisefilter,RMTcapturecircuitandRMTEcontrol.

Noise Filte�

IO CKT

IR RX CKT

IR TX:SC5104

8-�itx� RMT

RMT0FRMTVFRMT1FRMT0RMT1

RMTE_CTL

RMTE

IR_RX Blo�k

10-�it CTMCTM_Int

RX_IN

RX_Int

Infrared Receiver Block Diagram

TheexternalRX_INpinisconnectedtoaninternalfiltertoreducethepossibilityofunwantedeventcountingeventsorinaccuratepulsewidthmeasurementsduetoadversenoiseorspikesontheRX_INinputsignal.InordertoensurethattheIRCodeRxcircuitandthemotorcontrolcircuitworksnormally.

TheRMTCapturecircuitisimplementedusingtwo8-bitRMTcircuits,RMT0andRMT1registerstodecodeIR.AstheIRcodecanbetransmittedrepeatedly,theRMTEcontrolcircuitcanmakethedecodingtimeshortandreducetheeffectswhichgeneratedbytheremotecontrollingonthemotorcontrolling.Thenoisefiltercircuit isaI/Ofilteringsurgecomparewhichcanfiltermicro-secondgradesharp-noise.

Antinoisepulsewidthmaximum:(NF_VIH[5:0]-NF_VIL[5:0])×5μs

Rev. 1.30 80 De�e��e� 1�� 01� Rev. 1.30 81 De�e��e� 1�� 01�



RMT Timing

Noise FilterAnoisefiltercircuitisincludedtoreducethepossibilityofnoisespikesorerroneoussignalinputsbeingdecodedasgenuineinputssignals.

Dat_In

Dat_Out

Noise Filte�Dat_In Dat_Out

NF_VIH[4:0] NF_VIL[4:0]

Noise Filter

Noise Filter Registers Description

NF_VIH Register

Bit 7 6 5 4 3 2 1 0Na�e NF_BYPS — — D4 D3 D� D1 D0R/W R/W — — R/W R/W R/W R/W R/WPOR 0 — — 1 1 0 0 1

Bit 7 NF_BYPS:BypassNoiseFilterEnable0:Disable1:Enable,Dat_Out=Dat_In

Bit6~5 Unimplemented,readas"0"Bit4~0 NF_VIHBit4~Bit0

NF_VIL Register

Bit 7 6 5 4 3 2 1 0Na�e — — — D4 D3 D� D1 D0R/W — — — R/W R/W R/W R/W R/WPOR — — — 0 1 0 1 0

Bit7~5 Unimplement,readas"0"Bit4~0 NF_VILBit4~Bit0

Rev. 1.30 8� De�e��e� 1�� 01� Rev. 1.30 83 De�e��e� 1�� 01�



Remote Control Timer – RMTThedevicecontains two8-bitRMTtimerfunctionswhichareusedforIRsignaldecoding.Thisfunctioncanbeusedtoallowremotecontrollerstochangetherequiredmotoroperatingmode.

TheRemoteControlTimercandetectanedge transitionon theRX_INpin,afterwhich threeinterrupt.

signalscanbegenerated.Theseare,risingedgeinterruptsignal,fallingedgeinterruptsignalanda timeroverflowinterruptsignal.Thecontrolregisters,RMT0andRMT1,areusedtostore thecaptureddatawhichmeasurestheinfraredinputsignaledgeintervalchanges.TherecordeddatacanthenbeusedforIRdecodingpurposes.

TheapplicationprogramcanbeusedtodecodetheIRcodeframedatainthefollowingways:

• Disabling the RMTE

WhenanIRdataframehasbeendecodedbytheprogram,thentheRMTcanbedisabledbythefollowing:RME=0→RMTE=0.

• Enabling the RMTE

Use the10-bitCTMas the IRDecodescan restartmechanism to improve themotorcontrolefficiency.

♦S/WMode:RMEissettohighbytheS/W.

♦H/WMode:whenaCTM_IntisdetectedbytheH/W(about0.3s~1s),thensetRMTE.

Note:fTBCisselectedastheCTMclocksourcebyS/WandadjustedusingtheTBCregister.

CTM_Int/RME_Reg

RMTE

RME_Reg

0.3se�~1se�

Hardware Mode

Rev. 1.30 8� De�e��e� 1�� 01� Rev. 1.30 83 De�e��e� 1�� 01�



RMT Register DescriptionThreeregistersareusedforoverallcontroloftheRemoteControlTimer.Acontrolregister,RMTC,isusedtosetupthetimer,whileregisters,RMT0andRMT1,areusedtostorethedecodedsignaldata.

RMTC Register

Bit 7 6 5 4 3 2 1 0Na�e RMS1 RMS0 RMCS RME ERMTV ERMT1 ERMT0 RMEMSR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit 7~6 RMS1, RMS0:SelectstheRemoteControlTimerclock00: fX/25

01:fX/26

10:fX/27

11:fX/28

Bit 5 RMCS:SelectstheRemoteControlTimerclocksourcefX0: fsys/41:fsys

Bit 4 RME:Controlstheremotecontroltimer0:Disableandclearcounterto01:Enableandstartcounting

Bit 3 ERMTV:ControlstheRemoteControlTimeroverflowinterrupt0:Disable1:Enable

Bit 2 ERMT1:ControlstheRemoteControlTimerfallingedgeinterrupt0:Disable1:Enable

Bit1 ERMT0:ControlstheRemoteControlTimerrisingedgeinterrupt0:Disable1:Enable

Bit 0 RMEMS:RMTECircuitModeSelect0:S/WMode,RMTEstartcircuitisdefinedbyRMEbitviaS/W1:H/WMode,RMTEstartcircuitisdefinedbyCTMinterruptviaH/W

RMT0 Register


Bit 7~0 RMT0:lowleveledgecaptureregisterBit7~Bit0

RMT1 Register


Bit 7~0 RMT1:highleveledgecaptureregisterBit7~Bit0

Rev. 1.30 84 De�e��e� 1�� 01� Rev. 1.30 85 De�e��e� 1�� 01�



Analog to Digital ConverterTheneedtointerfacetorealworldanalogsignals isacommonrequirementformanyelectronicsystems.However, toproperlyprocess these signalsbyamicrocontroller, theymust firstbeconverted intodigitalsignalsbyA/Dconverters.By integrating theA/Dconversionelectroniccircuitryintothemicrocontroller,theneedforexternalcomponentsisreducedsignificantlywiththecorrespondingfollow-onbenefitsoflowercostsandreducedcomponentspacerequirements.ThisdevicealsoincludessomespecialA/Dfeaturesforspecificuseinmotorcontrolapplications.

A/D OverviewThisdevicecontainsa9-channelanalogtodigitalconverter,8-channelcanbedirectlyinterfacetoexternalanalogsignals,suchasthatfromsensorsorothercontrolsignalsandconvertthesesignalsdirectlyintoeithera10-bitdigitalvalue.Anadditionalchannelisconnectedtotheexternalcurrentsense inputpin, Is,viaan internaloperationalamplifier forsignalamplification,beforebeingtransferredtotheA/Dconverterinput.Asetofwhatareknownashighandlowboundaryregisters,allowtheA/Dconverterdigitaloutputvaluetobecomparedwithupperandlowerlimitvaluesandacorrespondinginterrupttobegenerated.AnadditionaldelayfunctionallowsadelaytobeinsertedintothePWMtriggeredA/Dconversionstartprocesstoreducethepossibilityoferroneousanalogvaluesamplingwhentheoutputpowertransistorsareswitchinglargemotorcurrents.

Input Channels A/D Channel Select Bits Input Pins9 ACS3~ACS0 AN0~AN7� Is

TheaccompanyingblockdiagramshowstheoverallinternalstructureoftheA/Dconverter,togetherwithitsassociatedregisters.

ADRH

ADRL

ADHVDH

ADHVDL

ADLVDH

ADLVDL

ADCHVE

ADCLVE

High Bounda�y Value

Low Bounda�y Value

Co�pa�ison Type Cont�ol Bits

Int_AHL_Li�Inte��upt Signal

ADC

Int_AD_EOC

EOCB �it

Co�pa�e Conve�tedValue with Uppe� and

Lowe� Li�its

ADDL

Delay Registe�

MUX

ADSTS �it

Sta�t Conve�tDelay Ti�e

ADSTR �it

PWM Pe�iodInte��upt signal

PWM dutyInte��upt signal

MUX

PWIS �it

A/D Conve�sionSta�t Signal

DLSTR �itDelay on/off �ont�ol

P�og�a��a�le Gain A�plifie�

PB3/Is Cu��ent Sense Pin Input

OPAVS0

OPAVS�Gain Cont�ol BitsGain = X1/X5/X10/X�0

ACS3~ACS0

PA3/AN3

PA5/AN5PA�/AN�PA7/AN7

PA0/AN0PA1/AN1PA�/AN�

PA4/AN4AD

HL/LVT�igge�

A/D Converter Structure

Rev. 1.30 84 De�e��e� 1�� 01� Rev. 1.30 85 De�e��e� 1�� 01�



A/D Converter Register DescriptionOveralloperationoftheA/Dconverteriscontrolledusingseveralregisters.AreadonlyregisterpairADRL/ADRHexiststostoretheADCdata10-bitvalue.TheADLVDL/ADLVDHandADHVDL/ADHVDHregistersareusedtostoretheboundarylimitvaluesoftheADCinterrupttriggerwhiletheADDLregister isused tosetup thestartconversiondelay time.TheremainingregistersarecontrolregisterswhichsetuptheoperatingandcontrolfunctionoftheA/Dconverter.

Register NameBit

7 6 5 4 3 2 1 0ADRL D7 D� D5 D4 D3 D� D1 D0ADRH — — — — — — D9 D8ADCR0 ADSTR EOCB ADOFF — ACS3 ACS� ACS1 ACS0ADCR1 ADSTS DLSTR PWIS ADCHVE ADCLVE ADCK� ADCK1 ADCK0ANCSR0 PCR7 PCR� PCR5 PCR4 PCR3 PCR� PCR1 PCR0ANCSR1 — — — — — — — PCR8ADDL D7 D� D5 D4 D3 D� D1 D0ADLVDL D7 D� D5 D4 D3 D� D1 D0ADLVDH — — — — — — D9 D8ADHVDL D7 D� D5 D4 D3 D� D1 D0ADHVDH — — — — — — D9 D8

A/D Converter Register List

A/D Converter Data Registers – ADRL, ADRHAsthisdevicecontainsaninternal10-bitA/Dconverter, itrequirestwodataregisterstostoretheconvertedvalue.Theseareahighbyteregister,knownasADRH,andalowbyteregister,knownasADRL.After theconversionprocess takesplace, these registerscanbedirectly readby themicrocontrollertoobtainthedigitisedconversionvalue.

ADRL Register

Bit 7 6 5 4 3 2 1 0Na�e D7 D� D5 D4 D3 D� D1 D0R/W R R R R R R R RPOR x x x x x x x x

"x"unknownBit7~0 A/DLowByteRegisterBit7~Bit0

ADRH Register

Bit 7 6 5 4 3 2 1 0Na�e — — — — — — D9 D8R/W — — — — — — R RPOR — — — — — — x x

"x"unknownBit7~2 Unimplemented,readas"0"

Bit1~0 A/DHighByteRegisterBit1,Bit0

Rev. 1.30 8� De�e��e� 1�� 01� Rev. 1.30 87 De�e��e� 1�� 01�



A/D Converter Control Registers – ADCR0, ADCR1, ANCSR0, ANCSR1, ADDLTocontrolthefunctionandoperationoftheA/Dconverter,fourcontrolregistersknownasADCR0,ADCR1,ANCSR0andANCSR1areprovided.These8-bitregistersdefinefunctionssuchas theselectionofwhichanalogchannel isconnected to the internalA/Dconverter, thedigitiseddataformat, theA/Dclocksourceaswellascontrolling thestart functionandmonitoring theA/Dconverterendofconversionstatus.TheACS3~ACS0bitsintheADCR0registerdefinetheADCinputchannelnumber.Asthedevicecontainsonlyoneactualanalogtodigitalconverterhardwarecircuit,eachoftheindividual9analoginputsmustberoutedtotheconverter.ItisthefunctionoftheACS3~ACS0bitstodeterminewhichanalogchannelinputpinsorIspinisactuallyconnectedtotheinternalA/Dconverter.

TheANCSR0andANCSR1controlregisterscontainthePCR8~PCR0bitswhichdeterminewhichpinsonPortAorPB3isusedasanaloginputsfortheA/DconverterinputandwhichpinsarenottobeusedastheA/Dconverterinput.SettingthecorrespondingbithighwillselecttheA/Dinputfunction,clearingthebit tozerowillselecteither theI/Oorotherpin-sharedfunction.Whenthepin isselected tobeanA/Dinput, itsoriginal functionwhether it isanI/Oorotherpin-sharedfunctionwillberemoved.Inaddition,anyinternalpull-highresistorsconnectedtothesepinswillbeautomaticallyremovedifthepinisselectedtobeanA/Dinput.

TheADDLregisterexiststostoretheADCdelaystarttime.

ADCR0 Register

Bit 7 6 5 4 3 2 1 0Na�e ADSTR EOCB ADOFF — ACS3 ACS� ACS1 ACS0R/W R/W R R/W — R/W R/W R/W R/WPOR 0 1 1 — 0 0 0 0

Bit 7 ADSTR:StarttheA/Dconversion0→1→0:Start0→1:ResettheA/DconverterandsetEOCBto“1”

ThisbitisusedtoinitiateanA/Dconversionprocess.Thebitisnormallylowbutifsethighandthenclearedlowagain,theA/Dconverterwillinitiateaconversionprocess.WhenthebitissethightheA/Dconverterwillbereset.

Bit 6 EOCB:EndofA/Dconversionflag0:A/Dconversionended1:A/Dconversioninprogress

ThisreadonlyflagisusedtoindicatewhenanA/Dconversionprocesshascompleted.Whentheconversionprocessisrunning,thebitwillbehigh.

Bit 5 ADOFF:ADCmodulepoweron/offcontrolbit0:ADCmodulepoweron1:ADCmodulepoweroff

Thisbitcontrols thepowerto theA/Dinternalfunction.ThisbitshouldbeclearedtozerotoenabletheA/Dconverter.IfthebitissethighthentheA/Dconverterwillbeswitchedoffreducingthedevicepowerconsumption.AstheA/Dconverterwillconsumealimitedamountofpower,evenwhennotexecutingaconversion,thismaybeanimportantconsiderationinpowersensitivebatterypoweredapplications.Note:1.itisrecommendedtosetADOFF=1beforeenteringIDLE/SLEEPModefor

savingpower.2.ADOFF=1willpowerdowntheADCmodule.

Bit4 Unimplemented,readas"0"

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Bit 3~0 ACS3 ~ ACS0:SelectA/Dchannel0000:AN00001:AN10010:AN20011:AN30100:AN40101:AN50110:AN60111:AN71000:Iscurrrentsenseinput-viaamplifier

ThesearetheA/Dchannelselectcontrolbits.AsthereisonlyoneinternalhardwareA/DconvertereachoftheeightA/Dinputsmustberoutedtotheinternalconverterusingthesebits.

ADCR1 Register

Bit 7 6 5 4 3 2 1 0Na�e ADSTS DLSTR PWIS ADCHVE ADCLVE ADCK� ADCK1 ADCK0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit 7 ADSTS:SelectADCtriggercircuit0:SelectADSTRtriggercircuit1:SelectDELAYtriggercircuit

Bit 6 DLSTR:Delaystartfunctioncontrol0:DisablebutneedtosetADDLto"0"1:EnablebutneedtosetADDLtononzerovalue

Bit 5 PWIS:SelectPWMModuleinterruptsource0:SelectPWMperiodinterrupt1:SelectPWMdutyinterrupt

Bit 4~3 ADCHVE~ADCLVE:SelectADCinterrupttriggersource00:ADLVD[9:0]<ADR[9:0]<ADHVD[9:0]01:ADR[9:0]<=ADLVD[9:0]10:ADR[9:0]>=ADHVD[9:0]11:ADR[9:0]<=ADLVD[9:0]orADR[9:0]>=ADHVD[9:0]

Bit 2~0 ADCK2~ADCK0:SelectADCclocksource000: fSYS

001:fSYS/2010:fSYS/4011:fSYS/8100:fSYS/16101:fSYS/32110:fSYS/64111:Undefined

ThesethreebitsareusedtoselecttheclocksourcefortheA/Dconverter.

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ANCSR0 Register

Bit 7 6 5 4 3 2 1 0Na�e PCR7 PCR� PCR5 PCR4 PCR3 PCR� PCR1 PCR0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 1 1 1 1 1 1 1 1

Bit 7 PCR7:A/Dinputpinselect0:NotA/Dinput1:A/Dinput,AN7






Bit1 PCR1:A/Dinputpinselect0:NotA/Dinput1:A/Dinput,AN1


ANCSR1 Register

Bit 7 6 5 4 3 2 1 0Na�e — — — — — — — PCR8R/W — — — — — — — R/WPOR — — — — — — — 1

Bit7~1 Unimplemented,readas"0"Bit 0 PCR8:A/Dinputpinselect

0:NotA/Dinput1:A/Dinput,Isinput,AN8

ADDL Register


Bit7~0 ADCDelay-TimeregisterBit7~Bit0Delay-TimeValue(countbysystemclock)

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A/D Converter Boundary Registers – ADLVDL, ADLVDH, ADHVDL, ADHVDH

ThedevicecontainswhatareknownasboundaryregisterstostorefixedvaluesforcomparisonwiththeA/DconverterconvertedvaluestoredinADRLandADRH.Thereare twopairsofregisters,ahighboundarypair,knownasADHVDLandADHVDHanda lowboundarypairknownasADLVDLandADLVDH.

ADLVDL Register


Bit7~0 ADCLowBoundaryLowByteRegisterBit7~Bit0

ADLVDH Register


Bit7~2 Unimplemented,readas"0"Bit1~0 ADCLowBoundaryHighByteRegisterBit1,Bit0

ADHVDL Register


Bit7~0 ADCHighBoundaryLowByteRegisterBit7~Bit0

ADHVDH Register


"x"unknownBit7~2 Unimplemented,readas"0"Bit1~0 ADCHighBoundaryHighByteRegisterBit1~Bit0

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A/D OperationTherearetwowaystoinitiateanA/DConverterconversioncycle,selectedusingtheADSTSbit.Thefirstof theseis tousetheADSTRbit intheADCR0registerusedtostartandreset theA/Dconverter.Whenthemicrocontrollerprogramsets thisbit fromlowtohighandthenlowagain,ananalogtodigitalconversioncyclewillbeinitiated.WhentheADSTRbit isbroughtfromlowtohighbutnotlowagain,theEOCBbitintheADCR0registerwillbesethighandtheanalogtodigitalconverterwillbereset.Thesecondmethodof initiatingaconversion is touese thePWMinterruptsignal.Thiscanbesourcedfromeither thePWMperiodorduty interruptsignal,selectedusing thePWISbit.TheDLSTRbitcanactivateadelayfunctionwhichinsertsadelaytimebetweentheincomingPWMinterruptsignalandtheactualstartoftheA/Dconversionprocess,withtheactualtimebeingsetupusingtheADDLregister.Theactualdelaytimeiscalculatedbytheregistercontentmultipliedbythesystemclockperiod.ThedelaybetweenthePWMinterruptandthestartoftheA/Dconversionistoreducethepossibilityoferroneousanalogsamplesbeingtakenduringthetimeoflargetransientcurrentswitchingbythemotordrivetransistors.Notethat if theDLSTRbitselectsnodelaytheADDLregistermustbeclearedtozeroandvice-versaifthedelayisselected,thenanon-zerovaluemustbeprogrammedintotheADDLregister.TheEOCBbit in theADCR0register isused to indicatewhentheanalogtodigitalconversionprocess iscomplete.Thisbitwillbeautomatically set tozeroby themicrocontroller afteraconversioncyclehasended.Inaddition, thecorrespondingA/Dinterruptrequestflagwillbesetintheinterruptcontrolregister,andif theinterruptsareenabled,anappropriateinternalinterruptsignalwillbegenerated.ThisA/Dinternal interruptsignalwilldirect theprogramflowto theassociatedA/Dinternal interruptaddressforprocessing.If theA/Dinternal interrupt isdisabled,themicrocontrollercanbeusedtopolltheEOCBbitintheADCR0registertocheckwhetherithasbeenclearedasanalternativemethodofdetectingtheendofanA/Dconversioncycle.TheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockfSYS,canbechosentobeeither fSYSorasubdividedversionof fSYS.Thedivisionratiovalue isdeterminedby theADCK2~ADCK0bitsintheADCR1register.AlthoughtheA/Dclocksourceisdeterminedbythesystemclocky,fSYS,andbybitsADCK2~ADCK0,therearesomelimitationsonthemaximumA/Dclocksourcespeed thatcanbeselected.As theminimumvalueofpermissibleA/Dclockperiod, tADCK, is0.5μs,caremustbe takenforsystemclockfrequenciesequal toorgreater than4MHz.Forexample,ifthesystemclockoperatesatafrequencyof4MHz,theADCK2~ADCK0bitsshouldnotbesetto“000”.DoingsowillgiveA/DclockperiodsthatarelessthantheminimumA/DclockperiodwhichmayresultininaccurateA/Dconversionvalues.Refertothefollowingtableforexamples,wherevaluesmarkedwithanasterisk*showwhere,dependinguponthedevice,specialcaremustbetaken,asthevaluesmaybelessthanthespecifiedminimumA/DClockPeriod.

fSYS

A/D Clock Period (tADCK)ADCK2, ADCK1, ADCK0

=000 (fSYS)

ADCK2, ADCK1, ADCK0

=001 (fSYS/2)

ADCK2, ADCK1, ADCK0

=010 (fSYS/4)

ADCK2, ADCK1, ADCK0

=011 (fSYS/8)

ADCK2, ADCK1, ADCK0

=100 (fSYS/16)

ADCK2, ADCK1, ADCK0

=101 (fSYS/32)

ADCK2, ADCK1, ADCK0

=110 (fSYS/64)

ADCK2, ADCK1, ADCK0

=111

5MHz �00ns* 400ns* 800ns 1.6μs 3.2μs 6.4μs 12.8μs Undefined10MHz 100ns* �00ns* 400ns* 800ns 1.6μs 3.2μs 6.4μs Undefined�0MHz 50ns* 100ns* �00ns* 400ns* 800ns 1.6μs 3.2μs Undefined

A/D Clock Period Examples

Controlling thepoweron/off functionof theA/Dconvertercircuitry is implementedusing theADOFFbitintheADCR0register.ThisbitmustbezerotopowerontheA/Dconverter.EvenifnopinsareselectedforuseasA/DinputsbyclearingthePCR7~PCR0bitsintheANCSR0registerandPCR8intheANCSR1register, if theADOFFbitiszerothensomepowerwillstillbeconsumed.InpowerconsciousapplicationsitisthereforerecommendedthattheADOFFissethightoreducepowerconsumptionwhentheA/Dconverterfunctionisnotbeingused.

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Theboundary registerpairs,ADHVDL/ADHVDHandADLVDL/ADLVDHcontainpresetvalueswhichcanbecomparedwiththeA/DconvertedvaluesintheADRL/ADRHregisters.VarioustypesofcomparisonscanbemadeasdefinedbytheADCLVEandADCHVEbitsandaninterruptgeneratedtoinformthesystemthateitherthelowerorhigherboundaryhasbeenexceeded.Thisfunctioncanbeusedtoensurethatthemotorcurrentoperateswithinsafeworkinglimits.

A/D Input PinsAlloftheA/Danaloginputpinsarepin-sharedwiththeI/OpinsonPortAaswellasotherfunctions.ThePCR7~PCR0bits intheANCSR0registerandPCR8bit in theANCSR1register,determinewhether the inputpinsare setupasA/Dconverter analog inputsorwhether theyhaveotherfunctions.IfthePCR8~PCR0bitsforitscorrespondingpinissethighthenthepinwillbesetuptobeanA/Dconverterinputandtheoriginalpinfunctionsdisabled.Inthisway,pinscanbechangedunderprogramcontroltochangetheirfunctionbetweenA/Dinputsandotherfunctions.Allpull-highresistors,whicharesetupthroughregisterprogramming,willbeautomaticallydisconnectedifthepinsaresetupasA/Dinputs.NotethatitisnotnecessarytofirstsetuptheA/DpinasaninputinthePACorPBCportcontrolregisterstoenabletheA/DinputaswhenthePCR8~PCR0bitsenableanA/Dinput,thestatusoftheportcontrolregisterwillbeoverridden.

Summary of A/D Conversion StepsThefollowingsummarisestheindividualstepsthatshouldbeexecutedinordertoimplementanA/Dconversionprocess.

• Step1SelecttherequiredA/DconversionclockbycorrectlyprogrammingbitsADCK2~ADCK0intheADCR1register.

• Step 2EnabletheA/DbyclearingtheADOFFbitintheADCR0registertozero.

• Step 3SelectwhichchannelistobeconnectedtotheinternalA/DconverterbycorrectlyprogrammingtheACS3~ACS0bitswhicharealsocontainedintheADCR0register.

• Step 4SelectwhichpinsaretobeusedasA/DinputsandconfigurethembycorrectlyprogrammingthePCR7~PCR0bitsintheANCSR0registerandPCR8intheANCSR1.

• Step 5Selectwhich triggercircuit is tobeusedbycorrectlyprogramming theADSTSbits in theADCR1.

• Step 6If theinterruptsare tobeused, theinterruptcontrolregistersmustbecorrectlyconfiguredtoensuretheA/Dconverterinterruptfunctionisactive.Themasterinterruptcontrolbit,EMI,andtheA/Dconverterinterruptbit,AEOCE,mustbothbesethightodothis.

• Step 7If thestep5selectsADSTRtriggercircuit, theanalog todigitalconversionprocesscanbeinitialisedbysettingtheADSTRbitintheADCR0registerfromlowtohighandthenlowagain.Notethatthisbitshouldhavebeenoriginallyclearedtozero.Ifthestep5selectsPWMinterrupttriggerDelaycircuit, theDelaystartfunctioncanbeenabledbysettingtheDLSTRbit intheADCR1register.

• Step 8Tocheckwhentheanalogtodigitalconversionprocessiscomplete,theEOCBbitintheADCR0

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registercanbepolled.Theconversionprocessiscompletewhenthisbitgoeslow.WhenthisoccurstheA/DdataregisterADRLandADRHcanbereadtoobtaintheconversionvalue.Asanalternativemethod,iftheinterruptsareenabledandthestackisnotfull,theprogramcanwaitforanA/Dinterrupttooccur.Note:Whencheckingfortheendoftheconversionprocess,ifthemethodofpollingtheEOCBbitintheADCR0registerisused,theinterruptenablestepabovecanbeomitted.

Theaccompanyingdiagramshowsgraphicallythevariousstagesinvolvedinananalogtodigitalconversionprocessanditsassociatedtiming.AfteranA/Dconversionprocesshasbeeninitiatedby theapplicationprogram, themicrocontroller internalhardwarewillbegin tocarryout theconversion,duringwhichtimetheprogramcancontinuewithotherfunctions.ThetimetakenfortheA/Dconversionis16tADCKwheretADCKisequaltotheA/Dclockperiod.

0 1 2 3 4 10 11 12

Tdeo�

ADCLK

START

EOCB

D[5:0]

TdoutADON

T�kl T�khTadc

k

Tst

Tsta�t

Ton

000H

Toff

A/D Conversion Timing

Programming ConsiderationsDuringmicrocontrolleroperationswhere theA/Dconverter isnotbeingused, theA/Dinternalcircuitrycanbeswitchedoff to reducepowerconsumption,bysettingbitADOFFhigh in theADCR0register.Whenthishappens, theinternalA/Dconvertercircuitswillnotconsumepowerirrespectiveofwhatanalogvoltageisappliedtotheirinputlines.IftheA/DconverterinputlinesareusedasnormalI/Os,thencaremustbetakenasiftheinputvoltageisnotatavalidlogiclevel,thenthismayleadtosomeincreaseinpowerconsumption.

A/D Transfer FunctionAsthedevicecontainsa10-bitA/Dconverter, itsfull-scaleconverteddigitisedvalueisequal to3FFH.Sincethefull-scaleanaloginputvalueisequal to theVDDvoltage, thisgivesasinglebitanaloginputvalueofVDDdividedby1024.

1LSB=VDD÷1024

TheA/DConverterinputvoltagevaluecanbecalculatedusingthefollowingequation:

A/Dinputvoltage=A/Doutputdigitalvalue×VDD ÷1024

Thediagramshowsthe ideal transferfunctionbetweentheanaloginputvalueandthedigitisedoutputvaluefor theA/Dconverter.Exceptfor thedigitisedzerovalue, thesubsequentdigitisedvalueswillchangeatapoint0.5LSBbelowwheretheywouldchangewithouttheoffset,andthelastfullscaledigitisedvaluewillchangeatapoint1.5LSBbelowtheVDDlevel.

Rev. 1.30 9� De�e��e� 1�� 01� Rev. 1.30 93 De�e��e� 1�� 01�



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� � � � � � � � � � � � ��

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Ideal A/D Transfer Function

A/D Programming ExampleThefollowingtwoprogrammingexamplesillustratehowtosetupandimplementanA/Dconversion.Inthefirstexample, themethodofpollingtheEOCBbit intheADCR0registerisusedtodetectwhentheconversioncycleiscomplete,whereasinthesecondexample,theA/Dinterruptisusedtodeterminewhentheconversioniscomplete.

Example: using an EOCB polling method to detect the end of conversionclr AEOCE ;disableADCinterruptmov a,03Hmov ADCR1,a ;selectfSYS/8asA/Dclockclr ADOFFmov a,0Fh ;setupANCSR0andANCSR1toconfigurepinsAN0~AN3mov ANCSR0,amov a,00hmov ANCSR1,amov a,00hmov ADCR0 ;enableandconnectAN0channeltoA/Dconverter:start_conversion: clrADSTR ;highpulseonstartbittoinitiateconversion setADSTR ;resetA/D clrADSTR ;startA/Dpolling_EOC: sz EOCB ;polltheADCR0registerEOCBbittodetectend ;ofA/Dconversion jmppolling_EOC ;continuepolling mova,ADRL ;readlowbyteconversionresultvalue movADRL_buffer,a ;saveresulttouserdefinedregister mova,ADRH ;readhighbyteconversionresultvalue movADRH_buffer,a ;saveresulttouserdefinedregister::jmp start_conversion ;startnexta/dconversion

Example: using the interrupt method to detect the end of conversionclr MF1E ;disableADCinterruptCLR AEOCEmov a,03H

Rev. 1.30 94 De�e��e� 1�� 01� Rev. 1.30 95 De�e��e� 1�� 01�



mov ADCR1,a ;selectfSYS/8asA/DclockClr ADOFFmov a,0Fh ;setupANCSR0andANCSR1toconfigurepinsAN0~AN3mov ANCSR0,amov a,00hmov ANCSR1,amov a,00hmov ADCR0,a ;enableandconnectAN0channeltoA/DconverterStart_conversion: clrADSTR ;highpulseonSTARTbittoinitiateconversion setADSTR ;resetA/D clrADSTR ;startA/D clrAEOCF ;clearADCinterruptrequestflag setAEOCE ;enableADCinterrupt setMF1E ;enableMulti_interrupt1 setEMI ;enableglobalinterrupt:: ; ADC interrupt service routineADC_ISR: movacc_stack,a ;saveACCtouserdefinedmemory mova,STATUS movstatus_stack,a ;saveSTATUStouserdefinedmemory:: mova,ADRL ;readlowbyteconversionresultvalue movadrl_buffer,a ;saveresulttouserdefinedregister mova,ADRH ;readhighbyteconversionresultvalue movadrh_buffer,a ;saveresulttouserdefinedregister::EXIT_INT_ISR: mova,status_stack movSTATUS,a ;restoreSTATUSfromuserdefinedmemory mova,acc_stack ;restoreACCfromuserdefinedmemory reti

Rev. 1.30 94 De�e��e� 1�� 01� Rev. 1.30 95 De�e��e� 1�� 01�



Over-current DetectionThedevice contains an fully integratedover-current detect circuitwhich isused formotorprotection.

+_

OPCM

Int_IsIs

OPA : Av=1/5/10/20

DAC8-bit

OPA

Comparator 0

Int_AD_EOC

Int_AHL_ LimADC

ADR

EOC

AD HL/LVTrigger

IntTrigger

C0BPE

ADLVD/ADHVD

Over-current Detector Block Diagram

Over-current Functional DescriptionTheover-currentfunctionalblockincludesanamplifier,10-bitA/DConverter,8-bitD/AConverterandcomparator.Ifanover-currentsituationisdetectedthenthemotorexternaldrivecircuitcanbeswitchedoff immediately topreventdamagetothemotor.Twokindsof interruptsaregeneratedwhichcanbeusedforover-currentdetection. 1.A/DConverterinterrupt-Int_AHL_Lim

2.Comparator0interrupt-Int_Is

Over-current Register DescriptionTherearethreeregisterstocontrolthefunctionandoperationoftheovercurrentdetectioncircuits,knownasOPOMS,OPCMandOPACAL.These8-bitregistersdefinefunctionssuchastheOPAoperationmodeselection,OPAcalibrationandcomparison.OPCMisan8-bitDACregisterusedforOPAcomparison.

Rev. 1.30 9� De�e��e� 1�� 01� Rev. 1.30 97 De�e��e� 1�� 01�



OPOMS Register

Bit 7 6 5 4 3 2 1 0Na�e CMP0_EG1 CMP0_EG0 — — — OPAVS� OPAVS1 OPAVS0R/W R/W R/W — — — R/W R/W R/WPOR 0 0 — — — 0 1 0

Bit 7~6 CMP0_EG1, CMP0_EG0:DefinesComparatoractiveedge00:DisableComparator0andDAC001:Risingedge10:Fallingedge11:Dualedge

Bit5~3 Unimplemented,readas"0"Bit 2~0 OPAVS2~OPAVS0:OPAAvmodeselect

000:DisableOPA001:Av=5010:Av=10011:Av=20111:AV=1

OPCM Register


Bit7~0 8-bitOPAcomparisonregisterbit7~bit0

OPACAL Register

Bit 7 6 5 4 3 2 1 0Na�e — ARS AOFM AOF4 AOF3 AOF� AOF1 AOF0R/W R R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 1 0 0 0 0

Bit7 Unimplemented,readas"0"Bit 6 ARS:Comparatorinputoffsetcalibrationreferenceselect

0:Comparatornegativeinput1:Comparatorpositiveinput

Bit 5 AOFM:NormalorCalibrationModeselect0:OpamporComparatorMode1:OffsetCalibrationMode

Bit 4~0 AOF4~AOF0:Comparatorinputoffsetvoltagecalibrationcontrol00000:Minimum10000:Center11111:Maximum

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Linear Hall Sensor DetectionThemotorpositionisdetectedusingHallSensorsforwhichthedeviceincludescircuitrytoprocesssignalsfromthesesensors.

Int_AD_EOCInt_AHL_ LimADCHb

ADR

EOC

AD HL/LVTrigger

8bitDAC

+

_

Comparator 1

Int_HbDet

Ha

Hc

HACM

IntTrigger

C1BPE

ADLVD/ADHVD

ACS[3:0]

Hall Sensor Detector Block Diagram

Hall Sensor Detection Function DescriptionThesignalsfromtheexternallinearHallSensorsaremonitoredusingtheinternal8-bitDAC,theinternal10-bitADCandinternalcomparator1.ThemotorpositionismonitoredbytwointerruptsInt_HbDetorInt_AHL_Limwhichareenabled/disabledbytheLHMCandHACMregisters.ThesixsteprotationalchangeofstateofthemotorpositioncanbetrackedbysettingtheDACdataandtheLHMCregister,tocontrolthemotordirectionandspeed,asshowninthefigure.

SHa

SHb

SHc

4V

2.5V

1V

HL/Hb

S1 S2 S3 S4 S5 S6 S1 S2 S3

linear Hall Sensor Output

Rev. 1.30 98 De�e��e� 1�� 01� Rev. 1.30 99 De�e��e� 1�� 01�



Linear Hall Sensor Control Register DescriptionTheLHMCisthelinearHallsensorModecontrolregisterandtheHACMisthe8-bitDACregisterforLinearHallSensorcomparison.

LHMC Register

Bit 7 6 5 4 3 2 1 0Na�e — — CMP1_EG1 CMP1_EG0 — — C1BPE C0BPER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas"0"Bit 5~4 CMP1_EG1, CMP1_EG0:DefinesComparatoractiveedge

00:DisableComparator1andDAC101:Risingedge10:Fallingedge11:Dualedge

Bit3~2 Unimplemented,readas"0"Bit1 C1BPE:Comparator1InterruptBypass(testoption)

0:DisableComparator1interrupt1:EnableComparator1interrupt

Bit 0 C0BPE:Comparator0InterruptBypass(testoption)0:DisableComparator0interrupt1:EnableComparator0interrupt

HACM Register


Bit7~0 8-bitLinearHallSensorcomparisonregisterbit7~bit0

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BLDC Motor Control CircuitThissectionsdescribeshowthedevicecanbeused tocontrolBrushlessDCMotors,otherwiseknownasBLDCMotors.Itshighleveloffunctionalintegrationandflexibilityofferafullrangeofdrivingfeaturesformotordriving.

Functional DescriptionThePWMcountercircuitoutputPWMOishasanadjustablePWMDutytocontroltheoutputmotorpowerthuscontrollingthemotorspeed.ChangingthePWMfrequencycanbeusedtoenhancethemotordriveefficiencyortoreducenoiseandresonancegeneratedduringphysicalmotoroperation.

The internalMaskcircuit isused todeterminewhichPWMmodulationsignalsareenabledordisabledfor themotorspeedcontrol.ThePWMmodulationsignalcanbeoutputboththeupperarms,GAT/GBT/GCTandthelowerarms,GAB/GBB/GCB,oftheexternalGateDriverTransistorPairsundersoftwarecontrol.TheDead-TimeinsertioncircuitisusedtoensuretheupperandlowerGateDriverTransistorPairsarenotenabledsimultaneouslytopreventtheoccurrenceofavirtualpowershortcircuit.Thedeadtimeisselectedundersoftwarecontrol.

TheStaggeredcircuitcanforceall theoutputs toanoffstatus if thesoftwaredetectsanerrorconditionwhichcouldbeduetoexternalfactorssuchasESDproblemsorbothupperandlowerexternalGateDriverTransistorpairsbeingsimultaneouslyon.ThePolaritycircuitcanselect theoutputpolarityoftheBLDCmotoroutputcontrolporttosupportmanydifferenttypesofexternalMOSgatedrivedevicecircuitcombinations.

TheMotorProtectcircuit includesmanydetectioncircuits for functionssuchasamotorstallcondition,overcurrentprotection,externaledgetriggeredPausepin,external level triggerFaultpinetc.TheHallSensorDecodercircuitisasix-stepsystemwhichcanbeusedcontrolthemotordirection.

Twelveregisters,eachusing6bits,areusedtocontrolthedirectionofthemotor.Themotorforward,backward,brakeandfreefunctionsarecontrolledbytheHDCD/HDCRregisters.TheHa/Hb/HcorSHA/SHB/SHCcanbeselectedastheHallSensorDecodercircuitinputs.

v

v

GAT

GAB

GBT

GBB

GCT

GCB

IR�101 x3Gate D�ive�HT45FM�C

MAT

MAB

MBT

MBB

MCT

MCB

VCCM

PB3/Is

INT0A

INT0B

INT0C

Fault

Pause

Rev. 1.30 100 De�e��e� 1�� 01� Rev. 1.30 101 De�e��e� 1�� 01�



BLDC Application Circuit

10-bit PWMcounter

CKT

PWMR

Fpwm

PWMOPWMP_Int

PWMD_Int

MPTC1

Mask

GATGABGBTGBBGCTGCB

Fault

Over Current Protection

Stall ProtectionS/W

Pause

PWMB

MCF DTSPWMCDUTR PRDR PLC

HDCD

HCHBHA

SHASHBSHC

SASBSC

HDMS

0

1

HallSensorDcoder

12x6 Register

HDCR FRSBRKE

MotorProtectCKT

HATHABHBT HBBHTHHCB

PROTECT

HD_EN

PWMComplement Polarity

DeadTimeInsert

StallCircuit

AT2AB2BT2BB2CT2CB2

AT0AB0BT0BB0CT0CB0

AT1AB1BT1BB1CT1CB1

BRKE

MCD

MPTC2

Hall Noise Filter Hall

DelayCKT

HCHK_NUM HNF_MSEL

CTM16-Int

HDLY_MSEL CTM_SEL[1:0]

BLDC Motor Control Block Diagram

PWM Counter Control Circuit Thedeviceincludesa10-bitPWMgenerator.ThePWMsignalhasbothadjustabledutycycleandfrequencythatcanbesetupbyprogramming10-bitvaluesintothecorrespondingPWMregisters.

10-bit PWMcounter

CKT

PWMR

fPWM

PWMO

PWMP_Int

PWMD_Int

PWMCDUTR PRDR

PWM Block Diagram

Rev. 1.30 100 De�e��e� 1�� 01� Rev. 1.30 101 De�e��e� 1�� 01�



PWM Register DescriptionOverallPWMoperationiscontrolledbyaseriesofregisters.TheDUTRL/DUTRHregisterpairisusedforPWMdutycontrol foradjustmentof themotoroutputpower.ThePRDRL/PRDRHregisterpairareusedtogethertoforma10-bitvaluetosetupthePWMperiodforPWMFrequencyadjustment.BeingabletochangethePWMfrequencyisusefulformotorcharacteristicmatchingforproblemssuchasnoisereductionandresonance.ThePWMRL/PWMRHregistersareusedtomonitorthePWMcounterdynamically.ThePWMONbitinthePWMCregisteristhe10-bitPWMcounteron/offbit.ThePWMclocksourceforthePWMcountercanbeselectedbyPCKS1~PCKS0bitsinthePWMCregister.ItshouldbenotedthattheorderofwritingdatatoPWMregisterisMSB.

PWMC Register

Bit 7 6 5 4 3 2 1 0Na�e — — PCKS1 PCKS0 PWMON — — GATSELR/W — — R/W R/W R/W — — R/WPOR — — 0 0 0 — — 0

Bit7~6 Unimplemented,readas"0"Bit 5~4 PCKS1, PCKS0:ClocksourceofthePWMcounterselect

000: fPWM,PWMfrequencyMin.=20kHz,fPWMbaseon20MHz001:fPWM/2,PWMfrequencyMin.=10kHz010:fPWM/4,PWMfrequencyMin.=5kHz011:fPWM/8,PWMfrequencyMin.=2.5kHz

Bit 3 PWMON:PWMCircuitOn/Offcontrol0: Off1:On

Thisbitcontrolstheoverallon/offfunctionofthePWM.Settingthebithighenablesthecounter torun,clearingthebitdisablesthePWM.Clearingthisbit tozerowillstopthecounterfromcountingandturnoff thePWMwhichwill reduceitspowerconsumption.

Bit2~1 Unimplemented,readas"0"Bit 0 GATSEL:GATEDriveroutputselect

0:GAT/GAB/GBT/GBB/GCT/GCBareusedforGatedriveroutputpins1:GAT/GAB/GBT/GBB/GCT/GCBareusedasPC[5:0]

DUTRL Register


Bit7~0 10-bitPWMDutyregisterlowbyteregisterbit7~bit010-bitDUTRregisterbit7~bit0

Rev. 1.30 10� De�e��e� 1�� 01� Rev. 1.30 103 De�e��e� 1�� 01�



DUTRH Register


Bit7~2 Unimplemented,readas"0"Bit1~0 10-bitPWMDutyregisterhighbyteregisterbit1~bit0

10-bitDUTRregisterbit9~bit8

PRDRL Register


Bit7~0 10-bitPWMPeriodregisterlowbyteregisterbit7~bit010-bitPRDRregisterbit7~bit0

PRDRH Register


Bit7~2 Unimplemented,readas"0"Bit1~0 PWMPeriodhighbyteregisterBit1~Bit0

10-bitDUTRregisterBit9~Bit8

PWMRL Register


Bit7~0 10-bitPWMCounterregisterlowbyteregisterBit7~Bit010-bitPWMCounterBit7~Bit0

PWMRH Register

Bit 7 6 5 4 3 2 1 0Na�e — — — — — — D9 D8R/W — — — — — — R RPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 10-bitPWMCounterregisterhighbyteregisterBit1~Bit0

PWM10-bitCounterBit9~Bit8

Rev. 1.30 10� De�e��e� 1�� 01� Rev. 1.30 103 De�e��e� 1�� 01�



Mask FunctionThedeviceincludesaMotorControlMaskFunctionforincreasedcontrolflexibility.

Pola�ity

PWMBIR�101x3

Gate D�ive�

MAT

MAB

MBT

MBB

MCT

MCB

PWMO

Hall Senso� De�ode�1�x�

HAT/HAB/HBT/HBB/HCT/HCB

Mask

GAT

GAB

GBT

GBB

GCT

GCB

MCF DTS PLC

DeadTi�eInse�t

Stagge�ed�i��uit

AT�

AB�

BT�

BB�

CT�

CB�

AT0

AB0

BT0

BB0

CT0

CB0

AT1

AB1

BT1

BB1

CT1

CB1

MCD

BRKE PROTECT

Mask Function Block Diagram

Moto�

U

V

W

Powe� MOS

Moto HV

MAT MBT MCT

MAB MBB MCB

Mask Switching

Functional DescriptionTheinternalMASKcircuithasthreeoperationmodes,whichareknownastheNormalMode,BrakeModeandMotorProtectMode.

• NormalMode

IntheNormalMode,themotorspeedcontrolmethodisdeterminedbythePWMS/MPWEbitsintheMCFregister.

WhenPWMS=0,thebottomportPWMoutputselectstransistorpairbottomarmGAB/GBB/GCB.

WhenPWMS=1,thetopportPWMoutputselectstransistorpairtoparm,GAB/GBB/GCB.

WhenMPWE=0,thePWMoutputisdisabledandAT0/BT0/CT0/AB0/BB0/CB0areallon.

WhenMPWE=1, thePWMoutput isenabledandAT0/BT0/CT0/AB0/BB0/CB0canoutputavariablePWMsignalforspeedcontrol.

WhenMPWMS=0,thePWMhasaComplementaryoutput

WhenMPWMS=1,thePWMhasaNon-complementaryoutput

Rev. 1.30 104 De�e��e� 1�� 01� Rev. 1.30 105 De�e��e� 1�� 01�



Complementary control, MPWMS=0

PWMS=0

HAT HAB AT0 AB0

PWMS=1

HAT HAB AT0 AB00 0 0 0 0 0 0 0

0 1 PWMB PWMO 0 1 0 1

1 0 1 0 1 0 PWMO PWMB

1 1 0 0 1 1 0 0

PWMS=0

HBT HBB BT0 BB0

PWMS=1

HBT HBB BT0 BB00 0 0 0 0 0 0 0

0 1 PWMB PWMO 0 1 0 1

1 0 1 0 1 0 PWMO PWMB

1 1 0 0 1 1 0 0

PWMS=0

HCT HCB CT0 CB0

PWMS=1

HCT HCB CT0 CB00 0 0 0 0 0 0 0

0 1 PWMB PWMO 0 1 0 1

1 0 1 0 1 0 PWMO PWMB

1 1 0 0 1 1 0 0

Non-complementary control, MPWMS=1

PWMS=0

HAT HAB AT0 AB0

PWMS=1

HAT HAB AT0 AB00 0 0 0 0 0 0 0

0 1 0 PWMO 0 1 0 1

1 0 1 0 1 0 PWMO 0

1 1 0 0 1 1 0 0

PWMS=0

HBT HBB BT0 BB0

PWMS=1

HBT HBB BT0 BB00 0 0 0 0 0 0 0

0 1 0 PWMO 0 1 0 1

1 0 1 0 1 0 PWMO 0

1 1 0 0 1 1 0 0

PWMS=0

HCT HCB CT0 CB0

PWMS=1

HCT HCB CT0 CB00 0 0 0 0 0 0 0

0 1 0 PWMO 0 1 0 1

1 0 1 0 1 0 PWMO 0

1 1 0 0 1 1 0 0

• BrakeModeTheBrakeModehasthehighestpriority.Whenactivated,theexternalGateDriverTransistorPairToparmwillbeoffandtheBottomarmwillbeon.TheBrakeTruthdecodetableisshownbelow.

BRKE=1AT0 BT0 CT0 AB0 BB0 CB0 1 0

0 0 0 1 1 1 D9 D8

Rev. 1.30 104 De�e��e� 1�� 01� Rev. 1.30 105 De�e��e� 1�� 01�



• MotorProtectMode

WhentheMotorProtectModeisactivated,theexternalGateDriverTransistorPaircanselectthebrake,wherethetoparmisoffandthebottomarmison,orselectfreerunningwherethetopandbottomarmarebothoff.Theprotectiondecodetableisshownbelow.

PROTECT =1 GAT GBT GCT GAB GBB GCB

FMOS=0 0 0 0 0 0 0FMOS=1 0 0 0 1 1 1

For6-Stepcommunication,iftheUwindingandWwindingareonthenturnofftheVwinding.

IfGAT=1andGAB=0,turnontheUwinding

IfGBT=0andGBB=0,turnofftheVWinding.

IfGCT=PWMDandGCB=PWM,turnontheWwindingandadjusttheoutputpowerofthemotorusingtheDUTRregistertocontrolthespeed.

HT45FM�C

MATMAB

MBTMBB

MCTMCB

IR�101x3

GATGABGBTGBBGCTGCB

Drive Signal Block Diagram

v

v

U

V W

Moto HV

MAT

MBT MCT

MAB

MBB MCB

Moto HV Moto HV

1

0

0

0

PWMD

PWM

Current direction

Motor

Motor Winding Connection

Rev. 1.30 10� De�e��e� 1�� 01� Rev. 1.30 107 De�e��e� 1�� 01�



Register DescriptionThedevicehastworegistersconnectedwiththeMaskFunctioncontrol.ThesearetheMCFregisterwhichisusedforcontrolandtheMCDregisterwhichisusedtoreadthestatusofthegatedriveroutputs.

MCF Register

Bit 7 6 5 4 3 2 1 0Na�e — — — — MPWMS MPWE FMOS PWMSR/W — — — — R/W R/W R/W R/WPOR — — — — 0 1 0 0

Bit7~4 Unimplemented,readas"0"Bit 3 MPWMS:MaskPWMModeselect

0:Complementary1:Non-complementary

Bit 2 MPWE:PWMoutputcontrol0:PWMoutputdisable(AT0/BT0/CT0/AB0/BB0/CB0cannotoutputPWM)1:PWMoutputenable(AT0/BT0/CT0/AB0/BB0/CB0canoutputPWMtocontrolspeed)

Bit1 FMOS:FaultMaskoutputselect0:AT0/BT0/CT0=0,AB0/BB0/CB0=01:AT0/BT0/CT0=0,AB0/BB0/CB0=1

Bit 0 PWMS:Topport/BottomportPWMselect0:SelectBottomportPWMoutput1:SelectTopportPWMoutput

MCD Register

Bit 7 6 5 4 3 2 1 0Na�e — — GAT GAB GBT GBB GCT GCBR/W — — R R R R R RPOR — — 0 0 0 0 0 0

Bit7~6 Unimplemented,readas"0"Bit 5~0 GAT/GAB/GBT/GBB/GCT/GCB: Gatediveroutputmonitor

Rev. 1.30 10� De�e��e� 1�� 01� Rev. 1.30 107 De�e��e� 1�� 01�



Other FunctionsSeveralotherfunctionsexistforadditionalmotorcontroldrivesignalflexibility.ThesearetheDeadTimeFunction,StaggeredFunctionandPolarityFunction.

PolarityPWMB IR2101x3

GateDriver

MATMABMBTMBBMCTMCB

PWMO

HallSensorDecoder12x6 HAT/

HAB/HBT/HBB/HCT/HCB

Mask

GATGABGBTGBBGCTGCB

MCF DTS PLC

DeadTimeInsert

Staggered

Circuit

AT2AB2BT2BB2CT2CB2

AT0AB0BT0BB0CT0CB0

AT1AB1BT1BB1CT1CB1

MCD

BRKE PROTECT

Dead Time, Staggered and Polarity Function Block Diagram

Dead Time FunctionDuringtransistorpairswitching,theDeadTimefunctionisusedtopreventbothupperandlowertransistorpairsfromconductingat thesametimethuspreventingavirtualshortcircuitconditionfromoccurring.Theactualdeadtimevaluecanbesetuptobewithinavaluefrom0.3μs to5μswhichisselectedbytheapplicationprogram.

TheDeadTimeInsertioncircuitrequiressixindependentoutputcircuits:

• WhentheAT0/AB0/BT0/BB0/CT0/CB0outputsexperiencearisingedge,thenaDeadTimeisinserted.

• WhentheAT0/AB0/BT0/BB0/CT0/CB0outputsexperienceafallingedge,thentheoutputsremainunchanged.

TheDead-TimeInsertionCircuitisonlyduringmotorcontrol.TheDeadTimefunctionisenabled/disabledbytheDTEbitintheDTSregister.

.AT0,AB0,BT0,BB0,CT0,CB0

Dead-Time Insertion

Dead-Time Insertion

Dead-Time Insertion

Dead-Time Insertion1.Rising Add Dead-Time Insertion2.Falling Unchange

AT1,AB1,BT1,BB1,CT1,CB1

Dead Time Insertion Timing

Rev. 1.30 108 De�e��e� 1�� 01� Rev. 1.30 109 De�e��e� 1�� 01�



Asingleregister,DTS,isdedicatedforusebytheDeadTimefunction.

DTS Register

Bit 7 6 5 4 3 2 1 0Na�e DTCKS1 DTCKS0 DTE D4 D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit 7~6 DTCKS1, DTCKS0:Dead-Timeclocksourceselection00: fDTisfSYS,fSYSbasedon20MHz01:fDTisfSYS/210:fDTisfSYS/411:fDTisfSYS/8

Bit 5 DTE:Dead-TimeEnable0:Dead-Time=01:Dead-Time=(DTS[4:0]+1)/fDT

Bit 4~0 D4~D0:Dead-TimeRegisterbit4~bit0Dead-Timecounter.5-bitDead-TimevaluebitsforDead-TimeUnit.Dead-Time=(DTS[4:0]+1)/fDT

Staggered FunctionTheStaggeredFunction isused to forcealloutputdrive transistors toanoffconditionwhenasoftwareerroroccursorduetoexternalfactorssuchasESD.

AT1 AB1 AT2 AB20 0 0 00 1 0 11 0 1 01 1 0 0

ThedefaultconditionfortheBLDCmotorcontrolcircuitisdesignedfordefaultN-typetransistorpairs.Thismeansa“1”valuewillswitchthetransistoronanda“0”valuewillswitchitoff.

Polarity FunctionThis functionallowssetupof theexternalgatedrive transistorOn/Offpolaritystatus.Asingleregister,PLC,isusedforoverallcontrol.

Rev. 1.30 108 De�e��e� 1�� 01� Rev. 1.30 109 De�e��e� 1�� 01�



PLC Register

Bit 7 6 5 4 3 2 1 0Na�e — — PCBC PCTC PBBC PBTC PABC PATCR/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0

Bit7~6 Unimplemented,readas"0"Bit 5 PCBC: CpairBottomportGateoutputinversecontrolBit 4 PCTC: CpairTopportGateoutputinversecontrolBit 3 PBBC: BpairBottomportGateoutputinversecontrolBit 2 PBTC: BpairTopportGateoutputinversecontrolBit1 PABC: ApairBottomportGateoutputinversecontrolBit 0 PATC: ApairTopportGateoutputinversecontrol

Bit Value Status0 Output not inve�ted

1 Output inve�ted

PLC Register Values

NotethatthedefaultoutputpinGAT/GAB/GBT/GBB/GCT/GCBstatusishighimpedance.

Hall Sensor DecoderThisdevicecontainsafullyintegratedHallSensordecoderfunctionwhichinterfacestotheHallSensorsintheBLDCmotorfordirectionalandspeedcontrol.

Hall Sensor Dcoder12x6 Regsietr

HDCD

HC

HB

HA

SHA

SHB

SHC

SA

SB

SC

HDMS

HDCR

FRS

BRKE

HAT

HAB

HBT

HBB

HCT

HCB

Mask

AT0

AB0

BT0

BB0

CT0

CB0

0

1

HDCEN

PWMO

PWMB

BRKE PROTECT

HallNoise Filter

HallDelayCKT

HCHK_NUM HNF_MSEL

CTM-Int x3

HDLY_MSEL CTM_SEL[1:0]

Hall Sensor Decoder Block Diagram

TheHallSensorinputsignalsareselectedbysettingtheHDMSbithigh.IftheHDMSbitiszerothenSHA/SHB/SHCwillbeusedinsteadoftheactualHallSensorsignals.

Rev. 1.30 110 De�e��e� 1�� 01� Rev. 1.30 111 De�e��e� 1�� 01�



Hall Sensor Noise FilterThisdeviceincludesaHallNoiseFilterfunctiontofilterouttheeffectsofnoisegeneratedbythelargeswitchingcurrentsofthemotordriver.ThisgeneratednoisemayaffecttheHallSensorinputs(HA/HB/HC),whichinturnmayresultinincorrectHallSensoroutputdecoding.

Severalregistersareusedtocontrolthenoisefilter.TheHNF_ENbitintheHNF_MSELregisterisusedastheoverallenable/disablebitforthenoisefilter.

HNF_EN bit Status0 Noise Filte� Off – HA/HB/HC not used

1 Noise Filte� On

Hall Sensor Noise Filter Enable

ThesamplingfrequencyoftheHallnoisefilterissetupusingtheHFR_SEL[3:0]bits.

TheHCK_NUM[4:0]bitsareusedtosetuptheHallSensorinputcomparenumbers.

HCK_NUM[4:0]×Samplingspace=Anti-noiseability=HallDelay-Time.

Itshouldbenoted that longerHalldelay timeswill result inhigherrotorspeedfeedbacksignaldistortion.

Hall Sensor Delay FunctionTheHallsensorfunctioninthedeviceincludesaHalldelayfunctionwhichcanimplementasignalphaseforwardorphasebackwardoperation.Thefollowingsteps,whichshouldbeexecutedbeforetheHallDecoderisenabled,showhowthisfunctionisactivated.

• Step1

SettheHallDecodetabletoselecteitherthephaseforwardorphasebackwardfunction.

• Step 2

SelectwhichCTMisused togenerate theDelayTimeandset theselectedCTMto run in theCompareMatchModebyprogrammingtheCTM_SEL1~CTM_SEL0bits.

• Step 3

UsetheHDLY_MSELbit toselect theHallDelaycircuitoperatingmode.ThedefaultvalueofHDLY_MSELiszerowhichwilldisabletheHallDelaycircuit.IftheHDLY_MSELbitissethigh,thentheHallDelaycircuitwillbeenabled.

• Step 4

EnabletheHallDecoderusingtheHDCENbit.

ThefollowingpointsshouldbenotedregardingtheHDLY_MSELbit. ♦ Whenthisbitislow,BUF1[2:0]andBUF2[2:0]willbeclearedtozero. ♦ Whenthisbitislow,TM0/TM1/TM5retaintheiroriginalTMfunctions. ♦ Whenthebitishigh,theCTMwhichisselectedbytheDelayfunctionwillbededicatedforusebytheHallDelaycircuit.

TheoriginalTMfunctionswillstillremainactiveexceptfortheTnONbitwhichwillbecontrolledautomaticallybythehardware.

Rev. 1.30 110 De�e��e� 1�� 01� Rev. 1.30 111 De�e��e� 1�� 01�



WithregardtotheTMfunctionsthefollowingstepsshouldbetakenbeforetheDelayfunctionisenabled.

1.KeepTnONandTnPAU=0

2.TheTMshouldbesetupintheCompareMatchMode

3.TnCCLR=1,thereforetheTMisclearedwithacomparatorAmatchcondition.

4.SetuptheDelaytimeusingTMnAandTnCKx.

AftertheDelayfunctionisenabled,HDLY_MSELwillchangefromlowtohigh.TheDelaytimemustnotbemorethanonesteptimeoftheHallinput,whichhassixsteps,Otherwisetheoutputcannotbeanticipated,willdropoutofstep.

HallSenso�

De�ode�1�x� Registe�

BUF�[�:0]BUF1[�:0]

D

D

D

CTM-1�(TM5)

CTM-10(TM0)

CTM-10(TM1)

HallNoiseFilte�

HDCD

HAHBHC

HDLY_MSEL

HATHABHBTHBBHCTHCB

CTM_SEL[1:0]

SHASHBSHC

HDMS

Hall DELAY Ci��uit

HDCEN

HA0

HB0

HC0

HA1

HB1

HC1

HA�HB�HC�

SASBSC

Delay Function Block Diagram

HA0

HB0

HC0

SA

SB

SC

Delay time

Delay Function Timing

Rev. 1.30 11� De�e��e� 1�� 01� Rev. 1.30 113 De�e��e� 1�� 01�



Motor Control Drive SignalsThedirectionoftheBLDCmotoriscontrolledusingtheHDCR,HDCDregistersandasetofsixHDCTregisters,HDCT0~HDCT11.WhenusingtheHallSensorDecoderfunction, thedirectioncanbedeterminedusingtheFRSbitandthebrakecanbecontrolledusingtheBRKEbit.BothbitsareintheHDCRregister.SixbitsintheHDCT0~HDCT5registersareusedfortheMotorForwardtable,andsixbits intheHDCT6~HDCT11registersareusedfor theMotorBackwardtable.Theaccompanyingtablesshowthetruthtablesforeachoftheregisters.

Fo�wa�d(HDCEN=1�

FRS=0�BRKE=0)

60 degree 120 degree Bit5 Bit4 Bit3 Bit2 Bit1 Bit0SA SB SC SA SB SC HAT HAB HBT HBB HCT HCB1 0 0 1 0 0 HDCT0[5:0]1 1 0 1 1 0 HDCT1[5:0]1 1 1 0 1 0 HDCT�[5:0]0 1 1 0 1 1 HDCT3[5:0]0 0 1 0 0 1 HDCT4[5:0]0 0 0 1 0 1 HDCT5[5:0]

Hall Sensor Decoder Forward Truth Table

Ba�kwa�d(HDCEN=1�

FRS=1�BRKE=0)

60 degree 120 degree Bit5 Bit4 Bit3 Bit2 Bit1 Bit0SA SB SC SA SB SC HAT HAB HBT HBB HCT HCB1 0 0 1 0 0 HDCT�[5:0]1 1 0 1 1 0 HDCT7[5:0]1 1 1 0 1 0 HDCT8[5:0]0 1 1 0 1 1 HDCT9[5:0]0 0 1 0 0 1 HDCT10[5:0]0 0 0 1 0 1 HDCT11[5:0]

Hall Sensor Decoder Backward Truth Table

Thetruthtablesforthebrakefunction,halldecoderdisablefunctionandhalldecodererrorfunctionarealsoshownbelow.

B�ake(BRKE=1�

HDCEN=X�FRS=X)

60 degree 120 degree Bit5 Bit4 Bit3 Bit2 Bit1 Bit0SA SB SC SA SB SC HAT HAB HBT HBB HCT HCB

V V V V V V 0 1 0 1 0 1

Brake Truth Table

Hall De�ode� disa�le

(HDCEN=0)

60 degree 120 degree Bit5 Bit4 Bit3 Bit2 Bit1 Bit0SA SB SC SA SB SC HAT HAB HBT HBB HCT HCBV V V V V V 0 0 0 0 0 0

Hall Decoder Disable Truth Table

Hall De�ode� e��o�(HDCEN=X)

60 degree 120 degree Bit5 Bit4 Bit3 Bit2 Bit1 Bit0SA SB SC SA SB SC HAT HAB HBT HBB HCT HCB1 0 1 1 1 1 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 0 0

Hall Decoder Error Truth Table

Rev. 1.30 11� De�e��e� 1�� 01� Rev. 1.30 113 De�e��e� 1�� 01�



Therelationshipbetween thedata in the truth tablesandhowtheyrelate toactualmotordrivesignalsisshownintheaccompanyingtimingdiagram.Thefull6stepcycleforbothforwardandbackwardmotorrotationisprovided.

S1 S2 S3 S4 S5 S6S1 S2 S3 S4 S5 S6

HAT

SA

SB

Sc

Hall sensor :120 degree Motor Forward

N S

Ha

H� H�

�-pole Moto�

MotorUVW

Moto HV

MAT MBT MCT

MAB MBB MCB

MBT

MBB

MCT

MCB

MAT

MAB

HT45FM2C IR2101x3

HBT

HCT

HBB

HCB

HAB

Motor Drive Signal Timing Diagram - Forward Direction

S1 S2 S3 S4 S5 S6S1 S2 S3 S4 S5 S6

SA

SB

Sc

Hall sensor :120 degree Motor Backward

N S

Ha

H� H�

�-pole Moto�

MotorUVW

Moto HV

MAT MBT MCT

MAB MBB MCB

MBT

MBB

MCT

MCB

MAT

MAB

HT45FM2C IR2101x3HAT

HBT

HCT

HBB

HCB

HAB

Motor Drive Signal Timing Diagram - Backward Direction

Rev. 1.30 114 De�e��e� 1�� 01� Rev. 1.30 115 De�e��e� 1�� 01�



Hall Sensor Decoder Register DescriptionTheHDCRregisteristheHallSensorDecodercontrolregister,HDCDistheHallSensorDecoderinputdataregister,andHDCT0~HDCT11aretheHallSensorDecodertables.TheHCHK_NUMregister is theHallNoiseFilterchecknumberregisterandHNF_MSELis theHallNoiseFilterModeselectregister

HDCR Register

Bit 7 6 5 4 3 2 1 0Na�e CTM_SEL1 CTM_SEL0 HDLY_MSEL HALS HDMS BRKE FRS HDCENR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 1 0 0 0 0

Bit 7~6 CTM_SEL1~CTM_SEL0:CTMTimerselectoftheHallDelayCircuit00:TM5(16-bitCTM)01:TM0(10-bitCTM)10:TM1(10-bitCTM)11:Unused

Bit 5 HDLY_MSEL:HallDelayCircuitselect0:Selectoriginalpath1:SelectHallDelayCircuit

Bit 4 HALS:HallSensorDecoderModeselect0:HallSensor60degree1:HallSensor120degree

Bit 3 HDMS:HallSensorDecoderModeselect0:S/WMode1:HallSensorMode

Bit 2 BRKE:motorbrakecontrol0:GAT/GBT/GCT/GAB/GBB/GCB=V1:GAT/GBT/GCT=0,GAB/GBB/GCB=1

Bit1 FRS:MotorForward/Backwardselect0:Forward1:Backward

Bit 0 HDCEN:HallSensorDecoderenable0:Disable1:Enable

HDCD Register

Bit 7 6 5 4 3 2 1 0Na�e — — — — — SHC SHB SHAR/W — — — — — R/W R/W R/WPOR — — — — — 0 0 0

Bit7~3 Unimplemented,readas"0"Bit 2 SHC:S/WHallCBit1 SHB:S/WHallBBit 0 SHA:S/WHallA

Rev. 1.30 114 De�e��e� 1�� 01� Rev. 1.30 115 De�e��e� 1�� 01�



HDCT11~0 Register

Bit 7 6 5 4 3 2 1 0Na�e — — HATD HABD HBTD HBBD HCTD HCBDR/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0

Bit7~6 Unimplemented,readas"0"Bit 5 HATD:GAToutputstatecontrolBit 4 HABD:GABoutputstatecontrolBit 3 HBTD:GBToutputstatecontrolBit 2 HBBD:GBBoutputstatecontrolBit1 HCTD:GCToutputstatecontrolBit 0 HCBD:GCBoutputstatecontrol

Bit Value Status0 Output is low

1 Output is high

Output Status

HCHK_NUM Register

Bit 7 6 5 4 3 2 1 0Na�e — — — HCK_N4 HCK_N3 HCK_N� HCK_N1 HCK_N0R/W — — — R/W R/W R/W R/W R/WPOR — — — 0 0 0 0 0

Bit7~5 Unimplemented,readas"0"Bit 4~0 HCK_N4~HCK_N0:HallNoiseFilterchecknumber

HNF_MSEL Register

Bit 7 6 5 4 3 2 1 0Na�e — — — — HNF_EN HFR_SEL� HFR_SEL1 HFR_SEL0R/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas"0"Bit 3 HNF_EN:Hallnoisefilterenable

0:Disable(bypass)1:Enable

Bit 2~0 HFR_SEL2~HFR_SEL0:Hallnoisefilterclocksourceselect000:fSYS/2001:fSYS/4010:fSYS/8011:fSYS/16100:fSYS/32101:fSYS/64110:fSYS/128111:Unused

Rev. 1.30 11� De�e��e� 1�� 01� Rev. 1.30 117 De�e��e� 1�� 01�



Motor Protection FunctionMotorsnormallyrequire largecurrentsfor theiroperationandassuchneedtobeprotectedfromtheproblemsofexcessivedrivecurrents,motorstallingetctoreducemotordamageorforsafetyreasons.Thisdeviceincludesarangeofprotectionandsafetyfeatures.

Mask

AT0AB0BT0BB0CT0CB0

MotorProtectCKT

OPA &

CompareCKTIs

CAPTMINT0A

Pause

Fault

MPTC1

INT0BINT0C

PROTECTInt_AHL_Lim

Int_Is

CapTM_Cmp

CapTM_Over

MPTC2

Int_Pau

Int_FLT

Protection Function Block Diagram

Pause

Fault

FLTHE

PSWE

PSWD

D

reset

OPA &

CompareCKT

CAPTM

AHLHE

Int_AHL_Lim

ISHE

Int_Is

CapCHECapTM_Cmp

CapTM_Over

CapOHE

PROTECT

PSWPS=0

PSWPS=1

ISPS=0

CAPCPS=0

CAPOPS=0

ISPS

=1C

AC

PS=1

CA

POPS

=1

PAUHE QPAUTS

EdgeCKT

Int_Pause

Protection Function Control

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Motor Protection Function DescriptionThisdeviceprovidesfivekindsofprotectionfeatures,allowingactiontobetakentoprotect themotorfromdamageortoprovideadditionalsafety.

Theprotectionfeaturesare:

1.AnexternaledgetriggeronthePausepin-edgetrigger

2.AnexternalleveltriggeronFaultpin-leveltrigger

3.Stalldetectionfunction

4.Overcurrentprotection

5.Turnoffthemotorusingsoftware

Whenthemotorprotectioncircuitison,theexternalGateDrivetransistorpaircanbeputintotwodifferentprotectionmodes.ThefirstistheBrakeModewhichiswherethetoparmisoffandthebottomarmison,andthesecondistheFreeRunningModewherebothtopandbottomarmsareoff.TheFMOSbitintheMCFregisterdetermineswhichtypeisused.

Themotorprotectioncircuitoperatesintwomodes,whichisselectedbytheMPTC2register.Onemodeis theFaultModeandtheother isPauseMode.In theFaultMode,activatingtheprotectfunctionisdeterminedbythetriggersourcestartingstatus.Endingtheprotectfunctionisdeterminedby the trigger sourcedisarmingstatus. In thePauseMode, turningon theprotect function isdeterminedbythetriggersource.Endingtheprotectionfunctionisdeterminedbysoftware.

Fault Pin Function TheFaultPinisusedtodetectwhetheranexternalcircuithasdetectedamotorstallorovercurrentcondition.ThepinisaleveltriggertypeandisactivelowandPROTECTis"1".TheFaultpinandPROTECTarecontrolledbyFLTHEbitintheMPTC1register.

Pause Pin Function ThePausepinisusedtodetectwhetheranexternalcircuithasdetectedamotorstallorovercurrentcondition.ThePausepinisedgetriggeredandPROTECTis"1".ItwillcausetheexternalGateDrivertobeshutdown.ThePausepinModeconditionisdeterminedbythePSWD/PSWE/PSWPSbitsandPROTECTis"0", thentheexternalGateDrivercircuit iscontrolledbytheHallSensorDecodercircuit.ThePausepinfunctioniscontrolledbythePAUHEandPAUTSbitsintheMPTC1andMPTC2registers.

Current Protection FunctionAsthedevicecontainsa10-bitA/DConverter,an8-bitD/AConverterandanamplifier,theycanbeusedtogethertomeasurethemotorcurrentandtodetectforexcessivecurrentvalues.Ifanovercurrentsituationshouldoccur, then theexternaldrivecircuitcanbeshutdownimmediately topreventmotordamage.

TheInt_AHL_LiMOShasacurrent limitprotectionmechanism.Disable theH/WModewhenAHLHEis"0"andenable theH/WModewhenAHLHEis"1".The limitedcurrentcircuit isahardwarecircuit, forwhichtheA/Dconverterchannelmustselect theoperationamplifier tobeactive. If there isanovercurrentduringsystemstartup, thenthiscurrent limitcircuitshouldbedisabled.

TheInt_IsMOShasanovercurrentprotectionmechanism.DisabletheH/WModelwhenISHEis"0"andenabletheH/WModewhenISHEis"1".SelecttheFaultModewhenISPSis"0"andselectthePauseModewhenISPSis"1",.

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PWM counter

HAT~HCB x6

S1 S2 S3 S4 S5 S6

15KHz~64 us

GAT~GCB (x6)(PWMO)

TimeInt_ADC

MOS limited current protect：(AHLHE=1;AHLPS=1)Start the next cycle of the PWM output automaticly by hardware

Int_ADC

PWM counter

HAT~HCB x6

S1 S2 S3 S4 S5 S6

15KHz~64 us

GAT~GCB (x6)(PWMO)

TimeInt_CMP

MOS over current protection：(ISHE=1;ISPS=0) Restar the PWM output must by software

Int_CMP

Over Current

Motor Stall Detection FunctionFor3-phaseBLDCapplicationswithHallSensors,the16-bitCAPTMcanbeusedtomonitortheINT0A,INT0BandINT0Cinputsforrotorspeeddetection.TheovercurrentsignalisselectedbytheCAPTMAHandCAPTMALregisterswhichcanmonitor theHallsensor inputpinsINT0A,INT0BandINT0Ctodetect therotorspeed.Whenanovercurrentconditionoccurs,aCapTM_CmporCapTM_Overinterruptwillbegenerated.RefertotheCAPTMchapterfordetails.IntheCapTM_Cmpstalldetectmechanism,disabletheH/WModewhenCapCHEis"0",andenabletheH/WModewhenCapCHEis"1".SelecttheFaultModewhenCAPCPSis"0"andselectthePauseModewhenCAPCPSis"1".

In theCapTM_Overstalldetectmechanism,disable theH/WModewhenCapOHEis"0"andenabletheH/WModewhenCapOHEis"1".SelecttheFaultModewhenCAPOPSis"0"andselectthePauseModewhenCAPOPSis"1".

Motor Protection Circuit Register DescriptionThereare tworegisters,MPTC1andMPTC2,whichareusedfor themotorprotectioncontrolfunction.

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MPTC1 Register

Bit 7 6 5 4 3 2 1 0Na�e PSWD PSWE CapOHE CapCHE ISHE AHLHE PAUHE FLTHER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit 7 PSWD:ProtectS/WModedata0:PSWD=01:PSWD=1

Bit 6 PSWE:ProtectS/WModeenable0:Disable1:Enable

Bit 5 CapOHE:CapTM_OverH/WModeenable0:Disable1:Enable

Bit 4 CapCHE:CapTM_CmpH/WModeenable0:Disable1:Enable

Bit 3 ISHE:Int_IsH/WModeenable0:Disable1:Enable

Bit 2 AHLHE:Int_AHL_LimH/WModeenable0:Disable1:Enable

Bit1 PAUHE:PausePinH/WModeenable0:Disable1:Enable

Bit 0 FLTHE:FaultPinH/WModeenable0:Disable1:Enable

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MPTC2 Register

Bit 7 6 5 4 3 2 1 0Na�e — PAUTS1 PAUTS0 PSWPS AHLPS ISPS CAPCPS CAPOPSR/W R R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 Unimplemented,readas"0"Bit 6~5 PAUTS1~PAUTS0:Pausetriggerselect

00:DisablePauseInt.01:Risingedge10:Fallingedge11:Dualedge

Bit 4 PSWPS:Pause/FaultModeselect0:SelectFaultMode1:SelectPauseMode

Bit 3 AHLPS:Int_AHL_LimPause/FaultModeselect0:SelectFaultMode1:SelectPauseMode

Bit 2 ISPS:Int_IsPause/FaultModeselect0:SelectFaultMode1:SelectPauseMode

Bit1 CAPCPS:CapTM_CmpPause/FaultModeselect0:SelectFaultMode1:SelectPauseMode

Bit 0 CAPOPS:CapTM_OverPause/FaultModeselect0:SelectFaultMode1:SelectPauseMode

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Motor Position Detection MethodsTherearethreemethodsofBLDCmotorpositioningcontrolavailable.TheseareDigitalHallSensorMethod,LinearHallSensorMethodandSensorlessMethod.

Digital Hall Sensor MethodIn thismethod thereare threeexternaldigitaloutputs fromthehallsensors todetect the rotorposition.INT0A,INT0BandINT0Ccandetectrising,fallinganddualedgetriggerinterrupts.ThenumericalchangesfromtheHallsensorsisdetectediscontrolledbytheapplicationprogramandcanbeusedtomonitortherotorposition.HereHA/HB/HCandthe12Halldecoderregistersareusedtocontrolthedirectionofmotor.ThePWMfunctionalblockisusedtocontrolthemotorspeed.

Hall Dete�t INT0[A/B/C]HbHa

Hc

Digital Hall Sensor Method

Linear Hall Sensor Method:InthismethodalinearHallsensortodetecttherotorposition.ThenumericalchangesoftheexternallinearHall sensor ismonitoredby the8-bitDAC,10-bitADCandcomparator1.TheLHMCregister,HACM,andtheInt_HbDetorInt_AHL_Lim,areusedtomonitorthemotorposition.HereSHA/SHB/SHCandthe12Halldecodingregistersareusedtocontrol themotordirection.ThePWMfunctionalblockisusedtocontrolthemotorspeed.

Linea� Hall Dete�tHbInt_HbDet

Int_AHL_ LimADR

Linear Hall Sensor Method

Sensorless MethodIn thismethodthe3channels,AN0/AN1/AN2,of the10-bitA/Dconverter isusedtodetect thechangesinthebackEMFofthethree-phasemotor.ThechangescanbedetectedbytheInt_AD_EOC,Int_AHL_LimandADRL/ADRHregisters.There isasetof16-bitCTMstomonitor thepositionandspeedofthemotor.UseSHA/SHB/SHCandthe12Halldecoderregisterstocontrolthemotordirection.ThePWMfunctionalblockisusedtocontrolthemotorspeed.

EMF Dete�t

Int_AD_EOC

VU

W

Int_AHL_ Lim

ADR

Sensorless Method

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DC Motor ControlThedevicecancontrolmotorsusing1or2pins.TakingtheexampleofDCFanHeadmotorcontrol.a2-pinDCMotorInterfacecancontrolthefanheadmotorspeedanddirection,whilethe1-pinDCMotorInterfacecanonlycontrolthemotorspeed.TheFH_MSbitintheDCMCR1registerisusedtoselecteithera1-pinor2-pinDCMotorInterface.

2-pin DC Motor ControlIn thiscase the2-pinDCMotor interfacecancontrolboth themotorspeedanddirection.AnexternalcircuitusingalimitswitchoraVRcircuitcanbeusedtocontrolthemotordirection.The10-bitCTMoutputPWMOisusedtoadjustthePWMdutycycletocontrolDCmotorspeed.TheDC_MCTLcircuitcontrolstheDCmotordirection.

VDDM=5V

FH0_SAT

FH0_SBT

FH0_RI

FH0_LI

HT45FM2C

10-bit CTMTMR0

PWMO

FH0_FR

FH0_STOP

P P

N N

L_LSW R_LSW

VDDM=5V

FH1_SAT

FH1_SBT

FH1_RI

FH1_LI

10-bit CTMTMR1

PWMO

FH1_FR

FH1_STOP

P P

N N

L_LSW R_LSW

DC_MCTL

DC_MCTL

FH0_PAFH0_PB

FH1_PAFH1_PB

VDDM=5VVDDM=5V

VDDM=5VVDDM=5V

FH_MS

01

10

FH_MS

01

10

1

1

2-Pin DC Motor Interface Application Circuit

TheDCcontrolorderfortheMotordirectionis that themotorshouldbefree(FH[0/1]_STOP)beforeforward(FH[0/1]_FR)andthenchangedirection.It isusedtoadjust theoutputpolarityaccordingtotheexternalgatedriveconfiguration(PtypeorNtype).TheDCFanHeadinterfaceresetdefaultvalue isFH0_SAT=hi-z/FH0_SBT=hi-zandFH1_SAT=hi-z/FH1_SBT=hi-z.

FH[0/1]_STOP FH[0/1]_FR DC_Motor0 1 Fo�wa�d0 0 Ba�kwa�d1 V F�ee

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1-pin DC Motor ControlThe1-pinDCMotor interface isusedonly tocontrol themotorspeed.The10-bitCTMoutputPWMOisusedtoadjustthePWMdutycycletocontroltheDCmotorspeed.Itisusedtoadjusttheoutputpolarityaccordingtotheexternalgatedriveconfiguration(PtypeorNtype).TheDCFanHeadinterfaceresetdefaultvalueisFH1_SAT=hi-z/FH1_SBT=hi-z.

VDDM=5V

P

N

VDDM=5V

P

VDDM=5V

VDDM=5VFH0_SAT

FH0_SBT

FH0_RI

FH0_LI

HT45FM2C

10-bit CTMTMR0

PWMO

FH0_FR

FH0_STOP

FH1_SAT

FH1_SBT

FH1_RI

FH1_LI

10-bit CTMTMR1

PWMO

FH1_FR

FH1_STOP

DC_MCTL

DC_MCTL

FH0_PAFH0_PB

FH1_PAFH1_PBFH_MS

01

10

FH_MS

01

10

1

1

1-Pin DC Motor Interface Application Circuit

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Register DescriptionTworegisters,DCMCR0andDCMCR1areusedforoverallcontrol.

DCMCR0 Register

Bit 7 6 5 4 3 2 1 0Na�e FH1_PB FH1_PA FH0_PB FH0_PA FH1_STOP FH1_FR FH0_STOP FH0_FRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 1 0 1 0

Bit 7 FH1_PB:polarityoutputcontrol0:Non-inverse1:Inverse

Bit 6 FH1_PA:polarityoutputcontrol0:Non-inverse1:Inverse

Bit 5 FH0_PB:polarityoutputcontrol0:Non-inverse1:Inverse

Bit 4 FH0_PA:polarityoutputcontrol0:Non-inverse1:Inverse

Bit 3 FH1_STOP:FANHead1stopenable0:Motornormaloperation1:Motorfreerun

Bit 2 FH1_FR:FANHead1directionselect0:Backward1:Forward

Bit1 FH0_STOP:FANHead0stopenable0:Motornormaloperation1:Motorfreerun

Bit 0 FH0_FR:FANHead0directionselect0:Backward1:Forward

DCMCR1 Register

Bit 7 6 5 4 3 2 1 0Na�e — — — FH1_BE FH1_AE FH0_BE FH0_AE FH_MSR/W — — — R/W R/W R/W R/W R/WPOR — — — 0 0 0 0 0

Bit7~5 Unimplemented,readas"0"Bit4~1 FH[1/0]_[A/B]E:FanHeadInterfaceoutputenable

0:DisableFanHeadInterfaceoutput1:EnableFanHeadInterfaceoutput

Bit 0 FH_MS:FANHeadModeselect0:1-pinModefor1FANhead1:2-pinModefor1FANhead

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InterruptsInterruptsarean importantpartofanymicrocontroller system.WhenanexternaleventoraninternalfunctionsuchasaTimerModuleoranA/Dconverterrequiresmicrocontrollerattention,theircorrespondinginterruptwillenforcea temporarysuspensionof themainprogramallowingthemicrocontrollertodirectattentiontotheirrespectiveneeds.Thisdevicecontainssixexternalinterruptand21internalinterruptfunctions.TheexternalinterruptsaregeneratedbytheactionoftheexternalINT0A,INT0B,INT0C,INT1,FaultandPausepins,whiletheinternalinterruptsaregeneratedbyvarious internal functionssuchas the10-bitor16-bitCTMs,Comparators,MotorProtect,LinearHallSensordetect,PWMModule,16-bitCAPTMModule,8-bitRMTModule,TimeBase,LVD,EEPROMandtheA/Dconverter.

Interrupt RegistersOverall interrupt control,whichbasicallymeans the settingof request flagswhen certainmicrocontrollerconditionsoccurandthesettingofinterruptenablebitsbytheapplicationprogram,iscontrolledbyaseriesofregisters,locatedintheSpecialPurposeDataMemory,asshownintheaccompanyingtable.Thenumberofregistersfallintotwocategories.ThefirstistheINTC0~INTC3registerswhichsetuptheprimaryinterrupts,thesecondistheMFI0~MFI8registerswhichsetuptheMulti-functioninterrupts.

Eachregistercontainsanumberofenablebitstoenableordisableindividualregistersaswellasinterrupt flags to indicate thepresenceofan interrupt request.Thenamingconventionof thesefollowsaspecificpattern.Firstislistedanabbreviatedinterrupttype,thenthe(optional)numberofthatinterruptfollowedbyeitheran“E”forenable/disablebitor“F”forrequestflag.

Function Enable Bit Request Flag NotesGlo�al EMI — —

Exte�nal inte��upt 0(Hall Senso�)

HALLE HALLF —HALAE HALAF —HALBE HALBF —HALCE HALCF —

Exte�nal inte��upt 1 INT1E INT1F —Co�pa�ato� CnE CnF n=0�1Multifun�tion inte��upt MFnE MFnF n=1~8

A/D Conve�te�AEOCE AEOCF —ALIME ALIMF —

Exte�nal Fault inte��upt FLTE FLTF —Exte�nal Pause inte��upt PAUE PAUF —

PWMPWMDE PWMDF —PWMPE PWMPF —

Ti�e Base TBE TBF —

CAPTMCAPOE CAPOF —CAPCE CAPCF —

TMTMnAE TMnAF n=0�1��3�5TMnPE TMnPF n=0�1��3�5

RMTRMT0E RMT0F —RMT1E RMT1F —RMTVE RMTVF —

LVD LVDE LVDF —EEPROM EPWE EPWF —

Interrupt Register Bit Naming Conventions

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Interrupt Register Contents

NameBit

7 6 5 4 3 2 1 0INTC0 — C0F INT1F HALLF C0E INT1E HALLE EMIINTC1 PAUF FLTF MF1F C1F PAUE FLTE MF1E C1EINTC� MF4F MF3F TBF MF�F MF4E MF3E TBE MF�EINTC3 MF8F MF7F MF�F MF5F MF8E MF7E MF�E MF5EMFI0 — HALCF HALBF HALAF — HALCE HALBE HALAEMFI1 — — ALIMF AEOCF — — ALIME AEOCEMFI� — — PWMPF PWMDF — — PWMPE PWMDEMFI3 — — CAPCF CAPOF — — CAPCE CAPOEMFI4 TM1AF TM1PF TM0AF TM0PF TM1AE TM1PE TM0AE TM0PEMFI5 TM3AF TM3PF TM�AF TM�PF TM3AE TM3PE TM�AE TM�PEMFI� — RMTVF RMT1F RMT0F — RMTVE RMT1E RMT0EMFI7 — — TM5AF TM5PF — — TM5AE TM5PEMFI8 — — EPWF LVDF — — EPWE LVDE

INTC0 Register

Bit 7 6 5 4 3 2 1 0Na�e — C0F INT1F HALLF C0E INT1E HALLE EMIR/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas"0"Bit 6 CP0F: Comparator0interruptrequestflag

0:Norequest1:Interruptrequest

Bit 5 INT1F:External1interruptrequestflag0:Norequest1:Interruptrequest

Bit 4 HALLF:Hallsensorglobalinterruptrequestflag0:Norequest1:Interruptrequest

Bit 3 C0E: Comparator0interruptcontrol0:Disable1:Enable

Bit 2 INT1E:External1interruptcontrol0:Disable1:Enable

Bit1 HALLE:Hallsensorglobalinterruptcontrol0:Disable1:Enable

Bit 0 EMI:Globalinterruptcontrol0:Disable1:Enable

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INTC1 Register

Bit 7 6 5 4 3 2 1 0Na�e PAUF FLTF MF1F C1F PAUE FLTE MF1E C1ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit 7 PAUF:PauseInterruptRequestFlag0:Norequest1:Interruptrequest

Bit 6 FLTF:FaultInterruptRequestFlag0:Norequest1:Interruptrequest

Bit 5 MF1F:Multi-functionInterrupt1RequestFlag0:Norequest1:Interruptrequest

Bit 4 C1F:Comparator1InterruptRequestFlag0:Norequest1:Interruptrequest

Bit 3 PAUE: PauseInterruptInterruptControl0:Disable1:Enable

Bit 2 FLTE:FaultInterruptControl0:Disable1:Enable

Bit1 MF1E:Multi-functionInterrupt1Control0:Disable1:Enable

Bit 0 C1E:Comparator1InterruptControl0:Disable1:Enable

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INTC2 Register

Bit 7 6 5 4 3 2 1 0Na�e MF4F MF3F TBF MF�F MF4E MF3E TBE MF�ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit 7 MF4F:Multi-functioninterrupt4requestflag0:Norequest1:Interruptrequest


Bit 5 TBF:TimeBaseinterruptrequestflag0:Norequest1:Interruptrequest

Bit 4 MF2F:Multi-functioninterrupt2Requestflag0:Norequest1:Interruptrequest

Bit 3 MF4E:Multi-functioninterrupt4control0:Disable1:Enable


Bit1 TBE:TimeBaseinterruptcontrol0:Disable1:Enable


Rev. 1.30 1�8 De�e��e� 1�� 01� Rev. 1.30 1�9 De�e��e� 1�� 01�



INTC3 Register

Bit 7 6 5 4 3 2 1 0Na�e MF8F MF7F MF�F MF5F MF8E MF7E MF�E MF5ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0







Bit1 MF6E:Multi-functioninterrupt6control0:Disable1:Enable


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MFI0 Register

Bit 7 6 5 4 3 2 1 0Na�e — HALCF HALBF HALAF — HALCE HALBE HALAER/W — R/W R/W R/W — R/W R/W R/WPOR — 0 0 0 — 0 0 0

Bit7 Unimplemented,readas"0"Bit 6 HALCF:HallSensorCinterruptrequestflag


Bit 5 HALBF:HallSensorBinterruptrequestflag0:Norequest1:Interruptrequest

Bit 4 HALAF:HallSensorAinterruptrequestflag0:Norequest1:Interruptrequest

Bit3 Unimplemented,readas"0"Bit 2 HALCE:HallSensorCinterruptcontrol

0:Disable1:Enable

Bit1 HALBE:HallSensorBinterruptcontrol0:Disable1:Enable

Bit 0 HALAE:HallSensorAinterruptcontrol0:Disable1:Enable

MFI1 Register

Bit 7 6 5 4 3 2 1 0Na�e — — ALIMF AEOCF — — ALIME AEOCER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas"0"Bit 5 ALIMF:A/DConverterEOCcompareinterruptrequestflag


Bit 4 AEOCF:A/DConverterinterruptrequestflag0:Norequest1:Interruptrequest

Bit3~2 Unimplemented,readas"0"Bit1 ALIME:A/DConverterEOCcompareinterruptcontrol

0:Disable1:Enable

Bit 0 AEOCE:A/DConverterinterruptcontrol0:Disable1:Enable

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MFI2 Register

Bit 7 6 5 4 3 2 1 0Na�e — — PWMPF PWMDF — — PWMPE PWMDER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas"0"Bit 5 PWMPF:PWMPeriodmatchinterruptrequestflag


Bit 4 PWMDF:PWMDutymatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit3~2 Unimplemented,readas"0"Bit1 PWMPE:PWMPeriodmatchinterruptcontrol

0:Disable1:Enable

Bit 0 PWMDE:PWMDutymatchinterruptcontrol0:Disable1:Enable

MFI3 Register

Bit 7 6 5 4 3 2 1 0Na�e — — CAPCF CAPOF — — CAPCE CAPOER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas"0"Bit 5 CAPCF:CAPTMcomparematchinterruptrequestflag


Bit 4 CAPOF:CAPTMcaptureoverflowinterruptrequestflag0:Norequest1:Interruptrequest

Bit3~2 Unimplemented,readas"0"Bit1 CAPCE:CAPTMcomparematchinterruptcontrol

0:Disable1:Enable

Bit 0 CAPOE:CAPTMcaptureoverflowinterruptcontrol0:Disable1:Enable

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MFI4 Register

Bit 7 6 5 4 3 2 1 0Na�e TM1AF TM1PF TM0AF TM0PF TM1AE TM1PE TM0AE TM0PER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit 7 TM1AF:TM1ComparatorAmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit 6 TM1PF:TM1ComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest



Bit 3 TM1AE:TM1ComparatorAmatchinterruptcontrol0:Disable1:Enable

Bit 2 TM1PE:TM1ComparatorPmatchinterruptcontrol0:Disable1:Enable

Bit1 TM0AE:TM0ComparatorAmatchinterruptcontrol0:Disable1:Enable


Rev. 1.30 13� De�e��e� 1�� 01� Rev. 1.30 133 De�e��e� 1�� 01�



MFI5 Register

Bit 7 6 5 4 3 2 1 0Na�e TM3AF TM3PF TM�AF TM�PF TM3AE TM3PE TM�AE TM�PER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0





Bit 3 TM3AE:TM3ComparatorAmatchinterruptcontrol0:Disable1:Enable


Bit1 TM2AE:TM2ComparatorAmatchinterruptcontrol0:Disable1:Enable


Rev. 1.30 134 De�e��e� 1�� 01� Rev. 1.30 135 De�e��e� 1�� 01�



MFI6 Register

Bit 7 6 5 4 3 2 1 0Na�e — RMTVF RMT1F RMT0F — RMTVE RMT1E RMT0ER/W — R/W R/W R/W — R/W R/W R/WPOR — 0 0 0 — 0 0 0

Bit7 Unimplemented,readas"0"Bit 6 RMTVF:RMToverflowinterruptrequestflag


Bit 5 RMT1F:RMTfallingedgeinterruptrequestflag0:Norequest1:Interruptrequest

Bit 4 RMT0F:RMTrasingedgeinterruptrequestflag0:Norequest1:Interruptrequest

Bit3 Unimplemented,readas"0"Bit 2 RMTVE:RMToverflowinterruptcontrol

0:Disable1:Enable

Bit1 RMT1E:RMTfallingedgeinterruptcontrol0:Disable1:Enable

Bit 0 RMT0E:RMTrasingedgeinterruptcontrol0:Disable1:Enable

MFI7 Register

Bit 7 6 5 4 3 2 1 0Na�e — — TM5AF TM5PF — — TM5AE TM5PER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas"0"Bit 5 TM5AF:TM5ComparatorAmatchinterruptrequestflag



Bit3~2 Unimplemented,readas"0"Bit1 TM5AE:TM5ComparatorAmatchinterruptcontrol

0:Disable1:Enable


Rev. 1.30 134 De�e��e� 1�� 01� Rev. 1.30 135 De�e��e� 1�� 01�



MFI8 Register

Bit 7 6 5 4 3 2 1 0Na�e — — EPWF LVDF — — EPWE LVDER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas"0"Bit 5 EPWF:DataEEPROMinterruptrequestflag


Bit 4 LVDF:LVDinterruptrequestflag0:Norequest1:Interruptrequest

Bit3~2 Unimplemented,readas"0"Bit1 EPWE:DataEEPROMinterruptcontrol

0:Disable1:Enable

Bit 0 LVDE:LVDinterruptcontrol0:Disable1:Enable

Interrupt OperationWhentheconditionsforaninterrupteventoccur,suchasaTMComparePorCompareAmatchorA/Dconversioncompletionetc,therelevantinterruptrequestflagwillbeset.Whethertherequestflagactuallygeneratesaprogramjumptotherelevantinterruptvectorisdeterminedbytheconditionoftheinterruptenablebit.If theenablebit issethighthentheprogramwill jumptoitsrelevantvector;iftheenablebitiszerothenalthoughtheinterruptrequestflagissetanactualinterruptwillnotbegeneratedandtheprogramwillnotjumptotherelevantinterruptvector.Theglobalinterruptenablebit,ifclearedtozero,willdisableallinterrupts.

Whenaninterruptisgenerated,theProgramCounter,whichstorestheaddressofthenextinstructiontobeexecuted,willbetransferredontothestack.TheProgramCounterwillthenbeloadedwithanewaddresswhichwillbethevalueofthecorrespondinginterruptvector.Themicrocontrollerwillthenfetchitsnextinstructionfromthisinterruptvector.Theinstructionatthisvectorwillusuallybea“JMP”whichwilljumptoanothersectionofprogramwhichisknownastheinterruptserviceroutine.Hereislocatedthecodetocontroltheappropriateinterrupt.Theinterruptserviceroutinemustbe terminatedwitha“RETI”,whichretrieves theoriginalProgramCounteraddressfromthestackandallowsthemicrocontrollertocontinuewithnormalexecutionatthepointwheretheinterruptoccurred.

Thevarious interruptenablebits, togetherwith theirassociatedrequest flags,areshownin theaccompanyingdiagramswith theirorderofpriority.Some interrupt sourceshave theirownindividualvectorwhileothersshare thesamemulti-function interruptvector.Oncean interruptsubroutineisserviced,all theother interruptswillbeblocked,as theglobal interruptenablebit,EMIbitwillbeclearedautomatically.Thiswillpreventanyfurtherinterruptnestingfromoccurring.However, ifother interruptrequestsoccurduringthis interval,althoughtheinterruptwillnotbeimmediatelyserviced,therequestflagwillstillberecorded.

Rev. 1.30 13� De�e��e� 1�� 01� Rev. 1.30 137 De�e��e� 1�� 01�



Ifaninterruptrequiresimmediateservicingwhiletheprogramisalreadyinanotherinterruptserviceroutine,theEMIbitshouldbesetafterenteringtheroutine,toallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untiltheStackPointerisdecremented.Ifimmediateserviceisdesired,thestackmustbepreventedfrombecomingfull.Incaseofsimultaneousrequests,theaccompanyingdiagramshowstheprioritythatisapplied.Alloftheinterruptrequestflagswhensetwillwake-upthedeviceifit isinSLEEPorIDLEMode,however topreventawake-upfromoccurringthecorrespondingflagshouldbesetbeforethedeviceisinSLEEPorIDLEMode.

Multi-Fun�tion 0

INT1

HALLF

INT1F

HALLE

INT1E

EMI 04H

EMI 08H

CMP0 C0F C0E EMI 0CH

10HCMP1 C1F C1E EMI

14HMulti-Fun�tion 1 MF1F MF1E EMI

18HFault FLTF FLTE EMI

Inte��upt Na�e

Request Flags

Ena�le Bits

Maste� Ena�le Vector

EMI auto disa�led in ISR

Low

INT0B HALBF HALBE

INT0C HALCF HALCE

INT0A HALAF HALAE

Inte��upts �ontained within Multi- Fun�tion Inte��upts

P�io�ityHigh

XXE Ena�le Bits

xxF Request Flag� auto �eset in ISR

LegendxxF Request Flag� no auto �eset in ISR

1CH

�0H

�4H

�8H

�CH

30H

34H

38H

3CH

MF�F MF�E EMI

Pause PAUF PAUE EMI

MF8F MF8E EMI

MF7F MF7E EMI

MF�F MF�E EMI

MF5F MF5E EMI

MF4F MF4E EMI

MF3F MF3E EMI

Ti�e Base TBF TBE EMI

Multi-Fun�tion �

Multi-Fun�tion 3

Multi-Fun�tion 4

Multi-Fun�tion 5

Multi-Fun�tion �

Multi-Fun�tion 7

Multi-Fun�tion 8

AHL_Li� ALIMF ALIME

AEOCF AEOCE

PWMP PWMPF PWMPE

PWMD PWMDF PWMDE

CAPCF CAPCE

CapTM_Ove� CAPOF CAPOE

TM0 A TM0AF TM0AE

TM0 P TM0PF TM0PE

TM1 A TM1AF TM1AE

TM1 P TM1PF TM1PE

ADC EOC

CapTM_C�p

TM� A TM�AF TM�AE

TM� P TM�PF TM�PE

TM3 A TM3AF TM3AE

TM3 P TM3PF TM3PE

RMT 1 RMT1F RMT1E

RMT 0 RMT0F RMT0E

RMT V RMTVF RMTVE

TM5 A TM5AF TM5AE

TM5 P TM5PF TM5PE

EEPROM EPWF EPWE

LVD LVDF LVDE

Interrupt Structure

Rev. 1.30 13� De�e��e� 1�� 01� Rev. 1.30 137 De�e��e� 1�� 01�



External Interrupt 0Theexternal interrupt0,alsoknownas theHallSensor interrupt, iscontainedwithin theMulti-functionInterrupt.Itiscontrolledbysignaltransitionsonthepins,HallSensorinputpins,INT0A,INT0BandINT0C.Anexternalinterruptrequestwilltakeplacewhentheexternalinterruptrequestflag,HALAFHALBFandHALCFisset,whichwilloccurwhenatransition,appearsontheexternalinterruptpins.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andtheMulti-functioninterruptcontrolledbit,HALLEmustfirstbeset.WhentheMulti-functioninterruptcontrolledbitHALLEisenabledandthestackisnotfull,andeitheroneoftheinterruptscontainedwithineachofMulti-functioninterruptoccurs,asubroutinecall tooneoftheMulti-functioninterruptvectorswill takeplace.Whentheinterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterruptsandtherelatedMulti-Functionrequest flagHALLF,willbeautomaticallyreset,but theMulti-function interrupt request flags,HALAF,HALBF,HALCF,mustbemanuallyclearedbytheapplicationprogram..

External Interrupt 1Theexternal interrupt1iscontrolledbysignal transitionsonthepinINT1.Anexternal interruptrequestwill takeplacewhentheexternal interruptrequestflag,INT1F, isset,whichwilloccurswhena transitionappearson theexternal interruptpin.Toallow theprogramtobranch to itsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andrespectiveexternalinterruptenablebit, INT1E,mustfirstbeset.Whentheinterrupt isenabled, thestackisnotfullandthecorrecttransitiontypeappearsontheexternalinterruptpin,asubroutinecalltotheexternalinterruptvector,will takeplace.Whentheinterruptisserviced,theexternalinterruptrequestflag,INT1F,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.Notethatanypull-highresistorselectionsontheexternalinterruptpinswillremainvalidevenifthepinisusedasanexternalinterruptinput.

Comparator InterruptThecomparatorinterruptsarecontrolledbythetwointernalcomparators.Acomparatorinterruptrequestwill takeplacewhenthecomparator interruptrequestflag,C0ForC1F,isset,asituationthatwilloccurwhenthecomparatoroutputchangesstate.Toallowtheprogramtobranchto itsrespectiveinterruptvectoraddress, theglobal interruptenablebit,EMI,andcomparator interruptenablebit,C0EorC1E,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandthecomparatorinputsgenerateacomparatoroutputtransition,asubroutinecalltothecomparatorinterruptvector,will takeplace.Whentheinterrupt isserviced, thecomparator interruptrequestflags,C0ForC1F,willbeautomaticallyresetand theEMIbitwillbeautomaticallycleared todisableotherinterrupts.

Multi-function InterruptWithinthisdevicearenineMulti-functioninterrupts.Unliketheotherindependentinterrupts,theseinterruptshavenoindependentsource,butratherareformedfromotherexistinginterruptsources,namelytheHallSensorinterrupts,A/Dinterrupts,PWMModuleinterrupts,CAPTMInterrupts,TMInterrupts,RMTInterrupts,EEPROMandLVDInterrupt.AMulti-functioninterruptrequestwilltakeplacewhenanyoftheMulti-functioninterruptrequestflags,HALLFandMF1F~MF8Fareset.TheMulti-functioninterruptflagswillbesetwhenanyoftheirincludedfunctionsgenerateaninterruptrequestflag.Toallowtheprogramtobranchtoitsrespective interruptvectoraddress,whentheMulti-functioninterrupt isenabledandthestackisnotfull,andeitheroneoftheinterruptscontainedwithineachofMulti-functioninterruptoccurs,asubroutinecalltooneoftheMulti-functioninterruptvectorswilltakeplace.Whentheinterruptisserviced,therelatedMulti-Functionrequestflag,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.However, itmustbenotedthat,althoughtheMulti-functionInterruptflagswillbeautomaticallyresetwhentheinterruptisserviced,therequestflagsfromtheoriginalsourceoftheMulti-functioninterrupts,namely theHallSensor interrupts,A/Dinterrupts,PWMModule interrupts,CAPTMInterrupts,TMInterrupts,RMTInterrupts,EEPROMandLVDInterruptwillnotbeautomaticallyresetandmustbemanuallyresetbytheapplicationprogram.

Rev. 1.30 138 De�e��e� 1�� 01� Rev. 1.30 139 De�e��e� 1�� 01�



A/D Converter InterruptTheA/DConverterhastwointerrupts.AllofthemarecontainedinMulti-functioninterrupt.Theone iscontrolledby the terminationofanA/Dconversionprocess.AnA/DConverter interruptrequestwilltakeplacewhentheA/DConverterInterruptrequestflag,ALIMF,isset,whichoccurswhentheA/Dconversionprocessfinishes.TheotheriscontrolledbytheADCHVE/ADCLVEbitintheADCR1registerandthevalueintheADLVDH/ADLVDLandADHVDH/ADHVDLboundarycontrolregisters.AnA/DConverterInterruptrequestwilltakeplaceafterEOCcomparing.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andA/DInterruptenablebit,AEOCEorALIME,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheA/DconversionprocesshasendedorafterEOCcomparingasubroutinecalltotheA/DConverterInterruptvector,willtakeplace.Whentheinterruptisserviced,theA/DConverterInterruptflag,AEOCForALIMF,willbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.

Fault InterruptFaultpin isMotorControldisablepin, itsupports lowactive level trigger interrupt.Whenthishappens,itsinterruptrequestflag,FLTFwillbeset.Toallowtheprogramtobranchtoitsinterruptvectoraddress, theglobalinterruptenablebit,EMIandenablebit,FLTE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandalowactivelevelappearsonthepin,asubroutinecalltothisvectorlocationwilltakeplace.Whentheinterruptisserviced,theinterruptrequestflag,FLTF,willbeautomaticallyresetandtheEMIbitwillbeclearedtodisableotherinterrupts.

Pause InterruptPausepinisMotorControlenablepin, itsupportrising/falling/bothtrigger interrupt.Whenthishappens,itsinterruptrequestflag,PAUFwillbeset.Toallowtheprogramtobranchtoitsinterruptvectoraddress,theglobalinterruptenablebit,EMIandthecorrespondingenablebit,PAUE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandarising/falling/bothedgetriggerappearsonthepin,asubroutinecall tothisvectorlocationwill takeplace.Whentheinterruptisserviced,theinterruptrequestflag,PAUF,willbeautomaticallyresetandtheEMIbitwillbeclearedtodisableotherinterrupts.

PWM Module InterruptsThePWMModulehastwointerrups.ThetwoofthemarecontainedinMulti-functioninterrupt,which isknownasPWMDandPWMP.Theyare theDutyor thePeriodmachingof thePWMModule.AnPWMinterruptrequestwilltakeplacewhenthePWMinterruptrequestflag,PWMDForPWMPF,isset,whichoccurswhenthePWMDutyorPWMPeriodmatches.Whentheinterruptisenabled, thestackisnotfullandPWMDutyorPWMPeriodmaches,asubroutinecall tothisvectorlocationwill takeplace.Whentheinterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterruptsandtherelatedMulti-Functionrequestflagwillbeautomaticallyreset,but the interrupt request flag,PWMDForPWMPF,mustbemanuallyclearedby theapplicationprogram.

Rev. 1.30 138 De�e��e� 1�� 01� Rev. 1.30 139 De�e��e� 1�� 01�



Time Base InterruptThefunctionoftheTimeBaseInterruptistoprovideregulartimesignalintheformofaninternalinterrupt.Theyarecontrolledbytheoverflowsignalsfromits timerfunction.Whenthishappensits interruptrequestflag,TBFwillbeset.Toallowtheprogramtobranchtoits interruptvectoraddress,theglobalinterruptenablebit,EMIandTimeBaseenablebit,TBE,mustfirstbeset.Whentheinterruptisenabled, thestackisnotfullandtheTimeBaseoverflow,asubroutinecall to itsvectorlocationwilltakeplace.Whentheinterruptisserviced,theinterruptrequestflag,TBF,willbeautomaticallyresetandtheEMIbitwillbeclearedtodisableotherinterrupts.

ThepurposeoftheTimeBaseInterruptistoprovideaninterruptsignalatfixedtimeperiods.ItsclocksourceoriginatesfromtheinternalclocksourcefTB.ThisfTB inputclockpasses throughadivider, thedivisionratioofwhich isselectedbyprogrammingtheappropriatebits in theTBCregistertoobtainlongerinterruptperiodswhosevalueranges.TheclocksourcethatgeneratesfTB,whichinturncontrolstheTimeBaseinterruptperiod,canoriginatefromseveraldifferentsources,asshownintheSystemOperatingModesection.

TBC Register

Bit 7 6 5 4 3 2 1 0Na�e TBON TBCK TB1 TB0 — — — —R/W R/W R/W R/W R/W — — — —POR 0 0 1 1 — — — —

Bit 7 TBON: TB Control0:Disable1:Enable

Bit 6 TBCK:SelectfTBClock0: fTBC

1:fSYS/4Bit 5~4 TB1~TB0:SelectTimeBaseTime-outPeriod

00:4096/fTB

01:8192/fTB

10:16384/fTB

11:32768/fTB

Bit3~0 Unimplemented,readas"0"

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Time Base Interrupt

Rev. 1.30 140 De�e��e� 1�� 01� Rev. 1.30 141 De�e��e� 1�� 01�



CAPTM Module InterruptTheCAPTMModulehas two interrupts.Allof themarecontainedwithin theMulti-functionInterrupt,whichareknownasCapTM_OverandCapTM_Cmp.ACAPTMInterruptrequestwilltakeplacewhentheCAPTMInterruptsrequestflag,CAPOForCAPCF,isset,whichoccurswhenCAPTMcaptureoverflowsorcomparemaches.Toallowtheprogramtobranchtotheirrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andtheCAPTMInterruptenablebit,andMuti-functioninterruptenablebit,mustfirstbeset.Whentheinterrupt isenabled, thestackisnotfullandCAPTMcaptureoverflowsorcomparemaches,asubroutinecall totherespectiveMulti-functionInterruptvector,will takeplace.WhentheCAPTMInterruptisserviced,theEMIbitwillbeautomaticallycleared todisableother interrupts,howeveronly theMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheCAPOFandCAPCFflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.

TM InterruptTheCompactTMhas two interrupts.Allof theTMinterruptsarecontainedwithin theMulti-functionInterrupts.FortheCompactTypeTM,therearetwointerruptrequestflagsTnPFandTnAFandtwoenablebitsTnPEandTnAE.ATMinterruptrequestwilltakeplacewhenanyoftheTMrequestflagsisset,asituationwhichoccurswhenaTMcomparatorPorAmatchsituationhappens.

Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,respectiveTMInterruptenablebit,andrelevantMulti-functionInterruptenablebit,MFnE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandaTMcomparatormatchsituationoccurs,asubroutinecalltotherelevantMulti-functionInterruptvectorlocations,willtakeplace.WhentheTMinterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytherelatedMFnFflagwillbeautomaticallycleared.AstheTMinterruptrequestflagswillnotbeautomaticallycleared,theyhavetobeclearedbytheapplicationprogram.

RMT Module InterruptTheRMTModulehasthreeinterrupts.AllofthemarecontainedwithintheMulti-functionInterrupt,whichareknownasRMT0,RMT1andRMTV.TheRMTInterruptsrequestwilltakeplacewhentheRMTInterruptsrequestflag,RMT0F,RMT1ForRMTVF,isset,whichwilloccurswhenraisingedgetransitionorfallingedgetransitionappearsontheRx_INpinorTimeroverflows.Toallowtheprogramtobranchtotheirrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,RMTinterruptenablebit,andassociatedMulti-functioninterruptenablebit,mustfirstbeset.Whentheinterrupt isenabled, thestackisnotfullandraisingedgetransitionorfallingedgetransitionappearson theRx_INpinorTimeroverflow,asubroutinecall to therespectiveMulti-functionInterrupt,will takeplace.WhentheRMTInterrupt isserviced, theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheRMT0,RMT1andRMTVflagswillnotbeautomaticallycleared,thyhavetobeclearedbytheapplicationprogram.

Rev. 1.30 140 De�e��e� 1�� 01� Rev. 1.30 141 De�e��e� 1�� 01�



EEPROM InterruptTheEEPROMInterrupt, iscontainedwithintheMulti-functionInterrupt.AnEEPROMInterruptrequestwilltakeplacewhentheEEPROMInterruptrequestflag,EPWF,isset,whichoccurswhenanEEPROMWriteorReadcycleends.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress, theglobal interruptenablebit,EMI,EEPROMInterruptenablebit,EPWE,andassociatedMulti-functioninterruptenablebit,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandanEEPROMWritecycleends,asubroutinecalltotherespectiveMulti-functionInterruptvector,will takeplace.When theEEPROMInterrupt isserviced, theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheEPWFflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.

LVD InterruptTheLowVoltageDetector Interrupt iscontainedwithin theMulti-function Interrupt.AnLVDInterruptrequestwill takeplacewhentheLVDInterruptrequestflag,LVDF,isset,whichoccurswhentheLowVoltageDetectorfunctiondetectsalowpowersupplyvoltage.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,LowVoltageInterruptenablebit,LVDE,andassociatedMulti-functioninterruptenablebit,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandalowvoltageconditionoccurs,asubroutinecall to theMulti-function Interruptvector,will takeplace.When theLowVoltage Interrupt isserviced, theEMIbitwillbeautomaticallyclearedtodisableother interrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheLVDFflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.

Interrupt Wake-up FunctionEachof the interruptfunctionshas thecapabilityofwakingupthemicrocontrollerwhenin theSLEEPorIDLEMode.Awake-upisgeneratedwhenaninterruptrequestflagchangesfromlowtohighand is independentofwhether the interrupt isenabledornot.Therefore,even thoughthisdeviceareintheSLEEPorIDLEModeanditssystemoscillatorstopped,situationssuchasexternaledgetransitionsontheexternalinterruptpins,alowpowersupplyvoltageorcomparatorinputchangemaycause theirrespective interruptflag tobesethighandconsequentlygenerateaninterrupt.Caremustthereforebetakenifspuriouswake-upsituationsaretobeavoided.Ifaninterruptwake-upfunctionistobedisabledthenthecorrespondinginterruptrequestflagshouldbesethighbeforethedeviceenterstheSLEEPorIDLEMode.Theinterruptenablebitshavenoeffectontheinterruptwake-upfunction.

Rev. 1.30 14� De�e��e� 1�� 01� Rev. 1.30 143 De�e��e� 1�� 01�



Programming ConsiderationsBydisablingtherelevantinterruptenablebits,arequestedinterruptcanbepreventedfrombeingserviced,however,oncean interrupt request flag is set, itwill remain in thiscondition in theinterruptregisteruntilthecorrespondinginterruptisservicedoruntiltherequestflagisclearedbytheapplicationprogram.

Whereacertain interrupt iscontainedwithinaMulti-function interrupt, thenwhenthe interruptservice routine is executed, asonly theMulti-function interrupt request flags,HALLFandMF1F~MF8F,willbeautomaticallycleared,theindividualrequestflagforthefunctionneedstobeclearedbytheapplicationprogram.

It isrecommendedthatprogramsdonotusethe“CALL”instructionwithintheinterruptservicesubroutine.Interruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediately.Ifonlyonestackisleftandtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedamagedonceaCALLsubroutineisexecutedintheinterruptsubroutine.

EveryinterrupthasthecapabilityofwakingupthemicrocontrollerwhenitisintheSLEEPorIDLEMode,thewakeupbeinggeneratedwhentheinterruptrequestflagchangesfromlowtohigh.IfitisrequiredtopreventacertaininterruptfromwakingupthemicrocontrollerthenitsrespectiverequestflagshouldbefirstsethighbeforeenterSLEEPorIDLEMode.

AsonlytheProgramCounter ispushedontothestack, thenwhentheinterrupt isserviced, if thecontentsof theaccumulator,statusregisterorotherregistersarealteredbythe interruptserviceprogram,theircontentsshouldbesavedto thememoryat thebeginningof the interruptserviceroutine.

Toreturnfromaninterruptsubroutine,eitheraRETorRETIinstructionmaybeexecuted.TheRETIinstructioninadditiontoexecutingareturntothemainprogramalsoautomaticallysetstheEMIbithightoallowfurtherinterrupts.TheRETinstructionhoweveronlyexecutesareturntothemainprogramleavingtheEMIbitinitspresentzerostateandthereforedisablingtheexecutionoffurtherinterrupts.

Low Voltage Detector – LVDEachdevicehasaLowVoltageDetectorfunction,alsoknownasLVD.Thisenabledthedevicetomonitorthepowersupplyvoltage,VDD,andprovideawarningsignalshoulditfallbelowacertainlevel.Thisfunctionmaybeespeciallyusefulinbatteryapplicationswherethesupplyvoltagewillgraduallyreduceasthebatteryages,asitallowsanearlywarningbatterylowsignaltobegenerated.TheLowVoltageDetectoralsohasthecapabilityofgeneratinganinterruptsignal.

LVD RegisterTheLowVoltageDetectorfunctioniscontrolledusingasingleregisterwiththenameLVDC.Threebits inthisregister,VLVD2~VLVD0,areusedtoselectoneofeightfixedvoltagesbelowwhichalowvoltageconditionwillbedetermined.AlowvoltageconditionisindicatedwhentheLVDObitisset.IftheLVDObitislow,thisindicatesthattheVDDvoltageisabovethepresetlowvoltagevalue.TheLVDENbit isusedtocontrol theoverallon/offfunctionof thelowvoltagedetector.Settingthebithighwillenablethelowvoltagedetector.Clearingthebittozerowillswitchofftheinternallowvoltagedetectorcircuits.Asthelowvoltagedetectorwillconsumeacertainamountofpower,itmaybedesirabletoswitchoffthecircuitwhennotinuse,animportantconsiderationinpowersensitivebatterypoweredapplications.

Rev. 1.30 14� De�e��e� 1�� 01� Rev. 1.30 143 De�e��e� 1�� 01�



LVDC Register

Bit 7 6 5 4 3 2 1 0Na�e — — LVDO LVDEN — VLVD� VLVD1 VLVD0R/W — — R R/W — R/W R/W R/WPOR — — 0 0 — 0 0 0

Bit7~6 Unimplemented,readas"0"Bit 5 LVDO:LVDOutputFlag

0:NoLowVoltageDetect1:LowVoltageDetect

Bit 4 LVDEN:LowVoltageDetectorControl0:Disable1:Enable

Bit3 Unimplemented,readas"0"Bit 2~0 VLVD2~VLVD0:SelectLVDVoltage

000: 3.6V001:3.6V010:3.6V011:3.6V100:3.0V101:3.6V110:3.6V111: 3.6V

LVD OperationTheLowVoltageDetectorfunctionoperatesbycomparingthepowersupplyvoltage,VDD,withapre-specifiedvoltagelevelstoredintheLVDCregister.Thishasaspecifiedvoltage3.6V.Whenthepowersupplyvoltage,VDD, fallsbelowthispre-determinedvalue, theLVDObitwillbesethighindicatingalowpowersupplyvoltagecondition.TheLowVoltageDetectorfunctionissuppliedbyareferencevoltagewhichwillbeautomaticallyenabled.WhenthedeviceispowereddownthelowvoltagedetectorwillremainactiveiftheLVDENbitishigh.AfterenablingtheLowVoltageDetector,atimedelaytLVDSshouldbeallowedforthecircuitrytostabilisebeforereadingtheLVDObit.NotealsothatastheVDDvoltagemayriseandfallratherslowly,at thevoltagenearsthatofVLVD,theremaybemultiplebitLVDOtransitions.

LVD Operation

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TheLowVoltageDetectoralsohasitsowninterruptwhichiscontainedwithinoneoftheMulti-functioninterrupts,providinganalternativemeansoflowvoltagedetection,inadditiontopollingtheLVDObit.TheinterruptwillonlybegeneratedafteradelayoftLVDaftertheLVDObithasbeensethighbyalowvoltagecondition.WhenthedeviceispowereddowntheLowVoltageDetectorwillremainactiveif theLVDENbit ishigh.Inthiscase, theLVDFinterruptrequestflagwillbeset,causinganinterrupttobegeneratedifVDDfallsbelowthepresetLVDvoltage.Thiswillcausethedevicetowake-upfromtheSLEEPorIDLEMode,howeveriftheLowVoltageDetectorwakeupfunctionisnotrequiredthentheLVDFflagshouldbefirstsethighbeforethedeviceenterstheSLEEPorIDLEMode.

Rev. 1.30 144 De�e��e� 1�� 01� Rev. 1.30 145 De�e��e� 1�� 01�



Application Circuits

Hall Sensor × 3

H1

H�

H3

VDD

PB�/RxIN/INT1/TP�_0

VSS

PC7/Pause/TP5_1

PA0/AN0/INT0A

PA1/AN1/INT0B

PA�/AN�/INT0C

PB0

PB3/Is

PC�/Fault/TP5_0

PC5/GCB

PC4/GCT

PC3/GBB

PC�/GBT

PC1/GAB

PC0/GAT

VDD

HIN

LIN

COM

VB

HO

VS

LO

VDD

HIN

LIN

COM

VB

HO

VS

LO

VDD

HIN

LIN

COM

VB

HO

VS

LO

IP-N

IP-L

D�ain

D�ain

D�ain

D�ain

VDDFB

Sou��eSou��e

DC+370V

+15V

+5V

VIPER1�

IR�101

IR�101

IR�101

IR RXCKT

VIN

GNDVOUT

DC +5VHT7150

DC+370V

DC+370V

AC��0V

DC +15V

HT45FM�C

v

v

DC+370V

PB7/TCK0

PB�/TP0_0

PB5/TP1_0

PB4/TCK�

Key Matix 3x�

PA3/AN3/TCK5

PB1/TP�_1 Buzze�

vGateD�ive�CKT

PD0/FH1_SAT/TP0_1PD1/FH1_SBT/TP1_1



PA7/AN7/FH0_RI/TCK1PA�/AN�/FH0_LI/TP3_0


vGateD�ive�CKT

Pull-low O� Pull-high

Rev. 1.30 144 De�e��e� 1�� 01� Rev. 1.30 145 De�e��e� 1�� 01�



Hall Sensor × 1

H�

VDD

VSS

PC7/Pause/TP5_1

PA0/AN0/INT0A

PA1/AN1/INT0B

PA�/AN�/INT0C

PB0

PB3/Is

PC�/Fault/TP5_0

PC5/GCB

PC4/GCT

PC3/GBB

PC�/GBT

PC1/GAB

PC0/GAT

VDD

HIN

LIN

COM

VB

HO

VS

LO

VDD

HIN

LIN

COM

VB

HO

VS

LO

VDD

HIN

LIN

COM

VB

HO

VS

LO

IP-N

IP-L

D�ain

D�ain

D�ain

D�ain

VDDFB


DC+370V

+15V

+5V

VIPER1�

IR�101

IR�101

IR�101

IR RXCKT

VIN

GNDVOUT

DC +5VHT7150

DC+370V

DC+370V

AC��0V

DC +15V

HT45FM�C

v

v

DC+370V+5V

PB7/TCK0

PB�/TP0_0

PB5/TP1_0

PB4/TCK�

Key Matix 3x�

PA3/AN3/TCK5

PB1/TP�_1 Buzze�

vGateD�ive�CKT






vGateD�ive�CKT

Pull-low O� Pull-high


Rev. 1.30 14� De�e��e� 1�� 01� Rev. 1.30 147 De�e��e� 1�� 01�



Non-Hall Sensor

VDD

VSS

PB1/TP�_1

PC7/Pause/TP5_1

PA0/AN0/INT0A

PA1/AN1/INT0B

PA�/AN�/INT0C

PB0

PB3/Is

PC�/Fault/TP5_0

PC5/GCB

PC4/GCT

PC3/GBB

PC�/GBT

PC1/GAB

PC0/GAT

VDD

HIN

LIN

COM

VB

HO

VS

LO

VDD

HIN

LIN

COM

VB

HO

VS

LO

VDD

HIN

LIN

COM

VB

HO

VS

LO

IP-N

IP-L

D�ain

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Instruction Set

IntroductionCentral to thesuccessfuloperationofanymicrocontroller is its instructionset,whichisasetofprograminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontroller,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.

Foreasierunderstandingofthevariousinstructioncodes, theyhavebeensubdividedintoseveralfunctionalgroupings.

Instruction TimingMostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,call,or tablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5μsandbranchorcall instructionswouldbeimplementedwithin1μs.Although instructionswhichrequireonemorecycle to implementaregenerally limited totheJMP,CALL,RET,RETIandtablereadinstructions, it is important torealize thatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwill implyadirect jumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructionswouldbe“CLRPCL”or“MOVPCL,A”.Forthecaseofskipinstructions,itmustbenotedthatiftheresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.

Moving and Transferring DataThe transferofdatawithin themicrocontrollerprogram isoneof themost frequentlyusedoperations.MakinguseofthreekindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimmediatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsis toreceivedatafromtheinputportsandtransferdatatotheoutputports.

Arithmetic OperationsTheabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddandsubtract instructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbe taken toensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255foradditionandlessthan0forsubtraction.TheincrementanddecrementinstructionsINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.

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Logical and Rotate OperationThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontroller instructionset.Aswiththecaseofmost instructionsinvolvingdatamanipulation, datamust pass through theAccumulatorwhichmay involve additionalprogrammingsteps. Inall logicaldataoperations, thezero flagmaybeset if the resultof theoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregister intotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhichrotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.

Branches and Control TransferProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionor toa subroutineusing theCALL instruction.Theydiffer in the sense that in thecaseofasubroutinecall, theprogrammustreturn to the instruction immediatelywhenthesubroutinehasbeencarriedout.Thisisdonebyplacingareturninstruction“RET”inthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.ThereisnorequirementtojumpbacktotheoriginaljumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulsetofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmaderegardingtheconditionofacertaindatamemoryor individualbits.Dependingupon theconditions, theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.These instructionsare thekey todecisionmakingandbranchingwithin theprogramperhapsdeterminedbytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.

Bit OperationsTheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeature isespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe“SET[m].i”or“CLR[m].i”instructionsrespectively.Thefeatureremovestheneedforprogrammerstofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebitoperationinstructionsareused.

Table Read OperationsDatastorage isnormally implementedbyusing registers.However,whenworkingwith largeamountsoffixeddata, thevolumeinvolvedoftenmakesit inconvenienttostorethefixeddataintheDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgramMemorytobesetupasatablewheredatacanbedirectlystored.Asetofeasytouseinstructionsprovides themeansbywhich this fixeddatacanbereferencedandretrievedfromtheProgramMemory.

Other OperationsInaddition to theabovefunctional instructions,a rangeofother instructionsalsoexistsuchasthe“HALT”instructionforPower-downoperationsand instructions tocontrol theoperationoftheWatchdogTimerfor reliableprogramoperationsunderextremeelectricorelectromagneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.

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Instruction Set SummaryThefollowingtabledepictsasummaryoftheinstructionsetcategorisedaccordingtofunctionandcanbeconsultedasabasicinstructionreferenceusingthefollowinglistedconventions.

Table Conventionsx:Bitsimmediatedata m:DataMemoryaddress A:Accumulator i:0~7numberofbits addr:Programmemoryaddress

Mnemonic Description Cycles Flag AffectedArithmeticADD A�[�] Add Data Me�o�y to ACC 1 Z� C� AC� OVADDM A�[�] Add ACC to Data Me�o�y 1Note Z� C� AC� OVADD A�x Add i��ediate data to ACC 1 Z� C� AC� OVADC A�[�] Add Data Me�o�y to ACC with Ca��y 1 Z� C� AC� OVADCM A�[�] Add ACC to Data �e�o�y with Ca��y 1Note Z� C� AC� OVSUB A�x Su�t�a�t i��ediate data f�o� the ACC 1 Z� C� AC� OVSUB A�[�] Su�t�a�t Data Me�o�y f�o� ACC 1 Z� C� AC� OVSUBM A�[�] Su�t�a�t Data Me�o�y f�o� ACC with �esult in Data Me�o�y 1Note Z� C� AC� OVSBC A�[�] Su�t�a�t Data Me�o�y f�o� ACC with Ca��y 1 Z� C� AC� OVSBCM A�[�] Su�t�a�t Data Me�o�y f�o� ACC with Ca��y� �esult in Data Me�o�y 1Note Z� C� AC� OVDAA [�] De�i�al adjust ACC fo� Addition with �esult in Data Me�o�y 1Note CLogic OperationAND A�[�] Logi�al AND Data Me�o�y to ACC 1 ZOR A�[�] Logi�al OR Data Me�o�y to ACC 1 ZXOR A�[�] Logi�al XOR Data Me�o�y to ACC 1 ZANDM A�[�] Logi�al AND ACC to Data Me�o�y 1Note ZORM A�[�] Logi�al OR ACC to Data Me�o�y 1Note ZXORM A�[�] Logi�al XOR ACC to Data Me�o�y 1Note ZAND A�x Logi�al AND i��ediate Data to ACC 1 ZOR A�x Logi�al OR i��ediate Data to ACC 1 ZXOR A�x Logi�al XOR i��ediate Data to ACC 1 ZCPL [�] Co�ple�ent Data Me�o�y 1Note ZCPLA [�] Co�ple�ent Data Me�o�y with �esult in ACC 1 ZIncrement & DecrementINCA [�] In��e�ent Data Me�o�y with �esult in ACC 1 ZINC [�] In��e�ent Data Me�o�y 1Note ZDECA [�] De��e�ent Data Me�o�y with �esult in ACC 1 ZDEC [�] De��e�ent Data Me�o�y 1Note ZRotateRRA [�] Rotate Data Me�o�y �ight with �esult in ACC 1 NoneRR [�] Rotate Data Me�o�y �ight 1Note NoneRRCA [�] Rotate Data Me�o�y �ight th�ough Ca��y with �esult in ACC 1 CRRC [�] Rotate Data Me�o�y �ight th�ough Ca��y 1Note CRLA [�] Rotate Data Me�o�y left with �esult in ACC 1 NoneRL [�] Rotate Data Me�o�y left 1Note NoneRLCA [�] Rotate Data Me�o�y left th�ough Ca��y with �esult in ACC 1 CRLC [�] Rotate Data Me�o�y left th�ough Ca��y 1Note C

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Mnemonic Description Cycles Flag AffectedData MoveMOV A�[�] Move Data Me�o�y to ACC 1 NoneMOV [�]�A Move ACC to Data Me�o�y 1Note NoneMOV A�x Move i��ediate data to ACC 1 NoneBit OperationCLR [�].i Clea� �it of Data Me�o�y 1Note NoneSET [�].i Set �it of Data Me�o�y 1Note NoneBranchJMP add� Ju�p un�onditionally � NoneSZ [�] Skip if Data Me�o�y is ze�o 1Note NoneSZA [�] Skip if Data Me�o�y is ze�o with data �ove�ent to ACC 1Note NoneSZ [�].i Skip if �it i of Data Me�o�y is ze�o 1Note NoneSNZ [�].i Skip if �it i of Data Me�o�y is not ze�o 1Note NoneSIZ [�] Skip if in��e�ent Data Me�o�y is ze�o 1Note NoneSDZ [�] Skip if de��e�ent Data Me�o�y is ze�o 1Note NoneSIZA [�] Skip if in��e�ent Data Me�o�y is ze�o with �esult in ACC 1Note NoneSDZA [�] Skip if de��e�ent Data Me�o�y is ze�o with �esult in ACC 1Note NoneCALL add� Su��outine �all � NoneRET Retu�n f�o� su��outine � NoneRET A�x Retu�n f�o� su��outine and load i��ediate data to ACC � NoneRETI Retu�n f�o� inte��upt � NoneTable ReadTABRDC [�] Read ta�le to TBLH and Data Me�o�y �Note NoneTABRDL [�] Read ta�le (last page) to TBLH and Data Me�o�y �Note NoneMiscellaneousNOP No ope�ation 1 NoneCLR [�] Clea� Data Me�o�y 1Note NoneSET [�] Set Data Me�o�y 1Note NoneCLR WDT Clea� Wat�hdog Ti�e� 1 TO� PDFCLR WDT1 P�e-�lea� Wat�hdog Ti�e� 1 TO� PDFCLR WDT� P�e-�lea� Wat�hdog Ti�e� 1 TO� PDFSWAP [�] Swap ni��les of Data Me�o�y 1Note NoneSWAPA [�] Swap ni��les of Data Me�o�y with �esult in ACC 1 NoneHALT Ente� powe� down �ode 1 TO� PDF

Note:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthentwocyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.

2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.

3.For the“CLRWDT1”and“CLRWDT2”instructionstheTOandPDFflagsmaybeaffectedbytheexecutionstatus.TheTOandPDFflagsareclearedafterboth“CLRWDT1”and“CLRWDT2”instructionsareconsecutivelyexecuted.OtherwisetheTOandPDFflagsremainunchanged.

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Instruction Definition

ADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C

ADD A,x AddimmediatedatatoACCDescription ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+xAffectedflag(s) OV,Z,AC,C

ADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C

AND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z

AND A,x LogicalANDimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″xAffectedflag(s) Z

ANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z

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CALL addr SubroutinecallDescription Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthen incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe stack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.Operation Stack←ProgramCounter+1 ProgramCounter←addrAffectedflag(s) None

CLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None

CLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None

CLR WDT ClearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT1 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksin conjunctionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohave effect.RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2will havenoeffect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT2 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunction withCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect. RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhaveno effect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z

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CPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z

DAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C

DEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z

DECA[m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z

HALT EnterpowerdownmodeDescription Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower downflagPDFissetandtheWDTtime-outflagTOiscleared.Operation TO←0 PDF←1Affectedflag(s) TO,PDF

INC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z

INCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z

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JMP addr JumpunconditionallyDescription ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Program executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy instructionwhilethenewaddressisloaded,itisatwocycleinstruction.Operation ProgramCounter←addrAffectedflag(s) None

MOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None

MOV A,x MoveimmediatedatatoACCDescription TheimmediatedataspecifiedisloadedintotheAccumulator.Operation ACC←xAffectedflag(s) None

MOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None

NOP NooperationDescription Nooperationisperformed.Executioncontinueswiththenextinstruction.Operation NooperationAffectedflag(s) None

OR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z

OR A,x LogicalORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″xAffectedflag(s) Z

ORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z

RET ReturnfromsubroutineDescription TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored address.Operation ProgramCounter←StackAffectedflag(s) None

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RET A,x ReturnfromsubroutineandloadimmediatedatatoACCDescription TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecified immediatedata.Programexecutioncontinuesattherestoredaddress.Operation ProgramCounter←Stack ACC←xAffectedflag(s) None

RETI ReturnfrominterruptDescription TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning tothemainprogram.Operation ProgramCounter←Stack EMI←1Affectedflag(s) None

RL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None

RLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None

RLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C

RLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C

RR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None

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RRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bitwithbit0 rotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsofthe DataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None

RRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C

RRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C

SBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None

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SDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None

SET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None

SET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None

SIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None

SIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None

SNZ [m].i SkipifbitiofDataMemoryisnot0Description IfbitiofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None

SUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C

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SUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C

SUB A,x SubtractimmediatedatafromACCDescription TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumulator. TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC flagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−xAffectedflag(s) OV,Z,AC,C

SWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None

SWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None

SZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None

SZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None

SZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None

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TABRDC [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

XOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z

XORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z

XOR A,x LogicalXORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″xAffectedflag(s) Z

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Package Information

Note that thepackage informationprovidedhere is for consultationpurposesonly.As thisinformationmaybeupdatedatregularintervalsusersareremindedtoconsulttheHoltekwebsite for thelatestversionofthePackage/CartonInformation.

Additionalsupplementaryinformationwithregardtopackagingislistedbelow.Clickontherelevantsectiontobetransferredtotherelevantwebsitepage.

• PackageInformation(includeOutlineDimensions,ProductTapeandReelSpecifications)

• TheOperationInstructionofPackingMaterials

• Cartoninformation

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16-pin NSOP (150mil) Outline Dimensions

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SymbolDimensions in inch

Min. Nom. Max.A — 0.�3� BSC —B — 0.154 BSC —C 0.01� — 0.0�0 C' — 0.390 BSC —D — — 0.0�9 E — 0.050 BSC —F 0.004 — 0.010 G 0.01� — 0.050 H 0.004 — 0.010 α 0° ― 8°

SymbolDimensions in mm

Min. Nom. Max.A — �.000 BSC —B — 3.900 BSC —C 0.31 — 0.51 C' — 9.900 BSC —D — — 1.75 E — 1.�70 BSC —F 0.10 — 0.�5 G 0.40 — 1.�7 H 0.10 — 0.�5 α 0° ― 8°

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28-pin SOP (300mil) Outline Dimensions

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Min. Nom. Max.A — 0.40� BSC —B — 0.�95 BSC —C 0.01� — 0.0�0 C’ — 0.705 BSC —D — — 0.104 E — 0.050 BSC —F 0.004 — 0.01� G 0.01� — 0.050 H 0.008 — 0.013 α 0° ― 8°


Min. Nom. Max.A — 10.30 BSC —B — 7.5 BSC —C 0.31 — 0.51 C’ — 17.9 BSC —D — — �.�5 E — 1.�7 BSC —F 0.10 — 0.30 G 0.40 — 1.�7 H 0.�0 — 0.33 α 0° ― 8°

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28-pin SSOP (150mil) Outline Dimensions

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Min. Nom. Max.A — 0.�3� BSC —B — 0.154 BSC —C 0.008 — 0.01� C’ — 0.390 BSC —D — — 0.0�9 E — 0.0�5 BSC —F 0.004 — 0.010 G 0.01� — 0.050 H 0.004 — 0.010α 0° — 8°


Min. Nom. Max.A — �.0 BSC —B — 3.9 BSC —C 0.�0 — 0.30 C’ — 9.9 BSC —D — — 1.75 E — 0.�35 BSC —F 0.10 — 0.�5 G 0.41 — 1.�7 H 0.10 — 0.�5 α 0° — 8°

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44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions


Min. Nom. Max.A — 0.47� BSC —B — 0.394 BSC —C — 0.47� BSC —D — 0.394 BSC —E — 0.03� BSC —F 0.01� 0.015 0.018G 0.053 0.055 0.057H — — 0.0�3I 0.00� — 0.00�J 0.018 0.0�4 0.030K 0.004 — 0.008α 0° — 7°


Min. Nom. Max.A — 1�.00 BSC —B — 10.00 BSC —C — 1�.00 BSC —D — 10.00 BSC —E — 0.80 BSC —F 0.30 0.37 0.45G 1.35 1.40 1.45H — — 1.�0I 0.05 — 0.15J 0.45 0.�0 0.75K 0.09 — 0.�0α 0° — 7°

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Copy�ight© �01� �y HOLTEK SEMICONDUCTOR INC.The info��ation appea�ing in this Data Sheet is �elieved to �e a��u�ate at the ti�e of pu�li�ation. Howeve�� Holtek assu�es no �esponsi�ility a�ising f�o� the use of the specifications described. The applications mentioned herein are used solely fo� the pu�pose of illust�ation and Holtek �akes no wa��anty o� �ep�esentation that su�h appli�ations will �e suita�le without fu�the� �odifi�ation� no� �e�o��ends the use of its p�odu�ts fo� appli�ation that �ay p�esent a �isk to hu�an life due to �alfun�tion o� othe�wise. Holtek's p�odu�ts a�e not autho�ized fo� use as ��iti�al �o�ponents in life suppo�t devi�es o� syste�s. Holtek �ese�ves the �ight to alte� its products without prior notification. For the most up-to-date information, please visit ou� we� site at http://www.holtek.�o�.tw.

brushless dc motor flash mcu ht45fm2c - holtek...co pa e mat h output mode..... 9 ti e /counte mode...

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