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Chapter 9: Single Transistor Amplifier Stages:

9.1 Basic Amplifiers

The term amplifier as used in this chapter means a circuit (or stage) using a single active devicerather than a complete system such as an integrated circuit operational amplifier. An amplifier is adevice for increasing the power of a signal. This is accomplished by taking energy from a powersupply and controlling the output to duplicate the shape of the input signal but with a larger (voltageor current) amplitude. In this sense, an amplifier may be thought of as modulating the voltage orcurrent of the power supply to produce its output.

The basic amplifier, figure 9.1, has two ports and is characterized by its gain, input impedance andoutput impedance. An ideal amplifier has infinite input impedance (Rin = ), zero output impedance (Rout= 0) and infinite gain (Avo = ) and infinite bandwidth if desired.

Figure 9.1 Basic Amplifier Model

The transistor, as we have seen in the previous chapter, is a three-terminal device. Representing thebasic amplifier as a two port network as in figure 9.1, there would need to be two input and twooutput terminals for a total of four. This means one of the transistor terminals must be common toboth the input and output circuits. This leads to the names common emitter, etc. for the three basictypes of amplifiers. The easiest way to determine if a device is connected as common emitter/source,common collector/drain, or common base/gate is to examine where the input signal enters and theoutput signal leaves. The remaining terminal is what is thus common to both input and output. In thischapter we will primarily be using n-type transistors (NPN, NMOS) in the example circuits. The samebasic amplifier stages can just as easily be implemented using p-type transistors (PNP, PMOS). Whenlarger multi-stage amplifiers are assembled, both types of transistors are often interspersed with eachother.

Building-block amplifier stages:

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Inverting voltage amplifier (also called Common emitter or Common source amplifier)1.Current Follower (also called Common base or Common gate or cascode)2.Voltage Follower (also called Common collector or Common drain amplifier)3.Series feedback (more commonly: emitter/source degeneration)4.Shunt feedback5.

9.2 The inverting voltage amplifier or Commonemitter/source

The common emitter/source amplifier is one of three basic single-stage amplifier topologies. The BJTand MOS versions function as an inverting voltage amplifier and are shown in figure 9.2. The base orgate terminal of the transistor serves as the input, the collector or drain is the output, and the emitteror source is common to both input and output (it may be tied to the ground reference or the powersupply rail), which gives rise to its common name.

Figure 9.2: Basic n-type inverting voltage amplifier circuit (neglecting biasing details)

The common emitter or source amplifier may be viewed as a transconductance amplifier (i.e. voltagein, current out) or as a voltage amplifier (voltage in, voltage out). As a transconductance amplifier,the small signal input voltage, vbe for a BJT or vgs for a FET, times the device transconductance gm,modulates the amount of current flowing through the transistor, ic or id. By passing this varyingcurrent through the output load resistance, RL it will be converted back into a voltage Vout. However,the transistors small signal output resistance, ro, is not typically high enough for a reasonabletransconductance amplifier (ideally infinite). Nor is the output load, RL, low enough for a decentvoltage amplifier (ideally zero). Another major drawback is the amplifiers limited high-frequencyresponse due in part to the built in collector base or drain gate capacitance inherent to the transistor.More on how this capacitance effects the frequency response in a later section of this chapter.Therefore, in practice the output often is routed through either a voltage follower (common collectoror drain stage), or a current follower (common base or gate stage), to obtain more favorable outputand frequency characteristics. This latter combination is called a cascode amplifier as we will see laterin the chapter on multi-stage amplifiers.

In comparison to the BJT common emitter amplifier, the FET common source amplifier has higherinput impedance. The generally lower gmof the FET vs. the BJT at equal current levels leads to lowervoltage gain for the MOS version.

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9.2.1 DC Bias techniques, common emitter/source

In order for the common emitter or source amplifier to provide the largest output voltage swing, thevoltage at the Base or Gate terminal of the transistor is offset in such a way that the transistor isnominally operating halfway between its cut-off and saturation points. Note the NMOS (a) and NPN (b)characteristic curves in figure 9.2.1. This allows the amplifier stage to more accurately reproduce thepositive and negative halves of the input signal superimposed upon the DC Bias voltage. Without thisoffsetting Bias Voltage only the positive half of the input waveform would be amplified.

(a) NMOS

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(b) NPN

Figure 9.2.1 (a) ID vs. VDScurves and (b) IC vs. VCE curves

The red line superimposed on the two sets of curves represents the DC load line of a 400 ohm RL. Tomaximize the output swing it is desirable to set the operating point of the transistor, with a zero inputsignal, at a drain or collector voltage of one half the supply voltage, which would be 4 volts in thiscase. Finding the corresponding drain or collector current along the load line gives us the targetcurrent level. This is around 10mA for RL equal to 400 ohms. The next step is to determine thecorresponding VGS or IB for a 10mA ID or IC. In the NMOS example each curve represents a different VGSfrom 0.9 volts to 1.5 volts in 0.1 volt steps. The NMOS device used in this example has atransconductance of about 40mA/V. The ID equal to 10mA point on the load line falls between the 1.4Vand 1.3V curves or a VGS of 1.32V. In the NPN example each curve represents a different IB from 10uAto 100uA in 10uA steps. The 50uA curve happens to cross the load line at IC =10mA. The of thetransistor must therefore be about 200. The task now is to somehow provide this DC offset or bias atthe Gate or Base of the transistor.

The first bias technique we will explore is called voltage divider bias and is shown in figure 9.2.2. If wechoose the correct resistor values for R1 and R2 that will result in a collector or drain current such thatone half of the supply voltage, V+ appears across RL we should have our desired value of VGS or VBE (IB)for biasing with no signal input. For the MOS case we know that no current flows into the gate so thesimple voltage divider ratio can be used to pick R1 and R2. If V+ = 8V and we want VGS to equal 1.32 Vthen:

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The actual values of R1 and R2 are not so important just their ratio. However, the divider ratio wechoose will be correct for only one set of conditions of power supply voltage, transistor thresholdvoltage and transconductance, and temperature. Actual designs often use more involved biasschemes.

Figure 9.2.2 Voltage divider bias

For the NPN case the calculation is somewhat more involved. We know we want IB to be equal to 50uA.The current that flows in R1 is the sum of the current in R2 and IB which puts an upper bound on R1when R2 is infinite and no current flows in R2. If we assume a nominal VBE of 0.65 volts then R1 must beno larger than 7.35V/50uA or 147K. The purpose of the voltage divider is to attenuate the variationsin V+ and thus make the DC operating point of the transistor less sensitive to V+. To that end weneed to make the current in R2 many times larger than IB. If we, for example, choose to make IR2 9times IB then the current in R1 will be 10*IB or 500uA. R1 will be 1/10 what we just calculated as theupper bound or 14.7K. R2 will be VBE divided by 450uA or 1.444K which is a divider ratio of 0.8921.If we had simply used 8V-VBE/8V as the ratio (assume VBE = 0.65V) the divider ratio would have been0.8125. Taking IB into account shifted the required ratio. These values would need to be adjustedslightly if the actual VBE was not the 0.65 volts (or was not 200) we used in this calculation. Thispoints out a major limitation of this bias scheme as we pointed out in the MOS example above. That isthe sensitivity to device specific characteristics like VBE and as well as supply voltage andtemperature.

A consequence of including this bias scheme is a lowering of the input impedance. The input nowincludes the parallel combination of R1 and R2 across the input. For the MOS case this now sets theinput resistance. For the BJT case we now have R1||R2||r as the effective input resistance.

There is another minor inconvenient problem with this bias scheme when it is connected to a priorstage in the signal path. This bias configuration places the AC input signal source directly in parallelwith R2 of the voltage divider. This may not be acceptable, as the input source may tend to add orsubtract from the DC voltage dropped across R2.

One way to make this scheme work, although it may not be obvious why it will work, is to place acoupling capacitor between the input voltage source and the voltage divider as in figure 9.2.3 below.

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Figure 9.2.3 Coupling capacitor CC prevents voltage divider bias current from flowing into the inputsignal source.

The capacitor forms a high-pass filter between the input source and the DC voltage divider, passingalmost the entire AC portion of the input signal on to the transistor while blocking all the DC biasvoltage from being shorted through the input signal source. This makes much more sense if youunderstand the superposition theorem and how it works. According to superposition, any linear,bilateral circuit can be analyzed in a piecemeal fashion by only considering one power source at atime, then algebraically adding the effects of all power sources to find the final result. If we were toseparate the capacitor and the R1/R2voltage divider circuit from the rest of the amplifier, it might beeasier to understand how this superposition of AC and DC would work.

With only the AC signal source in effect, and a capacitor with an arbitrarily low impedance at the inputsignal frequency, almost all the AC voltage appears across R2.

9.2.2 Small signal voltage gain, common emitter or source

To calculate the small signal voltage gain of the common emitter or source amplifier we need to inserta small signal model of the transistor into the circuit. The small signal models of the BJT and MOS FETare actually very similar so the gain calculation for either version is much the same. The small signalhybrid- models for the BJT and MOS amplifiers are shown in figure 9.2.4.

Figure 9.2.4 Common emitter or source small signal models.

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The following are some of the key model equations we will need to calculate the amplifier stagevoltage gain. These equations are used for the other amplifier configurations that we will discuss infollowing sections as well.

(BJT)

(MOS)

The small signal voltage gain Av is the ratio of the input voltage to the output voltage:

The input voltage Vin (vbe for the BJT and vgs for the MOS) times the transconductance gm is equal tothe small signal output current, io in the collector or drain. Vout will be simply this current times theload resistance RL,neglecting the small signal output resistance ro for the moment. Notice the minussign because of the direction of the current io.

Rearranging for the gain we get:

Substituting the BJT and MOS gm equations we get:

(BJT)

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(MOS)

Comparing these two gain equations we see that they both depend on the DC collector or draincurrents. The BJT gain is inversely proportional to VT (the Thermal Voltage) which is approximately26mV at room temperature. The Thermal Voltage, VT increases with increasing temperature so fromthe equation we see that the gain will actually decrease with increasing temperature. The MOS gain isinversely proportional to the over drive voltage, Vov (VGS Vth) which is often much larger than VT atsimilar drain currents leading to the lower gain for the MOS stage vs. the BJT stage for approximatelyequal bias currents.

If RL is relatively large when compared to the small signal output resistance then the gain will bereduced because the actual output load is the parallel combination of RL and ro. In fact ro puts anupper bound on the possible gain that can be achieved with a single transistor amplifier stage.

9.2.3 Small signal input impedance, common emitter or source

Again looking at the small signal models in figure 9.2.4 we see that for the BJT case the input Vin willsee r as a load. For the MOS case Vin will see basically an open circuit (for low frequencies anyway).This will of course be the case absent any Gate or Base bias circuitry.

9.2.4 Small signal output impedance, common emitter or source

Again looking at the small signal models in figure 9.2.4 we see that for both the BJT case and the MOScase the output impedance is the parallel combination of RL and ro. For most practical applications wecan ignore ro because it is very often much larger than RL. Below are the BJT and MOS ro equations.

(BJT)

(MOS)

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9.2.5 common emitter and source Lab Activities

Common emitter amplifierCommon source amplifierAmplifier Frequency Response

9.3 The Current Follower also known as Common base orgate amplifier

The Current Follower or Common base/gate amplifier has a high voltage gain, relatively low inputimpedance and high output impedance compared to the voltage follower or common collector/drainamplifier. The BJT and MOS versions are shown in figure 9.3

Figure 9.3: Basic n-type current follower or common base/gate circuit (neglecting biasing details)

9.3.1 DC Biasing techniques, current follower or common base/gate amplifier

In applications where only a positive power supply voltage is provided some means of providing thenecessary DC voltage level for the common gate or base terminal is required. This might be as simpleas a voltage divider between ground and the supply. In applications where both positive and negativesupply voltages are available, ground is a convenient node to use for the common gate or baseterminal.

The common gate or base stage is most often used in combination with the common emitter orsource amplifier in what is known as the cascode configuration. The cascode will be covered in thenext chapter on multi stage amplifiers in greater detail.

9.3.2 Small signal voltage gain, current follower or common base/gateamplifier

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To calculate the small signal voltage gain of the common base or gate amplifier we insert the smallsignal model of the transistor into the circuit. The small signal models for the BJT and MOS amplifiersare shown in figure 9.3.1.

Figure 9.3.1 Current follower or Common base/gate small signal models.

Much like in the common emitter/source amplifier stage the small signal input voltage, Vin (vbe for theBJT and vgs for the MOS) times the transconductance gm is equal to the small signal output current, ioin the collector or drain. Vout will be simply this current times the load resistance RL,neglecting thesmall signal output resistance ro for the moment.

It is perhaps more useful to consider the current gain of the current follower stage rather than itsvoltage gain. In the case of the MOS version we know that IS = IDbecause IG= 0. Thus the MOS stagecurrent gain is exactly 1. In the case of the BJT version we know that the ratio of IC to IEis equal to and thus will be slightly less than 1.

9.3.3 Input impedance, current follower or common base/gate amplifier

Again looking at the small signal models in figure 9.3.1 we see that for the BJT case the input Vin willsee rin parallel with the series combination of gm and RL as a load. For the MOS case Vin will seebasically just the series combination of gm and RL. The equation below (from the BJT small signal Tmodel) relates gm and the resistance seen at the emitter rE. We can also use this relationship to giveus the resistance seen at the source rS.

(also rS for MOS)

It is also important to note here that 100% (neglecting IB in the BJT case) of the current from the inputsource flows through the transistor and becomes the output current. Thus the name current follower.

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9.3.4 Output impedance, current follower or common base/gate amplifier

Again looking at the small signal models in figure 9.3.1 we see that for both the BJT case and the MOScase the output impedance is the parallel combination of RL and ro. We can generally assume this istrue if we consider that Vin is driven from a low impedance (nearly ideal) voltage source. If this is notthe case then the finite output impedance must be added in series with ro. If the input of the currentfollower is driven by the relatively high output impedance of a transconductance amplifier such as thecommon emitter or source amplifier from earlier then the output impedance for the combinedamplifier can be very high. For most practical applications we can ignore ro because it is very oftenmuch larger than RL.

9.4 Voltage followers (also called Emitter or Source follower or Commoncollector or drain amplifiers)

The Emitter or Source follower is often called a common Collector or Drain amplifier because thecollector or drain is common to both the input and the output. This amplifier configuration, figure 9.4,has its output taken from the emitter/source resistor and is useful as an impedance matching devicesince its input impedance is much higher than its output impedance. The voltage follower is alsotermed a buffer for this reason.

Figure 9.4:Basic n-type Voltage follower or common collector/drain circuit (neglecting biasing details)

The gain of the voltage follower is always less than one since rEand RLor rS and RL form a voltagedivider. The input to output offset is set by the VBE drop of about 0.65 volts below the base for the BJTand VGS below the gate for the MOS. This configurations function is not voltage gain but current orpower gain and impedance matching. The input impedance is much higher than its output impedanceso that a signal source does not have to supply as much power to the input. This can be seen from thefact that the base current is on the order of 100 times () less than the emitter current. The lowoutput impedance of the emitter follower matches a low impedance load and buffers the signal sourcefrom that low impedance.

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9.4.1 DC Biasing techniques, Voltage Follower or common collector/drainamplifier

The collector/source current is basically determined by the emitter/source resistor so the main designvariables in this case is simply RL and the power supply voltage.

9.4.2 Voltage gain, common collector or drain amplifier

To calculate the small signal voltage gain of the voltage follower configuration we insert the smallsignal model of the transistor into the circuit. The small signal models for the BJT and MOS amplifiersare shown in figure 9.4.1.

Figure 9.4.1 Voltage Follower small signal models.

Example 9.4.2 Calculating the Voltage Gain

For the circuit in figure 9.4.2 calculate the voltage gain AV = Vout/Vin.

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Figure 9.4.2 BJT Voltage gain example

To use the voltage gain formula we just obtained using the small signal models we need to firstcalculate rE. From section 9.3.3 we are given the equation for rE:

To use this formula we need to know IE. We know that the voltage across RL is Vout. We also know thatVout = Vin - VBE. If we use an estimate of VBE to be 0.6 volts, we get Vout = 5.6 - 0.6 or 5 volts. If RL is 1Kthen IE is 5mA. Using a room temperature value for VT = 25mV, we get rE is equal to 3. Substitutingthese values into our gain equation we get:

9.4.3 Input impedance, Voltage Follower (common collector or drain)

(BJT)

9.4.4 Output impedance, Voltage Follower (common collector or drain)

The output impedance is simple the parallel combination of the Emitter (Source) resistor RL and thesmall signal emitter (source) resistance of the transistor rE. Again from section 9.3.3, the equation forrE is as follows:

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Similarly, the small signal source resistance, rS, for a MOS FET is 1/gm.

Referring back to our gain example in figure 9.4.2, we can also calculate the output resistance, whichwill be the parallel combination of the 1K RL and the 3 rE or 2.99.

9.4.5 Voltage Follower (common collector or drain) Lab Activities

BJT Emitter followerMOS source follower

9.5 Series Feedback: emitter/source degeneration

Common emitter/source amplifiers give the amplifier an inverted output and can have a very highgain and can vary widely from one transistor to the next. The gain is a strong function of bothtemperature and bias current, and so the actual gain is somewhat unpredictable. Stability is anotherproblem associated with such high gain circuits due to any unintentional positive feedback that maybe present. Other problems associated with the circuit are the low input dynamic range imposed bythe small-signal limit; there is high distortion if this limit is exceeded and the transistor ceases tobehave like its small-signal model. When negative feedback is introduced, many of these problemsare reduced, resulting in improved performance. There are several ways to introduce feedback in thissimple amplifier stage, the easiest and most reliable of which is accomplished by introducing a smallvalue resistor in the emitter circuit (RE). This is also referred to as series feedback. The amount offeedback is dependent on the relative signal level dropped across this resistor. The signal seen acrossRE is out of phase with the signal seen at Vout and thus subtracts from Vout reducing its amplitude.When the emitter resistor value approaches that of the collector load resistor (RL), the gain willapproach unity (Av ~ 1).

Figure 9.5: Adding an emitter/source resistor decreases gain. However, with increased linearity and

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stability

It is much less common to include a degeneration resistor in MOS designs. This is because, inmicroelectronic integrated circuits, the gain (gm) of the device can be adjusted by changing the W/Lratio. This degree of design freedom is not generally available in Bipolar (BJT) processes.

DC Biasing example with emitter degeneration

There are some BJT biasing rules of thumb:

1. Set IE not IB or VBE : less dependence on and temperature (VT)2. Allow 1/3VCC across RC, VCE and RB23. Save power by allowing only 10% of IE in RB

We are given the following for circuit in figure 9.5.1, VCC = 20V ; IE = 2mA ; = 100. From our rules ofthumb we set VB = 1/3*VCC = 6.7 V.

Figure 9.5.1 DC Biasing example

VB = (RB2/(RB1+RB2))*VCC 6.7V = (RB2/(RB1+RB2))*20 (1)

VCC /(RB1 + RB2 ) = 0.1*IE 20/(RB1 + RB2) = 200 A (2)

Solving equations (1) and (2) we get:

RB1=2RB2 then from (2)

3RB2 = 20/200 A = 100k

So, RB2 = 33k and RB1 = 66k

Now we have VE = VB VBE = 6.7 0.7 = 6 V and IE is 2 mA: RE = VE/IE = 6/2mA = 3k.

IC = (/(+1))*IE = (100/101)*2mA = 1.98 mA and IB = IC/ = 1.98mA/100 = 19.8A.

From our rules of thumb we know that VC = 2/3*20V = 13.3 V

So to find RL we have: RL = (VCC VC)/IC = (20 13.3)/1.98mA = 3.4k

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9.5.1 Small signal voltage gain with emitter/source degeneration

To calculate the small signal voltage gain of the common emitter/source amplifier with the addition ofemitter/source degeneration we again insert the small signal model of the transistor into the circuit.The small signal models for the BJT and MOS amplifiers are shown in figure 9.5.1.

Figure 9.5.1 Common emitter/source with degeneration

The impedance RE reduces the overall transconductance gm of the circuit by a factor of gmRE + 1,which makes the voltage gain:

(when gmRE 1)

So the voltage gain depends almost exclusively on the ratio of the resistors RL / RE rather than thetransistors intrinsic and unpredictable characteristics. The distortion and stability characteristics ofthe circuit are thus improved at the expense of a reduction in gain.

Going back to our earlier biasing example, figure 9.5.1, values for IC = 2mA, RL = 3.4K and RE = 3Kto calculate the small signal gain we first find gm = IC/VT = 2mA/25mV = 0.08. Using our formula for AV:

9.5.2 Small signal input impedance with emitter/source degeneration

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Again looking at the small signal models in figure 9.4.1 we see that for the BJT case the input Vin see rin series with degeneration resistor RE as a load. For the MOS case Vin see basically an open circuit.

9.5.3 Small signal output impedance with emitter/source degeneration

Again looking at the small signal models in figure 9.5.1 we see that for both the BJT case and the MOScase, much like in the earlier common emitter/source stage, the output impedance is the parallelcombination of RL and ro but now degeneration resistor RE is in series with ro. For most practicalapplications we can ignore ro because it is very often much larger than RL.

9.5.4 DC Biasing techniques with emitter/source degeneration

Basically the same techniques used in the simple common emitter/source amplifier stage, which werediscussed in section 9.2.1, can be used when the emitter degeneration resistor is added. The addedvoltage across the RE (RE*IE) must be added to the bias level. This added voltage drop actually makethe operating point (IC) much less sensitive to the bias level.

The small signal voltage gain of the common emitter amplifier with the emitter resistance isapproximately RL / RE. For cases when a gain larger than 5-10 is needed, RE may be become so smallthat the necessary good biasing condition, VE = RE*IE > 10* VT cannot be achieved. A way to restorethe small signal voltage gain while maintaining the desired DC operating bias is to use a by-passcapacitor as is figure 9.5.4. The small AC signal sees an emitter resistance of just RE1 while for DC biasthe emitter resistance is the series combination of RE = RE1+RE2. Calculations for the common emitteramplifier with emitter degeneration can be applied here by replacing RE with RE1 when deriving theamplifier gain, and input and output impedances, because a sufficiently large bypass capacitor ineffects shorts RE2and is effectively removed from the circuit for sufficiently high frequency inputs.

Figure 9.5.4 addition of emitter by-pass capacitor

Using our earlier biasing exercise in figure 9.5.1 as an example but splitting the 3K RE into tworesistors as in figure 9.5.4 with RE1= 1K and RE2 = 2K with C1 = 1uF we can recalculate the small

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signal gain for high frequencies, where C1 effectively shorts out RE2, to be:

The addition of by-pass capacitor C1, however, modifies the low frequency response of the circuit. Weknow from our two gain calculations that the DC gain of the circuit is -1.13 and the gain increases to-3.36 for high frequencies. We can therefore assume that the frequency response consists of arelatively low frequency zero followed by a somewhat higher frequency pole. The formulas for thezero and pole are as follows:

where RE= RE2 || (RE1 + re)

For our example problem with RE1 = 1K , RE2 = 2K and C1 = 1uF we get the frequency for the zeroequal to 80 Hz and the frequency for the pole equal to 237 Hz. The simulated frequency responsefrom 1 Hz to 100 KHz for the example circuit is shown in figure 9.5.5.

Figure 9.5.5 simulated frequency response

9.5.5 Summary - performing small-signal analyses:

1. Find DC operating point.

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2. Calculate small-signal parameters: gm, r, re etc.3. Replace DC voltage sources with AC grounds and DC current sources with open circuits.4. Replace transistor with small-signal model (hybrid- model or T model)

9.6 Millers Theorem

At this point we are going to take a diversion to discuss Millers Theorem. While the methods we havebeen using up to this point are completely general, there are certain configurations that lendthemselves to be analyzed more simply by Millers Theorem. Millers theorem states that in a linearcircuit, if there is a branch where an impedance Z, connects two nodes with node voltages V1and V2,this branch can be replaced by two other branches connecting the corresponding nodes to ground byimpedances respectively Z / (1-K) and KZ / (K-1), where the gain from node 1 to node 2 is K = V2 / V1.

Figure 9.6.1 Millers Theorem

At this point we will go through the steps that show how the Miller impedances are arrived at. We canuse the equivalent two-port network technique to replace the two-port represented in figure 9.6.1(a)to its equivalent in figure 9.6.2.

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Figure 9.6.2

Replacing the voltage sources in figure 9.6.2 with their Norton equivalent current sources we getfigure 9.6.3.

Figure 9.6.3

Using the source absorption theorem (see the Appendix at the end of this chapter), we get figure9.6.4.

Figure 9.6.4

Which gives us figure 9.6.5 (which is figure 9.6.1(b) ) when we parallel combine the two impedances.

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Figure 9.6.5

9.7 Shunt feedback:

Another biasing technique for the common emitter or source amplifier, called shunt feedback, isaccomplished by the introduction of some fraction of the collector or drain signal back to the input atthe base or gate. This is done via the biasing resistor (RF), as shown in figure 9.7.1. Resistor RFconnects between two nodes that have gain, AV (K), between them and thus the application of Millerstheorem is the best way analyze the small signal characteristics of this circuit.

Figure 9.7.1 Drain-to-Gate (a) and Collector-to-Base (b) shunt feedback

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9.7.1 MOS version

Figure 9.7.1(a) shows a common source NMOS amplifier using drain feedback biasing. This type ofbiasing is often used with enhancement mode MOSFETS and can be useful when operating with a lowvoltage power supply (V+). If Vin is AC coupled, the voltage on the gate is equal to the voltage on thedrain (VGS = VDS) since no gate current flows through RF. If Vin is DC coupled then a voltage divider isformed by RF and RS and VGS will be less than VDS. It is useful to note that the transistor is always insaturation when VGS = VDS. If the drain current increases for some reason, such as a change in V+, thegate voltage drops. The decreased gate voltage in turn causes the drain current to decreases whichcauses the gate voltage to increase. The negative feedback loop reaches an equilibrium that is thebias point for the circuit.

Some data sheets for enhancement MOSFETS give a value for ID(on), where VGS = VDS lf ID(on) is known,the circuit component can be easily calculated as shown in Example 9.3. The input impedance of acircuit using drain feedback biasing is equal to the value of RF divided by the voltage gain plus one.

9.7.2 BJT Version DC Biasing techniques

This configuration employs negative feedback to stabilize the operating point. In this form of biasing,the base feedback resistor RF is connected to the collector instead of connecting it to the DC source V+.So any large increase in the collector current will induce a voltage drop across the RL resistor that willin turn reduce the transistors base current.

If we assume that the input source Vin is AC coupled and no DC bias current flows in RS, fromKirchhoffs voltage law, the voltage VRFacross the base resistor RF is:

By the EbersMoll model, Ic = Ib, and so:

From Ohms law, the base current Ib=VRF/RF, and so:

Hence, the base current Ib is:

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If VBE is held constant and temperature increases, then the collector current Ic increases. However, alarger Ic causes the voltage drop across resistor RL to increase, which in turn reduces the voltage VRFacross the base resistor RF. A lower base-resistor voltage drop reduces the base current Ib, whichresults in less collector current Ic. Because an increase in collector current with temperature isopposed, the operating point is kept more stable.

Pros:

Circuit stabilizes the operating point against variations in temperature and (ie. Transistor process1.variations)

Cons:

In this circuit, to keep Ic independent of , the following condition must be met:1.

which is the case when:

As is fixed (and generally not known precisely) for a given transistor, this relation can be satisfied1.either by keeping RL fairly large or making RF very low.If RL is large, a high V+ is necessary, which increases cost as well as precautions necessary while2.handling.If RF is low, the reverse bias of the collectorbase region is small, which limits the range of collector3.voltage swing that leaves the transistor in active mode.The resistor RF causes an AC feedback, reducing the voltage gain of the amplifier. This undesirable4.effect is a trade-off for greater quiescent operating point stability.

Usage: The feedback also decreases the input impedance of the amplifier as seen from the base,which can be advantageous. Due to the gain reduction from feedback, this biasing form is used onlywhen the trade-off for stability is warranted.

Example 9.7.2 Using Millers Theorem

For the amplifier shown in figure 9.7.2(a) with a DC coupled input source Vin calculate the input andoutput resistance and voltage gain AV. We first need to start with some preliminary DC analysis todetermine the operating point of Q1. For this we set Vin to zero volts, i.e. short it out. If we assume a VBEof 0.65 volts we will have 65 uA flowing in the 10K resistor RS. Given that V+ is 10V, we would like Voutto be 5 volts. The current in RL is equal to 500uA and will split between the collector of Q1 and thefeedback resistor RF. The voltage across the 62.7K feedback resistor is 5-0.65 or 4.35 volts. Thecurrent in RF splits between the current in RS and IB. The base current IB is equal to 4.35/62.7K 65uAor 4.3 uA. We should get a collector current of 500uA - 69.3uA or 430.3uA with a of about 100.

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If we use Millers theorem to replace the feedback resistor RF with its two equivalent impedances weget figure 9.7.2(b). Assuming that the voltage gain from base to collector AV is significantly greaterthan 1 we can make the simplification that AV/(AV-1) is close to 1. The effective load resistance, RLeq wewill use to calculate the gain will be 10K||62.7K or 8.62K. Now we can use the same commonemitter or source small signal gain equations we used in section 9.2.2. The 430uA collector currentsgives us a gm of 430uA/25mV or 0.0172. We know that AV = -gmRLeq or AV = -0.0172*8.62K = -148which is 1. The input resistance seen at the base of Q1 will be the rof Q1, which is equal to /gm or100/0.0172 = 5.814K, in parallel with the Miller resistance 62.7K/149 = 421 thus the effectiveinput resistance, Rbase will be about 392.5.

Figure 9.7.2 Example using Millers theorem

The input source resistance RS and the equivalent resistance at the base, Rbase form a voltage divider.To calculate the overall voltage gain from voltage source Vin to Vout we multiply this divider ratio timesthe base to collector gain, AV we just calculated.

From our investigation of the inverting op amp configuration in Chapter 3 we learned that foramplifiers with less than infinite gain the actual gain will be less than the ideal gain equation, Gain =-RF/RS predicts. If our single transistor amplifier had infinite gain the gain from Vin to Vout would be62.7K/10K or 6.27. In Chapter 3 we got an estimation of the percentage error, , due to finite gainAV (remember in this equation is the feedback factor not the current gain of the transistor):

The actual gain of 5.6 is about 10% smaller than the ideal gain of 6.27.

Exercise 9.7

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Part 1 DC operating point:

For the circuit in figure 9.7.3 calculate the required RF to bias the DC operating point such that Vout isequal to the supply voltage or +5V when Vin = 0. Assume VBE = 0.65V and = 200.

Figure 9.7.3

Part 2 Small signal gain and impedance:

Given the value for RF calculated in part 1 calculate the voltage gain AV, the input resistance Rbase andthe output resistance Rout. Also calculate the overall voltage gain Vout/Vin and explain why this isdifferent than the ideal value of RF/RS.

9.7.5 The Miller Effect

The Miller effect is key to predicting the frequency response of an inverting amplifier stage wherecapacitive feedback is included. Typically theres a low-pass pole in the voltage gain stage created byRS of the signal source and a feedback capacitor CC. But, the low pass cutoff is not simply determinedby RS and CC. The Miller effect creates an effective capacitance at the base/gate of the transistor thatappears as CC scaled by the amplifiers voltage gain.

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Figure 9.7.3 Miller feedback capacitor

The Miller effect is especially useful when youre trying to produce a low-pass filter on an IC op ampwith a relatively low frequency cut-off. The difficulty is that large capacitors are difficult to makebecause they take up so much space on the IC. The solution is to make a small capacitor and thenscale up its behavior using the Miller effect.

Equivalent Circuit

Heres a simplified version of the circuit above.

Figure 9.7.4 Miller feedback equivalent circuit

Miller said that you can approximate the input capacitance by replacing CC with a differentcapacitance CM across the RIN. How much bigger is CM? CC is multiplied by the voltage gain (AV = gmRL)of the amplifier. Millers theorem also states there will be a capacitor CC across RL that is equal to CCtimes (AV+1)/AV which for large values of AV we assume to be 1.

How does this work? Well, we know that forcing a voltage across a capacitor causes a current to flow.How much current depends on the capacitance: I = CC V/t. However, in this circuit, the voltagegain at RL causes a much larger V across CC - causing an even larger current to flow through CC.Therefore, it looks like a much larger capacitance from the point of view of VIN.

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Example 9.7.3 Miller Capacitance Example

In this example we will use the circuit shown in figure 9.7.5 to illustrate the Miller multiplication of thefeedback capacitor CC. Bias resistors R1 and RS are chosen to set the DC operating point such that Voutis at a DC value of approximately V+/2 or 5V. With the given RL of 10K the low frequency smallsignal voltage gain AV is approximately 80.

We can now calculate the -3 dB frequency and unity gain (0dB) frequency for a feedback capacitor, CC,of 0.001 uF. The frequency where the gain from Vin to Vout falls by -3 dB from its DC values isapproximately equal to:

The unity gain frequency is approximately equal to :

Figure 9.7.5 Miller Capacitance Example

The circuit in figure 9.7.5 was simulated and the AC frequency response from 1 Hz to 1 MHz is plottedin figure 9.7.6. The gain from Vin to Vout in dB is 20Log(AV) or about 38 dB. The -3 dB frequency in thiscase would be where the gain curve crosses 35 dB (~263 Hz) and the unit gain frequency would bewhere the gain curve crosses the 0 dB line (~21.7 KHz ). The simulation results are in reasonablyclose agreement with our approximate hand calculations. For our hand calculations we assumed thatR1 was sufficiently larger than RS so it could be ignored and likewise the r of Q1 was large enough tonot materially affect RS.

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Figure 9.7.6 Frequency sweep simulation

Chapter Summary:

The Common Emitter stage has high gain but low input and high output impedance.RE emitter degeneration improves input impedance and provides negative feedback to stabilize DCoperating point but with some loss in gain.The Common Base stage has low input, high output impedance but is good at high frequencies.Good current buffer sometimes called the current follower.The Common Collector or Emitter follower can be biased with large input impedance, low outputimpedance but has approximately unity gain. Good voltage buffer.

Appendix: Source absorption theorem

The source absorption theorem has two dual forms: the voltage source absorption and the currentsource absorption theorems.

The voltage source absorption theorem states that if, in one branch of the circuit with current I, thereis a voltage source controlled by I, the source can be replaced by a simple impedance with valueequal to the source controlling factor.

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Figure 9A.1

The proof is trivial. An impedance Z where a current I flows has the same voltage drop the I controlledsource generates at its terminals.

The current source absorption theorem states that if, in one branch of the circuit there is a currentsource controlled by a voltage V, the source can be replaced by a simple admittance with value equalto the source controlling factor.

Figure 9A.2

The proof is again trivial. An admittance Y submitted to a voltage V imposes the same current that thesource Y V provides.

Example A1: Finding the Emitter Resistance using Source absorption theorem

Figure A9.3 shows the small signal equivalent circuit model of a transistor. Find the resistance Rin

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looking into the emitter (with base and collector at small signal AC grounds).

Figure 9A.3

Using what we just learned about the source absorption theorem for current sources we know we canreplace the controlled source with a resistance equal to 1/gmits transconductance.

Advanced Topics:

AT1 Diode bias generation

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Figure AT1.1 Inserting a Diode connected device in the bias divider

Figure AT1.2 Inserting R2increases the input resistance

AT2 Bootstrapping for Higher Input Impedance

Depending on your component choices and signal source, the circuit in figure AT2.1 may load thesource so that the input signal is noticeably attenuated when connected to the circuit. That is, atsignal frequencies, the input impedance of the circuit may be low compared to the output impedance

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of the signal source, and so dissipation in the signal source causes attenuation of the signal enteringthe circuit. To ensure the current into the base of the transistor is negligible, the biasing network musthave a relatively low equivalent resistance at DC when looking out of the base. However, there is aclever method we can use to raise the impedance of the network at signal frequencies when lookingout of the capacitor. By bootstrapping some of the transistors output signal back into the input, wecan make the input impedance (at signal frequencies) very large (i.e., approximately RE, the inputimpedance of the transistor). Consider the modified circuit in figure AT2.1.

Instead of Equation (3.3) and Equation (3.4), assume that

(R1||R2) + RB RE and 100 and C 1 / 2f (R1 || R2 + RB). (A.1)

Otherwise, components can be chosen exactly as before. The bootstrapping capacitor CB must be verylarge so that it looks like a short circuit to signal frequencies. Theoretically, the resistor RB can bechosen arbitrarily. As long as Equation (A.1) can be met, a high choice of RB (e.g., RB > 1 k) is a goodidea. The signal at the transistors emitter follows the signal at its base. At signal frequencies, CB actslike a short circuit, and so both ends of RB see the same potential. Hence, RB carries no current atsignal frequencies. Thus, the R1R2 divider cannot load the input source because no current from thesource makes its way across RB (i.e., RB at signal frequencies). The current through R1R2 thatwould normally come from the source comes from the output instead. This method is calledbootstrapping because we use the circuits own output to reduce current required from the input.

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http://wiki.analog.com/university/courses/electronics/text/chapter-8http://wiki.analog.com/university/courses/electronics/text/chapter-10http://wiki.analog.com/university/courses/electronics/text/electronics-tocChapter 9: Single Transistor Amplifier Stages:9.1 Basic Amplifiers9.2 The inverting voltage amplifier or Common emitter/source9.2.1 DC Bias techniques, common emitter/source9.2.2 Small signal voltage gain, common emitter or source9.2.3 Small signal input impedance, common emitter or source9.2.4 Small signal output impedance, common emitter or source9.2.5 common emitter and source Lab Activities9.3 The Current Follower also known as Common base or gate amplifier9.3.1 DC Biasing techniques, current follower or common base/gate amplifier9.3.2 Small signal voltage gain, current follower or common base/gate amplifier9.3.3 Input impedance, current follower or common base/gate amplifier9.3.4 Output impedance, current follower or common base/gate amplifier9.4 Voltage followers (also called Emitter or Source follower or Common collector or drain amplifiers)9.4.1 DC Biasing techniques, Voltage Follower or common collector/drain amplifier9.4.2 Voltage gain, common collector or drain amplifierExample 9.4.2 Calculating the Voltage Gain9.4.3 Input impedance, Voltage Follower (common collector or drain)9.4.4 Output impedance, Voltage Follower (common collector or drain)9.4.5 Voltage Follower (common collector or drain) Lab Activities9.5 Series Feedback: emitter/source degeneration9.5.1 Small signal voltage gain with emitter/source degeneration9.5.2 Small signal input impedance with emitter/source degeneration9.5.3 Small signal output impedance with emitter/source degeneration9.5.4 DC Biasing techniques with emitter/source degeneration9.5.5 Summary - performing small-signal analyses:9.6 Millers Theorem9.7 Shunt feedback:9.7.1 MOS version9.7.2 BJT Version DC Biasing techniquesExample 9.7.2 Using Millers TheoremExercise 9.79.7.5 The Miller EffectExample 9.7.3 Miller Capacitance ExampleChapter Summary:Appendix: Source absorption theoremExample A1: Finding the Emitter Resistance using Source absorption theoremAdvanced Topics:AT1 Diode bias generationAT2 Bootstrapping for Higher Input Impedance