bias voltage generation. use cascode to increase output resistance rout is approximately g m3 r o3 r...
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![Page 1: Bias Voltage Generation. Use Cascode to Increase output Resistance Rout is approximately g m3 r o3 r o2 L1=L2, but L3 need not equal to L2. Design Criteria:](https://reader030.vdocuments.mx/reader030/viewer/2022032516/56649c7b5503460f9492e7a0/html5/thumbnails/1.jpg)
Bias Voltage Generation
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Use Cascode to Increase output Resistance
Rout is approximately gm3ro3ro2
L1=L2, but L3 need not equal to L2.
Design Criteria: Choose Vb so that VY and VX.
Question: How do you generate Vb?
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Cascode Current Source
Requirement: Choose Vb so that VX=VY
VN=VGS0+VX=VGS3+VY
Therefore, VGS3=VGS0
Since ID1=ID2, (W/L)3=(W/L)0
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Cascode Current Mirror
VDS1=249.6 mVVDS6=263.7 mV
VDS5=0.675 VVDS0=0.286 V
IDS5=20.41uAIDS0=10 uA
gmovergds_5=47gds6=10.35uS
Rout=4.5 MOhms
(Mismatch)
(Close)
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Sensitivity of IOUT due to VOUT
As VX decreases from VDD,M3 enters the triode region first.
M2 enters the triode region
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Sweep Output Voltage
VTH5=177.6 mVVG5=535.7 mVVG6=249.6 mVVTH6=136.9 mV
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VB Versus VX
VTH5=177.6 mVVG5=535.7 mVVG5-VTH5=535.7 mV-177.6 mV=358.1 mV
T5=SATT6=SAT
T5=TriodeT6=SAT
VG6=249.6 mVVTH6=136.9 mVVG6-VTH6=249.6 mV-136.9 mV=112.7 mV VB=112.7 mV →T6=Triode
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T5=SATT6=SAT
T5=TriodeT6=SAT
T5=TriodeT6=Triode
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Accuracy and Voltage Headroom Trade-Off
Vb is chosen to allow minimum VP.Problem: VX is not equal to VYIout is not equal to Iref.
Vb is chosen to allow VX=VYVP is not minimum.But Iout is equal to Iref.
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Design Criteria• Desirables:– IOUT should be IREF. (i.e. VX=VY)
– Vout should be minimized. (i.e. VOD2+VOD3)
VOUT=VOD3+VOD4
VA=VB→IOUT=mIREF
IREF produces VGS1 and VGS3.
If VA is to be defined by Vb, then VD1 must not be connected to VG1, otherwise, it becomes unclear which node defines VA.
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Extra Slides
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Low Voltage Cascode
To keep M2 in saturation: Vx>Vb-Vth→Vx+Vth2>Vb
To keep M1 in saturation: VA>Vx-Vth1
Since VA=Vb-VGS2, Vb>Vx-Vth1+VGS2
Design criteria for M2
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Vb Requirement
Vb=VOD3+VGS4 to produce a minimum outputVoltage of VOD3 and VOD4.
By design, VGS4=VGS2, VA=VB
Vb=VOD2+VTH2+VOD1.
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Minimum Vout
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Minimum Vout
VOD3=0.163 VVOD4=0.056 VVOUT(min)=VOD3+VOD4=0.219 V
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Vb Generation (Option 1)
Requirement:Vb=VOD2+VTH2+VOD1
VGS5=VGS2
VOD1=VGS6-I1Rb
Problem: M5 suffers from no body effectM2 suffers from body effect
Rb is not well controlled,unless Rb is off-chip.
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Vb Generation (Option 2)
Requirement:Vb=VOD2+VTH2+VOD1
VGS5=VGS2
VOD1=VGS6-VTH7
Problem: M5 suffers from no body effectM2 suffers from body effect
Design M7 (Large W7/L7) so that VGS7 is approx. VTH7
Need to have sufficiently largeVGS6, otherwise M6=triode since M7=Sat.
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Vb Generation Circuit
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Iout versus Vout