cascode amplifier - wayne state universitywebpages.eng.wayne.edu/cadence/ece6570/doc/lect8_1.pdf ·...
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Cascode Amplifier Figure 1(a) shows a cascode amplifier with ideal current source load. Figure 1(b) shows the ideal current source is implemented by PMOS with constant gate to source voltage.
Vo
VDD
M1
(a)
VG2
Vi
M2
VG3
VDD
Vo
Vi M1
M3
(b)
VG2M2
VTN0+∆V=
VDD-(|VTP0|+|∆V|)=
VTN0+VTN2+2∆V=
|VTP0|+|∆V|
VTN2+∆V
VTN0+∆V
(3)
(2)
(7)
(6)
(1)
(5)
(4) VSS=0
VTN0+∆V
∆V
∆V
Figure 1. Cascode amplifier with simple current load.
1. Low Frequency Small Signal Equivalent Circuit Figure 2(a) and 2(b) show its low frequency small signal equivalent circuit. Figure 2( c) shows its two-port representation and port variables assignment.
1
G1 D1
S1
S2 D2
Vo
+
Vi
--
gds1
gds2 gds3
+
gm1vgs1
gm2vgs2
gmb2vbs2
+
-
VS2
vgs2=-VS2; vbs2=-VS2
G1 D1
S1
S2 D2
Vo
+
Vi
--
gds1
gds2 gds3
+
gm1vgs1
gm2VS2
gmb2VS2
+
-
VS2
vgs2=-VS2; vbs2=-VS2
ZibZob
GLYa YbVi
+ +
V1a V2a = V1b
I1a I2bI2a I1b
Zoa
Figure 2. Cascode amplifier low frequency small signal equivalent circuit.
2
)0or Z(YY );ror Z(gYY SaSSds3
bLds3
bLL =∞=====
The current equation of network a is:
a2ds1
a1m1
a2
a1
VgVgI
0I
+=
=
The corresponding Y-parameter matrix is:
=
ds1m1
a
gg00
Y
The current equation of network b is:
b2ds2
b1ds2mb2m2
b2
b2ds2
b1ds2mb2m2
b1
Vg)Vggg(I
Vg-)Vggg(I
+++−=
++=
The corresponding Y-parameter matrix is:
++−
−++=
ds2ds2mb2m2
ds2ds2mb2m2b
g)ggg(gggg
Y
The common gate stage gain is:
ds3ds2
ds2mb2m2bL
b22
b21b
V ggggg
YyyA
+++
=+
−=
The input impedance of common gate stage (the load of common source stage) is:
m2ds3ds2mb2m2
ds3ds2bL
b11
b
bL
b22a
Lbi g
2g)ggg(
ggYydetY
YyZZ ≈++
+=
++
==
The gain of the common source stage is:
2gg
2g-g)gg(gggggg
)gg(g
g)ggg()g(gg)gg(g
ggg)ggg(
g
gYy
yA
mb2m2
m1
ds3mb2m2ds3ds2ds3ds1ds2ds1
ds3ds2m1
ds3ds2mb2m2ds3ds2ds1
ds3ds2m1
ds3ds2
ds3ds2mb2m2ds1
m1aL
a22
a21a
V
≈+
≈++++
+−=
+++++−
=
+++
+
−=
+−
=
Assuming all gm are equal, and all gds are equal. In addition gm >>gmb, and gm>>gds. With a gain of 2 the miller capacitance Cgd1 of the common source stage is negligible.
3
The overall gain is:
ds
m
ds3ds2mb2m2ds3ds1ds2ds1
ds2mb2m2m1
ds3mb2m2ds3ds2ds3ds1ds2ds1
ds3ds2m1
ds3ds2
ds2mb2m2aV
bVV
gg
g)ggg(gggg)ggg(g-
g)gg(gggggg)gg(g
ggggg
AAA
−≈
++++++
=
++++
+−
+
++==
The output impedance of the cascode amplifier is computed by obtaining the output impedance of the common source stage ( or the source impedance of the common gate stage) first. That is,
ds1a22
aS
a22
a
aS
a11b
Sao g
1y1
YydetYYy
ZZ ==++
==
The result is obtained by dividing the numerator and denominator by YSa . The output impedance of the
cascode is the output impedance of the common gate stage.
ds1ds2m2ds2ds1ds1ds2mb2m2ds1ds2
ds1ds2mb2m2b
Sb22
b
bS
b11b
o rrgrrrr)gg(gg
ggggYydetY
YyZ ≈+++=
+++=
++
=
That is, the output impedance is equal to the output impedance, rds1 , of the first stage (common source) magnified by the gain, gm2rds2 , of the second stage (common gate ). The effective load is the parallel combination of output impedance of the cascode amplifier and the load.
ds3ds3ds1ds2m2ds3ds2ds1ds1ds2mb2m2Lboo r)//rrrg(r//)rrrr)gg((Z//ZZ ≈≈+++==
The overall gain is approximately equal to :
ds3m1om1V rgZgA −≈−= Although the output impedance has been magnified but the effective load impedance is determined by smaller impedance. That is, rds3. The overall gain of the cascode amplifier can be increased if we can increased rds3. This can be achieved by adding a cascode at the load. This is shown in Figure 3. Figure 4 shows its low frequency small signal equivalent circuit and its two-port representations and port variables assignment. There are three two-port networks. The Y-parameter matrices are derived as follows: The current equation of network a is:
a2ds1
a1m1
a2
a1
VgVgI
0I
+=
=
The corresponding Y-parameter matrix is:
4
=
ds1m1
a
gg00
Y
The current equation of network b is:
b2ds2
b1ds2mb2m2
b2
b2ds2
b1ds2mb2m2
b1
Vg)Vggg(I
Vg-)Vggg(I
+++−=
++=
The corresponding Y-parameter matrix is:
++−
−++=
ds2ds2mb2m2
ds2ds2mb2m2b
g)ggg(gggg
Y
The current equation of network c is:
c2ds3
c1ds3mb3m3
c2
c2ds3
c1ds3mb3m3
c1
Vg)Vggg(I
Vg-)Vggg(I
+++−=
++=
The corresponding Y-parameter matrix is:
++−
−++=
ds3ds3mb3m3
ds3ds3mb3m3c
g)ggg(gggg
Y
The output impedance of network b has been obtained earlier it is,
ds1ds2m2ds2ds1ds1ds2mb2m2bo rrgrrrr)gg(Z ≈+++=
The output impedance of network c is computed as follows:
ds4ds3m3ds4ds3ds4ds3mb3m3ds4ds3
ds4ds3mb3m3cS
c22
c
cS
c11c
o rrgrrrr)gg(gg
ggggYydetY
YyZ ≈+++=
+++=
++
=
The effective load impedance is the parallel compbination of the output impedance of network b and c.
2rg
//ZZZ2dsmc
oboo ≈=
Assuming all gm are equal and all gds are equal.
5
Vo
VDD
M1
(a)
VG2
Vi
M2
VG4
VDD
M3
Vo
Vi M1
(b)
VG2M2
M4
VG3
VDD- (|VTP0|+|∆V|)=
VDD-(|VTP0|+|VTP3|+2|∆V|)=
VTN0+VTN2+2∆V=
VTN0+∆V=
(|VTP0|+|∆V|)
(|VTP3|+|∆V|)
VTN2+∆V
VTN0+∆V
(7)
(5)
(1)
(2)
(4) VSS=0
(8)
(9)
(3)
(6)
VDD
VSS VSS
Figure 3. Cascode amplifier with cascode current load.
6
G1 D1
S1
S2 D2
Vo
-
++
Vi
-
gds1
gds2
gds3
gm1vgs1
gm2VS2
gmb2VS2
+
-
VS2
vgs2=-VS2; vbs2=-VS2
gds4
gm3VS3
gmb3V3
+
VS3
-
Yd Yc
Ya Yb
D3S3D4
S4
Zob
Ya YbVi
+
V1a V2a = V1b
I1a I2bI2a I1b
Zoc
Zo
+
Vo
-
Yc
+
gds4
Figure 4. Cascode amplifier with cascode load low frequency small signal equivalent circuit.
7
2. High Frequency Small Signal Equivalent Circuit
VDD
Vo
CL
Vi
M2
M1
Cgd1
Cgs2
Cdb1
Csb2
Cdb2Cgd2
VG1
VG2Cdb3Cgd3
M3
Cgs1
Figure 5. Cascode amplifier parasitic capacitances. Figure 5 shows all the parasitic capacitances needed for high frequency modelling. Figure 6(a) shows the high frequency small signal equivalent circuit of cascode amplifier with simple current load. Figure 6(b) its two-port representation and port variables assignment.
CCCCCC ;CCCC ;CC)0or Z(Y ;CgYY
Lgd3db3db2gd23sb2gs2db12gd11
SS3ds3bLL
++++=++===∞=+== s
The input capacitance Cgs1 is assummed to be part of the input voltage source. Cgs1 is shorted out by the input voltage source, it does not affect the circuit operation, hence can be ignored or deleted.. C3 is assummed to be part of the load. The current of the first stage (network a) is given by:
a221ds1
a11m1
a2
a21
a11
a1
)]VC(Cg[)VC-g(I
VCVCI
+++=
−=
ssss
8
S1
G1 D1 S2 D2
Vo
+
--
gds1
gds2 gds3
+
gm1vgs1
gm2VS2
gmb2VS2
+
-
VS2
vgs2=-VS2; vbs2=-VS2
Zib Zob
GLYa YbVi
+ +
V1a V2a = V1b
I1a I2bI2a I1b
C1
Cgs1C2 C3
C2=Cdb1+Cgs2+Csb2 C3=Cgd2+Cdb2+Cdb3+Cgd3+CLC1=Cgd1
Vi
Figure 6. Cascode amplifier high frequency equivalent circuit. The corresponding Y-parameter matrix is:
++
−=
)]C(Cg[C-gCC
Y21ds11m1
11a
ssss
The current equation of network b is:
9
a2ds2
a1ds2mb2m2
b2
a2ds2
a1ds2mb2m2
b1
Vg )Vggg(I
Vg -)Vggg(I
+++−=
++=
The corresponding Y-parameter matrix is :
++−++
=ds2ds2mb2m2
ds2ds2mb2m2b
g)ggg(g-ggg
Y
The voltage gain of network b is:
3ds3ds2
ds2mb2m2bL
b22
b21b
V Cggggg
YyyA
s++++
=+
−=
The input impedance of network b or load of network a is:
)C)(ggg(gCgg
YydetYYyZZ
3ds3ds2mb2m2
3ds3ds2bL
b11
b
bL
b22a
Lbi s
s+++
++=
++
==
The voltage gain of network a is:
)C)(ggg(g)sCgg)()Cs(Cg()sCg)(gsC-(g-
sCgg)C)(ggg(g
)Cs(Cg
)sC-(g-Yy
y-A
3ds3ds2mb2m23ds3ds221ds1
3ds3ds21m1
3ds3ds2
3ds3ds2mb2m221ds1
1m1aL
a22
a21a
V
s
s
++++++++++
=
+++++
+++=
+=
The overall gain of the cascode amplifier is:
10
)ggg(ggggc)ggg(gggg
)g(gC)g(gC)ggg(gCb
)ggg(gggg)C(CC
a
:where]abc[1
)gg)(gsC-(g-)C)(ggg(g)sCgg)()Cs(Cg(
)gg)(gsC-(g-)C)(ggg(g)sCgg)()Cs(Cg(
)sCg)(gsC-(g-
Cggggg
AAA
ds2ds1mb2m2ds3ds2ds1
ds2ds1mb2m2ds3ds2ds1
ds3ds21ds3ds22mb2m2ds2ds13
ds2ds1mb2m2ds3ds2ds1
213
2ds2mb2m21m1
3ds3ds2mb2m23ds3ds221ds1
ds2mb2m21m1
3ds3ds2mb2m23ds3ds221ds1
3ds3ds21m1
3ds3ds2
ds2mb2m2
aV
bVV
++++=++++
+++++++=
+++++
=
++++
=
++++++++++
=
++++++++
++
++++
=
=
ss
s
s
s
If the poles are far apart, it can be approximated as follows:
|p||p| :wherepp1
p11
pp1
p1
p11
p1
p1ab1)D(
12
2
211
2
212121
2
>>
+
−≈
+
+−=
−
−=++= sssssssss
That is,
21
m2
213
ds3ds21ds3ds22mb2m2ds2ds132
3
ds3
ds3ds21ds3ds22mb2m2ds2ds13
ds2ds1mb2m2ds3ds2ds11
CCg
)C(CC])g(gC)g(gC)ggg(gC[
abp
Cg
)g(gC)g(gC)ggg(gC)]ggg(ggg[g-
b1p
+−
≈+
+++++++−=
−=
−≈
+++++++++++
=−
=
Note that the poles are associated with the inverse product of the resistance and capacitance of a node to ground. p1 is associated with node D2 to ground, and p2 is associated with D1 (or S2) to ground. The cascode amplifier also has a zero at the right half plane given by:
1
m11 C
gz =
11
Cascode Amplifier Experiments
3. Cascode Amplifier with Simple Current Load The biasing voltages will be determined by ignoring the effect of the bulk voltage on M2. Using the biasing principle discussed in the current sink/source section. The biasing requirement from Figure 1(b) are:
5.2V|)5.1||1(|V|)V||V(|VV52(1.5)2(1)V2V2V
2.51.51VVV
DDDDTP0DDG3
TNG2
TN0bias
−=+−−=∆+−==+=∆+=
=+=∆+=
The output voltage dynamic range with the above biasing is:
5.7V If ;6V45.1VV42(1.5)1
VVVV2V
DDO
DDO
DDOTN
=≤≤−≤≤=+∆−≤≤∆+
52.57.52.5-VV DDG3 =−== The effect of bulk bias on M2 on the output voltage will be considered next. The actual minimum output voltage will be determined. The threshold voltage of M2 is no longer equal to VT0, due to the present of the bulk bias.
6V325.3
25.35.175.1VVV
1.5VV
1.751.5-1.75-5VVVV75.1V
iterationby Vfor Sove)VVV(VV
VVVV)V(V)V(VV
VV
O
DS2(min)DS1(min)O(min)
DS2(min)
TN2G2DS1(min)
TN2
TN2
TN2G2T0TN2
TN2G2DS1
DS1TN0BS2TN0TN2
DS1BS2
≤≤
=+=+=
=∆=
==∆−−==
−∆−−++=
∆−−=
−++=−−+=
−=
φφγ
φφγφφγ
The bulk bias increases the output voltage dynamic range. Using the above biasing voltages, Pspice simulation is conducted to obtain the DC transfer characteristic curve. The Pspice netlist below is used to obtain the DC transfer characteristic.
12
*PSpice file for NMOS Common Gate Amplifier with *PMOS Current Load *Filename="Lab3.cir" VIN 1 0 DC 2.5212VOLT AC 1V VDD 3 0 DC 7.5VOLT VSS 4 0 DC 0VOLT VG2 6 0 DC 5VOLT VG3 7 0 DC 5VOLT M1 5 1 4 4 MN W=9.6U L=5.4U M2 2 6 5 4 MN W=9.6U L=5.4U M3 2 7 3 3 MP W=25.8U L=5.4U .MODEL MN NMOS VTO=1 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .MODEL MP PMOS VTO=-1 KP=15U + GAMMA=0.6 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 *Analysis .DC VIN 0 7.5 0.05 .TF V(2) VIN .AC DEC 100 1HZ 10GHZ .PROBE .END The exact Vbias is determined by locating a point in the DC transfer characteristic curve with the highest slope. The AC small signal characteristic and operating node voltages are then obtained at this operating point. The Pspice node voltages at the operating point is given below: NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE ( 1) 2.5212 ( 2) 4.6987 ( 3) 7.5000 ( 4) 0.0000 ( 5) 1.7410 ( 6) 5.0000 ( 7) 5.0000 The voltage at node 5 is 1.7410 which is reasonably closed to the calculated value of VDS1(min)=1.75. If we ignore the bulk bias of M2 the calculated value is :
2.51.51VVV TN0DS1(min) =+=∆+= The DC transfer characteristic curve is given below:
13
Theoretical calculations of the small signal parameters are given below:
36.355dbor 65.756)(.495E6)-E79.132(RgA
mho79.1326)-6)(101E-E3.87(2I2gg
M495.6)-E101)(02(.
1I1rR
A1011)-0-26/2)(2.521-E3.87()V-V-V)(2/(I
87.3uA/V4u)6)(9.6u/4.-E40((W/L)K
outm1V0
DSQN1m2m1
DSQds3out
22T0SSbiasN1DSQ
21NN1
−=−=−=
====
====
===
===
u
u
β
λ
β
β
The Pspice results are:
36.644dbor 95.67AM5.R
V0
out
−==
**** SMALL-SIGNAL CHARACTERISTICS
14
V(2)/VIN = -6.795E+01 INPUT RESISTANCE AT VIN = 1.000E+20 OUTPUT RESISTANCE AT V(2) = 5.000E+05
4. Cascode Amplifier High Frequency Model Experiments The parasitic capacitances will be determined to check the theory against Pspice simulation results. The capacitances are determined at the operating point. The reverse bulk bias are first calculated at the quiescent operating point. For M1 VBD=V(4)-V(5)=0-1.7410=-1.7410 VBS=0, bulk connected to source For M2 VBD=V(4)-V(2)=0-4.6987=-4.6967 VBS=V(4)-V(5)=0-1.7410=-1.7410 For M3 VBD=-(V(3)-V(2))=-(7.5-4.6987)=-2.8013 The MATLAB program is invoked to obtain the parasitic capacitances. For M1, [CGS,CGD,CBD,CBS]=cap(9.6,5.4,-1.7410,0) CGS=23.2704fF, CGD=3.84fF, CGD=24.1791fF, CBS=61.84fF For M2,
[CGS,CGD,CBD,CBS]=cap(9.6,5.4,-4.6987,-1.7410) CGS=23.2704fF, CGD=3.84fF, CGD=16.0715fF, CBS=38.2591fF For M3,
[CGS,CGD,CBD,CBS]=cap(25.8,5.4,-2.8013,0) CGS=62.5392fF, CGD=10.32fF, CGD=47.956fF, CBS=152.02Ff In the simulation without specifying the area and perimeter of source and drain, only Cgs and Cgd are accounted in computing the parasitic capacitances. These are calculatedbelow: C1=Cgd1=3.84fF C2=Cgs2=23.2704fF C3=Cgd2+Cgd3+CL=3.84fF+10.32fF+0=14.16fF
15
19.1243.6238.15904.898E9
E938.9tan-34.1E99.38E9tan-90
pw
tan-z
wtan-90PM
G43.52
E91.342zf
E91.3415-E84.3
6-E79.132Cgz
G7799.2
E9898.42pf
E9898.415-E)2704.2384.3(
6-E79.132CC
gp
G493.12
E938.92
wf
9.38E9E6)67.142)(75.65(wAw
M7.222
E667.1422
wf
E667.14215)-E6)(14.16E495.0(
1Cr
1pw
1-1-
2
GBW1-GBW1-
z
1
m1
2p2
21
m22
GBWGBW
BWV0GBW
BWBW
3ds31BW
=−−=
=
=
===
===
===
=+−
=+
−=
===
===
===
====
ππ
ππ
ππ
ππ
In the Pspice simulation, if the PM is determined at the frequency where zero db gain occurs the result is:
33.84PM@0dbG 1fGBW
==
This result seem to be quite different from the theoretical result of
12.19PMG493.1fGBW
==
The discrepancy occurs because the non-dominant pole p2=4.898E9 occurs before the gain bandwith product wGBW=9.38E9. The gain bandwidth calculation assume that the slope of –20db/dec is maintain before intersecting the zero db line. With p2 occuring before wGBW means that the slope becomes –40db/dec, causing it to intersect the zero db gain line sooner. If one extend the –20db/dec line in the Pspice simulation, this line will intersect the zero db gain axis at:
1.53GM)496.22)(95.67(fAf BWV0GBW === If the phase margin is determined at 1.53G, the result is 16.744° which is closer to the theretical calculation of 12.19°. That is, the
16
theretical calculation will be in error if the non-dominant pole p2 occurs before wGBW.
17
The PM of 33.84 is rather low. For stability a PM of at least 60 is desirable. Looking at the PM calculation, one can increase the PM by decreasing wGBW. Increasing the value of capacitor C3 will decrease wGBW while maintaining the value of p2. C3 is a function of the load capacitance CL. One can compute the value of CL needed to achieve the desired PM. To illustrate this we will compute the value of CL for a PM=80. First compute wGBW to achieve PM=80.
G75.0w
104.898E9
wtan
34.1E9w
tan
10p
wtan
zw
tan
80p
wtan-
zw
tan-90PM
GBW
GBW1-GBW1-
2
GBW1-GBW1-
2
GBW1-GBW1-
=
=
+
=
+
=
=
The value of load capacitance is then calculated to achieve wGBW.
18
168.87fF14.16fF-183.03fF14.16fF-.75E9)(.495E6)(0
67.95fF16.14wr
AC
C fF16.14wr
AC
Cr1Aw
GBWds3
V0L
LGBWds3
V03
3ds3V0GBW
===−=
+==
=
The result of Pspice simulation with CL added shows that PM is now 82.195°.
Filename=”cascexp3.doc”
5. Cascode Amplifier With Cascode Current Load Experiments The derivation of the biasing circuit is shown in Figure 7. The complete circuit is shown in Figure 8.
19
MBP2
MBP1
(3) VDD
(4) VSS
(9)
(8)
IBP=101UA
MBN2
MBN1
(7)
(10)
+Vin (1)
IBN=101UA
MBP2
MBP1
(9)
(8)
(3) VDD
(4) VSS
IBP=101UA
MBN2
MBN1
(7)
(10)
+Vin (1)
(9)
(8)
(a) (b)
(c) Figure 7. Biasing circuit for the cascode amplifier with cascode load.
20
MBP2
MBP1
(9)
(8)
(3) VDD=10
(4) VSS=0
MBN2
MBN1
(7)
(10)
+Vin (1)
(9)
(8)
MBP4
MBP3
M4
M3
M2
M1
(2)
(6)
(5)
Vo
IBP
Figure 8. Complete circuit of the cascode amplifier with cascode load. Netlist for the complete circuit of Figure 8 is shown below: *PSpice file for NMOS Common Gate Amplifier with *PMOS Current Load *Filename="Lab32b.cir" *All bulks are connected to supply rail .PARAM Wn=9.6U, Ln=5.4U .PARAM Wp=25.8U, Lp=5.4U VIN 1 10 DC 0VOLT AC 1V VDD 3 0 DC 10VOLT VSS 4 0 DC 0VOLT M1 5 1 4 4 NMOS1 W={Wn} L={Ln} M2 2 7 5 4 NMOS1 W={Wn} L={Ln} M3 2 8 6 3 PMOS1 W={Wp} L={Lp} M4 6 9 3 3 PMOS1 W={Wp} L={Lp} *Biasing circuit MBN1 10 10 4 4 NMOS1 W={Wn} L={Ln} MBN2 7 7 10 4 NMOS1 W={Wn} L={Ln} IBP 8 4 100UA MBP1 8 8 9 3 PMOS1 W={Wp} L={Lp} MBP2 9 9 3 3 PMOS1 W={Wp} L={Lp} MBP3 7 8 11 3 PMOS1 W={Wp} L={Lp} MBP4 11 9 3 3 PMOS1 W={Wp} L={Lp}
21
.MODEL NMOS1 NMOS VTO=1 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .MODEL PMOS1 PMOS VTO=-1 KP=15U + GAMMA=0.6 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 *Analysis .DC VIN -2.5 7.5 0.05 .TF V(2) VIN .AC DEC 100 1HZ 10GHZ .PROBE .END NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE ( 1) 2.4774 ( 2) 5.9211 ( 3) 10.0000 ( 4) 0.0000 ( 5) 2.4774 ( 6) 7.5450 ( 7) 5.9211 ( 8) 4.4772 ( 9) 7.5280 ( 10) 2.4774 ( 11) 7.5450 The biasing voltages are obtained from the above table VG1=Vbias=V(10)=2.4774 VG2=V(7)=5.9211 VG3=V(8)=4.4772 VG4=V(9)=7.5280 The low frequency small signal parameters are:
mho13.1326)-6)(100E-E3.87(2I2gg
M5.6)-E100)(02(.
1I1rr
IuA 100I87.3uA/V4u)6)(9.6u/4.-E40((W/L)K
DSQN1m2m1
DSQds2ds1
BIASDSQ
21NN1
u====
====
=====
β
λ
β
22
2182.78)6)(16.52E6-E13.132(RgA
M52.162
0.5E6)6)(0.5E6)(-E13.132(2
rrgR
outm1V0
ds1ds2m2out
===
===
Pspice simulation results: **** SMALL-SIGNAL CHARACTERISTICS V(2)/VIN = -3.136E+03 INPUT RESISTANCE AT VIN = -2.424E+19 OUTPUT RESISTANCE AT V(2) = 2.342E+07
23
6. Cascode Amplifier Design Example
24
Design specification Given: AV>=10,000 Ro>=10Meg Find: VDD, acceptable output voltage swing, and transistor sizing
MBP2
MBP1
(9)
(8)
(3) VDD
(4) VSS=0
MBN2
MBN1
(7)
(10)
+Vin (1)
(9)
(8)
MBP4
MBP3
M4
M3
M2
M1
(2)
(6)
(5)
Vo
IBP
(11)
VTN0+∆V
VTN+∆V
|VTP0|+|∆V|
|VTP|+|∆V|
VDD-(|VTP0|+|VTP|+2|∆V|)
VTN0+VTN+2∆V
Design Procedure
umho1000M10
10000RA
g
R-gA
O
Vm1
Om1V
−=−=−=
=
OOPON
OPONO
2RRR//RRR==
=
M141.010000
2M)10(A2R
AR2
gR2
r
rr ; 2RrgrrgR
VO
V
2O
m1
OO1
O2O1O2
O1m1O1O2m2ON
=====
===≈
25
uA354M)141.0)(02.0(
1r1I
I1r
O1DSQ
DSQO1
===
=
λ
λ
3.356)-6)(354E-2(40E
6)-E1000(I2K
gW/L)(W/L)(
I(W/L)K2I2g2
DSQN
2m1
21
DSQ1NDSQNm1
====
== β
708.06)(35.3)-E40(
6)-E354(2(W/L)K
2I2IV
V)/2)(()V-/2)(V(I
1N
DSQDSQ
22TGSDSQ
====∆
∆==
β
ββ
Output voltage swing neglecting bulk to source effect
e)(acceptabl V5.7V ; 084.5V416.2)acceptable(not V5V ; 584.2V416.2
416.2V))708(.21(VV416.2)708.0(21)V2V(VVV2V
DDDD
DDDD
DDDDO
T0PDDOT0N
=≤≤=≤≤
−=+−≤≤=+
∆+−≤≤∆+
Designing for equal ∆V or βR=1
13.94)3.35(5-15E6-40E(W/L)
KK
W/L)(W/L)( 1P
N33 ====
L3L282
3313.94
LW
LW
LW
L3L9.105
333.35
LW
LW
LW
Peff
P
3
3
3
3
Neff
N
2
2
1
1
=
===
=
===
For Lambda L=0.6
U3LL169.2U282(0.6U)L282W
3U2.8U2(0.5U)3(0.6U)2LD3LLD2LL63.6U63.54U)105.9(0.6UL9.105W
NP
P
NeffN
N
=====
≈=+=+=+=≈===
26
*PSpice file for NMOS Common Gate Amplifier with *PMOS Current Load *Filename="Lab61.cir" *All bulks are connected to supply rail .PARAM Wn=63.6U, Ln=3U .PARAM Wp=169.2U, Lp=3U VIN 1 10 DC 0VOLT AC 1V VDD 3 0 DC 7.5VOLT VSS 4 0 DC 0VOLT M1 5 1 4 4 NMOS1 W={Wn} L={Ln} M2 2 7 5 4 NMOS1 W={Wn} L={Ln} M3 2 8 6 3 PMOS1 W={Wp} L={Lp} M4 6 9 3 3 PMOS1 W={Wp} L={Lp} *Biasing circuit MBN1 10 10 4 4 NMOS1 W={Wn} L={Ln} MBN2 7 7 10 4 NMOS1 W={Wn} L={Ln} IBP 8 4 354UA MBP1 8 8 9 3 PMOS1 W={Wp} L={Lp} MBP2 9 9 3 3 PMOS1 W={Wp} L={Lp} MBP3 7 8 11 3 PMOS1 W={Wp} L={Lp} MBP4 11 9 3 3 PMOS1 W={Wp} L={Lp} .MODEL NMOS1 NMOS VTO=1 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .MODEL PMOS1 PMOS VTO=-1 KP=15U + GAMMA=0.6 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 *Analysis .DC VIN -2.5 7.5 0.05 .TF V(2) VIN .AC DEC 100 1HZ 10GHZ .PROBE .END **** SMALL-SIGNAL CHARACTERISTICS V(2)/VIN = -1.268E+04 INPUT RESISTANCE AT VIN = -1.318E+19 OUTPUT RESISTANCE AT V(2) = 1.321E+07 NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE ( 1) 1.7334 ( 2) 4.2146 ( 3) 7.5000 ( 4) 0.0000 ( 5) 1.7334 ( 6) 5.7694 ( 7) 4.2146 ( 8) 3.5826
27
( 9) 5.7657 ( 10) 1.7334 ( 11) 5.7694
The circuit is simulated with VDD=5V to show that the resulting the cascode does not yield the desired gain and output impedance. Replace the VDD line in the netlist to:
28
VDD 3 0 DC 5VOLT **** SMALL-SIGNAL CHARACTERISTICS V(2)/VIN = -1.216E+01 INPUT RESISTANCE AT VIN = 3.651E+18 OUTPUT RESISTANCE AT V(2) = 1.285E+04 NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE ( 1) 1.7233 ( 2) 4.1910 ( 3) 5.0000 ( 4) 0.0000 ( 5) 1.7233 ( 6) 4.3287 ( 7) 4.1910 ( 8) 1.0826 ( 9) 3.2657 ( 10) 1.7233 ( 11) 4.3287
29