baseband implementation of an ofdm system for 60ghz radios: from concept to silicon jing zhang...
DESCRIPTION
Design Challenges Meeting performance specification Multi-disciplinary design [communication theory to silicon] Design methodology challenge: Correctness & Efficiency in design representation, synthesis and verification. Tools and Flow needed. Behavior Model Architecture Model RTL Model Silicon Initial Concept Mature EDA tools available System (Behavior/Algorithm) Level Design Architecture Level Design Register Transfer Level Level Design Back-end Flow (Physical Level Design) Design synthesis Design Verification: verify against upper level modelTRANSCRIPT
Baseband Implementation of an OFDM System for 60GHz Radios: From Concept to Silicon
Jing ZhangUniversity of Toronto
System Overview
FEC Encoder
Constellation Mapping IFFT
GI Insertion & Time Domain Windowing
FEC Decoder
Constellation Demapping
Freq. Domain Correction
GI Removal
Freq. Domain Processing
Channel Estimation Synchronization
FFT
Modulation Core
DAC & RF
RF & ADC
Channel
Demodulation Core
• Data rate up to 1.6 Gbps (Possible application: Gigabit Wireless Ethernet) • BPSK/QPSK/16QAM• 1K point FFT/IFFT, 512 MHz sampling frequency
Design Challenges
• Meeting performance specification
• Multi-disciplinary design [communication theory to silicon]
• Design methodology challenge: Correctness & Efficiency in design representation, synthesis and verification. Tools and Flow needed.
Behavior Model
Architecture Model
RTL Model SiliconInitial
Concept
Mature EDA tools available
System (Behavior/Algorithm) Level Design
Architecture Level Design
Register Transfer Level Level Design
Back-end Flow(Physical Level Design)
Design synthesis
Design Verification: verify against upper level model
System Level Design
Performance Target (Data rate, BER…)
OFDM Calculator
Design Constraints (BW, Channel…)
Design Parameters (FFT Size
GI Length…)Meet Spec.?
Rapid Design Exploration Detailed Simulation
Architecture Design
N
Y
Floating PointMatlab Model
Simulation
20 22 24 26 28 30 32 34 36 38 4010
-7
10-6
10-5
10-4
10-3
10-2
10-1
SNR (dB)
BE
R
BER vs SNR (Num. of Symbols Simulated: 40000)
Ideal IFFT & Ideal FFTFinite IFFT & Finite FFT
Architecture Level Design
StatisticalAnalysis
Fixed PointMatlab Model
SimulationWord Length Meet Spec.?
NY
Word-lengthFine-tune
Macro Architecture
Design
Micro Architecture
Design
ArchitectureSpecification
•Finite-Word-Length effect evaluation is critical and time consuming
•Macro architecture design•Functional block identification and interface definition•Global control and data flow arrangement
•Micro architecture design•Pipelining and Parallel processing unit arrangement•Detailed data-path and local control design
Finite-Word-Length Effect Evaluation Architecture Mapping
RTL Level Design & Physical Design
RTL Coding
Fixed PointMatlab Model
ReferenceModel
Simulation
RTL Simulation
Logic Synthesis
ArchitectureSpecification
•Fixed point Matlab model serves as the reference model for RTL model verification
•Stimulus and response files used in the testbench of RTL simulation
•Logic synthesis and P&R: scripts widely used to speed up iteration
•Design result:•Die size: 4.05 mm by 4.85 mm, in TSMC 0.18μm 6LM CMOS process•I/O Signals: 76•Performance: 4 parallel pipelines running at 135 MHz
Stimulus &Response files
Place & Route GDSII