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Apodis

IPL4101M Datasheet

Revision 1.00 April 2011 Copyright © 2011 by IP Light Ltd.

Copyright © 2011 by IP Light Ltd.

All rights reserved.

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orders, that the information is current. IP Light does not assume any liability arising out of the application or use

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IP Light Ltd. 4 Hashiloach Street

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Israel

April 28, 2011

Creating an Intelligent Optical Layer IPL4101M Datasheet

iii Revision History IP Light Proprietary and Confidential

Revision History

The following table chronicles the changes made to the IPL4101M Datasheet.

Table 1: Revision History

Revision Date Description

1.00 April 2011 Initial version release.


iv Contents IP Light Proprietary and Confidential

Contents

IPL4101M – APODIS FAMILY OTN PROCESSOR ................................................................................. XI Key Features .................................................................................................................................................... xi

GETTING STARTED ........................................................................................................................... XII About This Manual .......................................................................................................................................... xii

Related Documents ......................................................................................................................................... xii

Document Conventions ................................................................................................................................... xii

1 HIGH LEVEL SYSTEM DESCRIPTION ............................................................................................ 1 1.1 Signal Descriptions ...................................................................................................................................9

1.1.1 Client Signal Processor Interfaces ..................................................................................................................10 1.1.2 Network Signal Processor Interfaces ..............................................................................................................14 1.1.3 Input Clock Signal Interface ...........................................................................................................................16 1.1.4 Output Reference Clock Signal Interface ........................................................................................................16 1.1.5 External Overhead Signal Interface ................................................................................................................20 1.1.6 Host Processor Interface Signal .....................................................................................................................21 1.1.7 Control Signal Interface .................................................................................................................................23 1.1.8 JTAG Interface ..............................................................................................................................................23

1.2 Power and Ground Pins .......................................................................................................................... 24

1.3 Pinout .................................................................................................................................................... 26

2 FUNCTIONAL DESCRIPTION ..................................................................................................... 30 2.1 Client and Network Interfaces ................................................................................................................ 30

2.1.1 IPLightSERDES™ ............................................................................................................................................31 2.1.2 Serial Interface..............................................................................................................................................35 2.1.3 XBI2 ..............................................................................................................................................................36 2.1.4 XAUI Interface ..............................................................................................................................................37 2.1.5 FEC ...............................................................................................................................................................38

2.2 Clock Outputs ......................................................................................................................................... 39

2.3 External Overhead Interface ................................................................................................................... 40 2.3.1 EOI Description .............................................................................................................................................42 2.3.2 EOI Timing Diagrams .....................................................................................................................................45

2.4 Host Processor Interface ........................................................................................................................ 46 2.4.1 HPI Description .............................................................................................................................................46 2.4.2 Freescale Mode ............................................................................................................................................47 2.4.3 Intel Mode ....................................................................................................................................................48

2.5 JTAG Interface ........................................................................................................................................ 50

3 DESIGN CONSIDERATIONS ....................................................................................................... 51 3.1 IPLightSERDES™ Interface ....................................................................................................................... 51

3.2 Reference Clock ..................................................................................................................................... 52

3.3 Power and Ground Connections ............................................................................................................. 53

3.4 Package Information .............................................................................................................................. 54

4 ELECTRICAL AND MECHANICAL DATA ...................................................................................... 55 4.1 Absolute Maximum Ratings .................................................................................................................... 55

4.2 Normal Operating Conditions ................................................................................................................. 56 4.2.1 DC Characteristics .........................................................................................................................................56 4.2.2 AC Characteristics .........................................................................................................................................57

4.3 High Speed Differential IO Characteristics ............................................................................................... 57

4.4 EOI Characteristics ................................................................................................................................. 57


v Contents IP Light Proprietary and Confidential

4.5 HPI Characteristics ................................................................................................................................. 58

4.6 JTAG Characteristics ............................................................................................................................... 60

4.7 Output Clock Parameters ....................................................................................................................... 61

4.8 Reset Signal Parameters ......................................................................................................................... 61

4.9 Thermal Information .............................................................................................................................. 62

4.10 Power .................................................................................................................................................... 62

5 ORDERING INFORMATION....................................................................................................... 64


vi Figures IP Light Proprietary and Confidential

Figures

Figure 1: IPL4101M Block Diagram...................................................................................................... 1

Figure 2: Client Signal Processor Detailed Block .................................................................................. 2

Figure 3: Client Side Port OTN Multiplexing and Mapping Structures .................................................. 4

Figure 4: Network Signal Processor Detailed Block .............................................................................. 5

Figure 5: OTU2 Add/Drop Example ..................................................................................................... 6

Figure 6: Network Side Port OTN Multiplexing and Mapping Structures .............................................. 7

Figure 7: IPLightSERDES™ Naming Convention .................................................................................... 9

Figure 8: IPL4101M Pinout Upper Left Quadrant (Bottom View) ....................................................... 26

Figure 9: IPL4101M Pinout Upper Right Quadrant (Bottom View) ..................................................... 27

Figure 10: IPL4101M Pinout Lower Right Quadrant (Bottom View) ................................................... 28

Figure 11: IPL4101M Pinout Lower Left Quadrant (Bottom View) ..................................................... 29

Figure 12: IPLightSERDES™ Block Diagram ........................................................................................ 31

Figure 13: Quad IPLightSERDES™ ...................................................................................................... 32

Figure 14: End-to-End Loopback Path ............................................................................................... 34

Figure 15: XBI2-4 Lane Assignments.................................................................................................. 36

Figure 16: XBI2-2 Lane Assignments.................................................................................................. 37

Figure 17: EFEC ................................................................................................................................. 38

Figure 18: Clock Outputs................................................................................................................... 39

Figure 19: External Overhead Interface............................................................................................. 40

Figure 20: EOI OTN Insertion ............................................................................................................ 41

Figure 21: EOI OTN Extraction........................................................................................................... 42

Figure 22: OHCID Bits ....................................................................................................................... 42

Figure 23: OTN OH Structure ............................................................................................................ 44

Figure 24: SONET/SDH OH Structure ................................................................................................. 44

Figure 25: EOI Clock and Signal Timing Relationship .......................................................................... 45

Figure 26: TxMFAS Timing ................................................................................................................ 45

Figure 27: HPI Interface with Host Processor .................................................................................... 46

Figure 28: Freescale Interface Read Timing Cycle .............................................................................. 47

Figure 29: Freescale Interface Write Timing Cycle ............................................................................. 48

Figure 30: Intel Mode Endian Selection ............................................................................................. 48

Figure 31: Intel Interface Read Timing Cycle ..................................................................................... 49

Figure 32: Intel Interface Write Timing Cycle .................................................................................... 49

Figure 33: IPLightSERDES™ Interface................................................................................................. 51

Figure 34: Reference Clock ............................................................................................................... 52

Figure 35: IPL4101M Decoupling for Power and Ground Connections ............................................... 53

Figure 36: IPL4101M Package Dimensions ........................................................................................ 54

Figure 37: EOI Timing Characteristics ................................................................................................ 58


vii Figures IP Light Proprietary and Confidential

Figure 38: HPI Read Timing Characteristics ....................................................................................... 59

Figure 39: HPI Write Timing Characteristics ...................................................................................... 59

Figure 40: JTAG TMS and TDI Timing ................................................................................................. 60

Figure 41: RST_N Timing ................................................................................................................... 61


viii Tables IP Light Proprietary and Confidential

Tables

Table 1: Revision History ................................................................................................................... iii

Table 2: Glossary of Terms ................................................................................................................. ix

Table 3: Apodis Product Family ......................................................................................................... xii

Table 4: Signal Mapping Options......................................................................................................... 3

Table 5: Client Side Signal Interface Pins ........................................................................................... 10

Table 6: Network Side Signal Interface Pins ...................................................................................... 14

Table 7: External Input Reference Clock Signal Interface Pins ............................................................ 16

Table 8: Output Reference Clock Signal Interface Pins ...................................................................... 16

Table 9: EOI Signal Pins ..................................................................................................................... 20

Table 10: HPI Signal Pins ................................................................................................................... 21

Table 11: Control Signal Interface Pins .............................................................................................. 23

Table 12: JTAG Interface Pins ............................................................................................................ 23

Table 13: Power and Ground Pins ..................................................................................................... 24

Table 14: Lane Assignment Configurations........................................................................................ 33

Table 15: Lane Rates ......................................................................................................................... 33

Table 16: OTU2/ODU2 Information Lane Assignment for XBI2-4 ....................................................... 36

Table 17: Lane Assignment for XBI2-2 ............................................................................................... 37

Table 18: XAUI Clock Rates ............................................................................................................... 37

Table 19: Clock Output Rates ............................................................................................................ 39

Table 20: OHCID Bit Descriptions ...................................................................................................... 43

Table 21: Output Drive Capability ..................................................................................................... 51

Table 22: Absolute Maximum Ratings ............................................................................................... 55

Table 23: DC Characteristics for CMOS Pins ...................................................................................... 56

Table 24: AC Characteristics for CMOS Pins....................................................................................... 57

Table 25: High Speed Differential IO Parameters .............................................................................. 57

Table 26: EOI Timing Characteristics ................................................................................................. 57

Table 27: HPI Characteristics ............................................................................................................ 58

Table 28: JTAG Characteristics .......................................................................................................... 60

Table 29: Input Reference Clock Parameters ..................................................................................... 61

Table 30: Output Reference Clock Tolerances ................................................................................... 61

Table 31: Reset Parameters .............................................................................................................. 61

Table 32: Thermal Resistance ........................................................................................................... 62

Table 33: Typical Power Dissipation .................................................................................................. 62

Table 34: Part Number ..................................................................................................................... 64


ix Glossary IP Light Proprietary and Confidential

Glossary

The glossary contains acronyms and terms specific to the Apodis family of optical transport network processors.

Table 2: Glossary of Terms

Term Description

AIS Alarm Indication Signal

ADM Add/Drop Multiplexer

AMP Asynchronous Mapping Procedure

APS Automatic Protection Switching

BEI Backward Error Indication

BER Bit Error Rate

BIAE Backward Incoming Alignment Error

BIP-8 Bit Interleaved Parity 8

BMP Bit Synchronous Mapping

CID Channel Identification

CPI Client side Physical Interface

CSF Client Signal Fail

CSP Client Signal Processor

DWDM Dense Wave Division Multiplexing

EFEC Enhanced FEC

EOI External Overhead Interface

FAS Frame Alignment Signal

FBC Fibre Channel

FEC Forward Error Correction

GbE Gigabit Ethernet

GFC Gigabit Fibre Channel

GFP-F Generic Framing Procedure—F

GFP-T Generic Framing Procedure—T

GMP Generic Mapping Procedure

HPI Host Processor Interface

IPG Inter-Packet Gap

JC Justification Control

LOF Loss of Frame

LOS Loss of Signal

MFAS Multi-Frame Alignment Signal

MLD Multiple Lane Distribution

NJO Negative Justification Opportunity

NPI Network side Physical Interface

NSP Network Signal Processor

OAM Operations, Administration, and Maintenance

ODTUjk Optical Channel Data Tributary Unit j into k


x Glossary IP Light Proprietary and Confidential

Term Description

ODU Optical Channel Data Unit

OHH OverHead Handler

OHO OverHead Operator

OPU Optical Channel Payload Unit

OTN Optical Transport Network

OTU Optical Channel Transport Unit

PCC Protection Communication Channel

PCS Physical Coding Sublayer

PJO Positive Justification Opportunity

PM Performance Monitoring

PRBS Pseudo-Random Binary Sequence

PT Payload Type

RMON Remote network MONitoring

SDH Synchronous Digital Hierarchy

SerDes Serializer/Deserializer

SFP Small Form-Factor Pluggable

SONET Synchronous Optical Network

TAF Transparent Agnostic Fabric

TCM Tandem Connection Monitoring

TCMA Tandem Connection Monitoring Activation

TIM Trail Trace Identifier Mismatch

TTI Trail Trace Identifier

XAUI 10Gb Attachment Unit Interface

XBI2 High Speed (10Gbps) Backplane Interface for OTU2/ODU2

XFI 10 Gigabit Small Form-Factor Pluggable Module Interface

XGMII 10 Gigabit Media Independent Interface


xi IPL4101M – Apodis Family OTN Processor IP Light Proprietary and Confidential

IPL4101M – Apodis Family OTN Processor The IPL4101M is a member of the Apodis family of ITU-T compliant Optical Transport Network (OTN) processors. The IPL4101M offers termination, processing, framing, multiplexing, demultiplexing, switching, and mapping of OTN signals, in addition to Client side mapping of SONET/SDH, Ethernet, and Fibre Channel signals to OTN signals. The Client side supports any-service, any-port over 16 ports, and the Network side gives full OTN capability over two 10Gbps ports, resulting in 20Gbps of full duplex bandwidth. The IPL4101M incorporates a fully available, non-blocking OTN switching fabric, allowing switching between Client/Network, Client/Client, and Network/Network ports. The tremendous flexibility and high bandwidth that the IPL4101M provides makes it ideal for access, metro, metro-core and long haul applications.

Key Features

Network ports support OTU2, OTU2e/1e, and OTU2f/1f signals

Two configurable network ports support serial (XFI or SFP+) and XBI2 (2 or 4 lane) interfaces

Client ports support the following signals:

1/10 Gigabit Ethernet 1/10 Gigabit Fibre Channel SONET OC-48/OC-192 SDH STM-16/STM-64 CBR 2G5/10G OTN OTU1 OTN

OTU2/OTU1e/OTU2e/OTU1f/OTU2f OTU0—A proprietary OTN signal at a

nominal rate of 1.328 Gbps (255/239x1244160 Kbps) with no FEC

16 configurable client ports support serial (XFI, SFP+, or SFP), XAUI, and XBI2 (2 or 4 lane) interfaces

20 Gbps full duplex bandwidth

Maps client signals (SONET/SDH, Ethernet, Fibre Channel, CBR) to OTN ODU0/1/2 signals

Non-blocking, fully transparent switch fabric for OTN signals with the following capabilities:

ODU0/1/2 switching granularity Simultaneous multicasting

Provides six levels of TCM (tandem connection monitoring) overhead processing for all ODU0/1/2 signals

Includes standard G.709 FEC for all OTU1/2 signals, plus enhanced FEC (EFEC, as specified in clause I.4 of ITU-T G.975.1) for network side OTU2 signals

Roundtrip delay measurements on ODU and TCM paths

Supports OTN Performance Monitoring counters, alarms and indications

Full internal processing of all OTN overhead bits

Maintenance is provided by terminal and network loopback capabilities supporting network level fault isolation

Full access to all OTN overhead fields, including GCC0/1/2

Multiple performance monitoring (PM) options, PM counters, alarms, indications and optional regeneration of SONET/SDH section level overheads

Access to SONET/SDH section level DCC, F1, and E1 fields

Multi-gigabit IPLightSERDES™ supports any-service, any-port configurations from 1G to 11.4G

Integrated jitter attenuators meet or exceed telecom and data communication standards with no need for external components

Integrated synthesizers generate all required internal timing from a single external reference clock

RMON support

GbE link layer OAM

ODU2 signal interface option to support applications requiring external circuitry, such as UFEC, and so on

Intel/Freescale host interface bus

Power savings mechanisms

Package: 31 x 31 mm, 896 pin HFC-BGA

Supply voltages: 1V and 2.5V

RoHS compliant


xii Getting Started IP Light Proprietary and Confidential

Getting Started

The IPL4101M device is a member of the Apodis OTN Processor family. The following table shows the Apodis family which leverages the same architecture to address various applications.

Table 3: Apodis Product Family

Product Name

Client Ports

Network Ports Capacity

Client Signals Network Signals

1GbE 1GFC

OC-48 STM-16 OTU1

OC-192 STM-64 OTU2

10GbE 10GFC OTU1 OTU2

IPL4001M 16 4 40G ✓ ✓ ✓ ✓ ✓

IPL4101M 16 2 20G ✓ ✓ ✓ ✓ ✓

IPL4201M 8 4 10G ✓ ✓ ✓ ✓ ✓ ✓

IPL4301F 4 4 40G ✓ ✓

IPL4401F 2 2 20G ✓ ✓

About This Manual

The IPL4101M Datasheet provides functional information on using the IPL4101M chip, the primary component of IP Light's comprehensive OTN solution. This Datasheet is organized as follows:

High Level System Description in Section ‎1 provides an overview of the IPL4101M chip with

signal and pin descriptions, including block diagrams.

Functional Description in Section ‎2 provides functional details of the IPL4101M interfaces.

Design Considerations in Section ‎3 describes board design guidelines for the IPL4101M chip.

Electrical and Mechanical Data in Section ‎4 describes the IPL4101M parameters and characteristics.

Ordering Information in Section ‎5 provides IPL4101M ordering details.

Related Documents

This IPL4101M Datasheet is intended to be used together with the documents listed below; they contain information and instructions that supplement this manual. This manual instructs you when to refer to these documents.

IPL4101M Product Description—provides a general overview of the IPL4101M.

IPL4101M User Manual—provides in depth information pertaining to the configuration and operation of the IPL4101M.

Document Conventions

This document uses the following term and design conventions.

Terminology Conventions

Except where otherwise noted, these terminology conventions are used throughout the document:

The signal type "OTU2" includes OTU2/1e/2e/1f/2f

The signal type "ODU2" includes ODU2/2e/1e/2f/1f

The signal type "OPU2" includes OPU2/2e/1e/2f/1f

"10G" or "10Gbps" is intended only as a descriptor, while the actual signal nominal rate may vary between 9.953 Gbps for OC-192 and 11.318 Gbps for OTU2f


xiii Getting Started IP Light Proprietary and Confidential

"2.5G" and "5G" are intended as descriptors, while the actual signal rate may vary

Hexadecimal numbers are prefixed with "0x"

Binary numbers are suffixed with the letter "b"

The names "network" and "line" are interchangeable, both representing the side of the chip opposite of the client side

Design Conventions

This document uses the following conventions:

Commands and keywords are in boldface font

Arguments for which you supply values are in italic font

Terminal sessions and information the system displays are in screen font

Information you must enter is in boldface screen font

Elements in square brackets ([ ]) are optional

Notes use the following conventions:

NOTE—Means reader take note. Notes contain helpful suggestions or references to material not covered in the publication.

The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully.

CAUTION—Indicates possibility of service interruption if precautions are not taken.

WARNING—Indicates possibility of damage to the device if precautions are not taken.


1 High Level System Description IP Light Proprietary and Confidential

1 High Level System Description The following figure shows the IPL4101M high level block diagram.

Figure 1: IPL4101M Block Diagram

The IPL4101M contains Client Signal Processor (CSP) blocks, Network Signal Processor (NSP) blocks, IPLightSERDES™ blocks, and the Transparent Agnostic Fabric (TAF) switching block at its core. The IPL4101M interfaces are compliant with the relevant ITU-T and IEEE standards. The IPL4101M also contains a generic host interface for configuration and monitoring, and an External Overhead Interface (EOI) that enables access into the OTN and SONET/SDH overheads.



The following figure shows the CSP block details.

Figure 2: Client Signal Processor Detailed Block

The CSP supports a variety of signal types, including OTN client signals, which can be mapped into OTN carrier signals. The CSP features four parallel paths to operate on up to four low-rate signals and a separate path, which processes high-rate signals.

Within the High Rate signal block the following interfaces are supported:

Serial, lane 2 only, is relevant for all signal types

XAUI, lanes 0-3, is relevant only for 10GFC/10GbE signal types

XBI2, lanes 1-2 (XBI2-2), lanes 0-3 (XBI2-4), is relevant only for OTU2/ODU2 signal types

In addition to the standard OTN interfaces, an OTU0 interface is also supported. OTU0 is a standard ODU0 signal to which the OTU overhead has been added with the FEC bytes set to zeros (0). The resulting signal rate is 255/239 x 1244160 Kbps. An OTU0 can be used to multiplex and map low rate client signals (for example, STM-1, STM-4, video, or FE) before forwarding them to the IPL4101M.



The following table describes the extensive set of mapping options offered by the IPL4101M.

Table 4: Signal Mapping Options

Signal Type ODU0 ODU1 ODU2

1GE GFP-T/GMP 2xGFP-F 8xGFP-F

1GFC GMP

10GE GFP-F (Frames only or

frames, preamble and ordered sets)

Bit Transparent ODU1e/ODU2e

10GFC GFP-T to ODU1e/ODU2e

Bit Transparent ODU1f/ODU2f

OC-48/STM-16/CBR-2G5 Bit Transparent Synch/Async

OC-192/STM-64/CBR-10G Bit Transparent Synch/Async

ODU0 AMP (PT20) GMP (PT21)

ODU1 AMP

These mappings enable non-OTN signal types (such as, SONET/SDH/CBR, Ethernet, and Fibre Channel) to be mapped into the payload of the corresponding ODU according to their relevant rates. In addition, these mappings enable the multiplexing of low order ODUk signals into high order ODUk signals.

NOTE—The payload sizes for an OTU1 and OTU2 exactly match the frame rates of OC-48 and OC-192, respectively.



Client Signal to Client Side Port OTN Multiplexing and Mapping Options

The following figure shows the IPL4101M client signal to client side port OTN multiplexing and mapping options.

Figure 3: Client Side Port OTN Multiplexing and Mapping Structures



The following figure shows the Network Signal Processor block details.

Figure 4: Network Signal Processor Detailed Block

The NSP supports OTN signals and offers ODU0/1/2 granularity connections to the TAF. The OTN signals can be processed at the ODU0, ODU1, or ODU2 levels.

The ODU2 interface supports signals at the ODU2 rate and is used when interfacing the IPL4001M to an external device, for example a device handling a higher order signal (ODU3 or ODU4), an external FEC, or an interface to a external switch matrix. The ODU2 signal is scrambled to allow clock recovery and includes the OPU2 signal (overhead and payload) and the ODU2 overhead.

NOTE—The ODU2 signal does not include the FEC. In addition, the OTU overhead fields are set to zero at the transmitter and ignored at the receiver, except for the FAS and MFAS, which are set at the transmitter and used at the receiver to synchronize with the ODU2 signal.

The MFAS signal is synchronized with the transmitted ODU2 frame. This synchronized signal is provided to help the higher order device to synchronize.

An ALM input signal can be activated by the external device to indicate the detection of a higher order alarm that requires consequent actions at the ODU2 level.



The following figure shows an example of an add/drop application involving two network side OTU2s and dropping a combination of SONET/SDH/CBR, Ethernet, and OTN client signals.

Figure 5: OTU2 Add/Drop Example

The West side OTU2 enters the device and is demultiplexed into ODU1 and ODU0 signals. One ODU1 signal and one ODU0 signal are passed through the TAF to the EAST side OTU2 output. Two ODU1 signals and one ODU0 signal from the West side OTU2 and two ODU1 signals and one ODU0 signal from the East side OTU2 are used for add/drop.



Client Signal to Network Side Port OTN Multiplexing and Mapping Options

The following figure shows the IPL4101M client signal to network side port OTN multiplexing and mapping structure.

Figure 6: Network Side Port OTN Multiplexing and Mapping Structures

Two ODU0 signals can be multiplexed into an ODU1 and then into an ODU2, compliant with ITU-T G.709-PT20, or up to eight ODU0 signals can be multiplexed into an ODU2, compliant with ITU-T G.709-PT21. When multiplexing ODU0s into an ODU2 you can use the following mapping options:

In PT20 you can map up to two ODU0 signals into an OPU1, and then map up to four ODU1 signals into an OPU2

In PT21 you can directly map a combination of ODU0 and ODU1 signals into an OPU2

Support for GbE is provided by utilizing either the GFP-F or GFP-T processes, compliant with ITU-T G.7041. GFP-F removes the preamble and Inter-Packet Gap (IPG) to reduce the rate and utilizes the GFP idle frames to adapt the resultant bit rate to the ODU1 or ODU2 bearer signal rates. A GFP-F engine can be used to map up to two GbE signals into the payload of an ODU1, or up to eight GbE signals into the payload of an ODU2. The GFP-T process performs transcoding to achieve a rate reduction of the entire Ethernet signal (including IPG, preamble, and ordered sets), and reduces the resultant signal rate so that it can be mapped (using a GMP process) into the payload of an ODU0 signal. The clock rate for the GFP-T mapped frame is a derivative of the input Ethernet clock. For more information about ITU-T G.7041 specification, refer to ITU-T G.7041/Y.1303, Generic framing procedure (GFP).

Support for 10GbE is provided by a GFP-F process to adapt the 10GbE signal, with or without preamble and ordered sets, into the payload of an ODU2. The 10GbE signal can also be transparently mapped on the payload of an ODU2e/ODU1e signal. For more information about GbE and 10GbE signals, see Apodis IPL4101M Product Description.



Fibre Channel one gigabit (1GFC) and 10 gigabit (10GFC) signals are supported. 1GFC (1.0625Gbps) is mapped using GMP into the payload of an ODU0 signal. 10GFC is rate adapted by utilizing a GFP-T transcoding function and is then mapped into the payload of an ODU1e or ODU2e signal. The 10GFC signal can also be transparently mapped to the payload of an ODU2f/ODU1f. For more information about 1GFC and 10GbE signals, see Apodis IPL4101M Product Description.

NOTE—OTU2f and OTU1f are non-standard rates. The IPL4101M supports all the standard (ITU-T G.709) rates plus several rates that are non-standard, but used in the industry.

SONET, SDH, and CBR signals can be mapped into an OTU signal, asynchronously or synchronously.

The basic data flows of the IPL4101M are as follows:

Client port to network port data flow:

1. Traffic enters the device through one of the client ports. The data is then passed through and processed, as follows:

Monitored for alarms and degradations Mapped into an appropriate OTN payload.

2. Data passes through the switch fabric (TAF) and is mapped into the required OTN container.

If required, the data is also multiplexed at this point in the flow.

3. Data is forwarded to the network ports for transmission to the OTN network.

Network port to client port data flow:

1. Traffic enters from one of the network ports and is monitored for alarms and degradations.

If required, the data is demapped or demultiplexed at this point in the flow.

2. Data passes through the TAF.

3. Data is converted into the desired output signal type.

4. Data is sent out from one of the client ports.

The TAF switching capability also enables connections between network to network or client to client ports.

NOTE—Client to client connections are allowed, provided the following requirements are met: At least one of the ports is OTN The non-OTN port is not GFP-F mapped

The IPL4101M supports multicasting through the TAF, which enables configurations, such as, ODU0 based protected ring topologies. For example, a 1+1 protection scheme can be achieved by multicasting the transmit signal to both East and West (network) sides, while presenting the receive side the highest quality signal out of those received from both network ports.

The IPL4101M provides multiple Performance Monitoring (PM) options, available for all network or client signals, including advanced Tandem Connection Monitoring (TCM), PM counters, alarms and indications.

The IPL4101M contains functions that support network level maintenance. It offers both loopbacks and pseudo-random binary test sequences for every interface on the device, as well as, several other maintenance functions for specific interfaces. For more information about the available maintenance

functions, see IPLightSERDES™ Maintenance in Section ‎2.1.1.3.

IPL4101M system details are described in the following sections:

Signal Descriptions in Section ‎1.1

Power and Ground Pins in Section ‎1.2

Pinout By Quadrant in Section ‎1.3



1.1 Signal Descriptions

NOTE—Pins not listed are reserved and must remain unconnected.

The IPL4101M pin type description includes several parameters:

Pull-up is an input pin with an internal pull-up resistor (connected to 2.5V)

Pull-down is an input pin with an internal pull-down resistor (connected to ground)

Schmitt is an input pin with built-in hysteresis

High-speed differential pins are LVPECL/LVCML with internal termination

The following figure shows the naming convention for the differential data pins of client and network side ports.

Figure 7: IPLightSERDES™ Naming Convention

NOTE—For network Quad, the possible values are 0-1.

For example, the pin designated as CRxP1[3] comprises the following identification information:

C=client side

Rx=receive differential pair

P=positive lead of differential pair

1=second quad (1)

[3]=fourth lane (3)

The IPL4101M signal pins are described in the following sections:

Client Signal Processor Interfaces in Section ‎1.1.1

Network Signal Processor Interfaces in Section ‎1.1.2

External Input Reference Clock Signal Interface in Section ‎1.1.3

Output Reference Clock Signal Interface in Section ‎1.1.4

External Overhead Interface Signal Pins in Section ‎1.1.5

Host Processor Interface Signal in Section ‎1.1.6

Control Signal Interface in Section ‎1.1.7

JTAG Interface Signal Pins in Section ‎1.1.8



1.1.1 Client Signal Processor Interfaces

The following table describes the pin locations and functions for the client signal ports.

Table 5: Client Side Signal Interface Pins

Name Signal Description IO Type Pin

Number Notes

CRxP0[0] Client receive positive signal for CSP 0.

I

High-speed differential

D18 Client port 0, lane 0.

Pin is not used when the quad is configured to 10G single-lane serial or XBI2-2 multi-lane interfaces.

CRxN0[0] Client receive negative signal for CSP 0.

C18

CTxP0[0] Client transmit positive signal for CSP 0.

O

B17

CTxN0[0] Client transmit negative signal for CSP 0.

A17


I


A19 Client port 1, lane 1.

Pin is not used when the quad is configured to a 10G single-lane serial interface. CRxN0[1] Client receive negative

signal for CSP 0. B19


O

A21


B21


I


B25 Client port 2, lane 2.


A25


O

B23


A23


I


C26 Client port 3, lane 3.



D26


O

A27


B27


I


D13 Client port 4, lane 0.



C13


O

B14


A14




Number Notes


I


A12 Client port 5, lane 1.


signal for CSP 1. B12


O

A10


B10


I


B6 Client port 6, lane 2.


A6


O

B8


A8


I


C5 Client port 7, lane 3.



D5


O

A4


B4


I


AG13 Client port 8, lane 0.



AH13


O

AJ14


AK14


I


AK12 Client port 9, lane 1.


signal for CSP 2. AJ12


O

AK10


AJ10


I


AJ6 Client port 10, lane 2.


AK6


O

AJ8


AK8




Number Notes


I


AH5 Client port 11, lane 3.



AG5


O

AK4


AJ4


I


AG18 Client port 12, lane 0.



AH18


O

AJ17


AK17


I


AK19 Client port 13, lane 1.


signal for CSP 3. AJ19


O

AK21


AJ21


I


AJ25 Client port 14, lane 2.


AK25


O

AJ23


AK23


I


AH26 Client port 15, lane 3.



AG26


O

AK27


AJ27

CMFAS0 Multiframe alignment signal indication for CSP 0

O CMOS

Standard drive

G17 This signal is active for OTU2/ODU2 modes only.

The MFAS signal changes state once (toggles), from high to low or vice-versa on the start of each OTU2 or ODU2 multiframe. The toggling point is within 120-180 bits before the MFAS byte appears on the serial bit stream of the OTU2/ODU2 output signal. An external device can use this signal to simplify the synchronization process.




Number Notes


O CMOS

Standard drive

F15 The MFAS signal changes state once (toggles), from high to low or vice-versa on the start of each OTU2 or ODU2 multiframe. The toggling point is within 120-180 bits before the MFAS byte appears on the serial bit stream of the OTU2/ODU2 output signal. An external device can use this signal to simplify the synchronization process.


O CMOS

Standard drive

AD14 The MFAS signal changes state once (toggles), from high to low or vice-versa on the start of each OTU2 or ODU2 multiframe. The toggling point is within 120-180 bits before the MFAS byte appears on the serial bit stream of the OTU2/ODU2 output signal. An external device can use this signal to simplify the synchronization process.


O CMOS

Standard drive

AD17 The MFAS signal changes state once (toggles), from high to low or vice-versa on the start of each OTU2 or ODU2 multiframe. The toggling point is within 120-180 bits before the MFAS byte appears on the serial bit stream of the OTU2/ODU2 output signal. An external device can use this signal to simplify the synchronization process.

CALMQ0 High order multiplexer alarm indication for CSP 0, active high.

I CMOS: Pullup/ Schmitt

F16 This signal is active for ODU2 modes only.

The ALM alarm input is used for ODU2 signals to indicate that an external device detected an alarm in its receive direction. When ALM is set, the device activates the relevant consequent actions.



F14 The ALM alarm input is used for ODU2 signals to indicate that an external device detected an alarm in its receive direction. When ALM is set, the device activates the relevant consequent actions.



AE15 The ALM alarm input is used for ODU2 signals to indicate that an external device detected an alarm in its receive direction. When ALM is set, the device activates the relevant consequent actions.

CALMQ3 Client high order multiplexer alarm indication for CSP 3, active high.


AE16 The ALM alarm input is used for ODU2 signals to indicate that an external device detected an alarm in its receive direction. When ALM is set, the device activates the relevant consequent actions.



1.1.2 Network Signal Processor Interfaces

The following table describes the pin locations and functions for the network side interface signals.

Table 6: Network Side Signal Interface Pins


Number Notes

NRxP0[0] Receive positive signal for NSP 0.

I


V27 OTN network port 0, lane 0.

Pin is not used when the quad is configured to single-lane serial or XBI2-2 multi-lane interfaces.

NRxN0[0] Receive negative signal for NSP 0.

V28

NTxP0[0] Transmit positive signal for NSP 0.

O

U29

NTxN0[0] Transmit negative signal for NSP 0.

U30


I


W30 OTN network port 0, lane 1.

Pin is not used when the quad is configured to a single-lane serial interface. NRxN0[1] Receive negative signal

for NSP 0. W29


O

AA30


AA29


I


AE29 OTN network port 0, lane 2.


AE30


O

AC29


AC30


I


AF28 OTN network port 0, lane 3.



AF27


O

AG30


AG29


I


N27 OTN network port 1, lane 0.



N28


O

P29


P30




Number Notes


I


M30 OTN network port 1, lane 1.



M29


O

K30


K29


I


F29 OTN network port 1, lane 2.


F30


O

H29


H30


I


E28 OTN network port 1, lane 3.



E27


O

D30


D29

NMFAS0 Network port multiframe alignment signal indication for NSP 0.

O CMOS

Standard drive

U24 The MFAS signal changes state once (toggles), from high to low or vice-versa on the start of each OTU2 or ODU2 multiframe. The toggling point is within 120-180 bits before the MFAS byte appears on the serial bit stream of the OTU2/ODU2 output signal. An external device can use this signal to simplify the synchronization process.

NMFAS1 Network port multiframe alignment signal indication for NSP 1.

O CMOS

Standard drive

R25 The MFAS signal changes state once (toggles), from high to low or vice-versa on the start of each OTU2 or ODU2 multiframe. The toggling point is within 120-180 bits before the MFAS byte appears on the serial bit stream of the OTU2/ODU2 output signal. An external device can use this signal to simplify the synchronization process.

NALMQ0 High order multiplexer alarm indication for NSP 0, active high.

I CMOS: Pull-up/ Schmitt

T25 The ALM alarm input is used for ODU2 signals to indicate that an external device detected an alarm in its receive direction. When ALM is set, the device activates the relevant consequent actions.

NALMQ1 High order multiplexer alarm indication for NSP 1, active high.

I CMOS: Pull-up/ Schmitt

P24 The ALM alarm input is used for ODU2 signals to indicate that an external device detected an alarm in its receive direction. When ALM is set, the device activates the relevant consequent actions.



1.1.3 Input Clock Signal Interface

The following table describes the pin locations and functions for the external input reference clock interface signals.

Table 7: External Input Reference Clock Signal Interface Pins

Name Description IO Type Pin

Number Notes

REFCLKP Reference clock positive signal.

I High-speed differential

F18 Oscillator frequency and accuracy: 155.52 MHz +/-20 ppm

REFCLKN Reference clock negative signal.

G18

1.1.4 Output Reference Clock Signal Interface

The following table describes the pin locations and functions for the output reference clock interface signals.

Table 8: Output Reference Clock Signal Interface Pins


Number Notes

REC1P High-rate output reference clock positive signal.

O CMOS

High drive

AC22 After reset, these positive and negative signals are enabled, generating a clock signal by drawing on the external reference clock as its source. The high-rate output reference clock frequency is equal to the external reference clock frequency. Both positive and negative signal reference clocks represent the generated clock signal, but in opposite phases. To create a single differential signal, both positive and negative pins must be combined. You can disable and enable the high rate output reference clock, when disabled the clock output goes into Tri-state state.

You can select the source of any of the output reference clocks to be:

Any recovered clock (of any signal carried by OTN containers)

Any transmit clock

External input reference clock

For more information about reference clocks and clock signals, see Reference Clock in Section ‎3.2 and Clock Parameters in Section ‎4.7.

REC1N High-rate output reference clock negative signal.

AB22




Number Notes


O CMOS

High drive

AD25 After reset, these positive and negative signals are disabled. Both positive and negative signal reference clocks represent the generated clock signal, but in opposite phases. To create a single differential signal, both positive and negative pins must be combined. You can enable and disable the high rate output reference clock, when disabled the clock output goes into Tri-state state. You can select the source of any of the output reference clocks to be:


Any transmit clock




AD24


O CMOS

High drive

AE23 After reset, these positive and negative signals are disabled. Both positive and negative signal reference clocks represent the generated clock signal, but in opposite phases. To create a single differential signal, both positive and negative pins must be combined. You can enable and disable the high rate output reference clock, when disabled the clock output goes into Tri-state state. You can select the source of any of the output reference clocks to be:


Any transmit clock




AD23




Number Notes


O CMOS

High drive

AE22 After reset, these positive and negative signals are disabled. Both positive and negative signal reference clocks represent the generated clock signal, but in opposite phases. To create a single differential signal, both positive and negative pins must be combined. You can enable and disable the high rate output reference clock, when disabled the clock output goes into Tri-state state. You can select the source of any of the output reference clocks to be:


Any transmit clock




AD22

LRRC1 Low-rate output reference clock.

O CMOS

High drive

AE20 After reset, this low-rate reference output clock pin is enabled drawing on the external reference as its source. The low-rate reference clock frequency is equal to the external reference clock frequency divided by two. The low-rate reference clock is a single ended signal. You can disable and enable the low rate output reference clock, when disabled the clock output goes into Tri-state state. You can select the source of any of the low-rate reference clocks to be:

Any recovered clock from any signal carried by OTN bearers

Any transmit clock of any IPL4101M interface






Number Notes


O CMOS

High drive

AD20 After reset, this low-rate reference output clock pin is disabled. The low-rate reference clock is a single ended signal. You can disable and enable the low rate output reference clock, when disabled the clock output goes into Tri-state state. You can select the source of any of the low-rate reference clocks to be:





LRRC3 Low-rate output clock. O CMOS

High drive

AC21 After reset, this low-rate reference output clock pin is disabled. The low-rate reference clock is a single ended signal. You can disable and enable the low rate output reference clock, when disabled the clock output goes into Tri-state state. You can select the source of any of the low-rate reference clocks to be:






O CMOS

High drive

AB21 After reset, this low-rate reference output clock pin is disabled. The low-rate reference clock is a single ended signal. You can disable and enable the low rate output reference clock, when disabled the clock output goes into Tri-state state. You can select the source of any of the low-rate reference clocks to be:







1.1.5 External Overhead Signal Interface

The External Overhead Interface (EOI) provides access to received overhead (OH) bytes, where the OverHead Channel IDentification (OHCID) timeslot number establishes which specific OH is being

accessed. For information about EOI signal operation, see EOI Description in Section ‎2.3.1.

The following table describes the pin locations and functions for the EOI.

Table 9: EOI Signal Pins

Name Description IO Type Pin Number Notes

OHCLK Overhead Channel reference clock.

I CMOS: Pull-up

R24 All EOI signals are referenced to this clock.

Minimum frequency: 64MHz

Maximum frequency: 100MHz

OHCID[9:0] Overhead channel identification number.

O CMOS

High drive

L24 N22 M24 P23 N25 N24 R26 P22 R22 R23

The OHCID channel number controlling the specific OH channel being accessed. For more information about the OHCID, see EOI Description in Section ‎2.3.1.

RxOHD[15:0] Received overhead channel data bus.

O CMOS

High drive

F24 G24 F25 H24 H25 G23 J23 J24 J25 K23 K25 L23 L25 L22 M22 M23

The EOI provides read access to all the received OH bytes through the RxOHD data bus.

RxOHVLD Received overhead channel valid data

O CMOS

High drive

K22 When this signal is high the OH bytes are available in RxOHD for the channel indicated by OHCID.

TxOHD[15:0] Transmit overhead channel data bus.

I CMOS: Pull-up

F21 G22 G21 F20 J20 J19 H21 F19 H20 G19 H19 E16 J18 G16 J17 H17

The EOI provides write access to all the transmitted OH bytes through the TxOHD data bus.

TxOHRQ Transmit overhead channel data request.

O CMOS

High drive

J22 When this signal is high the OH bytes for the channel indicated by OHCID must be made available in TxOHD. The frame number can be derived from the TxOHMFAS signal.

TxOHMFAS Transmit overhead MFAS.

O CMOS

High drive

H22 A TxOHMFAS signal is provided for each overhead channel (according to the respective OHCID channel number). When TxOHMFAS is high it indicates the start of a new multiframe for the current channel. Accordingly, the TxOHMFAS signal associated with the particular channel remains high for the complete transaction for frame 0 and is low for the next 255 consecutive channel frames.

For more information about the EOI, see External Overhead Interface in Section ‎2.3.



1.1.6 Host Processor Interface Signal

The following table describes the pin locations and functions for the HPI.

Table 10: HPI Signal Pins


Number Notes

CCLK Host Processor timing input reference clock.

I CMOS AC15 All HPI signals are referenced to this clock.

Minimum frequency: 33MHz

Maximum frequency: 72MHz

FREE CPU operation mode selection.

I CMOS: Pull-up

and Schmitt

AC10 Select the CPU mode of operation between:

Freescale: FREE=1

Intel: FREE=0

END Endian selection. I CMOS: Pull-up

and Schmitt

AD15 Valid for Intel mode only (FREE=0).

Little endian: END=1

Big endian: END=0

For more information about endian modes, see HPI Intel Mode in Section ‎2.4.3.

LCS_ADS Chip Select or Address Status.

I CMOS: Pull-up

F13 Chip Select or Address Status mode depends on the selected CPU operation mode:

Freescale mode (FREE=1): Chip Select

Intel mode (FREE=0): Address Status

WE_R Write Enable or Read.

I CMOS J10 Write or Read Mode depends on the selected CPU operation mode:

Freescale mode (FREE=1):

WE_R=1 Read

WE_R=0 Write

Intel mode (FREE=0):

WE_R=1 Write

WE_R=0 Read

LGTA Acknowledgment or Ready Receive assertion.

O CMOS

High drive

H14 Transaction complete indication depends on the selected CPU operation mode:

Freescale mode (FREE=1): LGTA assertion

Intel mode (FREE=0): Ready Receive assertion

D[31:0] Data bus. I/O

CMOS

High drive

G14 H15 J15 J14 G12 G13 H11 J13 J12 F10 H10 F9 G9 H9 F8 G8 G7 F6 G6 H7 J8 J7 H6 K6 K8 L6 M7 K7 K9 L9 N7 M6




Number Notes

AD[23:2] Address bus. I CMOS AB9 AA9 AC7 AC6 AB8 AB6 AA6 AB7 W9 V9 AA8 Y6 Y8 Y7 V7 W7 W8 V6 U9 T9 T8 U8

The lower two address bits (A0 and A1 in the microprocessor) are not connected and all addresses must be aligned to 32 bits, as the IPL4101M operates as a 32-bit peripheral.

OE Output enable. I CMOS AC14 Active low. Controls the data signal drivers. When active low the data signals are active.

IRQ_N Master interrupt request.

O CMOS: Tri-state /normal

High drive

J9 Active low. This pin has the following operational modes:

Normal mode Normal mode drives the signal as a regular output pin. High level (1) indicates that there is no interrupt. Low level (0) indicates that there is an active non-masked pending interrupt.

Tri-state mode Tri-state mode is a WIRED-OR connection that allows multiple sources to drive a single host processor pin. When there are no interrupts active, the output is High-Z. When a non-masked pending interrupt is active, the output drives a low level (0) signal. IRQ_N=0: outputs a 0 IRQ_N=1: output switches to high-Z

For more information about the host processor interface, see Host Processor Interface in Section ‎2.4.



1.1.7 Control Signal Interface

The following table describes the control signal interface pins.

Table 11: Control Signal Interface Pins


Number Notes

PMSYN Performance monitoring synchronization input.

I CMOS: Pull-up and

Schmitt

H12 When a performance monitoring counter is configured in Latching mode, changing (toggling) the state of this pin from high to low or low to high, it latches the contents of the counter into its respective shadow register. For more information about configuring options for the PM counters to use this signal, refer to the Apodis IPL4101M User Manual.

RST_N Device reset. I CMOS: Pull-up and

Schmitt

G11 Active low. Activating the reset pin resets the whole device and sets all registers to their default values.

1.1.8 JTAG Interface

The following table describes the pin locations and functions for the JTAG interface signals.

Table 12: JTAG Interface Pins


Number Notes

TDI Test data input I CMOS: Pull-up V25

TDO Test data output O

CMOS: Tri-state

Standard drive

V24

TCK Test clock I CMOS: Pull-up AC25

TMS Test selection mode I CMOS: Pull-up AE25

TRST Test reset I CMOS: Pull-up and Schmidt

F11

For more information about the JTAG interface, see JTAG Interface in Section ‎2.5 and JTAG

Characteristics in Section ‎4.6.



1.2 Power and Ground Pins

The following table describes the power and ground pin locations.

Table 13: Power and Ground Pins

Name Description Type Pin Number Notes

VDD10 1.0V digital power supply.

Power K20 K18 K16 K12 K10 L21 L19 L17 L15 L13 L11 M20 M18 M16 M14 M12 N21 N19 N17 N15 N13 N11 P20 P18 P16 P14 P12 P10 R21 R19 R17 R15 R13 R11 T20 T18 T16 T14 T12 T10 U21 U19 U17 U15 U13 U11 V20 V18 V16 V14 V12 V10 W21 W19 W17 W15 W13 Y20 Y18 Y16 Y14 Y12 Y10 AA21 AA19 AA17 AA15 AA13 AA11

VDD10B 1.0V analog power supply, bottom side.

Power AF24 AF7 AG25 AG24 AG23 AG21 AG20 AG19 AG12 AG11 AG10 AG8 AG7 AG6

VDD10L 1.0V analog power supply, left side.

Power F4 G5 G4 H4 K4 L4 M4 W4 Y4 AA4 AC4 AD5 AD4 AE4

VDD10O General 1.0V analog power supply, general purpose.

Power A16 B15 D15 R29 R27 R4 R2 T30 T28 T26 T5 T3 T1 AG16 AH15 AJ16 AK15

VDD10PB 1.0V analog power supply, phase-locked loop bottom side.

Power AG22 AG9 AH22 AH9

VDD10PL 1.0V analog power supply, phase-locked loop left side.

Power J4 J3 AB4 AB3

VDD10PR 1.0V analog power supply, phase-locked loop right side.

Power J28 J27 AB28 AB27

VDD10PT 1.0V analog power supply, phase-locked loop top side.

Power C22 C9 D22 D9

VDD10R 1.0V analog power supply, right side.

Power F27 G27 G26 H27 K27 L27 M27 W27 Y27 AA27 AC27 AD27 AD26 AE27

VDD10T 1.0V analog power supply, top side.

Power D25 D24 D23 D21 D20 D19 D12 D11 D10 D8 D7 D6 E24 E7

VDD25 2.5V digital power supply.

Power F22 F12 G25 G15 H18 H8 J21 J11 K24 K14 L7 M10 N23 P6 R9 T22 U25 U6 V23 V8 Y24 AA7 AB20 AB17 AB10 AC23 AC13 AD16 AD6 AE19 AE17 AE9

VDD25B 2.5V analog power supply, bottom side.

Power AH25 AH24 AH23 AH21 AH20 AH19 AH12 AH11 AH10 AH8 AH7 AH6

VDD25L 2.5V analog power supply, left side.

Power F3 G3 H3 K3 L3 M3 W3 Y3 AA3 AC3 AD3 AE3



Name Description Type Pin Number Notes

VDD25R 2.5V analog power supply, right side.

Power F28 G28 H28 K28 L28 M28 W28 Y28 AA28 AC28 AD28 AE28

VDD25T 2.5V analog power supply, top side.

Power C25 C24 C23 C21 C20 C19 C12 C11 C10 C8 C7 C6

VSS Digital ground pins.

Ground A29 A2 B30 B29 B2 B1 F17 F7 G20 G10 H23 H13 J16 J6 K21 K17 K15 K11 L20 L18 L16 L14 L12 M25 M19 M17 M15 M13 M11 N20 N18 N16 N14 N12 N10 N8 P25 P21 P19 P17 P15 P13 P11 R20 R18 R16 R14 R12 R10 T23 T21 T19 T17 T15 T13 T11 T7 U22 U20 U18 U16 U14 U12 V22 V19 V17 V15 V13 V11 W23 W20 W18 W16 W14 W12 W11 W10 W6 Y21 Y19 Y17 Y15 Y13 Y11 Y9 AA22 AA20 AA16 AA14 AA10 AB25 AB15 AC24 AC20 AC18 AC16 AC8 AD21 AD19 AD11 AE24 AE14 AE12 AF15 AJ30 AJ29 AJ2 AJ1 AK29 AK2

VSSA Analog ground pins.

Ground A28 A26 A24 A22 A20 A18 A15 A13 A11 A9 A7 A5 A3 B28 B26 B24 B22 B20 B18 B16 B13 B11 B9 B7 B5 B3 C30 C29 C28 C27 C17 C15 C14 C4 C3 C2 C1 D28 D27 D17 D16 D14 D4 D3 E30 E29 E26 E25 E23 E22 E21 E20 E19 E18 E13 E12 E11 E10 E9 E8 E6 E5 E2 E1 F26 F5 G30 G29 G2 G1 H26 H5 J30 J29 J26 J5 J2 J1 K26 K19 K13 K5 L30 L29 L26 L10 L5 L2 L1 M26 M21 M5 N30 N29 N26 N5 N2 N1 P28 P27 P4 P3 R30 R28 R3 R1 T29 T27 T4 T2 U28 U27 U10 U4 U3 V30 V29 V26 V21 V5 V2 V1 W26 W5 Y30 Y29 Y26 Y5 Y2 Y1 AA26 AA18 AA12 AA5 AB30 AB29 AB26 AB5 AB2 AB1 AC26 AC5 AD30 AD29 AD2 AD1 AE26 AE5 AF30 AF29 AF26 AF25 AF23 AF22 AF21 AF20 AF19 AF18 AF16 AF13 AF12 AF11 AF10 AF9 AF8 AF6 AF5 AF2 AF1 AG28 AG27 AG17 AG15 AG14 AG4 AG3 AH30 AH29 AH28 AH27 AH17 AH16 AH14 AH4 AH3 AH2 AH1 AJ28 AJ26 AJ24 AJ22 AJ20 AJ18 AJ15 AJ13 AJ11 AJ9 AJ7 AJ5 AJ3 AK28 AK26 AK24 AK22 AK20 AK18 AK16 AK13 AK11 AK9 AK7 AK5 AK3



1.3 Pinout

The following figure shows the IPL4101M pinout locations in the upper-left quadrant.

Figure 8: IPL4101M Pinout Upper Left Quadrant (Bottom View)

Key

Signal pins:

Power pins:

Ground pins:

Reserved: Pins not indicated are reserved and must remain unconnected.



The following figure shows the IPL4101M pinout locations in the upper-right quadrant.

Figure 9: IPL4101M Pinout Upper Right Quadrant (Bottom View)

Key

Signal pins:

Power pins:

Ground pins:




The following figure shows the IPL4101M pinout locations in the lower-right quadrant.

Figure 10: IPL4101M Pinout Lower Right Quadrant (Bottom View)

Key

Signal pins:

Power pins:

Ground pins:




The following figure shows the IPL4101M pinout locations in the lower-left quadrant.

Figure 11: IPL4101M Pinout Lower Left Quadrant (Bottom View)

Key

Signal pins:

Power pins:

Ground pins:



30 Functional Description IP Light Proprietary and Confidential

2 Functional Description Functional characteristics and features of the IPL4101M are described in the following sections:

Client and Network Interfaces in Section ‎2.1

Clock Outputs in Section ‎2.2

External Overhead Interface in Section ‎2.3

Host Processor Interface in Section ‎2.4

JTAG Interface in Section ‎2.5

2.1 Client and Network Interfaces

Each Client or Network interface includes an IPLightSERDES™.

The interfaces may be configured as serial, XAUI, or XBI2 interfaces.

Client and Network interfaces are described in the following sections:

IPLightSERDES™ in Section ‎2.1.1

Serial Interface in Section ‎2.1.2

XBI2 Interface in Section ‎2.1.3

XAUI Interface in Section ‎2.1.4

FEC in Section ‎2.1.5



2.1.1 IPLightSERDES™

The IPL4101M includes 24 multi-rate SERDES organized into six IPLightSERDES™ quads, meaning an IPLightSERDES™ quad for each CSP and NSP block. The following figure shows the block diagram of an individual IPLightSERDES™ within an IPLightSERDES™ quad.

Figure 12: IPLightSERDES™ Block Diagram

The IPLightSERDES™ operates between 1GFC (1.0625 Gbps) and OTU2f (11.318 Gbps) signal rates. The IPLightSERDES™ transmit clock generation PLL has jitter attenuation capability compliant with Telecom (SONET/SDH and OTN) and Datacom (GbE and 10GbE) standards. It complies with the standards for jitter generation, jitter acceptance, and jitter transfer as specified in the relevant IEEE, T11, Telcordia and ITU-T specifications.

The IPLightSERDES™ includes an equalizer on the Rx side and on-chip termination. The transmitter provides a programmable differential output swing, ranging from 200mV to 1200mV and programmable pre-emphasis. The electrical interfaces of the IPLightSERDES™ are AC-coupled differential LVCML/LVPECL signals.

IPLightSERDES™ IPL4101M functions are described in the following sections:

IPLightSERDES™ Description in Section ‎2.1.1.1

IPLightSERDES™ Rates in Section ‎2.1.1.2

IPL4101M Maintenance in Section ‎2.1.1.3



2.1.1.1 IPLightSERDES™ Description

The IPLightSERDES™ has a configurable filter pole, which can be set to either 100Hz or 300Hz. This option supports GbE synchronous Ethernet applications, which require tighter jitter attenuation.

The Tx and Rx lanes for the IPLightSERDES™ are differential pairs of pins. The differential pair has two pins designated for reference only as one positive (P) and one negative (N) pin. The logical value of 1 or 0, for the transmitted or received signal, is determined by the voltage difference between the P and the N pins. The IPLightSERDES™ provides the capability to swap the designation of the P and N pins of any differential pair, therefore, allowing incorrectly connected lanes to work properly.

The Transmit Phased Locked Loop (Tx PLL) of the IPLightSERDES™ provides an option for automatic primary and secondary reference clocks to the IPLightSERDES™. For more information about the IPLightSERDES™ clocking schemes, refer to the Apodis IPL4101M User Manual.

The IPL4101M can be configured to power down the IPLightSERDES™ blocks.

The IPLightSERDES™ receiver can detect and trigger the following alarms:

Analog LOS (energy based)

Digital LOS (zero count based)

SONET/SDH standard LOS

Loss of Lock (LOL)

The IPLightSERDES™ allows a configurable setting of the energy level threshold to declare analog LOS and the time interval in which no incoming signal is detected before a digital LOS alarm is triggered. For SONET/SDH interfaces, LOS is detected according to the ITU-T and Telcordia standard definitions.

NOTE—Since SONET/SDH interface LOS indication replaces the digital LOS, it is recommended to inhibit the digital LOS function for these client signals.

The Rx LOL is detected if the IPLightSERDES™ is unable to lock on the incoming signal.

The Tx PLL also provides a Loss Of Lock (LOL) alarm. When the Tx PLL is locked (the reference signal rate experiences a deviation of less than ±1464 ppm from its nominal frequency), the LOL alarm signal is pulled down to a logical 0. When the Tx PLL frequency drifts away for more than ±1464 ppm from the required nominal frequency, it triggers an LOL alarm.

The following figure shows how four SERDES blocks are grouped together to form a Quad IPLightSERDES™ block.

Figure 13: Quad IPLightSERDES™

A quad IPLightSERDES™ block is connected to either a CSP on the Client side or an NSP on the Network side.



Low-rate signals can be connected to any lane in a Quad. The following table describes the lane assignments available for the different interface types.

Table 14: Lane Assignment Configurations

Interface Type Lane Assignments

Serial, high rate Lane 2

XAUI Lane 0, 1, 2, and 3

XBI2-2 Lane 1 and Lane 2

XBI2-4 Lane 0, 1, 2, and 3

Serial, low-rate Lane 0, 1, 2, or 3

2.1.1.2 IPLightSERDES™ Rates

The following table describes the IPLightSERDES™ lane rates for the various types of signals that it supports.

Table 15: Lane Rates

Signal Type

Nominal Lane Rate

(GHz)

GbE 1.250

GFC 1.063

OTU0 1.328

OC-48/STM-16/CBR2G5 2.488

OTN OTU1 2.666

10GbE 10.313

OC-192/STM-64/CBR10G 9.953

XAUI 3.125

10GFC 10.519

fcXAUI 3.188

OTU2 10.709

OTU2 XBI2-2 5.355

OTU2 XBI2-4 2.677

OTU1e 11.049

OTU1e XBI2-2 5.525

OTU1e XBI2-4 2.762

OTU2e 11.096

OTU2e XBI2-2 5.548

OTU2e XBI2-4 2.774

OTU1f 11.270

OTU1f XBI2-2 5.635

OTU1f XBI2-4 2.818

OTU2f 11.318

OTU2f XBI2-2 5.659

OTU2f XBI2-4 2.829

ODU2 10.037

ODU2 XBI2-2 5.019



Signal Type

Nominal Lane Rate

(GHz)

ODU2 XBI2-4 2.509

ODU1e 10.356

ODU1e XBI2-2 5.178

ODU1e XBI2-4 2.589

ODU2e 10.400

ODU2e XBI2-2 5.200

ODU2e XBI2-4 2.600

ODU1f 10.563

ODU1f XBI2-2 5.281

ODU1f XBI2-4 2.641

ODU2f 10.608

ODU2f XBI2-2 5.304

ODU2f XBI2-4 2.652

2.1.1.3 IPL4101M Maintenance

Details of IPL4101M Maintenance are described in the following sections:

Loopbacks in Section ‎2.1.1.3.1

Received Signal Eye-Opening Measurement in Section ‎2.1.1.3.2

Pseudo-random Binary Sequences in Section ‎2.1.1.3.3

Square Wave Generation in Section ‎2.1.1.3.4

Pattern Generation and Detection in Section ‎2.1.1.3.5

2.1.1.3.1 Loopbacks

The following figure shows the end-to-end loopback capabilities for a single IPLightSERDES™ lane.

Figure 14: End-to-End Loopback Path

The terminal loopback connects the signal from the transmit path back to the receive path. The line loopback connects the signal from the receive path back to the transmit path. The loopback capability is available on each Client port and each Network port. The line loopback can be configured on the parallel or serial side of the IPLightSERDES™ and the terminal loopback can be configured on the serial side of the IPLightSERDES™. When the loopback is activated, the Client or Network signal passes through the loopback path and also continues into or out of the device accordingly.

For OTN signals, the loopback can also be established through the TAF, which can be configured to route the receive signal back to its transmit path. In addition to the loopback path, the TAF can also broadcast the Rx signal to other destinations. For more information about specific programming instructions for the IPLightSERDES™, see Apodis IPL4101M User Manual.



2.1.1.3.2 Received Signal Eye-Opening Measurement

The IPL4101M provides the ability to change the received signal sampling point. This function, together with the PRBS capabilities, can be used to create a bathtub curve to measure the received signal eye-opening. For more information about the received signal eye-opening measurement function, see Apodis IPL4101M User Manual.

2.1.1.3.3 Pseudo-random Binary Sequences

The IPL4101M provides Pseudo-Random Binary Sequence (PRBS) test signal generation on the transmit path of all of the Client and Network ports. Corresponding integrated PRBS monitoring is provided on the receive path of each port. The following test pseudo-random binary sequences are available:

PRBS7

PRBS7 is a proprietary sequence based on the polynomial x7+x6+1.

PRBS9

PRBS15

PRBS23

PRBS31

These test signals are defined in ITU-T O.150. For more information, refer to ITU-T Series O: Specifications of Measuring Equipment in the following recommendations:

PRBS9: O.150 Section 5.1 and O.153



PRBS31: O.150 Section 5.8.

2.1.1.3.4 Square Wave Generation

The IPL4101M can generate a square wave signal on its interfaces, which can be used to conduct measurements on optical signals. The square wave is generated by a user-defined number of ones (1) followed by the same number of zeros (0). For more information about specific programming instructions for square wave generation, refer to the Apodis IPL4101M User Manual. For more information about square wave signal generation, refer to IEEE 802 Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, Chapter 49.

2.1.1.3.5 Pattern Generation and Detection

The IPL4101M can generate, on any of its ports, a user-defined 40 bit pattern. This pattern is transmitted continuously and can be monitored on the Rx side of the IPL4101M by an integrated detector. For more information about specific programming instructions for pattern generation and detection, refer to the Apodis IPL4101M User Manual.

2.1.2 Serial Interface

Network and client side ports support serial (single lane) interfaces that can operate with signals from GFC (1 Gbps) up to OTU2f (11.32 Gbps) signal rates. The network side ports support XFI and SFP+ interfaces and the client side ports support XFI, SFP+, and SFP interfaces. A serial XFI interface operating at 10Gbps can drive signals up to 12 inches through standard FR4 material. The interfaces conform to the XFI and SFP specifications.

NOTE—XFI specification: INF-8077i, 10 Gigabit Small Form Factor Pluggable Module, Revision 4.5 August 31, 2005.

NOTE—SFP Revision 1.0, Small Form-factor Pluggable (SFP) Transceiver MultiSource Agreement (MSA).



2.1.3 XBI2

The IPL4101M offers a special OTU2/ODU2 interface on both its client and network ports called XBI2. While being similar to MLD, it is adapted for 10Gbps signal rates. XBI2 carries OTU2/ODU2 signals over a two-lane (XBI2-2) or four -lane (XBI2-4) parallel interface. XBI2-2 has two lanes, each running at half the respective OTU2/ODU2 rate, and XBI2-4 has four lanes, each running at quarter the OTU2/ODU2 rate. XBI2 interfaces can drive signals directly across backplanes or be used to interface with FPGAs. When OTU2 signals are carried over XBI2 interfaces, the OTU2 GFEC can optionally be activated to provide further enhanced signal integrity.

The following figure shows how OTU2x/ODU2x frames are being inversely multiplexed over XBI2-4 lanes, the 16-byte boundaries and their respective alignment with the OTU2x/ODU2x frames.

Figure 15: XBI2-4 Lane Assignments

Each 16 byte section is sequentially distributed to each of the lanes. On the frame boundary, the lane assignments are rotated.

The following table describes the lane assignment as determined by the two LSB bits of the MFAS of the OTU2/ODU2 for XBI2-4.

Table 16: OTU2/ODU2 Information Lane Assignment for XBI2-4

MFAS bits 7,8 Lane 0 Lane 1 Lane 2 Lane 3

00 1:16 17:32 33:48 49:64

01 49:64 1:16 17:32 33:48

10 33:48 49:64 1:16 17:32

11 17:32 33:48 49:64 1:16



The following figure shows OTU2x/ODU2x frames being inversely multiplexed over XBI2-2 lanes on 16-byte boundaries and aligned with the OTU2x/ODU2x frames.

Figure 16: XBI2-2 Lane Assignments

The following table describes the lane assignment determined by the LSB bit of the MFAS of the OTU2/ODU2 for XBI2-2.

Table 17: Lane Assignment for XBI2-2

MFAS bit 8 Lane 1 Lane 2

0 1:16 17:32

1 17:32 1:16

An XBI2 interface can compensate for up to an 80 bit skew. The skew is the difference in information arrival time between the fastest and slowest lanes of the interface. In addition, the XBI2 interface recognizes the correct logical sequencing of lanes irrespective of their physical location.

XBI2 interfaces provide improved drive capability. XBI2-2 can drive signals across 24 inches of standard FR4 material. XBI2-4 is capable of driving signals across 30 inches of standard FR4 material including two connector pairs, and can be used as a backplane interface.

2.1.4 XAUI Interface

10GbE signals can be transmitted/received via serial or XAUI interfaces. When using an XAUI interface, the incoming 10GbE signal is converted into XGMII that is then processed by a GFP-F engine or converted into 64B/66B blocks for transparent transport mode operation.

10GFC signals can be transmitted/received via serial or fcXAUI interfaces. When using fcXAUI, the 10GFC signal is converted into XGMII that is then handled by a GFP-T transcoding process or converted into 64B/66B blocks for transparent transport mode operation.

NOTE—fcXAUI is XAUI running at 10GFC clock rates (two percent higher than standard XAUI).

The XAUI interface can compensate for data skews of up to 80 bits. The skew is the difference in arrival times between the fastest and slowest lanes of the interface.

The following table describes the XAUI and fcXAUI clock rates.

Table 18: XAUI Clock Rates

Type Nominal

Rate (GHz)

XAUI 3.125

fcXAUI 3.1875



2.1.5 FEC

The IPL4101M provides integrated Forward Error Correction (FEC), the standard FEC specified by ITU-T G.709, or the Enhanced Forward Error Correction (EFEC) specified in clause I.4 of ITU-T G.975.1.

The following figure shows the performance of standard FEC (GFEC) versus enhanced (1.4) EFEC.

Figure 17: EFEC

NOTE—The above bit error rate figure is from the ITU-T G.975.1 specification, Figure I. 13/G.975.1

EFEC provides enhanced protection against bit error rates. Indications and counters are provided for corrected and uncorrected characters of the received signal.

The IPL4101M also provides the option to use an external FEC. This can be accomplished by using an ODU2 signal interface, or by using an OTU2 signal and disabling the internal FEC. Timing and alarm signals are provided to facilitate FEC insertion by an external device.



2.2 Clock Outputs

The following figure shows the four high-rate and four low-rate output clocks provided by the IPL4101M.

Figure 18: Clock Outputs

The internal clocks are derived from one of the following sources:

Signal clocks from the external interfaces (network or client ports)

Payload signals carried by the OTN bearer signals

External reference clock

Clock outputs can be configured to be high impedance.

The following table describes the high-rate clock outputs, depending on the selected reference signal type.

Table 19: Clock Output Rates

Reference Signal

Nominal Output Rate

(MHz)

GbE 78.13

GFC 66.41

OTU0 83.00

OC-48/STM-16/CBR2G5 155.50

OTN OTU1 166.25

10GbE 161.13

OC-192/STM-64/CBR10G 155.52

XAUI 195.31

10GFC 164.36

fcXAUI 199.22

OTU2 (Serial, XBI2-2, or XBI2-4) 167.34



Reference Signal

Nominal Output Rate

(MHz)

OTU1e (Serial, XBI2-2, or XBI2-4) 172.66

OTU2e (Serial, XBI2-2, or XBI2-4) 173.28

OTU1f (Serial, XBI2-2, or XBI2-4) 176.09

OTU2f (Serial, XBI2-2, or XBI2-4) 176.88

ODU2 (Serial, XBI2-2, or XBI2-4) 156.88

ODU1e (Serial, XBI2-2, or XBI2-4) 161.88

ODU2e (Serial, XBI2-2, or XBI2-4) 162.50

ODU1f (Serial, XBI2-2, or XBI2-4) 165.00

ODU2f (Serial, XBI2-2, or XBI2-4) 165.78

External reference clock 155.52

For low-rate clock outputs the selected reference signal rate is divided by a 16 bit configurable counter and is then further divided by two (2) to generate clock signals of frequencies of up to 100MHz. If the configurable counter is not used, then the low-rate is half the nominal high-rate output frequency of the selected reference signal rate shown in Table 19: Clock Output Rates.

For more information about clock signals and parameters, see Clock Signals Interface in Section ‎1.1.4

and Clock Parameters in Section ‎4.7.

2.3 External Overhead Interface

The External Overhead Interface (EOI) provides access to received overhead (OH) bytes through the RxOHD data bus and provides access to the transmitted OH bytes through the TxOHD data bus. Per byte selection of TxOHD data between internal and external data sources is set by configuring a bit in its corresponding register. Access is provided to all active OTN (OTU1/2, ODU0/1/2, and OPU0/1/2) OH bytes, and also to SONET/SDH section DCC, order wire (E1), and user defined F1 channel.

Each individual OTN and SONET/SDH signal has been assigned an associated OH block. For OTN signals, this block consists of 64 bytes of OH information and for SONET/SDH signals it consists of the F1, E1, and DCC bytes. The following figure shows how the EOI operates continuously and sequentially cycles through the OH blocks in the IPL4101M.

Figure 19: External Overhead Interface



Each overhead block is represented by a timeslot with an associated channel number. During each timeslot the complete OH block of any signal can be both read out and modified (written to) through the EOI.

The following figure shows an OTN signal data insertion/flow between the EOI and the Tx side overheads.

Figure 20: EOI OTN Insertion

For OH data insertion, the Tx OH block bytes can be overwritten through the TxOHD bus. Data must be written when the appropriate channel number (OHCID) is present and TxOHRQ is active. The data of Tx OH blocks configured for internal handling overrides the OH bytes received through the external interface. The TX OH request signal (TxOHRQ) indicates that the IPL4101M requests OH data for transmission. There is also an MFAS signal (TxOHMFAS) that indicates the multiframe alignment for the selected Tx signal. A TxOHMFAS signal is provided for each overhead channel (according to the respective OHCID channel number). When TxOHMFAS is high it indicates the start of a new multiframe for the current channel. Accordingly, the TxOHMFAS signal associated with the particular channel remains high for the complete transaction for frame 0 and is low for the next 255 consecutive channel frames.



The following figure shows an OTN signal data extraction/flow between the EOI and the Rx side overheads.

Figure 21: EOI OTN Extraction

For overhead extraction, each OH block is selected by its corresponding OHCID address, and then its contents are presented on the RxOHD bus. A data valid signal (RxOHVLD) indicates when the OH block data is ready. For the receive side the entire OTU and ODU overhead is presented, as a result, the Rx signal frame alignment can be monitored using the overhead MFAS byte.

The EOI operation is driven by an external clock. The received EOI data is valid if the corresponding interface is synchronized to the OTN or SONET/SDH signal.

The IPL4101M EOI functions are described in the following sections:

EOI Description in Section ‎2.3.1

EOI Timing Diagrams in Section ‎2.3.2

2.3.1 EOI Description

The OverHead Channel IDentification (OHCID) timeslot number establishes which specific OH is being accessed. The following figure shows the significance of the bits within the OHCID address.

Figure 22: OHCID Bits



The following table describes the OHCID bits.

Table 20: OHCID Bit Descriptions

OHCID bit(s) Select Block Description Notes

[1:0] Quad 00b for Quad0 (Q0) 01b for Quad1 (Q1) 10b for Quad2 (Q2) (for client only) 11b for Quad3 (Q3) (for client only)

Selects the specified CSP/NSP Quad based on the side selected in bit [2]. For an illustration of the CSP side/NSP side Quads, see Figure 1: IPL4101M Block Diagram.

[2] Client or Network Client: CL=1 Network: LN=0

Selects the side to access, client or network. For an illustration of the CSP/NSP sides, see Figure 1: IPL4101M Block Diagram.

[4:3] Source Client:

00b for OTU2/ODU2 01b for OTU1 10b for OC-n 11b Not used.

Network:

00b for OTU2/ODU2 01b for ODU1 10b for ODU0 11b Not used.

Selects the signal type, based on the side selected in bit [2], for the specified quad. For an illustration of signal types, see Figure 2: Client Signal Processor Detailed Block and Figure 4: Network Signal Processor Detailed Block.

[6:5] OTU1/ODU1 Client:

00b for OTU1 lane 0 01b for OTU1 lane 1 10b for OTU1 lane 2 11b for OTU1 lane 3

Network:

00b for ODU1 #0 01b for ODU1 #1 10b for ODU1 #2 11b for ODU1 #3

Selects the OTU1/ODU1 interface lane, based on OTU1/ODU1 type selected in bit [4:3], for the specified quad. For an illustration of quad OTU1/ODU1 interface lanes, see Figure 2: Client Signal Processor Detailed Block and Figure 4: Network Signal Processor Detailed Block.

[9:7] ODU0/OC-n Client:

000b for OC-192 001b for OC-48 lane 0 010b for OC-48 lane 1 011b for OC-48 lane 2 100b for OC-48 lane 3 101b Reserved 110b Reserved 111b Reserved

Network:

000b for ODU0 #0 001b for ODU0 #1 010b for ODU0 #2 011b for ODU0 #3 100b for ODU0 #4 101b for ODU0 #5 110b for ODU0 #6 111b for ODU0 #7

Selects the OC-n/ODU0 signal, based on OC-n/ODU0 source selected in bit [4:3], for the specified quad. For an illustration of quad OC-n/ODU0 signals, see Figure 2: Client Signal Processor Detailed Block and Figure 4: Network Signal Processor Detailed Block.

For an illustration of the layout of the client/network side blocks, see High Level System Description in

Section ‎1.



The following examples illustrate how the OHCID is decoded:

If the OHCID is 1111101101b decode it as follows:

Bits [1:0] are 01b, designating Quad 1 Bit [2] is 1, designating the Client side Bits [4:3] are 01b, designating OTU1/ODU1 Bits [6:5] are 11b, designating the #3 OTU1/ODU1 as OH Bits [9:7] are not significant because theODU0/OC-n field is set to 111b

The OH block being accessed corresponds to the #3 OTU1 or ODU1 from Quad #1 of the client side.

If the OHCID is 0011110111 decode it as follows:

Bits [1:0] are 11b, designating Quad 3 Bit [2] is 1, designating the Client side Bits [4:3] are 10b, designating OC-n Bits [6:5] are not significant because the type is OC-n Bits [9:7] are 001b, designating the #0 OC-48 OH

The OH block, which is being accessed, corresponds to an OC-48 signal on Lane #0 from Quad #3 of the client side.

The following figure shows the 64 byte OH of an OTN signal.

Figure 23: OTN OH Structure

The transmitted and received overhead data busses are 16 bits wide. The overhead information of the selected OTN signal is presented on the data bus two bytes at a time starting with the column 1 and 2 of the first OTN row and proceeding sequentially to the end of the OH row and then moving over to the next sequential row. Each two bytes of the OH data are assigned on the data bus as follows:

Bit 15 of the OH bus corresponds to the first bit received from the odd column of the OTN OH

Bit 0 corresponds to the last received bit of the even column

The following figure shows the 64 byte SONET/SDH OH containing bytes E1, F1, DCC1, DCC2, and DCC3 in bytes 2 through 6 of the first row, respectively.

Figure 24: SONET/SDH OH Structure

For SONET/SDH frames, each two OH bytes are assigned on the data bus as follows:

Bit 15 of the OH bus corresponds to the first bit received from the odd column (starting with column 1) of the SONET/SDH OH

Bit 0 corresponds to the last received bit of the even column

NOTE—Each byte in the OTN and SONET/SDH overhead can be configured to either carry the data presented through the EOI data bus or to continue with original overhead.

For information about the EOI signal pins, see External Overhead Interface in Section ‎1.1.5.



2.3.2 EOI Timing Diagrams

The following figure shows the relationship between the overhead clock and the overhead signals.

Figure 25: EOI Clock and Signal Timing Relationship

In this example, the EOI cycles through two timeslot channels, where each timeslot channel is associated with a separate signal overhead block, described as follows:

Timeslot Channel A and Timeslot Channel B have valid Rx overhead data, and are read via the RxOH data bus.

An indication is given (Transmit OH Data Request) for Timeslot Channel B conveys that the previous external OH data has been written to the associated transmit signals and that these timeslot channels are ready for new external OH data.

During each timeslot channel an OH block can be both read and written.

The following figure shows the timing of the MFAS signal (TxOHMFAS) indicating the multiframe alignment for the selected Tx signal.

Figure 26: TxMFAS Timing

In this example, a TxOHMFAS signal is provided for each overhead channel (according to the respective OHCID channel number). When TxOHMFAS is high it indicates the start of a new multiframe for the current channel. Accordingly, the TxOHMFAS signal associated with the particular channel remains high for the complete transaction for frame 0 and is low for the next 255 consecutive channel frames.

For more information about EOI timing, see EOI Characteristics in Section ‎4.4.



2.4 Host Processor Interface

The IPL4101M includes a generic synchronous Host Processor Interface (HPI), which enables the user to configure all the various operational modes of the IPL4101M and monitor Client and Network signal status and performance. The operation and configuration of the IPL4101M is performed by writing to and reading from internal registers using the HPI. This interface facilitates quick setup, easy status monitoring, and allows the IPL4101M to interface with the host processor.

The IPL4101M HPI is described in the following sections:

HPI Description in Section ‎2.4.1

HPI Freescale Mode in Section ‎2.4.2

HPI Intel Mode in Section ‎2.4.3

2.4.1 HPI Description

The HPI supports the following modes:

Freescale PowerQUICC™ II/III

Intel i960™

These modes are widely used industry standard bus protocols.

Other processor interfaces can be easily adapted to the IPL4101M control bus. All the internal timing for the HPI logic is derived from an external clock.

The following figure shows the HPI interface consisting of address, data, and control signals.

Figure 27: HPI Interface with Host Processor

The interrupt request pin (IRQ_N) for the IPL4101M has the following operational output modes.

Normal operation:

Drives the interrupt request signal as a regular, active low output.

Tri-state operation:

When IRQ_N=0, which indicates an interrupt request, a 0 is transmitted. When IRQ_N=1, the output switches to high impedance. This mode can be used to connect interrupt pins from several IPL4101M devices to the same

interrupt input pin on the host processor.



An interrupt signal output notification is provided by the IPL4101M. If an event that triggers an interrupt request is detected by the IPL4101M and is not internally masked by the user, the external interrupt request signal is asserted.

In addition, there is a pin used to select Freescale or Intel mode.

For more information about the HPI signal pins, see Host Processor Interface Signal in Section ‎1.1.6.

2.4.2 Freescale Mode

Read timing cycles:

The following figure shows the Freescale mode read timing.

Figure 28: Freescale Interface Read Timing Cycle

When data is read through the HPI the chip select (LCS_ADS) is set low and the address of the IPL4101M register to be read is presented on the AD bus. When the host processor receives the acknowledge strobe (LGTA), it responds with an appropriate output enable pulse (OE low) and the data can be read through the bus.

The address and control signals must remain valid for the length of the read cycle of 14 clock cycles (four of the clock cycles are for reads from global module registers) until the host processor receives from the IPL4101M the LGTA strobe, which indicates the end of the read operation. The next read operation can start two clock cycles after the LGTA strobe is received by the host processor.

Note—For high CCLK frequencies, Data (D) removal from the bus after Output Enable (OE) high may take longer than a single CCLK cycle. On these events Freescale relaxed mode can be

considered. For more information about HPI timing, see HPI Timing Characteristics in Section ‎4.5.

For more information about Freescale relaxed mode, refer to Freescale documentation.



Write timing cycles:

The following figure shows the Freescale mode write timing.

Figure 29: Freescale Interface Write Timing Cycle

To start a Write operation the chip select signal (LCS_ADS) is set low and the address of the IPL4101M register being accessed and the corresponding data are presented. One cycle later the write enable signal (WE_R) is set low. The host processor then waits for the acknowledge strobe (LGTA), which indicates the completion of a valid write operation.

The address, control signals, and the corresponding data must remain valid for the length of the write cycle of eight clock cycles (four of the clock cycles are for writes from global module registers) until the host processor receives the LGTA strobe, from the IPL4101M. The next write operation can start two clock cycles after the LGTA is received by the host processor.

2.4.3 Intel Mode

Endian support

With Intel mode the HPI provides a pin selection for little endian or big endian operation. The following figure shows the byte order for the endian modes.

Figure 30: Intel Mode Endian Selection



Read timing cycles

The following figure shows the Intel mode read cycles.

Figure 31: Intel Interface Read Timing Cycle

The Read data pin (LCS_ADS) is strobed low for one clock cycle. One cycle later the address of the IPL4101M internal register to be read is presented, while the output enable signal (OE) is set low. When the host processor receives the acknowledge (LGTA) indication pulse, valid data can be read through the data bus.

The address and control signals must remain valid until the host processor receives the LGTA signal, which requires up to 15 cycles for read. The next read operation can start two clock cycles after the LGTA is received by the host processor.

Note—For high CCLK frequencies, Data (D) removal from the bus after Output Enable (OE) high may take longer than a single CCLK cycle. For more information about HPI timing, see HPI

Timing Characteristics in Section ‎4.5.

Write timing cycles

The following figure shows the Intel mode write cycles.

Figure 32: Intel Interface Write Timing Cycle



The write data signal (LCS_ADS) is strobed low for one clock cycle. One cycle later the address of the IPL4101M internal register, the data bus, and the write enable (WE_R) signal are all presented with valid signals. The host processor then waits for the IPL4101M to generate a corresponding acknowledge (LGTA) strobe, which indicates that a valid write operation has been accomplished.

The address, controls signals, and data information must remain valid for nine clock cycles until the host processor receives the LGTA strobe from the IPL4101M. The next write operation can start two clock cycles after the LGTA is received by the host processor.

2.5 JTAG Interface

The IPL4101M supports JTAG IEEE Std 1149.1-1990, IEEE Standard Test Access Port and

Boundary. For information about JTAG timing values, see JTAG Characteristics in Section ‎4.6.


51 Design Considerations IP Light Proprietary and Confidential

3 Design Considerations IPL4101M design considerations are described in the following sections:

IPLightSERDES™ Interface in Section ‎3.1

Reference Clock in Section ‎3.2

Power and Ground Connections in Section ‎3.3

Package Information in Section ‎3.4

3.1 IPLightSERDES™ Interface

The following figure shows the IPLightSERDES™ external connections.

Figure 33: IPLightSERDES™ Interface

The IPL4101M can drive signals through standard FR4 material. The following table describes the IPLightSERDES™ output drive capabilities over different lane rates.

Table 21: Output Drive Capability

Interface Rate

Maximum Trace Length for Standard FR4 Material

(inches) Notes

11.4 Gbps 12

5.7 Gbps 24 For FPGA interconnection.

3.2 Gbps 30 Including two connectors in backplane interconnect.



3.2 Reference Clock

The input reference clock for the IPL4101M must operate at 155.52MHz±20ppm. The following figure shows how the external reference clock is connected to the IPL4101M.

Figure 34: Reference Clock

For information about the reference clock parameters, see Clock Parameters in Section ‎4.7.



3.3 Power and Ground Connections

Power pins must be decoupled. For each group, the 22μF and 2.2μF capacitors are common to the group. The 220nF and 22nFcapacitors must be placed, alternatingly, as close as possible to the power pins. The total number of 220nF and 22nF capacitors must equal the number of the power pins in the group.

The following figure shows the required decoupling scheme.

Figure 35: IPL4101M Decoupling for Power and Ground Connections



3.4 Package Information

The IPL4101M package is 896 pins and 31 x 31 mm HFC-BGA. For information about the package

markings and its storage parameters, see Absolute Maximum Parameters in Section ‎4.1 and Ordering

Information in Section ‎5.

The following figure shows the IPL4101M package dimensions.

Figure 36: IPL4101M Package Dimensions

NOTE—All dimensions and tolerances conform to ANSI Y14.5M-1994.


55 Electrical and Mechanical Data IP Light Proprietary and Confidential

4 Electrical and Mechanical Data The IPL4101M has two input voltages, 1.0V and 2.5V. The IPL4101M operates at 1.0V ±5% and 2.5V ±5%, unless otherwise specified.

IPL4101M electrical and mechanical characteristics are described in the following sections:

Absolute Maximum Ratings in Section ‎4.1

Normal Operating Conditions in Section ‎4.2

High Speed Differential IO Characteristics in Section ‎4.3

EOI Characteristics in Section ‎4.4

HPI Characteristics in Section ‎4.5

JTAG Characteristics in Section ‎4.6

Output Reference Clock Parameters in Section ‎4.7

Reset Signal Parameters in Section ‎4.8

Thermal Information in Section ‎4.9

Power in Section ‎4.10

4.1 Absolute Maximum Ratings

WARNING—Permanent device damage may occur if the Absolute Maximum Ratings are exceeded.

CAUTION—Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.

The following table describes the maximum limits that the IPL4101M can withstand without sustaining permanent damage. These limits are not indicative of normal mode operation conditions.

Table 22: Absolute Maximum Ratings

Description Limits

Voltage 1.0V (VDD10, VDD10A/B/C/D/E/F) -0.3V to 1.35V

Voltage 2.5V (VDD25, VDD25A/B/C) -0.3V to 3V

Static discharge voltage ±2000V (±1000 V for low voltage CML and low voltage PECL differential pins)

Storage temperature -40°C to 125°C

Lead temperature 230°C

Case temperature under bias -40°C to 105°C

Absolute maximum junction temperature 150°C

DC input current ±20 mA

Voltage on Digital Input or Bidirectional Pin -0.3V to 3.6V

Voltage on any digital output pin -0.3V to (VDD25+0.3 V)

Voltage on any differential pin -0.3V to (VDD10+0.3 V)

Latch-up current ±100mA

Voltage overshoot of duration <10ns on any pin (unless otherwise specified)

-1.0V to VDD+1.0V

Relative humidity, during assembly 30-60%

Relative Humidity, during storage 95%, non-condensing



4.2 Normal Operating Conditions

DC and AC characteristics determine the normal operating conditions for the IPL4101M and are described in the following sections:

DC Characteristics in Section ‎4.2.1

AC Characteristics in Section ‎4.2.2

4.2.1 DC Characteristics

The following table describes CMOS Pin DC Characteristics.

Table 23: DC Characteristics for CMOS Pins

Symbol Description Min Nominal Max Units Notes

VDD10 1.0V power supply 0.95 1.0 1.05 V

VDD25 2.5V power supply 2.375 2.5 2.625 V

VIL Input low voltage 0.7 V

VIH Input high voltage 1.7 V

VOL Output low voltage 0.7 V

VOH Output high voltage 1.7 V

VTL Schmitt Trigger Low to High Threshold Point 1.25 1.48 V

VTH Schmitt Trigger High to Low Threshold Point 0.85 1.06 V

IOL Low output voltage current:

High drive 36.9 96.1 mA

Standard drive 12.3 32.1 mA

IOH High output voltage current:

High drive 32.6 114.7 mA

Standard drive 12.2 43 mA

ILEAK Input Leakage current:

Pullup/pulldown resistor input ±90 μA VI=2.5V or VI=0V

Regular input ±10 μA

IOZ Tri-state output leakage current ±10 μA

IDD10 Input supply current 1V 14.2 21.5 A

IDD25 Input supply current 2.5V 1.9 2.85 A

CIN Input capacitance 5 pF

COUT Output capacitance 5 pF

TOP Ambient operating temperature -40 85 °C

HOP Relative Humidity, during operation 5 85 % Non-condensing.



4.2.2 AC Characteristics

The following table describes CMOS Pin AC Characteristics.

Table 24: AC Characteristics for CMOS Pins

Symbol Description Min Nominal Max Units Notes

TRISE Output rise time 0.6 1.1 ns 10% to 90% of full output swing with load capacitance of 10pF.

TFALL Output fall time 0.6 1.1 ns 90% to 10% of full output swing with load capacitance of 10pF.

TSETUP Setup time 1 ns Related to input signal and its sampling clock (unless otherwise specified).

THOLD Hold time 1 ns Related to input signal and its sampling clock (unless otherwise specified).

4.3 High Speed Differential IO Characteristics

The following table describes the high speed differential IO parameters.

Table 25: High Speed Differential IO Parameters

Parameter Min Nominal Max Units

Differential Input Resistance 85 100 115 Ω

Differential Input Data Level 20 2500 mVpp

Differential Output Resistance 85 100 115 Ω

Differential Output Data Level (LVCML/LVPECL) 200 1200 mVpp

Differential Output Rise time (10% to 90%) 30 ps

Differential Output Fall time (90% to 10%) 30 ps

Differential Skew 5 ps

NOTE—Differential output levels depend on output amplitude and pre-emphasis configurations.

4.4 EOI Characteristics

The following table describes the EOI timing characteristics.

Table 26: EOI Timing Characteristics

Symbol Description Min Nominal Max Units

TCID Delay from clock to OHCID 2.5 ns

TCRXOH Delay from clock to RxOH Data 2.5 ns

TCOHVAL Delay from clock to receive overhead valid 2.5 ns

TCREQ Delay from clock to transmit OH data request 2.5 ns

TTXSETUP TxOH Data setup time 2.5 ns

TTXHOLD TxOH Data hold time 2.5 ns

TCMFAS Delay from clock to transmit OH MFAS 2.5 ns

FEOIREF EOI reference clock frequency 64 100 MHz

Duty cycle EOI reference clock duty cycle 40 60 %



The following figure shows the EOI timing characteristics.

Figure 37: EOI Timing Characteristics

4.5 HPI Characteristics

The following table describes the HPI timing characteristics.

Table 27: HPI Characteristics


TAD-SU Address setup time 2.5 ns

TD-SU Data setup time 2.5 ns

TCS-SU Chip Select setup time 2.5 ns

TWE-SU Write Enable setup time 2.5 ns

TACK_OE Receive LGTA to Output Enable delay

2.5 ns

TOE_D Output Enable low to Data removed from bus

17 ns

TACK Clock to LGTA delay 2.5 ns

FHPIREF HPI reference clock frequency 33 72 MHz

Duty cycle HPI reference clock duty cycle 40 60 %



The following figure shows the HPI read timing characteristics.

Figure 38: HPI Read Timing Characteristics

The following figure shows the HPI write timing characteristics.

Figure 39: HPI Write Timing Characteristics



4.6 JTAG Characteristics

The following table describes the JTAG signal Characteristics.

Table 28: JTAG Characteristics


FTCK TCK Frequency 5 MHz

TCK-DUTY TCK Duty Cycle 40 60 %

THITCK TCK High Pulse Width 100 ns

TLOTCK TCK Low Pulse Width 100 ns

TTMS-SETUP TMS Set-up time 25 ns

TTMS-HOLD TMS Hold time to TCK 25 ns

TTDI-SETUP TDI Set-up time to TCK 25 ns

TTDI-HOLD TDI Hold time to TCK 25 ns

TPROP TCK Low to TDO Valid 25 ns

TRESET TRSTB Pulse Width 25 ns

TRISE TRSTB Rise Time 10 ns

Duty cycle TCK duty cycle 40 60 %

The following figure shows the setup and hold timing for the TDI and TMS JTAG signals.

Figure 40: JTAG TMS and TDI Timing



4.7 Output Clock Parameters

The output reference clock rate is calculated differently for high and low rate output clocks as follows:

High rate output clock—the configured reference clock divided by 64 for high rate references and by 16 for low rate references

Low rate output clock—the configured reference clock divided by 64 for High rate references and by 16 for Low rate references and further divided by a configurable even value between 2 and 131072

The following table describes the input reference clock parameters.

Table 29: Input Reference Clock Parameters

Parameter Name Min Nominal Max Units

REFCLK Frequency 155.52 MHz

REFCLK Differential swing 300 1200 mV

REFCLK Duty Cycle 45 55 %

REFCLK Accuracy -20 +20 ppm

REFCLK Input Jitter (12 KHz - 20 MHz BW) 155.52 MHz 0.7 ps

REFCLK Input Random Jitter 2.6 ps-rms

The following table describes the output reference clock tolerances.

Table 30: Output Reference Clock Tolerances

Parameter Name Min Nominal Max Units

High-rate clock frequency 155.52 200 MHz

Low-rate clock frequency 1 100000 KHz

High-rate clock duty cycle 48 50 52 %

Low-rate clock duty cycle 48 50 52 %

4.8 Reset Signal Parameters

The following table describes parameters for the reset signal.

Table 31: Reset Parameters

Parameter Name Description Min Nominal Max Units

TRST_N RST_N pulse width 100 ns

The following figure shows reset signal timing.

Figure 41: RST_N Timing

After the device is powered up, you must allow 1 ms before applying RST_N.



4.9 Thermal Information

NOTE—The values presented here are preliminary estimates.

The following table describes thermal resistance values.

Table 32: Thermal Resistance

Thermal Resistance Value

Junction to Ambient, JA 10.8° C/W for still air

7.6° C/W for 1m/s air flow

6.9° C/W for 2m/s air flow

Junction to Board, JB 4.0° C/W

Junction to Case, JC 0.2° C/W

It is recommended to use a heat sink to maintain normal operating conditions for the device. For more

information about the operating conditions, see Normal Operating Conditions in Section ‎4.2.

4.10 Power

The IPL4101M provides flexible operational modes, and therefore typical power dissipation can vary widely. The following table describes typical power utilizations for a variety of configurations.

Table 33: Typical Power Dissipation

Configuration Power

Dissipation

Two serial client OTU2 interfaces with FEC to two serial network OTU2 interfaces with EFEC.

9W

Two network OTU2 serial interfaces (one East side interface and one West side interface) to four client GbE (GFP-T) interfaces and two client OC-48 interfaces. Two ODU0 and one ODU1 pass through between East and West.

11W

Eight client OC-48 interfaces to two network XFI OTU2 interfaces with EFEC.

11W

Sixteen client GbE interfaces (GFP-T) to two network OTU2 serial interfaces.

13W

Two 10GbE client interfaces to two network OTU2 interfaces with EFEC.

9W

Sixteen GbE (GFP-F) client interfaces to two network OTU2 serial interfaces.

14

Four client OC-48 and GbE (GFP-T) interfaces to two serial network OTU2 interfaces with EFEC.

12W

The IPL4101M provides configuration dependent power optimization. Logic blocks and IPLightSERDES™ lanes can be powered off when not being used. For example, if one Network Signal Processor is configured for serial OTU2, then only one lane is used, and the three other unused lanes can be shutdown. Similarly, when configured to XBI2-2, only two lanes are used, and two must be shutdown.



Power Up/Down Sequences

WARNING—You must adhere to the following power up/down sequences carefully to avoid causing damage to the chip.

To power up the IPL4101M:

1. Connect the ground supply.

2. Connect the power supply.

3. Connect the IO signals.

To power down the IPL4101M:

1. Disconnect the IO signals.

2. Disconnect the power supply.

3. Disconnect the ground supply.


64 Ordering Information IP Light Proprietary and Confidential

5 Ordering Information The materials of the IPL4101M are compliant with RoHS requirements.

The following table describes the Apodis part number details to use when ordering the IPL4101M.

Table 34: Part Number

Part Number Description

IPL4101M 896 pin high performance flip-chip BGA

RoHS compliant

For information about availability and pricing, please contact your local IP Light distributor.

Reader Comments In an ongoing effort to produce more effective documentation, the documentation staff at IP Light Ltd. welcomes any comments regarding this manual. Please use this form to communicate suggestions for improving this publication, or to inform us of any needed corrections.

Thank you for your assistance.

Apodis IPL4101M Datasheet Revision 1.00 April 2011

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