ARTICLE IN PRESS

Microelectronics Journal 41 (2010) 440–446

Contents lists available at ScienceDirect

Microelectronics Journal

0026-26

doi:10.1

n Corr

E-m

f.amoro

(G. Cap

journal homepage: www.elsevier.com/locate/mejo

Analysis of op-amp phase margin impact on SC SD modulator performance

Andrea Pugliese n, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo

Department of Electronics, Computer Science and Systems, University of Calabria, Via P. Bucci, 42C, 87036-Rende (CS), Italy

a r t i c l e i n f o

Article history:

Received 28 September 2009

Received in revised form

27 April 2010

Accepted 3 May 2010Available online 15 May 2010

Keywords:

Sigma-delta modulator

Switched-capacitor (SC) integrator

Behavioural modelling

Operational amplifier (op-amp)

Transient response

Settling time

92/$ - see front matter & 2010 Elsevier Ltd. A

016/j.mejo.2010.05.002

esponding author. Tel.: +39 0984494108; fax

ail addresses: a.pugliese@deis.unical.it (A. Pug

so@deis.unical.it (F.A. Amoroso), cappuccino@

puccino), cocorullo@deis.unical.it (G. Cocoru

a b s t r a c t

The impact of operational amplifier (op-amp) phase margin on switched-capacitor (SC) sigma-delta

modulator (SDM) performance is investigated in this paper. An ad-hoc integrator settling model is

developed and verified by circuit simulations performed in a commercial 0.35 mm CMOS technology.

The model allows the effect of op-amp phase margin to be taken into account in SDM behavioural

analysis. Behavioural simulations of a typical single-bit second-order modulator are presented, as an

example. As shown, the proposed analysis allows well-found specifications for the op-amp unity-gain

frequency, slew rate and phase margin to be defined since the preliminary behavioural simulation

phase.

& 2010 Elsevier Ltd. All rights reserved.

1. Introduction

Sigma-delta modulators (SDMs) are fundamental buildingblocks in a wide variety of applications such as multimedia,telecommunication, measurement and sensor interface systems,in which they are especially used to implement robust, low-power, high-resolution analogue-to-digital converters (ADCs)[1–15]. The impact of basic modulator sub-circuit characteristicson the overall system performance has to be carefully evalu-ated in order to achieve high-performance SDM designs.Behavioural analysis is extensively used to specify convenientsub-circuit parameters in the early-design phase, whereas time-consuming transistor-level simulations are usually performed atthe end of the design process, to verify the circuit operation[2,4,8,9,12–15].

One of the most important issues in SDM designs is the noiseintroduced by the integrator non-idealities. These latter aremainly caused by operational amplifier (op-amp) limitationssuch as finite DC gain, bandwidth, slew rate and output swing.In particular, the non-null integrator settling time is one of themost significant noise sources in switched-capacitor (SC) SDMs[12–15].

In conventional SC SDM behavioural modelling, the op-amp isdescribed as a first-order system, whose settling performance

ll rights reserved.

: +39 0984494834.

liese),

deis.unical.it

llo).

solely depends on its unity-gain frequency and slew rate [12–18].Actually, high-frequency poles are also present in the frequencyresponse of many real op-amps, as occurs in typical two-stageconfigurations [2,4,8,19–21] as well as in single-stage topologies[6,10,11]. In these cases, the integrator settling is determinedby the combined effect of the amplifier unity-gain frequency,slew rate and phase margin. As a consequence, the unity-gainfrequency and slew rate values carried out by conventionalbehavioural analysis allow the required SDM performance to beactually reached only if the phase margin is properly adjusted atthe transistor level design phase.

However, this may reveal itself to be an inefficient designapproach, because the phase margin is related to the op-amp biascurrents and transistor dimensions, which also affect theamplifier unity-gain frequency, slew rate, dc gain, output swing,power consumption, silicon area and thermal noise [19,20]. Thus,an ineffective trial-and-error design procedure aiming to satisfyop-amp requirements may arise and the advantages of thebehavioural analysis for making the transistor level design phasemore affordable and efficient may be wasted.

To better understand and quantify the effect of op-amp phasemargin on SC SDM performance, an improved behaviouralanalysis is presented in this paper. In Section 2, the integratorsettling behavioural model is examined. After an exhaustiverevision of the conventional first-order system description, anadvanced integrator settling model is introduced and validatedby means of transistor-level simulations in the same section. Thebehavioural simulation results for a typical single-bit second-order SDM are reported in Section 3. Finally, some conclusionsare drawn in Section 4.

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A. Pugliese et al. / Microelectronics Journal 41 (2010) 440–446 441

2. SC integrator settling model

A typical fully differential SC integrator used in SDMs isshown in Fig. 1. vi(t) and vo(t) are the input and output signalsof the SC integrator, respectively. CS and CF are the samplingand integration capacitances, respectively. CIN models theop-amp input parasitic capacitance and CL is the lumped loadintegrator capacitance. In the sampling phase (f1 high), vi(t) issampled by CS. In the integration phase (f2 high), the chargeis transferred from CS to CF, causing a change in vo(t). By indicatingthe clock period with TS and the output voltage change with VS atthe end of the nth integration phase, the following relationshipholds:

voðnTSÞ ¼ voðnTS�TSÞþVS ð1Þ

The value of VS is determined by the integrator step responsey(t) at the nth integration phase, which is described by meansof an opportune settling model. Under the normally verifiedassumption that the sampling and integration phases have thesame duration, VS is given by

VS ¼ yTS

2

� �ð2Þ

and y(t) is the integrator response to a step of amplitude

VIS ¼ vi nTS�TS

2

� �ð3Þ

y(t) is in general determined by the slewing characteristics andthe linear time response (namely ylin(t)) of the integrator at thenth integration phase.

2.1. Conventional model

Conventionally, the integrator is modelled as a first-ordersystem [12–18] characterized by a time constant

t¼ 1

2pGBWð4Þ

In (4), GBW ¼ fUGF is the integrator loop-gain unity frequency(in Hz), f ¼ CF=ðCSþCINþCF Þ and UGF being the feedbackfactor [14] and op-amp open-loop unity-gain frequency (in Hz),respectively. Taking into account the charge conservation law atthe beginning of the integration phase [15–17], ylin(t) can bewritten as

ylinðtÞ ¼ G0VISð1�KmðtÞÞ ð5Þ

where G0 ¼ CS=CF is the integrator gain and K ¼ 1þC2F =½CLðCSþ

CINþ CF ÞþCF ðCSþCINÞ� and m(t) the response mode. For a first-order system

mðtÞ ¼ e�ðt=tÞ ð6Þ

Fig. 1. Fully differential SC integrator.

From (5,6), the maximum slope of the linear integratorresponse occurs at t¼0 and is given by

dylinðtÞ

dtt ¼ 0

¼KG0VIS

t

����� ð7Þ

In the absence of slew rate limitations, the integrator stepresponse y(t) is just ylin(t). Instead, if (7) exceeds the amplifierslew rate SR, y(t) is modelled by a straight line of slope SR fortrtLS, where tLS is the time instant at which the slewingbehaviour ends.

After the slewing period, the integrator dynamics is deter-mined by a linear response (namely ySS (t)) whose maximumslope is equal to SR

ySSðtÞ ¼VSS

VISylinðtÞ ð8Þ

where VSS ¼ tSR0=G0K and SR0 ¼ SR signðG0VISÞ. y(t) is thenobtained by joining the straight line of slope SR and ySS (t) att¼tLS. By imposing the continuity of both y(t) and its derivative att¼tLS, the following expression arises:

yðtÞ ¼SR0tþG0VISð1�KÞ trtLS

ySSðt�tLSÞþG0ðVIS�VSSÞ t4tLS

(ð9Þ

where tLS ¼ K9G0VIS9=SR�t. Eqs. (5–9) are extensively used inconventional behavioural analysis to evaluate the impact of theop-amp GBW and SR on the modulator performance. However, inreal situations the integrator time response typically shows high-order dynamics, the characteristics of which can be actuallyanalyzed by evaluating the combined effect of the op-amp GBW,SR and phase margin PM.

2.2. Proposed model

To take the op-amp PM into account in the integrator settlinganalysis, the typical two-pole open-loop transfer function char-acterising many real amplifiers [20,21] is referred in thefollowing:

AðsÞ ¼A0

ð1þs=p1OLÞð1þs=p2OLÞð10Þ

where A0 is the open-loop dc gain, and p1OL and p2OL are the twoopen-loop poles. GBW, PM, p1OL and p2OL are related by thefollowing Eqs. [20,21]:

p1OL ¼ 2pGBW

A0f

p2OL ¼ 2pGBW

ftanðPMÞ

8>>><>>>:

ð11Þ

From (10,11), taking the feedback factor f into account andassuming A0b1, the closed-loop integrator poles are the rootsof the polynomial rðsÞ ¼ s2þð2pGBW tanðPMÞ=f Þsþð2pGBWÞ2

tanðPMÞ=f . By comparing the latter with the generic second-orderpolynomial gðsÞ ¼ s2þ2zonsþon

2, the following expressions canbe carried out:

z¼1

2

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffitanðPMÞ

f

s

on ¼ 4pGBWz

8>><>>: ð12Þ

If zo1, the integrator is characterized by two complex poles

whose damping factor and natural frequency are z and on,

respectively. Otherwise, if zZ1, the integrator has two real poles

whose angular frequencies are oP1,2 ¼onðz7ffiffiffiffiffiffiffiffiffiffiffiffiz2�1

qÞ.

Thus, taking into account the two poles characterizingthe integrator dynamics, the response mode m(t) to be used in

ARTICLE IN PRESS

Fig. 3. Two-stage Miller-compensated op-amp.

Table 1Main parameters of the designed integrators.

Parameter Value

A. Pugliese et al. / Microelectronics Journal 41 (2010) 440–446442

ylin(t) (5) is the following:

mðtÞ ¼

e�zontffiffiffiffiffiffiffiffiffiffiffiffi1�z2

q sin on

ffiffiffiffiffiffiffiffiffiffiffiffi1�z2

qtþtan�1

ffiffiffiffiffiffiffiffiffiffiffiffi1�z2

qz

0@

1A

0@

1A zo1

ð1þoP1tÞe�oP1t z¼ 1oP2

oP2�oP1e�oP1tþ

oP1

oP1�oP2e�oP2t z41

8>>>>>>>><>>>>>>>>:

ð13Þ

In the absence of slew rate limitations, the integrator stepresponse y(t) is just ylin(t). Instead, if the slope of ylin(t) exceeds SR,the basic idea of the conventional model can be opportunelyextended to the case under examination by considering thefollowing important aspects (Fig. 2).

First, the slope of ylin(t) is in general less than SR for tot1. As aconsequence, y(t)�ylin(t) for tot1 and the slewing is modelledby a straight line of slope SR but which starts from the point(t1, ylin(t1)), to ensure the continuity of both y(t) and its derivativeat t¼t1. Second, the maximum of the derivative of ylin(t) occurs ingeneral at t¼Dt(DtZt1), and the following relationship holds forthe linear response ySS(t) whose maximum slope is equal to SR:

dySSðtÞ

dt t ¼ Dt ¼ SR0

�� ð14Þ

From (14), ySS(t) cannot be then roughly joined to the straightline of slope SR as in the case of first-order system, because thecontinuity of both y(t) and its derivative at the end of the slewingperiod (i.e. at t¼tLS) has to be guaranteed [22]. Taking the aboveremarks into account, simple geometric considerations lead to thefollowing expression for the slew-rate-limited integrator response(Fig. 2):

yðtÞ ¼

ylinðtÞ tot1

SR0ðt�t1Þþylinðt1Þ t1otrtLS

ySSðt�tLSþDtÞþG0ðVIS�VSSÞ t4tLS

8><>: ð15Þ

where

VSS ¼SRVIS

max signðG0VISÞdylinðtÞ

dt

h i

and

tLS ¼G0 VIS�VSSð ÞþySSðDtÞ�ylinðt1Þ

SR0þt1

With respect to the conventional approach, an analysis basedon (5), (8), (12–15) allows the effect of PM on the integratorsettling performance to be taken into account.

Fig. 2. Generic integrator step response: (dashed line) linear and (continuous line)

slew-rate-limited.

2.3. Transistor-level model validation

To validate the proposed model, three different designs of theintegrator in Fig. 1 were carried out in a commercial 0.35 mmCMOS technology by employing the well-established two-stageMiller-compensated op-amp [8,20,21] shown in Fig. 3.

In the circuit of Fig. 3, MOSFETs M1/M5 and M6/M9 constitutethe first and second amplifier stages, respectively, CC the Millercompensation capacitance and RC the nulling resistor. The latter isused to cancel the positive zero introduced in the op-amp transferfunction by the feedforward signal path through CC [8,20,21].Table 1 summarizes the main circuit parameters of the designedintegrators. In the table, I1 and gm1 are the bias current and thetransconductance of M1/M2, respectively, I2 and gm2 are thebias current and the transconductance of M7/M9, respectively.SR is given by the lowest slew rate of the two amplifierstages, SR¼minf2I1=CC ,2I2=ðCLþCCÞg [20]. Table 2 reports thecompensation network elements used in the integrator designs,and the resulting GBW, PM and SR values. Fig. 4 reports the plotsof the real integrator step response, the one predicted by theconventional model using the above GBW and SR values in (5–9),and the predicted one when PM is also taken into account,according to the proposed model, in (5), (8), (12–15). From theplots in the figures, it appears clearly that the proposed model ischaracterized by a high prediction capability, allowing an accuratedescription of oscillations which typically occur in real integrator

gm1 88 mA/V

gm2 250 mA/V

I1 5 mA

I2 161 mA

CS 2 pF

CF 2 pF

CL 4 pF

CIN 0.03 pF

Table 2Compensation network elements, GBW, PM and SR values of the designed

integrators.

Compensation network elements GBW (MHz) PM (1) SR (V/ms)

Design 1 CC¼1.3 pF; RC¼4 kO 7.3 47 7.7

Design 2 CC¼1.6 pF; RC¼6.8 kO 6.4 MHz 60 6.3

Design 3 CC¼2.3 pF; RC¼10 kO 5.2 MHz 80 4.3

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Fig. 4. 1V-amplitude integrator step response: (1) (dashed line) resulting from HSPICE simulations; (2) (continuous line) predicted by the proposed model (5), (8), (12–15)

when: (a) GBW¼7.3 MHz, SR¼7.7 V/ms and PM¼471; (b) GBW¼6.4 MHz, SR¼6.3 V/ms and PM¼601; (c) GBW¼5.2 MHz, SR¼4.3 V/ms and PM¼801; (3) (dotted line)

predicted by the conventional model (5–9) when: (a) GBW¼7.3 MHz and SR¼7.7 V/ms; (b) GBW¼6.4 MHz and SR¼6.3 V/ms; (c) GBW¼5.2 MHz and SR¼4.3 V/ms.

A. Pugliese et al. / Microelectronics Journal 41 (2010) 440–446 443

responses. Instead, the first-order model can be excessively rough,hiding critical information about the actual system dynamics.

Obviously, the response predicted by the conventional modeltends to approach the one predicted by the proposed high-order

settling description when the phase margin increases. This isbecause, according to (12), z tends to become greater than 1 whenthe phase margin increases, and the system poles tend to becometherefore real. From (12), it appears that the larger the value of the

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A. Pugliese et al. / Microelectronics Journal 41 (2010) 440–446444

phase margin is, the larger is the value of z. Since the angular

frequencies of the system poles are oP1,2 ¼onðz7ffiffiffiffiffiffiffiffiffiffiffiffiz2�1

qÞ, one

pole of the system tends to become dominant with respect to theother one when the phase margin increases, and the single-poleapproximation tends to describe the system frequency response.

This could lead to the incorrect conclusion that the necessity ofusing the proposed accurate settling description in the beha-vioural analysis could be overcome simply by choosing largephase margin values.

However, the arbitrary choice of an excessively large phasemargin value is not a costless operation. In fact, as shown by datain Table 2, increasing the phase margin can cause a strongreduction of GBW and SR for a given set of amplifier transcon-ductances and bias current, i.e. for a given power consumption. Asa consequence, the increase of PM generally leads to increase thepower consumption required to achieve the desired values ofGBW and SR [20].

In a realistic power-constrained scenario, over-sizing the op-amp phase margin just to make the integrator similar to afirst-order system could not be, therefore, a suitable designchoice.

Thus, it is crucial to analyze carefully what is the real impact ofthe op-amp phase margin on the overall system characteristics,and what phase margin is sufficient to achieve thedesired modulator performance. Clearly, this kind of analysiscannot be performed by means of SDM behavioural simulationsbased on the conventional model, in which the strong impactof the op-amp phase margin on the integrator settling isneglected.

Instead, the combined effect of GBW, SR and PM on theoverall modulator performance can be investigated by performingbehavioural simulations based on the proposed model.

Fig. 5. Second-order m

Fig. 6. Dependence of modulator SNDR on SR for a first

As an example, in the following the analysis will be carriedout for a typical single-bit second-order SDM without loss ofgenerality.

3. RDM behavioural analysis

The behavioural model of the considered second-order single-bit SDM is shown in Fig. 5. In this model, the second integratorand the comparator are both implemented as ideal blocks,because they do not affect the modulator performancesignificantly [13,14]. Instead, the first integrator takes settlinglimitations into account, as discussed in Section 2. In fact, fromthe scheme in Fig. 5, it appears that the first integrator modelimplements Eq. (1). The block indicated as ‘‘Integrator settlingmodel’’ calculates the term VS in (1) according to (2), andconsidering the real integrator time response y(t). This lattercan be calculated by using the conventional expression (9) in thecase of first-order integrator settling behaviour, or by usingthe proposed accurate settling model (15) to take high-ordersettling behaviour into account.

Obviously, the proposed settling description can be used in acomplete SDM behavioural analysis along with the modelsalready available in the literature describing the effects of othernoise sources such as the op-amp finite DC gain and output swing,the clock jitter and the switch thermal noise [12–18]. These latteraspects will not be considered in the following for the sake ofconciseness.

Behavioural simulations were performed for GSM basebandsignals (200 KHz bandwidth) by implementing the model of Fig. 5in MATLAB environment. A frequency sampling of 100 MHz anda 0.75 V-amplitude sinusoidal input signal with a frequency of

odulator model.

-order integrator characterized by GBW¼500 MHz.

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A. Pugliese et al. / Microelectronics Journal 41 (2010) 440–446 445

45.776 KHz was considered. The amplitude of the modulatoroutput was assumed to be 3 V peak-to-peak. The gains of the firstand second integrator were supposed to be equal to 0.25 and 0.5,respectively. For the first integrator, CS¼1 pF, CF¼4 pF andCL¼1 pF were assumed, and CIN was neglected in the analysis(resulting in K¼2.8). A signal-to-noise and distortion ratioSNDR¼92 dB were supposed as a goal in order to achieve 15 bitsof resolution [12]. The SNDR was measured according to theprocedure suggested in [13].

Whenever the integrator behaves as a simple first-order system,the conventional settling model can be used for behaviouralsimulations, allowing GBW equal to 500 MHz to be carried out asa suitable choice to achieve the 92-dB SNDR requirement. For thisGBW value, by analysing the SNDR dependence on SR shown inFig. 6, it appears that an amplifier characterized by SR¼550 V/mssuffices to the aim.

To highlight the impact of the op-amp phase margin on themodulator performance, the proposed model is then appliedreferring to a two-pole amplifier with the same values of GBW andSR, i.e. GBW¼500 MHz and SR¼550 V/ms. For this case, themodulator SNDR dependence on PM is plotted in Fig. 7.

Fig. 8. Modulator output PSDs for GBW¼500 MHz a

Fig. 7. Dependence of the modulator SNDR on

As shown, the SNDR is now significantly less than 92 dBeven for the sufficiently large value of 551 for PM. This poorperformance is also evidenced by the plot in Fig. 8, whichcompares both the power spectral densities (PSDs) of themodulator output for PM¼551 and 651, the latter being areasonable design choice for PM to reach the desired SNDR

(Fig. 7). In Fig. 8, the presence of a distortion peak (correspondingto the third harmonic of the output signal) in the GSM bandwidthis highlighted for the two PSDs. As it appears, the peak amplitudesare considerably different in the two cases.

Moreover, in accordance with the results shown in Section 2,the plot of Fig. 7 shows that the phase margin increasing tends tomake acceptable the GBW and SR values previously chosen on thebasis of the first-order behavioural model. However, as previouslydiscussed, a blind choice of a large PM value is not advisableaiming to avoid an inefficient design, above all in terms of powerconsumption.

On the other hand, the greater accuracy of the proposed modelresults in larger simulation times compared with the conventionalone (the simulation time to calculate a 65536-point FFT is 4.3 s byusing the proposed model, and 0.3 s by using the conventional

nd SR¼550 V/ms when PM¼551 and PM¼651.

PM for GBW¼500 MHz and SR¼550 V/ms.

ARTICLE IN PRESS

Fig. 9. Dependence of the modulator SNDR on PM and SR for GBW¼500 MHz.

A. Pugliese et al. / Microelectronics Journal 41 (2010) 440–446446

model). However, this can be a reasonable price to pay to benefitfrom important information about the phase margin impact onthe overall system performance since the behavioural simulationphase.

The usefulness of the approach can be further appreciated byconsidering the 3D plot in Fig. 9, which shows the dependence ofSNDR on PM and SR when GBW¼500 MHz. White regions in theplot identify the suitable (PM, SR) couples for which the desiredSNDR is reached. By tracing plots such as the one in Fig. 9for different GBW values, a clear understanding of the combinedimpact of PM, GBW and SR on the modulator performance can beeffectively obtained. Thus, well-founded early-design specifi-cations can be carried out, avoiding rough parameters choicesthat may directly result in poor system performance. Thebehavioural analysis based on the proposed integrator settlingmodel proves to be then a powerful tool in order to guarantee anefficient top-down SDM design approach.

4. Conclusions

In this paper, the impact of the op-amp phase margin on SCSDM performance has been investigated by means of a beha-vioural analysis based on a new integrator settling model. Theproposed model was validated by means of transistor-levelsimulations of an SC integrator implemented in a commercial0.35 mm CMOS technology. The behavioural simulation resultsfor a typical single-bit second-order SDM proved the usefulnessof the novel integrator settling description in order to evaluatethe combined impact of the op-amp GBW, SR and PM on theoverall modulator performance. The proposed approach allowswell-defined early-design specifications to be carried out in thebehavioural simulation design phase, avoiding inefficient blindchoices and trial-and-error process in the transistor-level-designphase.

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