An Analytical Subthreshold Drain Current Model for Pocket Implanted Nano Scale n-MOSFET

Muhibul Haque Bhuyan1, Quazi D. M. Khosru2 Department of Electrical and Electronic Engineering (EEE)

Bangladesh University of Engineering and Technology (BUET), Dhaka 1000, Bangladesh E-mail: 1muhibulhb@gmail.com and 2qdmkhosru@eee.buet.ac.bd

Received 8 September 2010, accepted 25 September 2010, online October 2010. Abstract: This paper presents an analytical subthreshold drain current model for pocket implanted nano scale n-MOSFET. The model is developed by using the linear pocket profiles at the source and drain edges and by solving the Poisson's equation in the depletion region at the surface with the appropriate boundary conditions at source and drain for deriving the surface potential. The model includes the effective doping concentration of the two linear pocket profiles. Electron current density is obtained from the conventional drift-diffusion equation. Integration of surface potential is obtained numerically. Effective channel thickness is obtained by applying Gauss's Law at the surface. The simulation results show that the derived subthreshold drain current model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI MOS devices. Keywords: Linear Pocket Profile, Pocket Implanted MOSFET, Subthreshold Drain Current, Surface Potential, Threshold Voltage

1. INTRODUCTION As the channel length of MOSFETs is scaled down to deep-submicrometer or sub-100 nm regime, we observe the reduction of threshold voltage with the reduction of channel length due to the charge sharing between the drain/source region and the channel [1]. Also, the off-state leakage current increases due to sensitivity of the source/channel barrier to the drain potential or drain induced barrier lowering (DIBL). This effect is known as short-channel effect (SCE). This effect arises as a result of two dimensional potential distribution and high electric fields in the channel region [2]. It can be reduced or can be even reversed (then it is called reverse short channel effect or RSCE in short) by locally raising the channel doping near source and drain junctions. RSCE was originally observed in MOSFETs due to oxidation-enhanced-diffusion [3] or implant-damage-enhanced diffusion [4] which are very difficult to control. Lateral channel engineering utilizing halo or pocket implant [5-9] surrounding drain and source regions is effective in

suppressing short channel effects. The halo or pocket implant can be either symmetrical [10] or asymmetrical [11] with respect to source or drain. Reported circuit applications include a 256 M-bit DRAM [12] and mixed-signal processor [13]. In fact, this pocket implant technology is found to be very promising in the effort to tailor the short-channel performances of deep-submicron as well as sub-100 nm MOSFETs although careful tradeoffs need to be made between minimum channel length and other device electrical parameters [6]. Already few papers have been published focusing on the subthreshold behaviour of pocket implanted MOSFET [14-16]. When the gate voltage is below the threshold voltage and the semiconductor surface is in weak inversion, the corresponding drain current is called the subthreshold current. The subthreshold region is particularly important for low-voltage, low-power applications, such as when the MOSFET is used as a switch in digital logic and memory applications, because the subthreshold region describes how the switch turns on and off. In [9], models for subthreshold and above subthreshold currents in 0.1 μm pocket n-MOSFETs for low-voltage applications have been derived based on the diffusion current transport equation. But this model characterizes the localized pile-up of channel dopants as step profile. The influences of halo implant dose and tilt angle on the off-state current have been investigated by technology computer-aided design (TCAD) simulation in [14]. A channel length independent subthreshold characteristic in submicron MOSFETs has been reported by Shin et al in [15] due to the presence of localized pileup of channel dopants near the source and drain ends of the channel. An analytical subthreshold current model for pocket-implanted n-MOSFETs has been presented in [16]. But this model also characterizes the localized channel dopants as step profile. In this paper, an analytical subthreshold current model for the sub-100 nm pocket implanted n-MOSFET has been derived assuming the linear profiles of pocket doping. Here the 1-D pocket profiles across the channel have been transformed to an effective doping concentration expression, which is used in the 1-D Poisson’s equation to derive the surface potential model applying the

Journal of Electron Devices, Vol. 8, 2010, pp. 263-267

© JED [ISSN: 1682 -3427 ]

Journal of Electron Devices www.jeldev.org

M. H. Bhuyan

appropriate boThe effective claw. Finally, conventional dshow that thewell for variowell as variouusefulness of onext generatio

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M. H. Bhuyan

We assume the1. At x=

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e following bo0= , i.e. at th( )0s bi BSVϕ −=

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2010, pp. 263-

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267

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IONS ubthreshold cuMOSFET, dif

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M. H. Bhuyan

Fig. 4 (a) Subthdrain biases of VL = 0.25 μm.

Fig. 4 (b) Subthdrain biases of VL = 100 nm. Fig. 5 shows variation with concentration.implant conceincreases for thto the additiondrain edges. Iimplant consubthreshold diminishes.

n et al, Journal o

hreshold drain cuVDS = 0.1 V and

hreshold drain cuVDS = 0.1 V and

the variation gate voltage f It is observed

entration decrehe same applie

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urrent versus gatVDS = 2.5 V wit

urrent versus gatVDS = 2.5 V wit

of subthresholfor three differe

that as the peaeases the subthed gate bias. Thms present nearrved that as th

decreases moases. Because

evices, Vol. 8, 2

te voltage for twth channel length

te voltage for twth channel length

ld drain currenent peak pockeak of the pockehreshold currenhis happens dur the source anhe peak pocke

ore then the then RSCE

2010, pp. 263-

266

wo h,

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Fig. 5 Subpeak pockelength, L = Fig. 6 shdifferent subthreshobias in thewith the found in tthe amousubthreshovoltage in

Fig. 6 Sudifferent sulength, L =

5. CONAn analytthin oxidehas been diffusion as the thren-MOSFEdrain biaassuming

267

threshold drain et concentration,100 nm.

hows the variasubstrate bia

old current dee negative diresubstrate bias

the literature. Bunt of currenold slope decrcreases in the s

ubthreshold draiubstrate biases,100 nm.

NCLUSIONStical subthreshe and nano sca

developed bequation and ueshold voltage

ETs incorporatas dependenctwo linear po

current versus , drain bias, VDS

ation of subthases. It is oecreases with iction. The resus effect on suBut it has alsont increment reases more rshorter channel

in current versdrain bias, VDS

S hold drain currale pocket impased on the using the surfae models for thting the effect

cies. The mocket profiles a

gate voltage forS = 2.5 V and ch

hreshold currenobserved thatincreasing subults are in consubthreshold cu

o been observeis less, and

rapidly as thel length device

sus gate voltag= 0.1 V and ch

rent model forplanted n-MOconventional

ace potential ashe pocket implts of substrateodel is devealong the chan

r three hannel

nt for t the bstrate sistent urrent d that d the e gate .

ge for hannel

r ultra SFET drift-

s well lanted e and

eloped nnel at

M. H. Bhuyan et al, Journal of Electron Devices, Vol. 8, 2010, pp. 263-267

267

the surface of the device from the source and drain edges. The effect of changing the device and pocket profiles parameters on the subthreshold current have been studied using the proposed model. The simulated results show that the proposed model predicts the subthreshold current down to 50 nm channel length. It shows similar behaviour as found in the literature. Hence this model efficiently evaluates the subthreshold drain current of scaled pocket n-MOSFETs having channel lengths in the nano scale regime.

ACKNOWLEDGMENT The authors would like to acknowledge the financial support provided by the Committee of Advanced Studies and Research, Bangladesh University of Engineering and Technology (BUET) for conducting the research work.

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