subthreshold and gate leakage current analysis and
TRANSCRIPT
Rochester Institute of TechnologyRIT Scholar Works
Theses Thesis/Dissertation Collections
2007
Subthreshold and gate leakage current analysis andreduction in VLSI circuitsVinay Chinta
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Recommended CitationChinta, Vinay, "Subthreshold and gate leakage current analysis and reduction in VLSI circuits" (2007). Thesis. Rochester Institute ofTechnology. Accessed from
Subthreshold and Gate Leakage Current Analysis and
Reduction in VLSI Circuits
by
Vinay Chinta
A Thesis Submitted in Partial Fulfillment of the Requirements for the Degree of Master of Science in Computer Engineering
Approved By:
Supervised by
Dr. Dhireesha Kudithipudi Department of Computer Engineering Kate Gleason College of Engineering
Rochester Institute of Technology Rochester, NY
April 2007
Dhireesha K. Dr. D. Kudithipudi Primary Advisor - R.I. T. Dept. of Computer Engineering
Kenneth Hsu Dr. K. Hsu Secondary Advisor - R.I. T. Dept. of Computer Engineering
Marcin Lukowiak Dr. M. Lukowiak Secondary Advisor - R.1. T. Dept. of Computer Engineering
Thesis Release Permission Form
Rochester Institute of Technology Kate Gleason College of Engineering
Title: Subthreshold and Gate Leakage Current Analysis and Reduction in
VLSI Circuits
I, VINAY CHINTA, HEREBY GRANT PERMISSION TO THE WALLACE MEMORIAL
LIBRARY TO REPRODUCE MY THESIS IN WHOLE OR PART.
(h. Vinay Vinay Chinta
Date
11
Dedication
To Father andMother
in
Acknowledgements
I offer my sincerest gratitude to my advisor, Dr. Kudithipudi who has guided me
throughout my thesis work with patience and knowledge. Without her guidance and
persistent help this thesis would not have been possible. I wish to thank my thesis
committee members, Dr. Hsu and Dr. Lukowiak for providing insights that guided and
challenged my thinking and thereby improving my thesis work. I would also like to thank
Mr. Mezzanini for providing all the required applications and software needed for this
thesis.
IV
Abstract
CMOS technology has scaled aggressively over the past few decades in an effort
to enhance functionality, speed and packing density per chip. As the feature sizes are
scaling down to sub-lOOnm regime, leakage power is increasing significantly and is
becoming the dominant component of the total power dissipation. Major contributors to
the total leakage current in deep submicron regime are subthreshold and gate tunneling
leakage currents. The leakage reduction techniques developed so far were mostly devoted
to reducing subthreshold leakage. However, at sub-65nm feature sizes, gate leakage
current grows faster and is expected to surpass subthreshold leakage current.
In this work, an extensive analysis of the circuit level characteristics of
subthreshold and gate leakage currents is performed at 45nm and 32nm feature sizes. The
analysis provides several key observations on the interdependency of gate and
subthreshold leakage currents. Based on these observations, a new leakage reduction
technique is proposed that optimizes both the leakage currents. This technique identifies
minimum leakage vectors for a given circuit based on the number of transistors in OFF
state and their position in the stack. The effectiveness of the proposed technique is
compared to most of the mainstream leakage reduction techniques by implementing them
on ISCAS89 benchmark circuits.
The proposed leakage reduction technique proved to be more effective in
reducing gate leakage current than subthreshold leakage current. However, when
combined with dual-threshold and variable-threshold CMOS techniques, substantial
subthreshold leakage current reduction was also achieved. A total savings of 53% for
subthreshold leakage current and 26% for gate leakage current are reported.
v
Table of Contents
THESIS RELEASE PERMISSION FORM II
DEDICATION Ill
ACKNOWLEDGEMENTS IV
ABSTRACT V
TABLE OF CONTENTS VI
LIST OF FIGURES VIII
LIST OF TABLES X
GLOSSARY XI
CHAPTER 1 INTRODUCTION 1
CHAPTER 2 SOURCES OF POWER DISSIPATION 5
2.1. Active Power 5
2.1.1 Switching Power 5
2.1.2 Short-circuit Power 6
2.2. Static Power 7
2.2.1 Subthreshold Leakage 7
2.2.2 Gate Leakage 8
CHAPTER 3 LEAKAGE REDUCTION TECHNIQUES 10
3.1. Introduction 10
3.2. LowPower Logic Family 10
3.2.1 Leakage Current 13
3.2.2 Short-Circuit Current 15
3.2.3 Switching Current 17
3.3. Transistor Stacks 19
vi
3.4. DualThreshold CMOS (DTCMOS) 21
3.5. VariableThreshold CMOS (VTCMOS) 22
CHAPTER 4 SUBTHRESHOLD AND GATE LEAKAGE CHARACTERISTICS 23
4.1. 4-Input CMOS NAND LeakageAnalysis 24
4.1.1 Case Study -1 25
4.1.2 Case Study -2 28
4.2. 4-Input CMOS NORLeakageAnalysis 33
4.3. NewLeakage ReductionAlgorithm 34
CHAPTER 5 RESULTS 38
5.1. Transistor Stacks 39
5.2. Dtcmos 42
5.3. Vtcmos 43
5.4. New Leakage Reduction Technique 45
5.5. Input-Pin Reordering CombinedWithDtcmos/Vtcmos 47
5.6. Comparison ofLeakage Reduction Techniques 50
CHAPTER 6 CONCLUSION 52
BIBLIOGRAPHY 55
vn
List of Figures
FIGURE 1. LEAKAGE POWER TRENDS - ITRS 2
FIGURE 2. SWITCHING CURRENT FLOW 6
FIGURE 3. SHORT-CIRCUIT CURRENT 6
FIGURE 4. NAND GATE IMPLEMENTATIONS IN DIFFERENT LOGIC FAMILIES 11
FIGURE 5. LEAKAGE CURRENT COMPARISON 13
FIGURE 6. XOR IMPLEMENTATIONS 14
FIGURE 7. SHORT-CIRCUIT CURRENT COMPARISON 15
FIGURE 8. SHORT-CIRCUIT CURRENT IN LEAP 16
FIGURE 9. SWITCHING CURRENT COMPARISON 17
FIGURE 10. INVERTER AND TRANSMISSION GATES SIZING 18
FIGURE 11. CAPACITANCE CALCULATIONS AT OUTPUT NODE 18
FIGURE 12. VOLTAGE DEVELOPED AT INTERMEDIATE NODE DUE TO SUBTHRESHOLD
CURRENT 19
FIGURE 14. DUAL VT CMOS CIRCUIT 22
FIGURE 15. SCHEMATIC OF VTCMOS CIRCUIT 22
FIGURE 16. TYPICAL SUBTHRESHOLD AND GATE LEAKAGE CURRENTS 24
FIGURE 17. SCHEMATIC OF A 4-INPUT CMOS NAND PULL-DOWN NETWORK 25
FIGURE 18. INTERMEDIATE NODE VOLTAGES BASED ON NUMBER OF OFF TRANSISTORS .26
FIGURE 19. SUBTHRESHOLD LEAKAGE DEPENDENCE ONV DROP AND ON CHANNEL
RESISTIVE DROP 27
FIGURE 20. TRANSISITOR SIZING FOR 4-INPUT NAND GATE 28
FIGURE 21. GATE CURRENT DRAWN BY TOP-MOST TRANSISTOR IN A STACK 28
FIGURE 22. GATE LEAKAGE CURRENT INCREASES THE NODE VOLTAGE 29
FIGURE 23. SUBTHRESHOLD LEAKAGE CURRENT ADDED TO GATE LEAKAGE CURRENT... 30
FIGURE 24. COMPARISON OF SUBTHRESHOLD AND TOTAL LEAKAGE CURRENTS 32
FIGURE 25. ISUB DEPENDENCE ON STATE OF BOTTOM TRANSISTOR IN THE STACK (T3) 34
Vlll
FIGURE 26. MINIMUM LEAKAGE VECTORS 35
FIGURE 27. TRANSISTOR STACKS 41
FIGURE 28. DTCMOS 43
FIGURE 29. LEAKAGE CURRENT AS A FUNCTION OF BODY BIAS 44
FIGURE 30. LEAKAGE CURRENT REDUCTION ACHIEVED BY VTCMOS 44
FIGURE 31. LEAKAGE CURRENT REDUCTION ACHIEVED BY INPUT PIN REORDERING 46
FIGURE 32. TOTAL LEAKAGE REDUCTION ACHIEVED BY INPUT PIN REORDERING 47
FIGURE 33. INPUT PIN REORDERING COMBINEDWITH DTCMOS 48
FIGURE 34. INPUT PIN REORDERING COMBINEDWITH VTCMOS 49
FIGURE 35. LEAKAGE REDUCTION ACHIEVED FOR ALL THE TECHNIQUES 50
IX
List of Tables
TABLE 1. SUBTHRESHOLD LEAKAGE FOR 2-INPUT NAND GATE 20
TABLE 2. SUBTHRESHOLD LEAKAGE CURRENTS FOR A 4-INPUT CMOS NAND GATE AT
45NMNODE 26
TABLE 3 . TOTAL LEAKAGE CURRENTS CATEGORIZED FOR 4-INPUT CMOS NAND GATE . 3 1
TABLE 4. TOTAL LEAKAGE CURRENTS FOR 4-INPUT CMOS NOR GATE 33
TABLE 5. INPUT PIN REORDERING 36
TABLE 6. STATISTICS FOR ISCAS89 BENCHMARK CIRCUITS 38
TABLE 7. LEAKAGE CURRENT REDUCTION ACHIEVED BY TRANSISTOR STACKS 40
TABLE 8 . VARIATIONS IN LEAKAGE REDUCTION IN TRANSISTOR STACKS 41
TABLE 9. LEAKAGE CURRENT REDUCTION ACHIEVED BY DTCMOS 43
TABLE 10. LEAKAGE CURRENT REDUCTION ACHIEVE BY VTCMOS 44
TABLE 1 1 . SUBTHRESHOLD AND GATE LEAKAGE CURRENTS BEFORE AND AFTER INPUT
PIN REORDERING 45
Glossary
Isub Subthreshold leakage current
Igate Gate-oxide leakage current
Vth Threshold voltage
VgS Gate-to-source voltage
vds Drain-to-source voltage
vDD Supply voltage
CMOS Complementary Metal Oxide Semiconductor
LEAP Single rail pass transistor logic
CPL Complementary pass logic
CMOS+ Single rail transmission gate logic
DPL Dual rail transmission gate logic
MTCMOS Multiple threshold CMOS
DTCMOS Dual threshold CMOS
VTCMOS Variable threshold CMOS
PUN
PDN
Pull-up network
Pull-down network
XI
Chapter 1 Introduction
Minimum feature size is scaling at a rate of 30% per technology generation to
reduce gate delay and power dissipation and increase transistor density [1]. With
technology scaling, there has been a corresponding scaling in supply voltage to maintain
proportionate electric fields ensuring normal mode of operation and to control power
dissipation. Scaling supply voltage is the most effective way of reducing dynamic power
dissipation since dynamic power has a quadratic dependence on supply voltage as shown
in the following equation
Pdyn (D
where /is the system clock frequency, Cioad is the load capacitance and Vbois the supply
voltage. ITRS (International Technology Roadmap for Semiconductors) studies have
shown that the supply voltage is approximately scaling at the rate of 30% per technology
generation [3]. Therefore, to maintain high drive current and delay performance, the
transistor threshold voltage has to be scaled accordingly (Eq. 2).
T ~
load
~
Qty _y
\load (2)
where fl is the device transconductance and V,i, is the threshold voltage. However, the
reduced threshold voltage causes a substantial increase in leakage current due to a weak
inversion state. This leakage mechanism is known as the subthreshold leakage current.
The dependence of subthreshold leakage on threshold voltage is further explained in
section 2.2.1. Reduced voltages also demand scaling of oxide thickness to maintain
sufficient transistor drive strength and reduce short channel effects [4,5,6]. Lower oxide
thicknesses mean higher electric fields across it and higher probability of electrons
tunneling through the oxide layer. This tunneling of electrons gives rise to the leakage
mechanism called gate tunneling leakage. ITRS (International Technology Roadmap for
Semiconductors) projects that the oxide thickness will be scaled down to as low as 1.6nm
by 2008 while utilizing silicon oxy-nitride for gate dielectric. Therefore, these two
leakage mechanisms namely, subthreshold and gate leakage have emerged as the
dominant leakage current mechanisms in deep sub-micron arena.
With each technology generation, leakage power has increased significantly and
has become comparable to dynamic power. With the ongoing trend in technology scaling,
it is anticipated that leakage power will become the dominant component in the total
power dissipation as depicted in Figure 1.
2001 2003
130nm
2005 2007 2009 2011 2013 2015 2017
90nm 65nm 45nm 32nm 22nm
Figure 1. Leakage Power Trends - ITRS [31]
Therefore, understanding the mechanisms of leakage current and its reduction is critical
for low power design. Leakage reduction can be achieved at either device level by
controlling various process parameters or at circuit level by controlling device terminal
voltages. This thesis is entirely devoted tocircuit level analysis and reduction of leakage
currents. The analysis of leakage currents and investigation of leakage reduction
techniques was divided in to the following steps.
Firstly, circuit level choices such as topologies and logic styles that impact power
dissipation are made. Parameters such as node capacitances, short-circuit currents,
number of transistors are strongly influenced by the chosen logic style. To understand the
impact of these parameters, we have chosen the following logic families: CMOS, single
and dual rail pass-transistor (LEAP, CPL), single and dual rail transmission gate logic
(CMOP+, DPL). Standard cells such as NAND, NOR, XOR, FA for the chosen logic
families were compared for static and dynamic power (total power dissipation).
Secondly, an evaluation of most of the prevailing leakage reduction techniques that target
subthreshold and gate leakage currents was performed. These techniques were
implemented on benchmark circuits [7] at 45nm and 32nm feature sizes. Previously,
these reduction techniques were implemented on technologies with feature sizes only
down to .18pm. However the leakage current characteristics may change at lower feature
sizes due to increased leakage currents. Therefore the efficiency of some leakage
techniques may not remain the same. The final part of this thesis consists of developing a
new algorithm based on the statistical data of interdependency of subthreshold and gate
leakage currents that will reduce the total leakage current by application of appropriate
input vectors and input pin reordering. The interdependency is a result of high growth
rate of gate leakage current at sub-lOOnm regime. Significant Igate (gate leakage current)
flowing through the circuit may affect Isub (subthreshold current) by changing the
intermediate node voltages making Isub and Igate interdependent. From preliminary
simulations, it could be inferred that this interdependency can be exploited to reduce total
leakage current thus making it an important property. This newly developed leakage
reduction technique was compared against the existing leakage reduction techniques to
measure its effectiveness.
Chapter 2 Sources of Power Dissipation
There are two sources of power dissipation in digital CMOS circuits: 1) Active
power and 2) Static power. Active power can be further classified into 1) Switching
power and 2) Short-circuit power. Switching power dissipation basically occurs due to
charging and discharging of capacitive nodes as a result of signal transitions at those
nodes. Short-circuit power dissipation occurs when there is a direct path from supply to
the ground terminal. This happens when the pull-up network and pull-down network
conduct simultaneously due to non-zero input rise and fall times. Together, switching and
short-circuit power comprise of active power because they only occur when the circuit is
in active mode of operation. The third source of power dissipation is called static power
dissipation which is comprised of leakage currents that flow when the input signals are
stable. In this chapter, the different sources of power dissipation in CMOS circuits are
discussed in detail.
2. 1. Active Power
2.1.1 Switching Power
Switching power dissipation occurs due to charging and discharging of capacitive nodes.
Consider an inverter stage with load capacitance Ci which is composed of intrinsic
capacitance of the transistors and input capacitance of next stage (Figure 2). With a'0'
input, CL gets charged through PMOS transistor and its voltage rises to VDD. When the
input switches to T, the capacitor discharges via the NMOS transistor to the ground.
Therefore a cycle of'0'
and'1'
inputs effectively creates a path from supply to the
ground for the current to flow.
5
vDD
00 i\ZV0Ut
^
p V0UT = 1 I p Vqut = 0
(a) (b) (c)
Figure 2. Switching currentflow (a) Schematic of inverter (b) Charging circuit (b) Discharging circuit
Switching power depends on switching frequency. A circuit with high switching
frequency incurs higher power dissipation than when the circuit with lower switching
frequency. It is also proportional to the square of the supply voltage and the capacitances
of circuit nodes. Higher capacitance leads to higher switching power dissipation.
Switching power dissipation is given as
Poc=aCoulVDD2f (3)
where a represents the probability that an output 0 to 1 transition takes place during one
period, Cout is output capacitance, Vdd is supply voltage and/is the switching frequency.
2.1.2 Short-circuit Power
Short-circuit power dissipation occurs due to non-zero rise and fall times of the
input waves driving the gate. There always exists a slope in the input wave when
transitioning from high to low and vice-versa due to the input capacitance of a gate.
During this short period of time, there exists a direct path between the supply rails when
both PMOS and NMOS devices conduct simultaneously. Consider an inverter stage as
shown in Figure 3.
v
-v vDD-vUl
v
I,
/ \ V.
tpeak
Figure 3. Short-circuit current
6
NMOS transistor turns ON when it's Vgs (=Vin) is greater than Vth. PMOS transistor turns
ON when it's Vsg (=VDD-Vin) is greater than|vj . Therefore, short-circuit current flows
when the input signal voltage is between Vth and VDD-Vth. The short-circuit power is
therefore dependent on rise and fall times of the input signal. It is also dependent on the
switching frequency since short-circuit power dissipation occurs only during signal
transitions. Short-circuit power dissipation is given as
Psc=tSCVDDIpeakf (4)
where tsc represents the time for which both devices are conducting, Ipeak is the short-
circuit current and/is the switching frequency.
2.2. Static Power
Static power dissipation occurs in static mode of operation as mentioned earlier.
However, it can also occur in active mode of operation due to the presence of idle
circuits. This static power is smaller when compared to that in static mode.
2.2.1 Subthreshold Leakage
Subthreshold current is the leakage current that exists when gate-to-source voltage
is less than threshold voltage. When the gate voltage is less than the threshold voltage, a
weak inversion state exists between source and drain. Any potential difference between
the drain and source terminals manifests as the voltage drop across the drain-to-substrate
depletion region. There is barely any potential drop along the channel and so the carriers
move by diffusion as opposed to drift. The subthreshold current is exponentially
dependent on Vgs (gate-to-source voltage), Vds (drain-to-source voltage) and V!h (threshold
voltage) as shown by the following equation for subthreshold current according to
BSIM4 model
hub Mo^o
fW\K-v,)
\Lj
v,,\
l-eVT
(5){m-l){vTfe^
J
where p0 is the carrier mobility, Cox is the oxide capacitance, W and L are width and
length of the gate, m is the body-effect coefficient and vT is the thermal coefficient.
Subthreshold current increases exponentially with increasing Vgs or decreasing Vth-
2.2.2 Gate Leakage
Gate oxide thickness has reduced along with supply voltage to maintain sufficient
current drive strength and reduce short channel effects. This leads to higher electrical
fields across the oxide layer and therefore an increase in the probability of electrons
tunneling through the oxide layer from the channel region into the gate and vice-versa.
This tunneling of electrons gives rise to a leakage current mechanism called gate
tunneling current. The equation for gate tunneling current according BSLM4 model is
shown below
Iga,e=WLSDEAsvDD
Texp
B.
-i\
vi
vDD
0To.
VDD
(6)
V J
where LSDe is the source-drain-extension length, <pox is the barrier height of tunneling
electron/hole, Ag and Bg are process related physical parameters and Tox is the oxide
thickness. It can be seen that the gate leakage current increases exponentially as the oxide
thickness decreases. It is also exponentially dependent on the supply voltage.
8
As described in chapter 1, subthreshold and gate leakage currents are the
significant components of static power dissipation in CMOS circuits. Therefore, the
remainder of this thesis concentrates on analyzing and optimizing these two leakage
currents.
Chapter 3 Leakage Reduction Techniques
3. 1. Introduction
The total power dissipation in CMOS circuits is a sum of active and static power
dissipation. When the circuit is in standby mode, the total power dissipation is a result of
static power only. However, with rapid scaling of technology, static power dissipated in
active mode of operation from idle circuits is increasing too. Therefore, it is necessary to
reduce the static power dissipation to achieve overall savings in total power dissipation.
Static power reduction techniques can be implemented at different levels of design
abstraction. At the device level, process parameters such as channel length, oxide
thickness and doping profile can be controlled. At circuit level, factors such as voltages at
transistor terminals, size of the transistors and choice of logic family can be controlled.
This thesis concentrates on analysis and reduction of leakage currents only in static mode
of operation. The leakage reduction techniques considered are circuit level techniques.
3.2. Low Power Logic Family
To implement a logic function, a number of topologies are available such as pass
transistor vs. CMOS logic and static vs. dynamic circuits. Parameters such as node
capacitances, short-circuit currents, number of transistors, are strongly influenced by the
chosen logic style. To understand the impact of these parameters on power dissipation,
we have chosen the following logic families: CMOS, single and dual rail pass-transistor
(LEAP and CPL), single and dual rail transmission gate logic (CMOS+ and DPL).
Standard cells such as NAND, NOR, XOR, FA for the chosen logic families is compared
10
for static and switching power (total power dissipation). As an example, NAND gate
implementations for all logic families are shown in Figure 4.
A A
S\.
J~~l
b-TL
a n
^H
^
(b)
(a)
-i>-o
-D>-o
_TL
_r
J~L
>
i^L o
(c)
^H
-Bja
-r>-o
-O-o
(d)
4n"H>i -t>-0
(e)
Figure 4. NAND gate implementations in different logicfamilies
(a) CMOS (b) CPL (c) LEAP (d) DPL (e) CMOS+
CMOS circuits have both NMOS and PMOS devices. The PMOS devices
implement the pull-up network while the NMOS devices implement the pull-down
network. In steady state there always exists a direct path from output to either the power
supply or ground. Thus the output is always a well-defined high or low voltage. Output
11
logic levels are independent of transistor sizes and hence this logic is called ratioless
logic. Figure 4(a) shows a NAND gate implemented using CMOS logic. The rest of the
logic families use pass transistors and transmission gates wherein the source of the
transistors are connected to input signals as opposed to power lines in CMOS logic.
Single rail pass transistor logic NAND gate (Figure 4(c)) uses only one type of device
(NMOS or PMOS) to perform the logic operation (requiring fewer transistors). NMOS
pass transistors are preferred to PMOS since NMOS ON resistance is smaller than that of
PMOS for the same width. However, NMOS devices cannot pass a strong logic T as
they exhibit a Vth drop. Therefore, level restoration circuit is added at the output to
overcome this problem. This restoration is realized by a pull-up PMOS transistor.
Inverters are added at the output to achieve better driving capabilities. These circuits
must have a multiplexer like structure because at any given time, there must exist only
one path from an input to an output (to avoid the inputs being shorted). Complementary
signals are required to implement these structures therefore requiring the use of inverters.
Dual-rail pass transistor logic (Figure 4(b)) provides all signals in complementary form.
However, two MOS networks are required to produce complementary output signals thus
annulling the advantage of fewer transistors. LEAP and CPL logic families fall under the
ratioed logic where output voltage levels depend on the relative sizing of transistors.
Single and dual rail transmission gate logic families (Figure 4(d,e)) are equivalent to pass
transistor logic families but use transmission gates instead of pass transistors. Since a
pass transistor is made of NMOS and PMOS devices connected in parallel, output signals
have full rail-to-rail swing. No level restoration circuitry is needed.
12
The next three sections show the active and static power simulation results for
NAND, NOR, XOR and full adder gates implemented in all the five logic families. All
simulations were performed using BSLM4 technology model for 45nm feature size [24].
Leakage currents were measured using Nanosim which provides a detailed distribution of
total power dissipation thus making it a suitable tool for power analysis.
3.2.1 Leakage Current
While measuring leakage currents, it is assumed that all inputs have an equal
probability of occurring. Therefore average leakage current is calculated by averaging the
leakage current over all possible input combinations. Figure 5 shows the average leakage
currents of NAND, NOR, XOR and full adder gates for all the logic families. The bars
for CPL and DPL (logic families with complementary outputs) have a different color.
NAND NOR
CMOS CPL LEAP DPL CMOSP CMOS CPL LEAP DPL CMOSP
XOR Full Adder
0.08
0.07
?0.06
3. 0.05
| 0.04
| 0.03
O 0.02
0.01
0MCMOS CPL LEAP DPL CMOSP
0.35
0.3
< 0.25
r 0.2
I 0.15
O 0.1
0.05
0IzE
CMOS CPL LEAP DPL CMOSP
Figure 5. Leakage current comparison
In case of CMOS NAND gate, highest leakage current occurs when inputs (1,1)
are applied since the PMOS transistors leak in parallel. If"Is"
is the subthreshold leakage
13
current in a stack of single OFF transistor, then leakage current for (1,1) inputs is 2%.
Least leakage current occurs for the case of (0,0) inputs due to stack effect. Stack effect is
a phenomenon where a stack of two series connected OFF transistors show significantly
less subthreshold current than in a single OFF transistor [8]. Stack effect is further
explained in section 3.3. For CPL NAND gate, highest leakage of 5*7, occurs for
(1,0)/(0,1) inputs and lowest leakage of 3*IS occurs for (0,0)/(l,l) inputs. For DPL
NAND gate, highest leakage of 6*IS occurs for (1,0)/(0,1) inputs and lowest leakage of
2*IS occurs for (l,l)/(0,0) inputs.
CMOS logic gates have lower average leakage currents compared to the rest of
the logic families. This is because only CMOS logic gates have transistor stacks resulting
in reduced leakage currents due to stack effect. Leap and CPL draw extra leakage current
through level-restoring and output-driving circuitry. Since CPL has two networks
implementing complementary outputs, it exhibits higher leakage than LEAP. DPL and
CMOS+ draw higher leakage currents than CMOS due to higher number of transistors
and output-driving circuitry. However, in the case of XOR gates, LEAP and CMOS+
logic gates draw equal or lower leakage currents than CMOS logic due to their efficient
MUX like implementations. LEAP and CMOS+ XOR gates are constructed from 5 and 8
transistors respectively while CMOS logic is constructed from 12 transistors (Figure 6).
hC^ElbHI
->-
?
HrinP
C^o
s
(a) (b)
Figure 6. Xor implementations (a) CMOS (b) CMOS+
14
Average leakage currents for full adder gate in different logic families is shown in Figure
5. CMOS full adder draws least leakage current compared to other logic families due to
the same reason that it has transistor stacks present in it. Therefore, CMOS logic family
was chosen for characterization and optimization of leakage currents. It must be noted
that leakage currents for CMOS+ is higher that that of CPL even when CPL has higher
number of transistors than CMOS+. Therefore, leakage currents do not entirely depend
on the number of transistors present in the circuit.
3.2.2 Short-Circuit Current
Short-circuit currents for all the logic families in NAND, NOR, XOR and full
adder gates are shown in Figure 7.
NAND NOR
0.12
0.1
0.08
30<M
0.02 fl-lnCMOS CPL LEAP DPL CMOSP
XOR
0.16
0.14
?0.12
3. 0.1
| 0.08
g 0.06
O 0.04
0.02
0In
0.07
0.06
< 0.05
^ 0.04
| 0.03
O 0.02
0.01
0
0.6
0.5
f 0.4
| 0.3
I 0.2O
0.1
LLLLICMOS CPL LEAP DPL CMOSP
Full Adder
:QJCMOS CPL LEAP DPL CMOSP CMOS CPL LEAP DPL CMOSP
Figure 7. Short-circuit current comparison
These currents are obtained from a transient analysis over an exhaustive set of inputs. As
outlined in the section 2.1.2, short-circuit current depends on rise and fall times of the
input signals which in turn depends on the capacitance of the gate. As seen from Figure 7,
CMOS logic shows least short-circuit current compared to the rest of the logic families.
15
In CMOS logic there never exists a direct path from supply to the ground during steady
state. The output node is either pulled up to the supply voltage or pulled to ground at a
single time. The short-circuit current is drawn only during switching when both pull-up
and pull-down paths conduct during the short period of rise or fall times. CPL and LEAP
show the highest short-circuit leakage currents because there exists competing signals in
the swing restoration circuitry trying to pull up a node to supply voltage and pull down to
ground simultaneously. Consider a LEAP NAND gate with inputs (1,1) as shown in
Figure 8(a).
A(l)
B(l) B(0)
_L
_r~L
>
xJ~L
X(l)
0^-
B(0) B(l)
_L
a(d-T~L
Xrr
t
(a) (b)
>*-
Figure 8. Short-circuit current in LEAP (a) Node X is at logic high (b) Contention at node X
Node X is at logic high. Now if input B makes a high to low transition then there would
be competing signals trying to pull node X to VDD and ground. During this period of
time, short-circuit current is drawn since there exists a direct path from supply to the
ground. With proper transistor sizing, node X can be brought to a logic low.
CMOS+ and DPL exhibit higher short-circuit current than CMOS and lower than
CPL and LEAP. Since circuits implemented in CMOS+ and DPL logic have higher
number of transistors, they include high capacitive nodes in them. Therefore more time is
required to charge up these high capacitive nodes resulting in higher rise and fall times.
This results in higher short-circuit currents.
16
3.2.3 Switching Current
Switching currents for all the logic families in NAND, NOR, XOR and full adder
gates (Figure 9) are obtained from transient analysis over an exhaustive set of inputs.
NAND NOR
=" 0.15
= 0.1
<J 0.05
0.12
0.1
3.08
| 0.06
0.04
0.02
0
O mCMOS CPL LEAP DPL CMOSP
Full Adder
0.25
0.2
r 0.15
I 0.13
o0.05
0
llnln
1.6
1.4
3. 1
I 0-8
t 0.6
O 0.4
0.2 4
0 ElCMOS CPL LEAP DPL CMOSP CMOS CPL LEAP DPL CMOSP
Figure 9. Switching Current Comparison
As mentioned in section 2.1.1, switching power dissipation occurs due to charging and
discharging of capacitive nodes and is therefore proportional to the capacitance of the
nodes. Figure 11 shows the capacitances of output nodes of NAND gates for all the logic
families. The total capacitance is the sum of drain and gate capacitances. CD and Cg
represent the drain and gate capacitances of a minimum sized transistor with width and
length of unit feature size. Since these capacitances are directly proportional to the width
of the transistor, the drain capacitance of a transistor with width of V is n*CD and gate
capacitance is n*CG. The sizing of inverters andtransmission gates used in different logic
families is shown in Figure 10. The total capacitance calculations are shown in Figure 11.
17
<
Figure 10. Inverter and Transmission gates sizing
CTotai = 2(3Cdp) + 4Cdn + 6Cgp + 4Cqn
= 6CDP + 4CDN + 6CGp + 4CGn
-1?
3
_J~L
3 _L
TL3
3
_TL
3
3h
^
^h
."^
CTotai = 2Cdp + 2(2Cdn) + 6Cgp + 4Cgn
= 2CDP + 4CDN + 6CGP + 4CGN
i>-
C = 2(2CDN) + 2CDP + 2CGP + 6CGP + 4CGN
CTotai = 2C = 4Cdp + 8Cqn + 16Cgp + 8Cgn
T>-
-E3-1
:^>-
>4>-
C = 2(3CDP) + 2(2CDN) + 6CGP + 4CGN
Cjotai - 2C = 12Cdp + 8Cqn + 12Cgp + 8Cqn
Cxotai = 2(3CDP) + 2(2CDN) + 6CGP + 4CGN
= 6CDp + 4CDN + 6CGp + 4CGN
Figure 11. Capacitance calculations at output node
18
It is seen from the Figure 1 1 that DPL and CPL logic families have high capacitive nodes
due to higher number of transistors. However, they also provide complementary output
signals. This is followed by CMOS+, CMOS and LEAP logic families. Simulation results
for NAND and NOR gates (Figure 9) follow this pattern. However, in the case of XOR
gate, the pass transistor and transmission gate logic families show lower switching
currents than CMOS because of their efficientMUX like implementations.
On the whole, CMOS logic family has shown better current dissipation results
than the rest of the logic families. Therefore, the rest of the thesis work will be
concentrating on CMOS logic family only. The next three sections will focus on leakage
reduction techniques for CMOS logic family.
3.3. Transistor stacks
Stack effect is a phenomenon where Isub flowing through a stack of series
connected transistors reduces when more than one transistor of the stack is turned off. For
example, a stack of two series connected OFF transistors is shown in Figure 12.
vDD
Figure 12. Voltage developed at intermediate node due to subthreshold current
A small potential V, is developed at the intermediate node between the two transistors as
a result of subthreshold current flowing through the series connected transistors. This
potential developed results in the following:
19
Reduced Vgs
Reduced Vds
Body effect (higher source-to-bulk voltage)
The reduced Vgs, Vds voltages and body effect result in reduced subthreshold current. It is
shown that the leakage of a two-transistor stack is an order of magnitude less than the
leakage in a single transistor [9]. As a result of stack effect, subthreshold leakage current
becomes dependent on the state of input vector. Subthreshold current values for a two
input NAND gate for all the input vectors are shown in the Table 1.
A B Subthreshold leakage currents (nA)1 1 17.26
0 1 17.4
1 0 6.45
0 0 0.876
Table 1. Subthreshold leakagefor 2-input NAND gate
Many algorithms have been proposed in pursuit of finding the input vectors that result in
least subthreshold current. The easiest way of finding minimum leakage vector is to
measure the leakage current for all possible input combinations. For an n-input vector,
there are2n
combinations of input vectors thus limiting the feasibility of this algorithm
only to circuits with small number of inputs. For circuits with larger number of inputs, a
random-search based technique was proposed in [10]. In this technique, leakage currents
are evaluated for a large number of random inputs and vectors giving minimal leakage
currents are monitored. A more efficient way of finding minimum leakage vectors which
employs a genetic algorithm was proposed in [11]. This technique exploits historical
information to speculate new search points with expected improved performance to find
near-optimal solution.
20
Since stacking results in a significantly reduced subthreshold current, this effect
can be utilized by forcing stack effect (by adding an extra transistor in the stack) to high
leakage gates. These stack transistors must be switched ON during active mode of
operation to avoid affecting the functionality of the circuit. However, introduction of
stack transistors results in reduced drive current and therefore degrading the delay
performance. The authors in [12] proposed that additional series stack transistors must be
added only in non-critical paths to maintain the overall delay performance of the circuit.
Usually a significant fraction of the devices can be forced-stack since a large number of
the paths are non-critical thus reducing the overall leakage power of the chip without
impacting operating clock frequency. The authors in [13] have developed a leakage
control insertion algorithm that provides a structured approach to inserting stack
transistors only in non-critical high-leakage paths and satisfying the slack conditions.
This algorithm makes an assumption that the size of the stack transistors is 30% of the
sum of the widths of transistors connected to power or ground.
3.4. Dual Threshold CMOS (DTCMOS)
DTCMOS leakage reduction technique utilizes the dependence of delay
performance of a transistor on its threshold voltage. It proposes that higher threshold
voltages can be assigned to transistors in non-critical paths so as to reduce leakage
current, while delay performance is maintained due to the use of low threshold transistors
in critical paths [16,17]. Unlike MTCMOS technique, no additional transistors are
required, leaving the delay performance unaffected while achieving low leakage results.
Moreover, this technique is good for leakage power reduction even in active mode of
operation. Not all the transistors in non-critical paths can be assigned high-threshold
21
voltages as this may result in the critical path being changed. The authors in [17]
proposed a Breadth-First Search (BFS) based algorithm for selecting and assigning an
optimal high Vth. BFS is used to explore every node of the circuit to check its slack.
Whether a node should be assigned to a high threshold depends on whether its slack is
still positive.
>Critical path Non-critical path Low Vth
o
High Vth
Figure 13. Dual V, CMOS circuit
3.5. Variable Threshold CMOS (VTCMOS)
VTCMOS technique involves achieving different threshold voltages by body-
biasing which was proposed in [18]. A body-bias circuit is used to control the source-to-
bulk voltage to achieve different threshold voltages as shown in Figure 14.
standby
active
VBP !
V,
active
standby
Figure 14. Schematic of VTCMOS circuit
In active mode, no body bias is applied while in standby mode the source-to-body
junction is reverse biased to increase the threshold voltage which reduces leakage current.
22
Chapter 4 Subthreshold and Gate Leakage Characteristics
In this chapter, an extensive analysis of circuit level characteristics of
subthreshold and gate leakage current is performed. Different scenarios that affect the
two leakage currents such as device terminal voltages, number of OFF transistors in a
stack and position of transistors are identified and analyzed. Emphasis is laid on the study
of interaction between the two leakage currents. Finally a new leakage reduction
technique is proposed that reduces both subthreshold and gate leakage currents based on
the analysis performed.
Significant Igate flowing through the circuit may affect ISUb by changing the
intermediate node voltages. In such cases, Isub and Igate become interdependent. Previous
studies concentrated on finding minimum leakage vectors to reduce ISUb [21,22].
However, they may not be applicable when Igate is considered along with Isub. In [23], the
authors examined the interdependence between Isub and Igate. However, Igate in PMOS
transistors and reverse Igate in OFF transistors was considered negligible. This fact does
not hold true for 45nm and 32nm technologies. As an example, the typical values of Isub
and Igate for an inverter with equal sized PMOS and NMOS devices at 45nm and 32nm
technology node are shown in Figure 15. Igate in the OFF NMOS transistor is comparable
to that in the ON NMOS transistor. However, Igate in PMOS transistors is relatively less
than in NMOS transistors and can be safely ignored.
23
Igate=2.77 pA
Isub=5.495 nA
Ieate=1.048nA
(a) 45r
Igate=5.56pA
8.49 nA
(b) 45nm
Igate=6 pA
Isub=18.8 nA
lgate=L05 nA
(c) 32nm
Igate=12pA
Lh=19.2 nA
=0.31 nA-=
(d) 32nm
Figure 15. Typical subthreshold and gate leakage currents
(a,c) Logic high input (b,d) Logic low input
In order to analyze the interdependence, representative CMOS combinational
logic blocks (NAND and NOR) and a sequential block (D flip-flop) have been chosen.
The NMOS and PMOS devices are sized for symmetrical DC and transient response.
However, the analysis holds true for minimum sized transistors too. The following steps
were used to break down the analysis 1) analysis of leakage current considering only Isub
and 2) analysis of interdependence between Isub and Igate.
4. 1. 4-Input CMOS NAND Leakage Analysis
In this section we perform leakage analysis for a 4-input NAND gate by dividing
it into two case studies. Case study I evaluates leakage current accounting only for Isub.
Case study II includes Igate to understand the interdependence between Isub and Igate. All
simulations were performed using BSIM4 technology model for 45nm feature size [24].
24
4.1.1 Case Study -1
The behavior of Isub can be visualized better by considering the pull-down
network of the 4-input NAND gate (Figure 16). Let TO, Tl, T2 and T3 be the transistors
in the stack from the output node to ground. Leakage results for all possible input
combinations are shown in Table 2. The entries are arranged in increasing order of the
leakage currents and are also categorized based on the number of OFF transistors.
Figure 16. Schematic ofa 4-input CMOS NAND pull-down network
The following observations were made for Isub
1) The higher the number of OFF transistors, the lower the subthreshold leakage current.
This pattern is a result of stack effect where two stacked OFF devices show significantly
reduced Isub compared to a single OFF device [25,26] and is determined by the transistor
with the highest negative Vgs [27]. Turning OFF more transistors in the stack raises the
stack's internal voltage as shown in Figure 17 for input vectors (0,0,1,1) and (0,0,0,1). In
the first case, TO and Tl are switched OFF and the voltage at the node between the two
transistors is 0.106V. In the second case where T2 is switched off, the voltage at the same
node is 0.127V which is higher than the first case and hence it has an increased stack
effect.
25
A B C D Isub (nA)4 OFF Transistors
0 0 0 0 0.296
3 OFF Transistors
10 0 0 0.4
0 0 0 1 0.413
0 0 10 0.413
0 10 0 0.413
2 OFF Transistors
110 0 0.798
10 0 1 0.809
10 10 0.809
0 0 11 0.879
0 10 1 0.879
0 110 0.879
1 OFF Transistor
1110 10.924
110 1 11.617
10 11 13.285
0 111 35.808
0 OFF Transistors
1111 34.319
Table 2. Subthreshold leakage currents for a 4-input CMOS NAND gate at 45nm node
Vr
PUN
o-
iE TO
0.
HC Tl
i HC T2
i C T3
Vout - VDD Vqut - VDD
0.127 V
0.0237 V
(a) (b)
Figure 17. Intermediate node voltages based on number ofOFF transistors
(a) (0,0,U) (b) (0,0,0,1)
26
2) For a fixed number of OFF transistors in the stack, the Isub varies based on whether the
top transistor in a stack is ON, since this would cause a Vtn drop across it and reduce Vds
of the OFF transistors below the ON transistor. This effect is predominant in cases with a
single OFF transistor. Among these cases, the input combination (0,1,1,1) has the highest
Isub because V^ across the top transistor nearly equals Vdd- For all other input patterns,
Isub is smaller because of the Vth drop across the top transistor. For (1,1,0,1) and (1,1,1,0)
input combinations, the Vdi across the OFF transistor is less due to the channel resistive
drop across the ON transistors in addition to the Vti, drop as depicted in Figure 18.
Therefore as the position of the OFF transistor goes down in a stack, Isub gets smaller
because of more ON channel resistive drops.
PUN PUN
Vqut _ ^DD
PUN
V0ut - Vqd
HI
'
Vqut - Vdd
0.761 V
0 HP TO HL TO 1 -| I TO
~J- 0.067 mVH- 0.756 V ~~J- 0.759 V
1 HL Tl HLti HLti3~
0.045 mV~}~ 0.016 mV ~J- 0.723 V j 0.72:- \
1 HL T2 HLT2 0-jrT2 1HLT2|-
0.022 mV~J- 0.008 mV "J- 0.007 mV
{- 0.70s V
1 HL T3 !HLt3 HLT3 HL 13
Vm>T = VOUT- v DD
(a) (b) (c) (d)
Figure 18. Subthreshold leakage dependence on V,h drop and ON channel resistive drop
(a) (0,1,1,1) (b) (1,0,1,1) (c) (1,1,0,1) (d) (1,1,1,0)
3) When (1,1,1,1) and (0,1,1,1) inputs are considered,the former input has all the PMOS
transistors leaking in parallel and summing up while the later input has only a single
NMOS transistor leaking. However, leakage current for (0,1,1,1) input is higher than
(1,1,1,1) input. This is because ISUb depends on the size of the transistor (from Eq. 5). As
mentioned previously, the NMOS and PMOS transistors are sized for symmetrical
27
transient and DC response as shown in Figure 19. This is not true for minimum-sized
transistors wherein (1,1,1,1) input results in highest leakage current.
Vdd
t
HCJ3 Hg^L3~HT
Figure 19. Transisitor sizingfor 4-input NAND gate
4.1.2 Case Study -2
In this study, the interdependence between Isub and Igate is considered. The leakage results
for all possible input combinations were obtained and were found to be predominantly
dependent on following three factors which are explained below.
1) Igate in the top-most transistor:
Late depends strongly on Vgs and Vgd voltages of the device as shown in the case of
inverter in Figure 15.
vDD vDD
t
PUN PUN
Vqut - Vdd
'5
Vqut - Vdd
PDN
5PDN
(a) (b)
Figure 20. Gate current drawn by top-most transistor in a stack
(a) Logic high input (b) Logic low input
28
Maximum Igate is observed when input is logic high and Vgs and Vgd of the NMOS device
is VDD. Using the same principle, reverse Igate is drawn when the top-most transistor of the
stack is switched OFF because of high negative Vgd voltage as shown in Figure 20. For a
stack with two or more OFF transistors, this particular reverse Igate component is the
dominant leakage component drawn from the supply rail.
2) Isub replaced by Igate:
In cases where there is at least one non-conducting transistor above and below a
conducting transistor, Igate replaces Isub. This is depicted in Figure 21 where a potential of
0.106V is developed at the node between TO and Tl due to Isub flowing through TO. The
voltage developed is sufficiently small for transistor Tl to exhibit Igate from its gate to
drain. Igate further increases the voltage at the node to 0.2V. This increase in voltage
reduces Isub through TO and also reduces Igate. But the dependence of Isub on Vgs is stronger
than the dependence of Igate on Vgd [23]. Thus, Igate displaces Isub and remains as the only
leakage component in the stack. This was also observed in [23].
Vqut - Vdd
0.106 V i
Vqut - Vdd
0.2 V
(a) (b)
Figure 21. Gate leakage current increases the node voltage between TO and Tl reducing subthreshold leakage
current (a) voltage of0.106 is developed due to subthresholdleakage (b) voltage raised to 0.2 due to gate leakage
29
3) Isub added to Igate:
Figure 22 illustrates the case where Isub is added to Igate. Since the node between TO and
Tl is connected to the ground via ON transistors, it remains at ground potential. The two
leakage currents do not affect the voltage at that particular node and are therefore not
interdependent but simply add up. This was also observed in [23]. The leakage results are
tabulated in ascending order and also grouped into five different categories based on the
factors explained as shown in Table 3. As mentioned earlier, for cases when two or more
transistors are OFF or when there is stack effect, Igate dominates ISUb and determines the
order of the table entries. Therefore the first four input combinations which have the top
most transistors ON, not drawing Igate from supply voltage (or drain node) to gate node,
are in the top of the table. The next seven input combinations have their top-most
transistors switched OFF, resulting in Igate flowing from the supply voltage to the gate
node.
PUN
Vout - Vdd
o HLto,I 35.78 nA
4.58 nA
Figure 22. Subthreshold leakage current added to gate leakage current
1) "No Igate drawn; Isub has only one input combination which draws the least
current from the power supply. This is because TO has no gate leakage and the gate
current of T2 replaces Isub of Tl. Therefore, effectively no current is drawn from the
supply. The only current reaching the ground isthe gate current from the gate of T2.
30
ABCD Leakage current drawn from supply (nA)
Igate not drawn; lsub replaced
1010 0.533
Igate not drawn; Stack effect
1000 0.873
1100 1.164
1001 1.251
Igate drawn; lsub replaced
0100 1.273
0110 1.276
0010 1.282
0101 1.302
lgate drawn; Stack effect
0000 1.544
0001 1.687
0011 2.151
No stack effect; lsub dominates
1110 11.09
1101 11.816
1011 13.546
0111 37.064
1111 34.314
Table 3. Total leakage currents categorizedfor 4-input CMOS NAND gate
2) "No Igate drawn; Stackeffect"
has three input combinations. Transistor TO being ON
does not draw any gate current from supply voltage. Because there are two or more OFF
transistors, low Isub flows due to stack effect.
3) "Igate drawn; ISUbreplaced"
has four input combinations. In these combinations,
transistor TO is switched OFF and therefore draws Igate from the power supply. Isub is
replaced because there is at least one non-conducting transistor above and below a
conducting transistor as describedpreviously.
4) "Igate drawn; Stackeffect"
has three input combinations. Similar to the previous
category, Igate is drawn from the power supply to the gate of transistor TO. Because there
are two or more OFF transistors, low Isub flows due to stack effect.
31
5) The last category has no stack effect making Isub the dominant leakage mechanism.
The pattern inside this category is because of the Vth drop plus ON channel resistive drop
as explained in section 4.1.1.
Thus, the top-most transistor in a stack plays an important role in deciding minimum
leakage vectors. It is also shown that minimum leakage vectors for the case of ISUb are not
the same when Igate is considered along with Isub. Figure 23 shows a comparison between
Isub values from case study 1 and total leakage values from case study 2. The y-axis of the
graph is scaled non-uniformly for a better display of leakage results.
*
35
JO :
=. 20 :
w ID
3 *. .
0> 4 |
LS
1
0.5
0
Total leakage
less than
subthreshold
leakage
v j
i 1 _I
is \
6- 5- a-
V V V
Input Combinations
n Subthreshold leakage b Total Leakage
Figure 23. Comparison ofsubthreshold and total leakage currents
It can be seen from the graph that for the input vector (1,0,1,0) the total leakage current is
less than the case when only Isub is considered. As explained earlier, for this input
combination neither Isub nor Igate is drawn from the power supply. Therefore, by utilizing
the interdependence between Isub and Igate, it is possible to reduce the total leakage current
beyond when only Isub is considered.
32
4.2. 4-Input CMOS NOR Leakage Analysis
Since Igate in PMOS devices is negligible as shown in the case of the inverter in
Figure 16, the total leakage current for a NOR gate is determined by Isub. Therefore, the
analysis would be similar to that of the NAND gate in case study I. NOR gate shows
similar dependence between the number of OFF transistors and Isub (or total leakage
current) as in NAND gate (Table 4).
A B C D Leakage current drawn from supply (nA)
4 OFF Transistors
1111 0.09
3 OFF Transistors
1110 0.143
110 1 0.149
10 11 0.162
0 111 0.184
2 OFF Transistors
110 0 0.324
10 10 0.334
0 110 0.367
10 0 1 0.375
0 10 1 0.408
0 0 11 0.442
1 OFF Transistor
10 0 0 7.696
0 10 0 8.433
0 0 10 10.28
0 0 0 1 36.282
0 OFF Transistors
0 0 0 0 34.075
Table 4. Total leakage currents for 4-input CMOS NOR gate
The higher the number of OFF transistors, the lower is the Isub because of stack effect. In
case of the NAND gate, for a fixed number of OFF transistors, Isub depends on whether
the first transistor in the stack is ON, since this would cause a Vth drop across it. For the
NOR gate, ISUb depends on whether the bottom transistor of the stack is ON, since the
inability of the PMOS device to pass a perfect zero reduces the Vds of the OFF transistors
above it. This effect is predominant in cases with a single OFF transistor as depicted in
33
Figure 24. The input combination (0,0,0,1) has the highest Isub since Vds across the
switched OFF transistor nearly equals VDD. For all other input combinations Isllb is lower
due to the inability of the bottom transistor to pass a perfect zero. In addition, for
(1,0,0,0) and (0,1,0,0) input combinations, Vds across the OFF transistor is less due to the
voltage developed as a result of ON channel resistance of the transistors below it.
Therefore, as the position of the OFF transistor goes up in a stack, Isub gets smaller.
0.3 V
0.281 v
0.238 V
Vn,rr = 0
0.999 V
0.284 V
0.24 V
Vn,iT = 0
0.999 V
0.999 V
0.246 V
0.999 V
0.999 V
0.999 V
VnT = 0
PDN
(a) (b) (c) (d)
Figure 24. lsub dependence on state ofbottom transistor in the stack (T3)
(a) (1,0,0,0) (b) (0,1,0,0) (c) (0,0,1,0) (d) (0,0,0,1)
4.3. New Leakage Reduction Technique
The categories described in NAND and NOR gate leakage analysis can be used in
predicting minimum leakage vectors for stacks with variable number of transistors,
considering bothsubthreshold and gate leakage currents.
For a stack of NMOS transistors, the following sequence of steps demonstrates a
structured approach to finding minimum leakage vectors.
1) The first step is to reduce Isub by turning off at least two transistors in the stack
thereby inducing stack effect.
34
2) With more than two transistors in the stack, the uppermost transistor must be turned
ON, as this would avoid drawing Igate from the supply voltage.
3) With more than three transistors in the stack, another transistor must be turned ON
such that is has at least one non-conducting transistor above and below it so that the
Igate of this ON transistor replaces Isub as described in section 4.1.2. The minimum
leakage vectors for a stack of two, three and four transistors are shown in Figure 25.
4) With more than four transistors, it is necessary to turn ON as many transistors in the
top as possible while satisfying the above conditions. Turning ON the top transistors
would avoid drawing Igate from their drains to their gates, as explained in the case of
the top-most transistor in section 4.1.2. Therefore, minimum leakage vectors in a
stack with a higher number of transistors would follow the pattern of (1,1,1,. . ..0,1,0).
'oUT =
PUN PUN PUN
\ = vDD vOUT:= VDD i
v
o HLto HC TO i HL to
o HL^ti oHL Tl o HL ti
0 -\r T2 i HL T2
Vqut Vdd
oHI T3
(a) (b) (c)
Figure 25. Minimum leakage vectorsfor (a) 2-transistor (b) 3-transistor (c) 4-transistor stacks
For a stack of PMOS transistors, since gate currents are small enough to be
ignored, minimum leakage is obtained when all the transistors in the stack are turned
OFF.
35
A new algorithm based on the above analysis is developed which makes use of
input pin-reordering. For a given input vector, all the inputs nodes of the gates in the
circuit will be checked for their logic states and then reordered according to the rules
discussed above. Consider a stack of transistors with input'A'
connected to the transistor
nearest to the output and input'B'
connected to the next transistor and so on. Table 5
shows all input combinations to 2, 3 and 4 transistor stacks and how they are reordered to
achieve minimum leakage.
Number of transistors in stack Number of ON TransistorsReordered
(A,B,C,D)NMOS Stack
Reordered
(A,B,C,D)PMOS Stack
2 1 (1,0) (0,1)
31 (1,0,0) (0,1,1)
2 (1.1.0) (0,0,1)
4
1 (1,0,0,0) (0,1,1,1)
2 (1,0,1,0) (0,0,1,1)
3 (1,1,1,0) (0,0,0,1)
Table 5. Inputpin reordering
In this chapter, the circuit level behavior of Isub and Late including their
interdependence was studied. It was shown that in stacks with two or more OFF
transistors, the total leakage current is predominantly determined by Igate. Leakage
analysis of the NAND gate showed that minimum leakage vectors are different when
only Isub is considered as compared to Isub with Igate. We have demonstrated that the
interdependence between Isub and Igate can be exploited to reduce total leakage current
drawn from the supply voltage. This was seen when the minimum leakage vector was
applied as an input to the NAND gate. The total leakage current was less than the case
when only ISUb was considered. A standard approach to predict minimum leakage vectors
for stacks with a variable number of transistors was developed by making use of the
interdependence between Isub and Igate. Finally, a new leakage reduction algorithm was
36
developed based on the above analysis which makes use of input pin reordering to
achieve minimum leakage.
37
Chapter 5 Results
The leakage reduction techniques described were implemented on ISCAS89 benchmark
circuits [7]. The functional descriptions for most of the circuits have not been provided.
The following is a summary of what is presently published in literature [32].
s298, s400, s444 and s526 are traffic light controllers
s953 is a controller synthesized from a high level description
sl238 is a combinational circuit with randomly inserted flip-flops
Table 6 shows statistical data consisting of the number of gates present in each
benchmark circuit.
ISCAS89
Benchmark CircuitsDFF NAND AND NOR OR Inverter
s27 3 1 1 4 2 2
s298 14 9 31 19 16 44
s382 21 30 11 34 24 59
s400 21l_
36 11 34 25 58
S444 21 58 13 34 14 62
S526 21 22 56 35 28 52
s820 5 54 76 66 60 33
s832 5 54 78 66 64 25
s953 29 114 49 112 36 84
S1238 18 125 134 57 112 80
Table 6. Statisticsfor ISCAS89 benchmark circuits
All simulations were performed using BSIM4 technology model for 45nm feature size
[24]. Leakage currents were measured using Nanosim [29] which provides a detailed
distribution of total power dissipation thus making it a suitable tool for power analysis.
Critical paths and critical delays were measured using Pathmill [30] which is a transistor
level static timing analysis tool.
38
5. 1. Transistor Stacks
This technique utilizes the leakage behavior in transistor stacks to reduce leakage
current. Input vector to a circuit is first identified that gives the least leakage current. This
is done by measuring leakage current for all possible input vector combinations.
However, due to increased number of inputs in large benchmark circuits, it is a difficult
task to test for all input combinations. Therefore, circuits with large number of inputs are
tested for randomly generated input vectors which form a subset of all possible input
combinations. These random numbers are generated using rand() function. Leakage
control transistors are then inserted in series to high leakage gates which do not lie in
critical paths. The following algorithm was used in implementing this technique.
1) Identify critical path
2) Identify minimum leakage vector.
3) For each logic gate in the circuit,
Ifgate not in critical path, then
Ifonly one transistor is OFF, then
1. Ifgate output = 1, insert NMOS stack transistor.
2. Ifgate output= 0, insert PMOS stack transistor.
3. Reevaluate critical path
a. If critical path is changed, then remove the stack
transistor.
b. If critical path is unchanged, then keep the stack
transistor.
4) Reevaluate total leakage current to find leakage reduction achieved.
39
In the first step, critical paths are identified by using Pathmill. Minimum leakage vector is
then found out by one of the two methods mentioned earlier. In step three, gates that
qualify for stack transistor insertion are identified. These are gates that that do not lie in
critical path and which have only one transistor switched OFF. After the insertion of a
stack transistor, critical path along with its path delay are reevaluated. If any of these two
parameters change, then the stack transistor is removed. This algorithm is partly adopted
from [13].
The stack transistors that are added to control leakage are sized equal to the sum of the
widths of transistors in the stack. Table 7 shows the subthreshold and gate leakage
currents before and after the stack transistors are added.
ISCAS89
BenchmarkGates Gates Controlled
Minimum Leakage Vector (uA)
'sub 'qate
Leakage Control (uA)
'sub 'qate
s27 12 4 0.47 0.06 0.424 0.06
s298 133 75 3.44 0.55 2.104 0.53
s382 179 116 4.13 0.59 2.807 0.57
s400 184 118 4.24 0.6 2.818 0.58
s444 202 95 4.36 0.66 3.1 0.63
s526 214 102 5.4 0.92 3.285 0.89
S820 294 159 5.35 0.88 2.0 0.82
s832 292 154 5.45 0.9 1.98 0.89
S1238 526 336 10.01 1.43 3.36 1.33
Table 7. Leakage current reduction achieved by transistor stacks
"Gatescontrolled"
column represents the number of gates with the stack transistors
added. "Minimum leakagevector"
column shows the leakage currents when minimum
leakage vectors are applied and "LeakageControl"
column shows the leakage currents
after leakage control transistors are added. Figure 26(a) shows the percentage reduction
achieved for subthreshold leakage currents. The highest leakage current reduction
achieved is 68% for the case of sl238. This leakage reduction technique does not have
40
any substantial effect on gate leakage current since it basically uses the stack effect
phenomenon which mainly targets the subthreshold leakage current.
100
C90
5 80
1 70
o 60cc
in 50
S 40
S 30o
5 20"
10
0 HL
s27 S298 S382 s400 s444 S526 s820 s832 s1238
(a)
| 100
o 90
80
8 70
3 60
a 50
o 40
> 30CO
20
8 10
S. o
S27 S298 S382 S400 S444 S526 s820 s832 S1238
(b)
Figure 26. Transistor Stacks (a) Leakage current reduction (b) Percentage ofgates with stack transistor inserted
It is seen from Figure 26 that there is no exact correspondence between the number of
control transistors added and percentage leakage reduction achieved. This is because the
leakage reduction achieved by adding a control transistor depends on how much leakage
current existed prior to the addition. As discussed in section 4.1.1, leakage current in a
stack depends on the position of the device that is switched OFF. The lower the OFF
transistor, the lower is the leakage current flowing through the stack. Therefore, in such
cases leakage reduction is not as high as when the OFF transistor lies at the top of the
stack. Table 8 shows the variations in leakage current reductions when a control transistor
is added to a stack of three transistors with the OFF transistor begin in different positions.
Consider a stack of NMOS transistors with input A connected nearest to the output and
input B connected next to A and so on.
ABC Leakage (nA) Leakage Control (nA) Leakage Reduction (nA)
0 1 1 37.1 0.879 36.221
1 0 1 13.55 0.809 12.741
1 1 0 11.82 0.798 1 1 .022
Table 8. Variations in leakage reduction in transistor stacks
As seen in Table 8, leakage reduction achieved for input vector "0 11"
is more than three
times that of leakage reduction achieved for input vector "1 1 0". Therefore, there is no
41
strict correlation between number of control transistors added and leakage reduction
achieved.
5.2. DTCMOS
As mentioned in the section 3.4, DTCMOS utilizes the dependence of delay
performance of a transistor on its threshold voltage. It proposes that higher threshold
voltages can be assigned to transistors in non-critical paths so as to reduce leakage
current, while delay performance is maintained due to the use of low threshold transistors
in critical paths [12,13]. This technique is implemented by the following algorithm which
is similar to the one implemented in stack effect.
I) Find critical path
2) For each logic gate in the circuit,
a. If gate not in critical path, then assign high-threshold voltage to
transistors in the gate.
b. Reevaluate critical path
Ifcritical path is changed, then reassign low threshold voltage to
the transistors.
Ifcritical path is unchanged, then keep the high Vtn transistor.
3) Reevaluate total leakage current to find leakage savings achieved.
Devices in non-critical paths are assigned a threshold voltage which is 1.06 times the
normal threshold voltage. This is because the normal Vth is 0.466 volts and is not
increased beyond 0.5*VDD to maintain substantial current drive. Table 9 shows leakage
current reduction achieved by this technique. "GatesControlled"
column represents the
number of gates with high Vth transistors. Figure 27(a) shows percentage leakage
42
reduction achieved and Figure 27(b) shows the percentage of transistors controlled.
Leakage reduction up to 42% is achieved by this method. It can be seen from Figure 27
that there is a correspondence between the number of transistors with high Vth and
leakage current reduction achieved. The bar graphs from Figure (a) and (b) show similar
variations across all the benchmarks. The higher the number of transistors with high Vth,
the higher is the leakage reduction achieved.
ISCAS89 Benchmark Gates Gates ControlledV,h (uA)
'sub 'aate
1.06*Vth (uA)
Uub 'gate
s27 12 5 0.5 0.066 0.42 0.065
s298 133 108 3.54 0.55 2.5 0.53
s382 179 164 4.343 0.59 2.76 0.57
s400 184 167 4.364 0.6 2.848 0.58
s444 202 146 4.46 0.65 3.047 0.62
s526 214 176 5.5 0.92 3.819 0.9
s820 294 197 5.59 0.95 3.9 0.93
s832 292 250 5.7 0.97 3.66 0.95
S1238 526 480 10.42 5.87 3.66 3.6
Table 9. Leakage current reduction achieved by DTCMOS
100
90
80
70
60
50
40
30
20
10
0 a
100
90
80
70
60
50
40
30
20
10
0
S27 S298 S382 s400 S444 s526 s820 S832 S1238 s27 S298 S382 S400 S444 S526 S820 S832 S1238
(a) (b)
Figure 27. DTCMOS (a) Leakage current reduction (b) Percentage of transistors with high V,h
5.3. VTCMOS
VTCMOS is based on the principle of applying a reverse body bias to the
transistors to increase the threshold voltage and thereby reducing subthreshold leakage
current. Table 10 shows the leakage currents for increasing reverse body bias in steps of
0.1 volts.
43
ISCAS89 Benchmark GatesBody Bias
0 -0.1 -0.2 -0.3 -0.4
s27 12 0.5 0.4 0.36 0.29 .29
s298 133 L3.542.934 2.653 2.16 2.16
s382 179 4.343 3.47 3 2.38 2.38
s400 184 4.364 3.476 3.035 2.4 2.4
s444 202 4.46 3.612 3.153 2.56 2.56
s526 214 5.5 4.53 4.02 3.36 3.36
s820 294 5.59 4.38 3.85 3.18 3.18
s953 424 8.98 7.21 6.43 5.42 5.42
S1238 526 10.42 8.17 7.17 5.88 5.88
Table 10. Leakage current reduction achieved by VTCMOS
Figure 28 shows the variation of subthreshold leakage with body bias. The leakage
current reduces almost linearly with the applied reverse body bias up to -0.3 volts. By
applying further reverse bias, the leakage current does not decrease but saturates.
Leakage current plateaus when reverse bias reaches -0.3 volts.
-0.4 -0.3 -0.2
Body Bias
Figure 28. Leakage current as afunction ofbody bias
Leakage current reduction for all the benchmark circuits is shown is Figure 29.
Reductions as high as 43% can be achieved by this method.
T3U
100
90
80
70
60
50
40
30
20
10
0
s27 s298 s382 s400 s444 s526 s820 s953 S1238
Figure 29. Leakage current reduction achieved by VTCMOS
44
5.4. New Leakage Reduction Technique
The techniques implemented so far only target subthreshold leakage current. The
new leakage reduction technique reduces both subthreshold and gate leakage currents. It
is based on input-pin reordering as discussed in section 4.3. For a given input vector to a
circuit, the input nodes of all the gates are traced and checked for their logic state.
Depending on the inputs present at a particular gate, reordering is done based on Table 5
to reduce both subthreshold and gate leakage currents. Table 11 shows the subthreshold
and gate leakage currents before and after input pin reordering. The leakage current
values are averaged over all applied input combinations.
ISCAS89 Benchmark Uub Optimized lsub 'qate Optimized lgate
s27 0.49 0.457 0.066 0.061
s298 3.54 3.2 0.55 0.46
s344 4.14 3.8 0.5 0.47
s382 4.34 4.07 0.59 0.53
s400 13.05 12.78 0.6 0.54
S444 4.5 4.23 0.65 0.59
s526 5.49 5.03 0.92 0.76
s820 8.98 7.91 1.26 1.12
s832 10.42 8.88 1.48 1.168
s953 8.98 7.91 1.26 1.12
S1238 10.42 8.88 1.48 1.168
Table 11. Subthreshold and gate leakage currents before and after inputpin reordering
Figure 30 shows the leakage current savings for both leakage currents. Subthreshold
leakage currents can be reduced up to 20% while gate leakage currents can be reduced up
to 26%. The percentage reduction achieved in not as high as in the other leakage
reduction techniques described earlier because, this technique does not modify the
structure of the circuits or any process parameters. It merely exploits the inherent
properties present in the circuit such as the interdependence between subthreshold and
gate leakage currents. However, this technique provides a way to reduce gate leakage
45
currents in addition to only subthreshold leakage currents. Another advantage of this
technique is that it can be combined with existing leakage reduction techniques such as
DTCMOS and VTCMOS. Section 5.5 gives the leakage results for DTCMOS and
VTCMOS combined with input pin reordering.
50
45
40
35
30
25
20
15
10
5
0 iR
a Subthreshold
Gate Leakage
# / / # / / & # f f^
Figure 30. Leakage current reduction achieved by Inputpin reordering
The above data is given to demonstrate the effectiveness of this technique in
terms of reducing subthreshold and gate leakage currents. However, for the application of
this leakage reduction technique in VLSI circuits, the input vector that is supplied to the
circuit in standby mode must be known beforehand. This is because the input pin
reordering for all the gates present in the circuit depends on the logic states at their input
nodes. These logic states are in turn dependent on the supplied input vector. Therefore,
the input vector to be supplied in the standby mode must be decided to realize the
necessary pin reordering in design phase. Best results can be achieved if input pin
reordering is done when minimum leakage vector is applied. The following algorithm
summarizes all the steps needed to implement this leakage reduction technique.
I) Identify and apply minimum leakage vector
2) For each gate in the circuit
a. Identify transistor stacks with greater than or equal to two transistors.
46
b. Find number of transistors in the stack
c. Find logic states ofall input ports
d. Perform input pin reordering based on Table 5
3) Reevaluate subthreshold and gate leakage currents to find leakage current
reduction achieved
Minimum leakage vector is found in a similar way as in "Stack Effect". The logic states
at the input nodes of all the gates are found using Nanosim. Figure 3 1 shows the savings
realized by this method. These savings represent the percentage difference between the
reduced leakage current and maximum leakage current (the highest leakage current
recorded over all possible input vectors).
50
g 45
S40
I35
| 30
<o 25S1
20
I 15
a 10"
IT
a. 5
* jy *# ,& & & &$ / f F F ?&~
r 4?&~
j?
Figure 31. Total leakage reduction achieved by inputpin reordering
This method shows savings up to 26% on various benchmark circuits. For application of
minimum leakage vectors to a part of the circuit which is idle, latches present in the
circuit can be modified to force minimum leakage vectors with very little area and delay
overhead [28].
5.5. Input-pin reordering combinedwith DTCMOS/VTCMOS
Among the techniques described above, only input pin reordering has the
capability of reducing both subthreshold and gate leakage currents as opposed to only
47
subthreshold leakage current. Therefore, this technique combined with other leakage
reduction techniques should result in an improved subthreshold leakage reduction along
with gate leakage reduction. Input pin reordering can only be combined with other
leakage reduction techniques wherein the circuit is not modified structurally. For
instance, in stack effect, transistors are added to the bottom of the stacks and therefore
this technique imposes a restraint on pin reordering. Input pin reordering can be
combined with DTCMOS or VTCMOS since the circuit is not modified in these
techniques.
To combine input pin reordering with DTCMOS/VTCMOS, the former must be
implemented first in a similar way as described in section 5.5. Minimum leakage vector is
applied to the circuit and input pin reordering is done accordingly. This is followed by
DTCMOS or VTCMOS leakage reduction techniques as implemented in sections 5.3 and
5.4 respectively. Figure 32 shows the leakage current reduction achieved when input pin
reordering is combined with DTCMOS.
100
g 90
g80
I 60
<i> 50S*
40
5 30
S 20
10
0
q! 10
? Subthreshold
Gate Leakage
Figure 32. Inputpin reordering combined with DTCMOS
This method shows subthreshold leakage reduction of up to 52% for the case of si238
benchmark circuit. The highest subthreshold leakage reduction achieved by using
DTCMOS was about 42%. This improvement in subthreshold leakage reduction is
accompanied by gate leakage reduction too. The gate leakage reductions achieved are the
48
same as in input-pin reordering since DTCMOS does not have any effect on gate leakage
currents. Therefore, the highest gate leakage reduction remains at 26% for the case of
s832. Figure 33 shows the percentage leakage reduction achieved when input pin
reordering is combined with VTCMOS.
c
o
o
aa
rr
4)
o>
ra
coot
a.
100
90
80
70
60
50
40
30
20
10
0
? Subthreshold
Gate Leakage
Figure 33. Inputpin reordering combined with VTCMOS
As seen from the figure, the highest subthreshold leakage reduction achieved is 53% for
the case of s820 benchmark circuit. Highest subthreshold leakage reduction achieved by
using VTCMOS alone was 43%. Therefore, similar to the previous technique, this
leakage reduction technique shows improvement in subthreshold leakage reduction and is
accompanied by gate leakage reduction too. Also, the gate leakage current reductions
achieved are the same as in input-pin reordering since VTCMOS does not have any effect
on gate leakage currents. Therefore, the highest gate leakage reduction again remains at
26% for the case of s832.
49
5.6. Comparison ofLeakage Reduction Techniques
The highest leakage reductions achieved from all the techniques described in
chapter 5 are graphically displayed in Figure 34 where the x-axis index numbers
represent different leakage reduction techniques: 1) Stack Effect 2) DTCMOS
3)VTCMOS 4)Input pin reordering 4) Input pin reordering combined with DTCMOS 5)
Input pin reordering combined with VTCMOS.
100
c
o
3 803
| 60
CD
O)
ra
c
CO
20
a.
40
1 - Stack effect
2 - DTCMOS
3 - VTCMOS
j 4 - Pin reordering
5 - Pin reordering & DTCMOS
6 - Pin reordering & VTCMOS
1 2 3 4 5 6
Leakage Reduction Technique
Figure 34. Leakage reduction achievedfor all the techniques
As seen from the figure, stack effect results in the highest leakage reduction. However,
the graph represents subthreshold leakage reduction only. Techniques such as 4, 5 and 6
are also accompanied by a highest of 26% reduction in gate leakage currents. Among 4, 5
and 6, 6 shows the highest subthreshold leakage reduction. Therefore, pin reordering
combined with VTCMOS has turned out to be the most effective technique for reducing
both subthreshold and gate leakage currents. Specially, as the gate leakage currents
increase rapidly, this leakage reduction technique should be the most effective technique
for upcoming generations.
It is also worthwhile to discuss the disadvantages associated with other leakage
reduction techniques. Since stack effect is based on inserting additional control transistors
to low leakage gates, this incurs a discernable area overhead. Moreover, choosing the size
of the control transistors in not a trivial task. One must always check to see that there is
50
no delay impact due to insertion of these control transistors even when placed in non-
critical paths. If the size is reduced beyond a certain point, then leakage control paths will
become critical paths. Sizing the control transistors too large can result in high leakage
currents since subthreshold leakage current is proportional to the width of a transistor.
There is no standard approach proposed in literature on sizing of the control transistors.
Dual threshold CMOS uses multiple Vth transistors. Circuits with multiple Vth
devices require additional steps in the fabrication process thus prolonging chip
manufacturing period. However, DTCMOS technique is good for leakage power
reduction in both idle and active mode. It also does not incur any delay or area overhead.
Input pin reordering and VTCMOS leakage reduction techniques do not exhibit
any of the disadvantages associated with stack effect and DTCMOS. Unlike stack effect,
no area overhead is incurred and unlike DTCMOS, there is no need of incorporating
multiple Vth devices. In the case of input reordering, if a portion of a large circuit is in
idle state, then minimum leakage vectors can be applied to the circuit by modifying the
latches present in the circuit. Therefore, area overhead incurred is quite negligible.
51
Chapter 6 Conclusion
With scaling feature sizes, leakage power is increasing significantly and is
becoming the dominant part of total power dissipation. Specially, at sub-65nm feature
size, gate leakage current grows faster than subthreshold leakage current. Most of the
leakage reduction techniques proposed are devoted towards subthreshold leakage current.
Very few gate leakage reduction techniques were proposed in literature. However these
techniques do not consider gate current in NMOS devices that are switched off. Our
analysis on 45nm and 32nm models shows that this component cannot be ignored.
Considering the gate leakage in NMOS devices, a new leakage reduction
technique that reduces both subthreshold and gate leakage currents was proposed. The
following steps were performed in the process. Different logic families such as CMOS,
pass-transistor and pass-transmission gate circuits were analyzed for static and active
power dissipations. CMOS logic family exhibited the least leakage currents due to the
presence of series transistors which induce the stack effect. CMOS logic family also
showed the least short-circuit power dissipation since CMOS circuits are ratioless. In the
case of switching power dissipation, pass-transistor and pass-transmission gates showed
superior results only in XOR and full adder gates as a result of their efficient MUX like
structure. CMOS logic family was chosen for the rest of the thesis as it showed overall
superior power dissipation results compared to other logic families.
In the next step, subthreshold and gate leakage currents were studied and analyzed
in terms of their circuit level behavior. The interdependence between the two leakage
currents was studied by running simulations on basic CMOS gates. The following steps
were performed in the analysis 1) analysis of leakage current considering only Isub and 2)
52
analysis of interdependence between ISUb and Igate. The key observations made from our
analysis are: 1) For a stack with two or more OFF transistors, the total leakage current
drawn from the power supply is predominantly determined by Igate 2) Minimum leakage
vectors for the case of ISUb are not the same when Igate is considered along with Isub 3) In
the case of a NAND gate, it was found that when minimum leakage vector is applied, the
total leakage current drawn from the supply voltage is less than when only Isub is
considered. Thus interdependence between Isub and Igate can be exploited to reduce total
leakage current 4) Different categories were identified based on the interdependence
between Isub and Igate which are useful for predicting low leakage input vectors. These
observations lead to the inference that the interdependence between Isub and Igate can be
exploited to reduce the total leakage current by application of appropriate input vectors
and input pin reordering. This was the motivation behind developing a new algorithm that
reduces both subthreshold and gate leakage currents.
The new leakage reduction technique was compared against most of the
prevailing reduction techniques such as stack effect, DTCMOS and VTCMOS by
implementing them on ISCAS89 benchmark circuits. While the new leakage reduction
technique did not measure up to the other techniques in terms of reducing subthreshold
current, it had the capability of reducing gate leakage currents. Therefore this technique
was combined with DTCMOS and VTCMOS and the results were promising. The new
technique combined with VTCMOS showed the best results by achieving up to 53%
subthreshold leakage reduction and 26% gate leakage reduction.
This work can be extended by modifying the new leakage reduction algorithm to
account for gate leakage currents in PMOS devices. This component was ignored in this
53
thesis as it was found negligible compared to gate leakage currents in NMOS devices.
However, at lower feature sizes, this component may increase. Furthermore, the code
written to implement the new leakage reduction algorithm only works for circuits built
from standard cells. It must be modified to work on a fully ASIC design.
54
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