powerpoint presentation
Post on 10-Jul-2015
583 Views
Preview:
TRANSCRIPT
Lattice IPTV solution
Jeffery Pu/Senior FAE
Copyright © Lattice Semiconductor 2003Slide Ref LO-2
Bringing the Best TogetherBringing the Best Together
♦ Low Cost, LUT-based FPGA– 6K to 70K LUT4s– 12K to 136K bits distributed memory– 95 to 628 I/O– High volume prices as low as $0.50 per 1K LUTs
♦ Flexible sysIOTM Buffers– LVCMOS 33/25/18/15/12, PCI– SSTL3/2/18 & HSTL15 & HSTL18– LVDS, RSDS, Bus-LVDS, MLVDS & LVPECL
♦ Pre-engineered Source Synchronous I/Os– DDR1/2 (400 Mbps)– Generic Source Synchronous (840 Mbps)
♦ sysDSPTM High Performance DSP Support– 12 to 88 18x18 multipliers
♦ sysMEMTM Block Memory– 55K to 1M bits
♦ sysCLOCKTM PLL and DLL♦ Enhanced Configuration Support
– Configuration bitstream encryption– Transparent updates– Dual boot support
LatticeECP2 – Low Cost & High Performance
Low Cost
840 Mbps Parallel I/O
28 GMAC DSP
Bitstream Encryption
Bringing the Best TogetherBringing the Best Together
400Mbps DDR2
Copyright © Lattice Semiconductor 2003Slide Ref LO-3
Bringing the Best TogetherBringing the Best Together
Extensive High Performance Clocking
♦High Performance Clock Distribution– Eight global clock networks– Eight regional secondary clocks– Two low-skew edge clocks per side
♦ sysCLOCK PLL and DLL Technology– 2 to 6 PLLs per device
» External capacitor allows operation as low as 1MHz» Dynamic phase shift capability
– 2 DLLs per device
♦On-Chip Oscillator (2.5 to 130MHz)♦ Edge Clock Divider
– X2, X4, X8– For high speed source synchronous implementations
Copyright © Lattice Semiconductor 2003Slide Ref LO-4
Bringing the Best TogetherBringing the Best Together
High Performance sysDSP Block
♦ Programmable Multiplier – One 36x36, or four 18x18 or
eight 9x9
♦ Programmable Addition, Subtraction & Accumulate
♦ Programmable Pipelining– Input / Intermediate / Output
♦ 325MHz Performance – Provides up to 28.6
GMAC/second per device
♦ Suitable For Wide Range of DSP Functions Including
– FIR Filters, FFTs and complex arithmetic
X
X+-Σ+-Σ
X
X+-Σ+-Σ
+ +
sysDSP BlocksysDSP Block
Copyright © Lattice Semiconductor 2003Slide Ref LO-5
Bringing the Best TogetherBringing the Best Together
DQS/Strobe Delay and Transition Detect*
PIO A Tri-stateRegister Block(2 Flip/flops)
Input
PIC
Pre-Engineered Source Synchronous I/O
♦ Implement High Speed Memory Interfaces
– DDR1/2
♦ Implement High Speed Source Synchronous Interfaces
– SPI4.2– ADC/DAC
♦ Pre-Engineered I/O Logic Support
– DDR to SDR conversion– Gearbox logic– DQS/Strobe alignment
DDR to SDR Conversion
OutputRegister Block(2 Flip/flops)
InputRegister Block(5 Flip/flops)
PIO B(Detail Not Shown)
* Selectedblocks
2:1 Gearbox
(Optional) Shared
With PIO B
Precision Strobe/DQS Alignment
2:1 Gearbox For operation Up to
840Mbps
Copyright © Lattice Semiconductor 2003Slide Ref LO-6
Bringing the Best TogetherBringing the Best Together
Advanced Configuration Support
♦Flexible Configuration Options– Low cost SPI boot memory,
microprocessor, JTAG
♦Bit Stream Encryption– On-chip 128-bit AES decryption – Encryption key securely stored on-chip
♦Automatic SPI Dual Boot– Allows recovery if power or
communication fails during field update
♦Simple Field Configuration– Define I/O state during field configuration– Reconfigure FPGA while system operates
Copyright © Lattice Semiconductor 2003Slide Ref LO-7
Bringing the Best TogetherBringing the Best Together
Encryption
♦ Design Security Increasingly Important– Overbuilding, reverse engineering and cloning all too common
♦ Encrypt Bitstreams With 128-bit AES Using ispVM♦ On-Chip OTP 128-bit Decryption Key Storage
– Choose your own unique key
♦ On-Chip 128-bit AES Decryption Engine
ConfigurationMemory
128-bit AES Encrypted Bitstream
LatticeECP2
DecryptionEngine
128-bit Key128-bit Key In OTP
Non-Volatile Memory
Decrypted Data Configures FPGA
Copyright © Lattice Semiconductor 2003Slide Ref LO-8
Bringing the Best TogetherBringing the Best Together
Dual Boot Mode
♦ Store Active and Backup (Golden) Configurations In SPI Configuration Memory
♦ LatticeECP2 Will Automatically Use Golden Configuration If Active Configuration is Invalid
♦ Increase System Reliability When Configurations are Field Updated
Sector 0
Sector 1
Read Data
Control
LatticeECP2
LatticeECP2 Loads Active Configuration (B) at Power
Up. If This Fails Configuration A is Used
SPI ConfigurationMemory
Golden (A)Configuration
Active (B)Configuration
Copyright © Lattice Semiconductor 2003Slide Ref LO-9
Bringing the Best TogetherBringing the Best Together
Performance
Element Performance (MHz)
PFU 375MHz*
sysCLOCK PLL Input Range 1 – 420MHz
Global Clock 500MHz
sysMEM EBR 350MHz
sysDSP Block 325MHz
sysIO Buffer400Mbps (DDR1/2 memory)
840Mbps (Generic DDR)
Performance Supports Designs In Excess of 325MHz
* Simple functions (For example 16-bit decoder, 16-bit counter)
Copyright © Lattice Semiconductor 2003Slide Ref LO-10
Bringing the Best TogetherBringing the Best Together
TransFR I/O For Live Field Updates
Field Update FPGAs and Maintain High System Uptime
Config. 1
LatticeECP2
(Config. 2)Config. Memory
Step 1Load New Config. To Configuration Memory
Step 2Lock The I/Os In
The Desired State
Config. 1
LatticeECP2
(Config. 2)Config. Memory
Step 3Apply New
Configuration
Config.2
LatticeECP2
(Config. 2)Config. Memory
Step 4FPGA Regains Control of I/O
Config.2
LatticeECP2
(Config. 2)Config. Memory
Copyright © Lattice Semiconductor 2003Slide Ref LO-11
Bringing the Best TogetherBringing the Best Together
LatticeECP2
Soft Error Detect (SED) Logic
♦ LatticeECP2 Devices Contain Hard SED Logic
♦ Checks Configuration Bits In Background
– Compares to CRC– Ignores EBR and distributed
memory
♦ In Case of Error Optionally:
– Generates an error flag– Background reconfigures
logic– Initiates a full reconfiguration
ConfigurationLogic
ConfigurationBits
Hard SED Logic
Copyright © Lattice Semiconductor 2003Slide Ref LO-12
Bringing the Best TogetherBringing the Best Together
I/O Support
* Includes PCI clamping diode. Bottom I/Os only** HSTL II outputs only supported for 1.8-volts*** Drivers on 50% of pairs left and right side of the device only**** LVPECL and BLVDS can be supported through emulation
Standard Clock Speed
Clock Speed
166MHz
66MHz
200MHz
200MHz
420MHz
200MHz
200MHz
LVTTL, LVCMOS
3.3/2.5/1.8/1.5/1.2 V
333Mbps
PCI* 66MHz
SSTL 18/2/3 (I, II) 400Mbps
HSTL 18/15 (I, II**) 400Mbps
LVDS*** 840Mbps
Differential HSTL 400Mbps
Differential SSTL 400Mbps
sysIO Buffer Support Chip Level Support
Standard Speed
Generic Source Synch. 840Mbps
DDR1/2 Memory 400Mbps
PCI 66MHz
Copyright © Lattice Semiconductor 2003Slide Ref LO-13
Bringing the Best TogetherBringing the Best Together
Device ECP2 6 ECP2 12 ECP2 20 ECP2 35 ECP2 50 ECP2 70
LUTs (K) 6.0 12 21 32 4821
38796
# 18x18 Multipliers 12 24 28 32 72 88
144-pin TQFP (20x20mm) 95 95208-pin PQFP (28x28mm) 127 127
Samples Q4 Q2 Q3 Q3 Q1 Q4
4/2Package & IO Combinations
339500
68sysMEM Blocks 3 12 15 18 56sysMEM (Kbits) 55 221 276 331 1,032Distributed RAM (Kbits) 12 24 42 65 136
PLLs/DLLs 2/2 2/2 2/2 2/2 6/2
256-ball fpBGA (17x17mm) 192 192 192
672-ball fpBGA (27x27mm) 363 452 500484-ball fpBGA (23x23mm) 297 332 332
900-ball fpBGA (31x31mm) 628
LatticeECP2 Family
Copyright © Lattice Semiconductor 2003Slide Ref LO-14
Bringing the Best TogetherBringing the Best Together
Copyright © Lattice Semiconductor 2003Slide Ref LO-15
Bringing the Best TogetherBringing the Best Together
LatticeSC Architecture
High Performance FPGA Fabric4 to 32 SERDES (Up to 3.4Gbps) with Physical
Coding Sublayer(PCS)
15K to 115K LUT4s
System-Level Features:
Embedded System Bus /
Dedicated Microprocessor Interface / SPI
Flash Configuration
2Gbps PURESPEED I/O
Up to 7.8 Mbits of Embedded
Memory Blocks
MACO: Embedded Structured ASIC
Blocks(LatticeSCM Devices)
8 Analog PLLs /12 DLLs per Device
1.0V-1.2V Operating Voltage
Copyright © Lattice Semiconductor 2003Slide Ref LO-16
Bringing the Best TogetherBringing the Best Together
LatticeSC Extreme Performance FabricVersatile Logic Blocks Running at 500MHz!
• Logic• RAM/ROM• Ripple• MUX• Shift Register
Hierarchical Clock Networks To Distribute High Speed Clocks Throughout The Device.
• Primary Clock At 700MHz• I/O Tuned Edge Clock At 1GHz
Large memory capacity to support fast, flexible RAM.Configure memory as Single-Port RAM, True Dual-Port RAM, Pseudo Dual-Port RAM, ROM, or FIFO.
Copyright © Lattice Semiconductor 2003Slide Ref LO-17
Bringing the Best TogetherBringing the Best Together
LatticeSC — Advanced Clocking Options
Edge Clocks:• High-speed, Fast Injection and VERY Low
Skew Clocks Designed for I/O Purposes.• Distributed Around the Edge of the Chip
(40 Total)
Primary Clocks:• Designed for Extremely High-performance• 12 Primary Clocks Per Quadrant• Can Be Driven by Local Routing• Up to 24 SERDES Clocks Drive Primary
ClocksSecondary Clocks:• Ideal for Routing Slower Speed Clock and
Control Signals Throughout the Device• Preserves Primary Clock Network for Timing
Critical Requirements• All SERDES Clocks Can Drive Secondary
Clocks Directly
The LatticeSC Devices Have Three Distinct Clock Networks for Use in Distributing High-performance Clocks Within the Device: Primary Clocks; Secondary Clocks; And, I/O
Tuned Edge Clocks.
Clock Options to Logic/RAM
Copyright © Lattice Semiconductor 2003Slide Ref LO-18
Bringing the Best TogetherBringing the Best Together
PURESPEED I/O Technology Overview
The Best Parallel I/O In The Industry:
♦ 15 Single-ended and 7 Differential Buffer Standards Supported With Speeds up to 2Gbps!
♦ Dedicated Source Synchronous Interface Logic With Built-in Dynamic Alignment Capability (Available on Every Pin)
♦ Dedicated DQS Circuitry and DDR-II On-Die Termination for Best-in-class Memory Controller Support
♦ Digitally Controlled On-chip Output Impedance/input Termination for Consistent Performance Over PVT
Lattice EnhancementIndustry Standard Lattice Innovation
I/O Technology Evolution
Copyright © Lattice Semiconductor 2003Slide Ref LO-19
Bringing the Best TogetherBringing the Best Together
PIO A
OutputRegister Block
Tri-stateRegister Block
Bond Pad
Input
Programmable I/O Cell (PIC)
High performance sysIO Buffer (up to 2 Gbps)
• Supports multiple standards
• Includes on-chip termination
InputRegister Block
+ Dynamic Alignment
Output register block containsdedicated high-speed MUX/DEMUX gearing circuitry to support:
• DDR/SDR• Shift x2• Shift x4
ControlSelect
Input register block contains dedicated high-speed MUX/DEMUX gearing circuitry to support…
• DDR/SDR• Shift x2• Shift x4
+ Dynamic Alignment Logic thatenables Source Synchronous I/O via dedicated:
• Input Delay block (INDEL)• Adaptive Input Logic (AIL)
Clock domain transfers guaranteed over PVT
Edge clocks1GHz
PURESPEED I/O Logic
Copyright © Lattice Semiconductor 2003Slide Ref LO-20
Bringing the Best TogetherBringing the Best Together
The Most Robust Solution - Bit-based Alignment: Data Rates Up to 2Gbps- Automatic Voltage/Temperature Compensation
PURESPEED Innovations: INDEL & AIL
Adaptive Input Logic
Edge CLK
DataD Q
AIL LockedDelay Adjust
MUX/deMUX Logic(SDR/DDR)
FPGA System Clock
DIV2 or DIV4
Setup & Hold Time Monitor
INput DELay
INput DELay Block Provides 144 Delay Tap Settings (40ps Typical Step Size)
Adaptive Input Logic (AIL) Examines Setup / Hold Times of Every Input Data Pin and Adjusts the Delay Until the Data Edge Falls Outside The Setup/Hold Time Margin
• DDR to SDR Conversion• Logic Operates on Both Edges of the Clock • Dedicated FIFO for Automatic Clock Transfer between
High Speed I/O and Lower Speed Internal Clock
FPGAFabric
Dedicated Phase-Matched Clock Divider Eliminates Need For PLL
Copyright © Lattice Semiconductor 2003Slide Ref LO-21
Bringing the Best TogetherBringing the Best Together
PURESPEED DDR Memory Solutions
At the Controller (FPGA) We Must Delay the
Incoming DQS Signal and Center–align It to the Incoming Data in Order
to Capture It
DQS
DQDQ
INput DELayMux/demux
9
n
DQS
CLK DLL
DQS postamble gate,shuts off DQS at end of READ
cycle
INput DELay
Set to match DQS edge clock injection delay, static
90° phase shift, compensated over PVT and speed of operation
DDR CONTROLLER REQUIREMENT LatticeSC PURESPEED I/O IMPLEMENTATION
Feature DDR SDRAM Controller
DDR II SDRAM Controller
QDR II SRAM Controller
RLDRAM I/II Controller
Speed of Operation 200 MHz/400 Mbps 267 MHz/534 Mbps 300 MHz/600 Mbps 300 MHz/600 Mbps400 MHz/800 Mbps
Data Width 8,16,32,40,64,72-bits 8,16,32,40,64,72-bit 8,9,18,36-bit 9,18,36-bit
Copyright © Lattice Semiconductor 2003Slide Ref LO-22
Bringing the Best TogetherBringing the Best Together
LatticeSC — System Standards Support
I/O Standard Buffer Type Bus Width Data Rate Clock Frequency Pin ThroughputGeneric LVDS, Mini-LVDS, RSDS LVDS Variable DDR 1GHz Up to 2Gbps
RapidIO Differential 8, 16 DDR 125 — 500MHz 250 Mb — 1Gbps
HyperTransport LVDS 32 DDR 200 — 400MHz 400 — 800Mbps
SPI-4 (PL4) LVDS 16 DDR 311 — 450MHz 622 — 900Mbps
SFI-4 / XSBI LVDS 16 SDR 622/645MHz 622/645Mbps
XGMII HSTL 32 DDR 156MHz 311Mbps
CSIX L1 HSTL 32 — 128 SDR 250MHz 250Mbps
QDR2 SRAM HSTL Variable DDR 300MHz 600Mbps
DDR1 / 2 SDRAM SSTL Variable DDR 300MHz 600Mbps
PCI / PCI-x LVTTL 32/64 SDR 66/133MHz 66/133/266Mbps
RLDRAM 1 / 2 HSTL Variable DDR 300/400MHz 600/800Mbps
Copyright © Lattice Semiconductor 2003Slide Ref LO-23
Bringing the Best TogetherBringing the Best Together
LatticeSC PURESPEED I/O — Best in Class♦ Performance up to 1GHz / 2Gbps♦ Dedicated Input Delay Block Provides 144 Taps With 40ps Typical
Steps♦ Bit-based Dynamic Alignment for Guaranteed Performance♦ Dedicated High Speed Mux/demux♦ Programmable On-chip Termination Simplifies Board Layout♦ DQS Postamble Detect Logic for High Speed Memory Interfaces♦ DDR II Dynamic Bus Control♦ Dedicated Clock Dividers Eliminate Need for PLLs
Copyright © Lattice Semiconductor 2003Slide Ref LO-24
Bringing the Best TogetherBringing the Best Together
LatticeSC Industry-Leading SERDES/PCS♦ Up to 32 Channels Per Device♦ Speeds From 600 Mbps up to 3.4 Gbps♦ High Rx Jitter Tolerance (0.8UI)♦ Low Tx Jitter (0.29UI) ♦ Receiver Programmable Coupling (AC or DC)
– Supports SMPTE292M With External Cap and Cable Equalizer
♦ Tx Pre-emphasis and Rx Equalization for Improved BER Over Long (>60”) and Legacy Backplanes
– PE of 16%, 32%, 48%, 64%, 80% and 96%– Equalization Settings of 6dB and 12dB
♦ Very Low Power (100mW Per Channel Typical @ 3.125 Gbps)
♦ flexiPCS Compliant to a Number of Current and Emerging Standards
– PCS Is Bypass-able in 8/10/16/20 Bit Modes
Copyright © Lattice Semiconductor 2003Slide Ref LO-25
Bringing the Best TogetherBringing the Best Together
Masked Array for Cost Optimization♦ Multiple 90nm Embedded 50K ASIC Blocks
♦ Ample FPGA-to-ASIC Signal Connectivity
♦ Ample ASIC-to-IO Connectivity
♦ High-speed Clock Connectivity
Copyright © Lattice Semiconductor 2003Slide Ref LO-26
Bringing the Best TogetherBringing the Best Together
MACO: Standard Offerings
LatticeSCM25
EMBC
D
EMBA B
PLC Array
EMBE
EMBMACO MACOSER
DES
Qua
d
SER
DES
Qua
d
SER
DES
Qua
d
SER
DES
Qua
d
F
A A
B B
C CC
Block IP Type
KLUTs forSoft IP
KLUTs for MACODesign
Blocks on
SCM15
Blocks on
SCM25
Blocks on
SCM40
Blocks on
SCM80
Blocks on
SCM115flexiMAC 1GbE 2.7 0flexiMAC 10GbE 6 0flexiMAC PCIe 11 4 to 7Memory Controller DDR1/2
2 0
Memory Controller QDR2
2 0
Memory Controller RLDRAM
3 0
C SPI4.2 6 0.8 1 2 2 2 2
A
B
1
1
2
2
2
2
2
2
4
2
Copyright © Lattice Semiconductor 2003Slide Ref LO-27
Bringing the Best TogetherBringing the Best Together
MACO Value Proposition: Lower Cost Per Function
♦ MACO Provides Cost- and Power-efficient, High Performance “Extra” Gates♦ Commonly-used Functionality Embedded As Hard IP♦ Advantages: 10x Area Savings, 2x the Performance, and ½ the Power of
Equivalent FPGA Based Functions♦ Development Cost Savings Due to Efficient Die Use and Use of Pre-
engineered Blocks
IP Core SC FPGA Soft IP Fee
PCIe x 4 7000 11000 $20,000
Memory Controller 0 2500 $20,000
SPI4.2 1600 8000 $25,000
Customer LUTs 20,000 20,000
Total LUTs 28600 41500
SC vs. Generic FPGA
Soft IP comes at a significant cost to
customer and can be difficult to implement
90-100% of IP is designed into MACO resulting in large LUT
savings
MACO allows very efficient use of
resources Bottom Line: LatticeSC+MACO is Less Expensive and Easier to Design
Customer needs to struggle to get standard
functions working in FPGA logic.
Lattice supplied MACO IP is “pre-engineered”
Copyright © Lattice Semiconductor 2003Slide Ref LO-28
Bringing the Best TogetherBringing the Best Together
LatticeSC Family Device SC15 SC25 SC40 SC80 SC115
LUT4s (K) 15.2 25.4 40.4 80.1 115.2
sysMEM Blocks (18Kb) 56 104 216 308 424
Embedded Memory (Mbits) 1.03 1.92 3.98 5.68 7.8
Max. Distributed Memory (Mbits) 0.24 0.41 0.65 1.28 1.84
Number of 3.4G SERDES (Max) 8 16 16 32 32
DLLs 12 12 12 12 12
Analog PLLs 8 8 8 8 8
MACO Blocks 4 6 10 10 12
Package I/O + SERDES Channel Combinations (1mm ball pitch)
256-ball fpBGA (17x17) 139 + 4
900-ball fpBGA (31x31) 300 + 8 378 + 8
1020-ball ffBGA (33x33) 484 + 16 562 + 16
1152-ball fcBGA (35x35) 660 + 16 660 + 16
1704-ball fcBGA (42.5x42.5) 904 + 32 942 + 32
OPNsLFSC xx- NO MACO
LFSCM xx- MACO ENABLED
Copyright © Lattice Semiconductor 2003Slide Ref LO-29
Bringing the Best TogetherBringing the Best Together
LatticeXP FPGA Key Features
♦ Non-Volatile Reconfigurable– Instant-on– Single-chip– High-security
♦ TransFR™ (TFR) Technology – Simplifies in-field logic updates
♦ Wide Density & I/O Selection– 3k to 20k LUTs– 62 to 340 I/Os
♦ Embedded & Distributed Memory♦ High Performance (225MHz+) ♦ sysIO™ Interface Support
– LVCMOS, LVTTL, PCI, LVDS, SSTL, HSTL
♦ 333Mbps DDR Memory Interfaces♦ sysCLOCK™ PLLs♦ Low Power Sleep Mode♦ Two Core Power Supply Versions
– C = 1.8, 2.5, 3.3V Support– E = 1.2V Support
Non-Volatile
Flexible LUT-BasedReconfigurable
“No Compromise”
Copyright © Lattice Semiconductor 2003Slide Ref LO-30
Bringing the Best TogetherBringing the Best Together
LatticeXP Integrates Multiple Components
FPGAData Pathfunction
Microprocessor
CPLDPower up logic
FPGA boot logic and bus decode
Processor Address and D
ata Busses
Data PathPower up
Bus Decode
Microprocessor
Processor Address and D
ata Busses
Voltage Regulator
Copyright © Lattice Semiconductor 2003Slide Ref LO-31
Bringing the Best TogetherBringing the Best Together
LatticeXP Provides “Instant-On”
LatticeXP Logic is Available <1mS After Power Good-- Supports “Instant-On” Application Requirements --
XP A
dvan
tage
Altera
Lattice0
20
40
60
80
100
120
140
EP1C12 XC3S1000 XP10
Wak
e-up
Tim
e (m
S)
Xilinx
Fastest serial configuration
Copyright © Lattice Semiconductor 2003Slide Ref LO-32
Bringing the Best TogetherBringing the Best Together
Sleep Mode Reduces Power by Factor of 1000
Mode
Characteristic Normal Off Sleep
SLEEPN Pin High X Low
Static Icc Typical <100mA 0 Typical <100uA
Power Supplies Normal Range Off Normal Range
Logic Operation User Defined Non Operational Non Operational
I/O Operation User Defined Tri-State Tri-State
LatticeXPSLEEPN Pin
DeviceState Normal Sleep Mode Normal
Typical 100nS Typical 2mS
Note: Sleep Mode is only available on 1.8/2.5/3.3V “C” version
Copyright © Lattice Semiconductor 2003Slide Ref LO-33
Bringing the Best TogetherBringing the Best Together
LatticeXP FPGAs Secure Your Design
♦ FPGA Security Important Due To Multiple Threats
– Reverse engineering– Cloning– Overbuilding– Theft of service
♦ LatticeXP Security Scheme Allows Devices To Be Locked
– Secures SRAM and FLASH– Erasing memory is only
allowable operation– 0.13um technology and 9
metal layers makes probing next to impossible
♦ Specify Secure Mode in ispLever or ispVM
0110110100111010010101
0110
1101
001 0100101
SRAM FPGAs Expose Your Intellectual Property At Power Up
LatticeXP FPGAs Secure Your Design
Copyright © Lattice Semiconductor 2003Slide Ref LO-34
Bringing the Best TogetherBringing the Best Together
LatticeXP Benefits
Self-Configuration in Under A Millisecond• Ideal for system “heartbeat” control logic• Supports configuration “scrubbing” for SEU control• Supports rapid power cycling
High Security• Security bits prevent readback• No exposed power-up bitstream
Single Chip• Simplify design• Reduced PCB footprint• Save boot PROM costs
SRAM + FLASH• TransFR (TFR) technology
enables in field updates while system operates
On-Chip Regulation• Support legacy applications
with latest technology- Reduce costs- Improve performance
3.3, 2.5, 1.8 or 1.2V
3.3, 2.5, 1.8 or 1.2V
Copyright © Lattice Semiconductor 2003Slide Ref LO-35
Bringing the Best TogetherBringing the Best Together
LatticeXP Family
Device XP3 XP6 XP10 XP15 XP20LUTs (K) 3.1 5.8 9.7 15.4 19.7sysMEM Blocks 6 8 24 36 44sysMEM (Kbits) 54 72 216 324 396Distributed RAM (Kbits) 12 23 39 61 79Voltage (V) 1.2/1.8/2.5/3.3VPLLs 2 2 4 4 4Package I/O Combinations100-pin TQFP (14x14mm) 62144-pin TQFP (20x20mm) 100 100208-pin PQFP (28x28mm) 136 142256-ball fpBGA (17x17mm) 188 188 188 188388-ball fpBGA (23x23mm) 244 268 268484-ball fpBGA (23x23mm) 300 340
RoHS
Copyright © Lattice Semiconductor 2003Slide Ref LO-36
Bringing the Best TogetherBringing the Best Together
Copyright © Lattice Semiconductor 2003Slide Ref LO-37
Bringing the Best TogetherBringing the Best Together
MachXO Key Features
♦ Non-Volatile Solution– Single chip, instant-on, high security
♦ TransFR for Simple Logic Updates ♦ High Performance
– 3.5ns pin-to-pin
♦ LUT Based Flexibility– 256 to 2,280 LUT4s– 2K to 8K bits distributed memory
♦ I/O Intensive– 78 to 271 I/O
♦ Flexible sysIOTM Buffers– LVCMOS 33/25/18/15/12, LVDS, PCI
♦ sysMEMTM Block Memory– Up to 28K bits of memory
♦ sysCLOCKTM PLLs♦ On-Chip Oscillator ~20MHz♦ Low Power Sleep Mode♦ 1.2/1.8/2.5/3.3V Power Supply Options
LUT Flexibility
Embedded MemoryNon-Volatility
Performance
Copyright © Lattice Semiconductor 2003Slide Ref LO-38
Bringing the Best TogetherBringing the Best Together
MachXO Family MembersDevice MachXO 256 MachXO 640 MachXO 1200 MachXO 2280LUTs 256 640 1200 2280Distributed RAM (KBits) 2 6.1 6.4 7.7EBR SRAM (KBits) 0 0 9.2 27.6# EBR SRAM Blocks (9Kb) 0 0 1 3VCC VoltageNumber of PLLs 0 0 1 2Max I/O 78 159 211 271
Packages:100-TQ (14X14) 78 74 73 73144-TQ (20X20) 113 113 113csBGA 100 (8X8) 78 74csBGA 132 (8X8) 101 101 101ftBGA 256 (17X17) 159* 211 211ftBGA 324 (19X19) 271
1.2/1.8/2.5/3.3V
RoHS RoHS Compliant /Lead Free Versions
csBGAs Idealfor Space-
Constrained Applications
LVDS Pairs -- -- 27 33
Copyright © Lattice Semiconductor 2003Slide Ref LO-39
Bringing the Best TogetherBringing the Best Together
ispGDX2 Features
• High Performance SwitchingIn-system programmable (ISP) 38Gbps* switch and associated control logic optimized for bus switching.• 3.0ns pin-to-pin, 360MHz fMAX (Toggle)
• sysCLOCKTM PLLUp to four PLLs to modify timing to match system for optimum performance.
• High Performance InterfacingAdvance sysIOTM capability supports multiple advance I/O standards• Up to 8 sysHSITM providing 16
800 Mbps Duplex SERDES channels
*256 I/O (128 Rx, 128 Tx) with data lines running at 300MHz
Copyright © Lattice Semiconductor 2003Slide Ref LO-40
Bringing the Best TogetherBringing the Best Together
ispGDX Concept
♦Allows Integration of Multiple Buffers and Interface Chips
– Cost and board space savings
♦ Provides Time to Market Benefits of Programmability
– No board re-spins to modify connections or change I/O characteristics
Flexible Interconnect
ispGDX – Programmable Interface and Interconnect
Programm
able I/OB
uffers & SER
DES
Programm
able I/OB
uffers & SER
DES
Copyright © Lattice Semiconductor 2003Slide Ref LO-41
Bringing the Best TogetherBringing the Best Together
PLLGlobal Routing
Pool (GRP)
FIFO
SERDES
GDX BLOCK
SERDES sysHSI
sysIO Block
PLL
FIFO
GDX BLOCK
FIFO
SERDES
GDX BLOCK
SERDES sysHSI
sysIO Block
FIFO
GDX BLOCK
sysIO B
lock
sysIO B
lock
1532JTAGisp
sysIO B
lock
sysIO B
lock
sysIO Block
sysIO Block
ispGDX2 Block Diagram: Top Level
ispGDX2-64 shown
sysIOs forAdvanceInterface
Flexible routing Optimized for Bus Switching
GDX Blockincludes Control
Logic and Multiplexors
FIFOs forBuffering
Data streams15X10 bits
10-320MHzsysCLOCK
PLL
sysHSI BlockDuplex SERDES800Mbps LVDS
Support
JTAG, 1532 isp Interface
Copyright © Lattice Semiconductor 2003Slide Ref LO-42
Bringing the Best TogetherBringing the Best Together
Power Manager II
Copyright © Lattice Semiconductor 2003Slide Ref LO-43
Bringing the Best TogetherBringing the Best Together
What is Power Management?Power Management Is the Implementation of One or More Of These Functions in a Circuit Board
Hot-swap / Soft Start
Sequencing/ Tracking- Power Up / Down
Microprocessor ResetGeneration
Supervisor (Supply FaultDetection), Interrupt
Processor
- Add-in Circuit Boards
- Boards Using MultiVoltage ICs
- Boards Using Microprocessor
- Boards Using Microprocessor
Trimming / Margining - High Reliabilty Equipment
Copyright © Lattice Semiconductor 2003Slide Ref LO-44
Bringing the Best TogetherBringing the Best Together
Power Manager II Offers Integrated Solution!
All Power Management Functions on One Chip!
Hot-swap / Soft Start
Sequencing/ Tracking- Power Up / Down
Microprocessor ResetGeneration
Supervisor (Supply FaultDetection), Interrupt
Processor
Trimming / Margining
Copyright © Lattice Semiconductor 2003Slide Ref LO-45
Bringing the Best TogetherBringing the Best Together
… Replaces Competing Power Management Devices
♦ Advantages– Increased Flexibility– Higher Accuracy– Software Based Power Management Design– Reduced Part Count Improves…
» Inventory Management» Reliability
Copyright © Lattice Semiconductor 2003Slide Ref LO-46
Bringing the Best TogetherBringing the Best Together
Power Manager II Beats Competition
Manufacturer Lattice Power1220AT8
Lattice Power1014/A
Analog Devices
ADM1062, 1066, 1067
Summit SMM6XX, SMM7XX
Advantages of Lattice Over Competition
Analog Inputs 12 10 10 6 More Analog Inputs Window Compares
Type MonitoringProgrammable
Comparator (16 us)
Programmable Comparator
(16 us)
Programmable Comparator
(20 us)
Sampled Through ADC
(2-12 ms)Fastest Fault Identification
Monitoring Accuracy Across Temperature and Process 0.7% 0.7% 1% 0.75% Highest Precision
Digital Inputs 6 - Programmable 4 - Programmable 0 0 Most Digital Inputs
Number of MOSFET Drivers 4 - Programmable 2 - Programmable 6-fixed NO Multiple MOSFET ControlNumber of Digital Outputs 20 14 10 6 Most Digital Outputs
Power Management Algorithm 48 M/C CPLD 24 M/C CPLD 10 Macrocells NO Most Flexible (CPLD)
Number of Trimming and Margining Controls 8 None 6 6 Maximum Number of Trimming Outputs
Programming interface JTAG JTAGSMBus
(I2C Compatible)Factory
ProgrammedJTAG is the Preferred Method of Programming
I2C Interface Yes Yes Yes Yes Most Flexible Support of Microprocessors
SoftwareAdvanced PAC Designer with LogiBuilder
Advanced PAC Designer with LogiBuilder
Primitive PrimitivePAC-Designer Provides the Best Software
Interface
Copyright © Lattice Semiconductor 2003Slide Ref LO-47
Bringing the Best TogetherBringing the Best Together
Lattice solution - Cable Modem
Functions Performed•Memory controller performance of greater than 200MHz (400Mbps DDR) •Memory controller supports data widths of 16, 32 and 64 Bits •Interface to USB/Fast Ethernet on user side, DOCSIS MAC on line side
Lattice Advantages•Low-cost solution for cost-sensitive application •Reconfigurability results in rapid development and reduced time-to-market •Programmable flexibility to support changing standards •Existing IP speeds deployment to market
Copyright © Lattice Semiconductor 2003Slide Ref LO-48
Bringing the Best TogetherBringing the Best Together
Lattice solution - Set-Top Boxes
Functions Performed•Memory Controller •Clock distribution and system timing •IrDA Controller function receives data from the remote control •Peripheral Controller to control interfaces like Ethernet, UBS, RS232, etc. •System bug fixes
Lattice Advantages•5-volt tolerant with high-performance: 2.5 ns Tpd, 400 MHz Fmax •Low-cost and reduced time to market for initial and follow-on derivative products •Flexibility to support changing standards and feature upgrades/additions through field reprogrammability •Larger devices support higher system integration
Copyright © Lattice Semiconductor 2003Slide Ref LO-49
Bringing the Best TogetherBringing the Best Together
Lattice solution - Set-Top Boxes
Functions PerformedI/O Controller Lattice Advantages•High performance interfacing and switching •Connect to virtually any system interface •I/O intensive: 64 to 256 I/Os •I/O Control using standard interfaces such as LVCMOS, HSTL, SSTL, etc.
Functions Performed•Forward Error Correction (FEC) decoding •MPEG-2 Decoding •NTSC/ PAL Encoding Lattice Advantages•Reduced time to market for initial and follow on products •Add features remotely to box installed in home •Larger devices (>10K logic elements) support higher integration
Functions PerformedPower and smart battery management Lattice Advantages•CPLD provides efficient implementation of sequencing, monitoring and supervisory signal logic •Programmable analog input thresholds monitor power supply voltages •Programmable delay timers (32µs to 512ms) provide flexible timing control •Internal 250 kHz oscillator provides on-chip clock generation
Copyright © Lattice Semiconductor 2003Slide Ref LO-50
Bringing the Best TogetherBringing the Best Together
Lattice solution - VoIP and WLAN DSL Modem Residential Gateway
Functions Performed•10/100 MAC •Memory Controller •Power Management •Network Interface •Clock Generator
Lattice Advantages•Lowest Cost FPGA Solution •Density and Packages Targeted for High Volume Applications •Embedded and Distributed Memory •Popular IO Interfaces Support, Including LVDS and DDR •Embedded PLLs
Copyright © Lattice Semiconductor 2003Slide Ref LO-51
Bringing the Best TogetherBringing the Best Together
Lattice solution - Smart Card Reader
Functions Performed•Keypad and Fingerprint Interface and decoding •Smart Card Reader •LCD Display Control •Security Decoding •Network Interface
Lattice Advantages•Instant-On: Powers up in microseconds via on-chip E2CMOS based memory •Excellent design security, no bit stream to intercept •Reduced time to market for initial and follow-on derivative products •Flexibility to support changing standards through field reprogrammability
Copyright © Lattice Semiconductor 2003Slide Ref LO-52
Bringing the Best TogetherBringing the Best Together
Lattice IPTV solution – Summary
Devices UsedXPECP2Power ManagerispGDX2MachXO
Functions PerformedClock distribution and system timing IrDA Controller function receives data from the remote control Peripheral Controller to control interfaces like Ethernet, UBS, RS232, etc. System bug fixes Keypad and Fingerprint Interface and decoding Smart Card Reader LCD Display Control Security Decoding Network Interface 10/100 MAC Power Management Memory controller performance of greater than 200MHz (400Mbps DDR) Memory controller supports data widths of 16, 32 and 64 Bits Interface to USB/Fast Ethernet on user side, DOCSIS MAC on line side
Copyright © Lattice Semiconductor 2003Slide Ref LO-53
Bringing the Best TogetherBringing the Best Together
Lattice IPTV solution – Summary
Lattice Advantages•Reconfigurability results in rapid development and reduced time-to-market •Existing IP speeds deployment to market•Low-cost and reduced time to market for initial and follow-on derivative products •Larger devices support higher system integration •High performance interfacing and switching •Connect to virtually any system interface •I/O Control using standard interfaces such as LVCMOS, HSTL, SSTL, etc. •Add features remotely to box installed in home •Larger devices (>10K logic elements) support higher integration•Programmable analog input thresholds monitor power supply voltages •Density and Packages Targeted for High Volume Applications •Embedded and Distributed Memory •Embedded PLLs•Instant-On: Powers up in microseconds via on-chip E2CMOS based memory •Excellent design security, no bit stream to intercept
top related